Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Current driver prints error messages when it fails
registration for the display clients with the hw-fence
driver, however, this is not an error as currently
feature is disabled by default in hw-fence driver,
which as result will fail registration for clients.
Therefore, silent the error messages for a failed
registration.
Change-Id: I13b872db3452a57a885c73cc8f1cf512be986dd0
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Add rc feature disable handling in case set rc feature fails.
This will disable rc feature for all instances if set rc feature
fails for any instance.
Change-Id: I159b9bd3ed1416c4b2d32440d10132cb024f9529
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
Currently when calculating interface timing value, driver uses
drm_mode_vrefresh API which uses the mode clock and mode timing
values to determine the vertical refresh rate.
On a dual-DSI panel, the mode clock is calculated based on the full
display width which causes the interface vrefresh value to be 2x
greater than what it is supposed to be.
This change uses the cached_mode value, which has the correct
interface based mode clock.
Change-Id: I51bccf4962ec802b37e1ee9a463bfc08f162e5d6
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Remove debug info log and extra braces
from UCSC code.
Change-Id: I3dcd01aaebdeda81c08d3724e65f13ee7959ef5c
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
This change adds support for dynamically enabling and disabling
additional physical encoder IRQs.
Change-Id: I500fa69d1b8b8df39fd608391c906257efdea63b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Correcting the string name of UCSC in the register dump.
Change-Id: I2c8976d6d9bf4804ed6454b848c4a3b326b56f54
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
Add a debugfs node to set maximum bpp for the base panel which will
be used in both SST and MST use cases to limit the bpp.
Change-Id: I0ef7866e2b82a2078d6cdf97ee0d7226c2125b21
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
add memory barrier before and after last command to avoid
out of order packet queuing to lut dma packet queue.
add memory barrier after ctrl flush to ensure lut dma
trigger, dspp flush and ctrl flush all are written to dpu
before control start.
Change-Id: I7e1613034af8407d55529cf3f95c70994334af82
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
DSI PHY isolation is unused and considered deprecated. Previous uses
were for power measurements and emulated platform support. Use on
emulated platforms has been supplanted by PHY PLL bypass.
Change-Id: I547681912ff82f0df09a1b98c671eac32c19412a
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
MDSS 10.0 supports additional dedicated cwb pingpong pair.
This change updates downscaler block mux programming to
support when second dcwb pinpong pair is in use.
Change-Id: I1d5bdb557132c56874b13d06b9fe1aafeaadb36a
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Current dpu hw settings do not match the protocol id with
the ipcc hw protocol id for the fencing protocol.
This change adjusts the programming of the dpu configuration
register to properly select and use the fencing protocol.
Change-Id: I253c15856b8b3baaa3780681d953c2e79a30d686
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Enable hw-fence driver for Display in pineapple.
This change only allows Display to import the
hw-fence driver api's, but does not enable the
feature by default. Enablement of the feature in
the driver is done through the device tree property.
Change-Id: I4fe97e0cc76f780d1326a69c4162dc4908e89724
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
This change adds debug changes to dump the input fences during a
commit done timeout, when input hw-fences are enabled.
Change-Id: Ia778d3d73ab8ee795613587da70ef9bebb7c73ca
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
devm_of_pwm_get is deprecated and need to change
to devm_pwm_get.
Change-Id: Ibeee90261ff40dc50b6a5e40e583bee11a5b177c
Signed-off-by: Maria Yu <quic_aiquny@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Map UCSC plane properties to dirty bits to perform operations
correctly.
Change-Id: I6903b62846b8b535477aeca21a6c6e910dd4f6ad
Signed-off-by: Sabarinath M B <quic_sabamb@quicinc.com>
Remove the redundant log from the ucsc code.
Change-Id: Ic3e828706248e79f9aa949e2f0875cb41ad291aa
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
Include msm external display as required module for pineapple
and enable the config flag required for the same.
Change-Id: I55b94d594b8d1ee3c20b5e06b67b4e2fd5b21e7c
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Enable DP and DP MST compilation flags. This change also
includes the config flag to specify the aux switch used for
pineapple target.
Change-Id: I48e4953c9745bf9774ce1411a629b418b0c1a652
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change adds support for bypassing hw access in DSI PHY/PLL
drivers which enables the DSI driver to run on emulation
platforms that might be missing those modules.
Change-Id: I3e83155a79d60f2357606746214d776cefabd651
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
Currently get vcpi info call is returning wrong slot info since update
payload function is called afterwards. The latter function is calculating
the slot info which is read back by get vcpi call. This change reorders
these function calls. Also, this change sets start_slot to be always 1.
This is the value expected by upstream driver for atomic drivers.
This is a follow up change for the commit 19a9abf064
("disp: msm: dp: update MST first link slot information").
Change-Id: I620125a2d73afb7537a3540ee129e2a4eb0c488c
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Increase the log level of the prink statements to dev_err
when a register dump is triggered. This will allow user to
capture the values independently of the target default log level.
Change-Id: I67f8c854a274b70d1595e74136095ef91584ca90
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Update the LUT DMA register range registration to target
specific ranges of valid registers instead of the full
memory region of the LUT DMA module. This ensures that
unused LUT DMA register regions are not dumped.
Change-Id: I3739692ae7fcfd5777bb8774dd34c16ab87c3ae1
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
This change adds support for enabling the system cache
slices with staling. This allows back to back static display
cache usecases to self evict prior to using cache.
Change-Id: Iea71da26a8f7a450822624305dc20a3bab323d4b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Pipe csc configuration is being cached in the sde plane which can cause
race conditions between hardware programming and caching.
All drm properties should be cached in sde plane state to avoid race
conditions. Change moves caching to sde plane state.
Change-Id: I22470a82b2fc2812f8c526ababc2b517db13a3ce
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
This change avoid programming of legacy bit fields which
are conflicting with TE alignment feature bit fields
of split control register of peripheral top block.
Change-Id: Ib9f519ec82ee3b3885351dff960b176c99dcf08d
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
