In API hif_batch_send(), the variable ce_tx_hdl is dereferenced in
if_batch_send() without null check. Check for null before use to
avoid dereference a NULL pointer.
Change-Id: I05c38e180a448522d13d68369b77b45314eac227
CRs-Fixed: 2968584
Runtime put should be done in hif_pm_runtime_get when
return value of __hif_pm_runtime_get is negative. In
the issue scenario, the ret value will be set to 0 when
the return value of __hif_pm_runtime_get is positive.
The store operation for ret variable somehow did not take
effect and the if check for non-zero ret value to do
runtime put did go through. The return value to
dp_tx_hw_enqueue from hif_pm_runtime_get is the updated
ret value of 0. This will result in double runtime put
for a single runtime get.
Fix is to modify the ret variable check to negative
instead of non-zero to ensure runtime put happens
correctly.
Change-Id: Idc380a11c82b6d1acf7c750e7b93776ac9d6b4f2
CRs-Fixed: 2969879
Some latency stats need to do book keeping before interrupts are
enabled to avoid the counters being overwirtten by ISRs.
Also include latency stats in the case when rx is still pending.
Change-Id: Icff6f7876cd5db103693c6d38a396f1571b1d0aa
CRs-Fixed: 2965601
Four new CEs are introduced in QCN9224. Update MSI mapping
for 16 CEs in QCN9224.
Change-Id: I781e2b42453a4ec4f31f4076be1f5813d3637eff
CRs-Fixed: 2969994
FW is not setting up any context for CE5 but host is still
configuring the dest and status ring for CE5. This can
result in CE5 HW to write to MSI iova address when PCIe is
in low power state.
Fix is to disable MSI intr configuration for CE5 on
Lithium based targets.
Change-Id: I964305ad1258d41d7afe6422f87286904c0a6739
CRs-Fixed: 2954723
Select window failed sometimes, then following register writing by offset
leaded to NOC error.
PCIe local register space is mapped to BAR0 lower address, don't need
select window when write wake up umac register.
Add read back to confirm select window register writing passed through.
Change-Id: Iaa5359722e9b7a3434efd1a819a951ce6c8d3f4f
CRs-Fixed: 2952127
As per current design, in failure path of hdd_wlan_start_modules,
mem_free of hif_ext_group is done (in cds_dp_close) before
free_irq (in hdd_hif_close), during next hdd_wlan_start_modules,
request_irq adds new handler entry to the list in irq_desc, this
leads to a crash on accessing older stale entry from irq handler,
so adding a bus_ops hif_grp_irq_deconfigure to free ext grp IRQs.
Change-Id: I4d0a2bee1fabee388cea8a85226fae641165a8d5
CRs-Fixed: 2949400
Add HI_TASKLET support for CE, to improve priority
of CE tasklet higher than softirq, since CPU hogging
caused by RT thread.
Change-Id: I88fe8c048e908b9780745bb26b177acd2baf6a5c
CRs-Fixed: 2948946
pfrm_request_irq() calls kmem_cache_alloc() which
needs to be called in a non-atomic context since
it can sleep.
The current call to pfrm_request_irq() is done
within a spinlock which disables preemption and
leads to sleep in an atomic context.
Avoid calling pfrm_request_irq() within atomic
context
CRs-Fixed: 2913515
Change-Id: Ic2b0a23360d4d2b753658499343f72bfb67ad82d
In wlan suspend and resume cases it is seen that group
irqs are getting disabled multiple times without getting
enabled which is causing irqs to be disabled permenantly.
Track for unbalanced disabling/enabling group irqs which
helps to root cause the issue.
Change-Id: Ic1ef637c317f04b3299f17f19208df11ece3c013
CRs-Fixed: 2939809
Provide multiple combinations to configure the msi interrupts
of DP and CE based on the number of MSIs available in the platform.
Number of MSIs used for CE and DP can be changed by modifying the
MSI assignment table in platform driver. Best possible mask for that
MSI is automatically chosen based on predetermined settings.
Change-Id: I02b44fb033631d69d97f2d8d2d3f698541d37aad
Even though HP/TP updates are posted writes at CPU level, they
are getting blocked until soc comes out retention which is hogging
CPU.
To avoid this if EP is in low power state update HP/TP writes from
delayed work context. In delayed work vote for EP awake wait till it
comes out low power state and then proceed to HP/TP update.
Change-Id: I61d5795f58f25f850b5a9ad4d30e3181dba23713
CRs-Fixed: 2913495
When CE tasklets and NET_RX gets scheduled on same CPU,
NET_RX is throttling CE tasklet resulting WMI timeouts.
To avoid this affine CE irqs to gold cores, so that CE
tasklets will get enough CPU time.
Change-Id: Ided81a0565958aca6611eba911824c3485eca472
CRs-Fixed: 2933335
To avoid excessive logging, we whould not logs RTPM lock init and
deinit to the console. Thus, change the log level to debug.
Change-Id: Ib11045fe50f729b0580284fa913da48d3a59b323
CRs-Fixed: 2927959
The hw_index reading from the DDR by the RRI feature might be not
updated in time which might cause the excessive logging in the dmesg.
Change-Id: Ic9c3648b032ba59a6b7f92d8c27b63cb6a650381
CRs-Fixed: 2919867
Runtime PM for HTC layer has multiple cases of GET/PUT operations.
Adding runtime PM stats for HTC layer, this helps in debugging
RTPM GET/PUT out of sync issues.
Change-Id: Ib27efd73dce0bb5bd3ff030bd7ae1bc833f29610
CRs-Fixed: 2923250
Currently, as part of device suspend, EXT GRP IRQs are disabled.
disable_irq_nosync() which is currently being used to disable
interrupts will not wait for pending IRQs to completion. With this
API, there is a chance where IRQ handler can be executed after the
device suspend. Use disable_irq() instead so that pending IRQs will
be completed before returing from disable_irq().
CRs-Fixed: 2904518
Change-Id: Ib9acabe89b0337add82918be24b4782a6b125d05
DHCP packet is received in the IPA exception path when
system is suspending. As part of DHCP packet processing,
WMI_PEER_SET_PARAM_CMDID is sent to FW after WOW is
enabled resulting in self recovery getting triggered by
host.
Fix is to do an explicit system wakeup if a WMI command
has to be sent post WOW enablement.
Change-Id: If1904a4fe5c861deed1b35071be10cb8cc8d6407
CRs-Fixed: 2890913
In epping mode, the host ce count is not set correctly. And
then host will receive interrupt with incorrect ce id which
will trigger watchdog bite. Set the correct host ce count
and this issue can be fixed.
Change-Id: Ia91534fcfd1265e96f39ffd961ad794db3a4748a
CRs-Fixed: 2901231
When sending BE stream in epping mode, it fails when writing
registers of CE3 because the addr is not defined. Add this addr
to support epping mode data transfer.
Change-Id: I0d01cbee889c272b35a02bd1aca47f341f1edd2e
CRs-Fixed: 2901231
This feature is used to detect CE tasklet scheduling delay
and credit response delay issues.
Change-Id: I9a8fcb425edd5cf96fae5f6cd3bfc7f51172c814
CRs-Fixed: 2874874
Any update to the SRNG TP/HP when the device is in low power
state would result in system errors. It is recommended to disable
EXT grp irqs and drain TXRX before sending power save enter command
to the FW. This will ensure that no interrupts are received while
in power save mode and as a result there wont be any HP/TP updates.
Change-Id: Ibf952bbc2c6d13fb3e4ca6b4845bc9cc887fa694
CRs-Fixed: 2883135
In Moselle, currently CE interrupts are not disabled from apps
side during ipci bus suspend, so adding changes to disable all
the CE interrupts except wake_irq during bus suspend and do the
symmetric inverse operation during bus resume, also drain all
the pending FW diag logs from copy engine.
Change-Id: Ib54fc6660fd81aff18787b0b699f3a6cd2d7803d
CRs-Fixed: 2879752
Need to protect prevent_suspend_list by runtime_lock.
Issue happens when
1 printing lock0 of prevent_suspend_list in thread0
2 thread0 scheduled out and lock0 is released.
3 return back to thread0, it will using lock0 pointer
to check next lock, then issue happens.
Fix is adding runtime_lock to protect.
Change-Id: I7182651e445cf5008dba73e15b2c261cc125577f
CRs-Fixed: 2883052
Enable force wake recipe feature DEVICE_FORCE_WAKE_ENABLE
and disable the generic shadow register write feature
GENERIC_SHADOW_REGISTER_ACCESS_ENABLE.
Force wake recipe will be used to write to the REO remap
control registers by waking up the UMAC instead of using
shadow register writes.
Assert soc wake reg and poll on the scratch reg to check
if UMAC is awake.
Enable HIF_REG_WINDOW_SUPPORT to enable windowed reg
read/write in HIF layer.
Change-Id: Ib696e27e19a07c0084c097b95b7780b56e643c8b
CRs-Fixed: 2850590
When hif_force_wake_request is called from non interrupt context
use msleep to avoid mdelay since it is busy wait function.
Change-Id: Icda50e9d18b64369128a4f669ca1259931e5194a
CRs-Fixed: 2883178
Add delayed SRNG register writes support for Tx Ring, also add
dedicated workqueue to do the delayed Tx SRNG register writes.
Change-Id: I8dd157d341f3035e988804eab50d1ca681ab789b
CRs-Fixed: 2868989
On one-msi platform, when some ce tasklet execute, other srng such
as reo generate the interrupt, the ce interrupt handler can also be
called and then schedule the ce tasklet, if the running ce tasklet
intend to re-schedule itself due to the rx pending, obviously will
fail, then ce active tasklet count leaked.
Decrease the ce active tasklet count if failed to re-schedule when ce
rx pending.
Change-Id: I36c1c6c007735e192bee5af12aab674ee8324ca9
CRs-Fixed: 2830443
Set proper error code when ce_state creation fails. Sending success from
here results in inconsistent state of CE data structures resulting in
invalid access. Send failure as return so that proper handling is done
by the caller.
CRs-Fixed: 2855116
Change-Id: I9c063760656a8125e627aaa62b309a2bb4c0ac6f
