Implement hal_rx_get_mpdu_sequence_control_valid
API based on the chipset as
the macro to retrieve sequence control valid
value is chipset dependent.
Change-Id: I01a006094d0330060e9ff1a91200c48c2426f38d
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr4 API based
on the chipset as the macro to retrieve
addr4 value is chipset dependent.
Change-Id: Ie35d01de1619a8ab540bb1b2019a15b436efb7d4
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr3 API
based on the chipset as
the macro to retrieve addr3 value is
chipset dependent.
Change-Id: I3983599b656e82170de5905c08daee3ec164e7a0
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr2 API
based on the chipset as
the macro to retrieve addr2 value is
chipset dependent.
Change-Id: I4026db892d4f2f41db72c50f780ba898b8a17fa7
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr1 API
based on the chipset as the macro to
retrieve addr1 value is
chipset dependent.
Change-Id: I7ed88f2243d397c9d605a08d3b93e17f0004c63d
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_frame_control_valid API
based on the chipset as the macro to retrieve
frame control valid value is chipset dependent.
Change-Id: I49d16ae44b2e9567ff746d2088058f0c1025ea40
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_fr_ds API
based on the chipset as the macro to
retrieve for_ds value is chipset
dependent.
Change-Id: I6d41d02ac50cae752567d98645f0447cc122a84f
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_to_ds API based
on the chipset as the macro to retrieve
to_ds bit value is chipset dependent.
Change-Id: I36d9d14e226bcc604b91d8aecbe52836c5a12272
CRs-Fixed: 2522133
Implement hal_rx_mpdu_start_sw_peer_id API
based on the chipset as the macro to retrieve
sw_peer_id value is chipset dependent.
Change-Id: Ifebaf2430731f5e0593dde4789d721e9fe7ce7c1
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_mac_ad4_valid API
based on the chipset as the macro to retrieve
mac_ad4 value is chipset dependent.
Change-Id: I9d7cc90e798d4f0775e915fe6edcb1a1f5129490
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_last_msdu_get API
based on the chipset as the macro to retrieve
last_msdu value is chipset dependent.
Change-Id: I561c28a49062d7b650e68c5a4ce4da0183be34d6
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_dat API based on
the chipset as the macro to retrieve da_is_valid
value is chipset dependent.
Change-Id: I79f06eaa2576e7516c21f963b2c149aac7f62c64
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_first_msdu_get API
based on the chipset as the macro to retrieve
first_msdu value is chipset dependent.
Change-Id: Iea325159a0349c45a249c1ae113664c41a54b0f1
CRs-Fixed: 2522133
Implement hal_rx_print_pn API based on the
chipset as the macro to retrieve
pn value is chipset dependent.
Change-Id: Id9d0d3b34a5f6a09fe5903e1d24bb0a59205174b
CRs-Fixed: 2522133
Implement hal_rx_encryption_info API based
on the chipset as the macro to retrieve
sa_idx value is chipset dependent.
Change-Id: I0c48800dfa5628898c53f7a9271e517b6bfa3da7
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_l3_hdr_padding_get API
based on the chipset as the macro to retrieve
sa_idx value is chipset dependent.
Change-Id: Ice1fc2d70e339dc1d80fa6f34f37c5a7aa074be5
CRs-Fixed: 2522133
Implement hal_rx_desc_is_first_msdu API
based on the chipset as the macro to
retrieve first_msdu bit value is chipset
dependent.
Change-Id: I8e8a3aceb225b591b96e6f8453ffbebf1f78e529
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_sa_idx API
based on the chipset as the macro to
retrieve sa_idx value is chipset
dependent.
Change-Id: Ib874520be9e7ad778c2a9a3c415e5c3047450b31
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_sa_is_valid_get API
based on the chipset as the macro to retrieve
sa_idx valid bit is chipset dependent.
Change-Id: I8bcb7030554331922ed12ea9da3ef51cd64b5c40
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_da_is_mcbc_get based
on the chipset as the macro to retrieve
mcbc value is chipset dependent.
Change-Id: I860d259515c31345501080577d7a34beb97e5f60
CRs-Fixed: 2522133
Implement hal_rx_get_rx_fragment_number
based on the chipset as the macro
HAL_RX_MPDU_GET_SEQUENCE_NUMBER is
chipset specific.
Change-Id: I967190fa3a55d45f46760f58eab5007bf5fa908f
CRs-Fixed: 2522133
added stats counter to check invalid release reason other than
FW and TQM in tx completion path.
added assert to make sure host is not releasing descriptors with NULL
address.
Change-Id: I3a30bd0f0c3954ed6435489d9b21f16201d1b840
Tags are programmed using wlanconfig commands. Rx IPv4/v6
TCP/UDP packets matching a 5-tuple are tagged using HawkeyeV2 hardware.
Tags are populated in the skb->cb in the REO/exception/monitor data
path and sent to upper stack
CRs-Fixed: 2502311
Change-Id: I7c999e75fab43b6ecb6f9d9fd4b0351f0b9cfda8
Add code to replace usage of void pointers from
HAL layer and instead use appropriate opaque pointers
Change-Id: Id950bd9130a99014305738937aed736cf0144aca
CRs-Fixed: 2487250
Add code to remove void pointer usage for hal_srng
and use opaque pointer dp_hal_ring_t instead.
Change-Id: I6907f7376d7fe3c9180b8795bd96f49fead2ec64
CRs-Fixed: 2484404
Make change to remove usage of void pointers for
ring descriptors and instead use a opaque pointer
dp_ring_desc_t.
Change-Id: Ia1e9a3da9eaa3cccf297b2135b52a72f2fe21431
CRs-Fixed: 2484409
Add code to remove void pointer usage for hal_soc
and introduce opaque pointer to be used intead of void
from dp layer into hal layer
Change-Id: Ia38571174c6ed79558d0f0c9cd1a0f4afaa66483
CRs-Fixed: 2480857
Add support to configure any HAL SRNG descriptor to
be allocated from cached memory area. This is to
optimize of CPU cycles spent on uncached
memory accesses. Also added prefetch of cached
descriptors
Change-Id: I2544e8596d48e2f5549bf687a764c16d73397545
CRs-fixed: 2267945
In case of duplicated rx descriptors from hardware,
it will hit issues in __dma_inv_range(), __qdf_nbuf_unmap_single.
Detect the duplicates, skip processing them, drop the mpdu.
CRs-Fixed: 2413816
Change-Id: I7efd4b0c1bda5578578927bb22fe9d487758897d
earlier we were extracting the tid from the rx tlvs, this
was in the last cache line of the 384 byte tlv. we are
extracting various fields from REO descriptor, now we are
also getting tid from the descriptor to avoid accessing
the last cache line of rx TLV there by avoiding one
cache miss per packet.
Change-Id: I1f4f12dca402604692ea374599add6763d68ab01
CRs-fixed: 2449706
With this feature, using appropriate commands, link layer, network layer,
transport layer and some of the application protocols can be tagged with
the user provided tag values for easier identification of protocols. The
supported protocols today are as follows.
ARP, DHCPv4, DHCPv6, DNS over TCP (v4), DNS over TCP (v6), DNS over UDP
(v4), DNS over UDP (v6), ICMPv4, ICMPv6, TCPv4, TCPv6, UDPv4,
UDPv6, IPv4, IPv6, EAP.
Receive packets are tagged by hardware. Tags are applied after the first
matching rule. Hence it is recommended that the rules are
programmed in such a way that tags are configured from application layer
to data link layer to get expected results.
Change-Id: Ibdc2bd2b78234f482074955e89fb93f05988eaca
On low memory platform rx_pkt_header tlv is not subscribed to get a
savings of 128bytes in skb. This is required to reduce the skb size from
4K to 2K on 32-bit platforms. Use HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
message to unsubscribe rx_pkt_header tlv for rxdma ring.
Change-Id: Ie684f1ca1de9c824a869b4e13fd0ee1d068004e7
CRs-Fixed: 2408424
Do not process RX packet header TLV for low memory config profile.
Also, drop decapped frames in invalid peer processing function.
Change-Id: Ifc7721bb25d85c7e277bebf4b962d2f1bfea150c
CRs-Fixed: 2395508
Some of the print messages in HAL module come very excessively.
Use hal_verbose_debug() API to print them.
CRs-fixed: 2405028
Change-Id: I4b4754af65c00edb571de898527026b6183ef15f
once in a while the HW is sending a descriptor which
is already processed by host. This can be a potential HW
issue, as a WAR we are not processing such duplicate descriptors
instead increment a counter and continue with next descriptor.
Change-Id: I6c9bc6a9fb4705b42284171a32855411aa5dd73f
CRs-Fixed: 2338543
Currently we are printing one single big print to dump the RX TLVS. This
is causing truncation at the QDF_TRACE level, which can accommodate only
512 bytes or so right now. Split the RX TLV print, so that it can fit
int the QDF buffer.
CRs-Fixed: 2370080
Change-Id: I1385ab0dfe2a52e34132487ac55973e291d84db5
Functions hal_rx_wbm_err_info_get, hal_tx_comp_get_release_reason,
hal_rx_dump_mpdu_start_tlv uses some hardware macros directly and the
value differs between qca8074v1 and qca8074v2 targets.
Move these functions to generic api file and compile it per target.
Change-Id: Ib78fb6e69238577aac64da3f60f38a72cee316b0
1. Disable host processing of REO2SW4 when IPA is enabled.
2. Change buffer memory location provide to IPA TX transfer
ring from consistent to non-consistent memory.
Change-Id: Ibb62d9faf5dc9adb5ee8a2e113d10a2912269cbd
CRs-Fixed: 2315889
Some of the macro names defined in qca8074v1, are defined with
a slightly different name in qca8074v2, and few macros have the
same name in both headers but are defined with different values.
Fixed the same.
Change-Id: I5e948baf5326d1d8fdfa2bd7ee8aa072c710d17c
