qcacmn: [1/2] Support both qca8074v1 and qca8074v2 from hal

Some of the macro names defined in qca8074v1, are defined with
a slightly different name in qca8074v2, and few macros have the
same name in both headers but are defined with different values.
Fixed the same.

Change-Id: I5e948baf5326d1d8fdfa2bd7ee8aa072c710d17c

hal/wifi3.0/hal_api.h

@@ -1,30 +1,19 @@
 /*
  * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 #ifndef _HAL_API_H_
@@ -970,25 +959,6 @@ static inline uint32_t hal_idle_list_num_scatter_bufs(void *hal_soc,
 	return num_scatter_bufs;
 }
 
-/**
- * hal_idle_scatter_buf_setup - Setup scattered idle list using the buffer list
- * provided
- *
- * @hal_soc: Opaque HAL SOC handle
- * @idle_scatter_bufs_base_paddr: Array of physical base addresses
- * @idle_scatter_bufs_base_vaddr: Array of virtual base addresses
- * @num_scatter_bufs: Number of scatter buffers in the above lists
- * @scatter_buf_size: Size of each scatter buffer
- * @last_buf_end_offset: Offset to the last entry
- * @num_entries: Total entries of all scatter bufs
- *
- */
-extern void hal_setup_link_idle_list(void *hal_soc,
-	qdf_dma_addr_t scatter_bufs_base_paddr[],
-	void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs,
-	uint32_t scatter_buf_size, uint32_t last_buf_end_offset,
-	uint32_t num_entries);
-
 /* REO parameters to be passed to hal_reo_setup */
 struct hal_reo_params {
 	/** rx hash steering enabled or disabled */
@@ -1003,14 +973,6 @@ struct hal_reo_params {
 	uint8_t padding[3];
 };
 
-/**
- * hal_reo_setup - Initialize HW REO block
- *
- * @hal_soc: Opaque HAL SOC handle
- * @reo_params: parameters needed by HAL for REO config
- */
-extern void hal_reo_setup(void *hal_soc,
-	 struct hal_reo_params *reo_params);
 
 enum hal_pn_type {
 	HAL_PN_NONE,
@@ -1128,7 +1090,6 @@ uint32_t hal_get_target_type(struct hal_soc *hal);
  */
 void hal_get_ba_aging_timeout(void *hal_soc, uint8_t ac,
 			      uint32_t *value);
-
 /**
  * hal_set_aging_timeout - Set BA aging timeout
  *
@@ -1138,5 +1099,69 @@ void hal_get_ba_aging_timeout(void *hal_soc, uint8_t ac,
  */
 void hal_set_ba_aging_timeout(void *hal_soc, uint8_t ac,
 			      uint32_t value);
+/**
+ * hal_srng_dst_hw_init - Private function to initialize SRNG
+ * destination ring HW
+ * @hal_soc: HAL SOC handle
+ * @srng: SRNG ring pointer
+ */
+static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
+	struct hal_srng *srng)
+{
+	hal->ops->hal_srng_dst_hw_init(hal, srng);
+}
 
+/**
+ * hal_srng_src_hw_init - Private function to initialize SRNG
+ * source ring HW
+ * @hal_soc: HAL SOC handle
+ * @srng: SRNG ring pointer
+ */
+static inline void hal_srng_src_hw_init(struct hal_soc *hal,
+	struct hal_srng *srng)
+{
+	hal->ops->hal_srng_src_hw_init(hal, srng);
+}
+
+/**
+ * hal_reo_setup - Initialize HW REO block
+ *
+ * @hal_soc: Opaque HAL SOC handle
+ * @reo_params: parameters needed by HAL for REO config
+ */
+static inline void hal_reo_setup(void *halsoc,
+	 void *reoparams)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)halsoc;
+
+	hal_soc->ops->hal_reo_setup(halsoc, reoparams);
+}
+
+/**
+ * hal_setup_link_idle_list - Setup scattered idle list using the
+ * buffer list provided
+ *
+ * @hal_soc: Opaque HAL SOC handle
+ * @scatter_bufs_base_paddr: Array of physical base addresses
+ * @scatter_bufs_base_vaddr: Array of virtual base addresses
+ * @num_scatter_bufs: Number of scatter buffers in the above lists
+ * @scatter_buf_size: Size of each scatter buffer
+ * @last_buf_end_offset: Offset to the last entry
+ * @num_entries: Total entries of all scatter bufs
+ *
+ */
+static inline void hal_setup_link_idle_list(void *halsoc,
+	qdf_dma_addr_t scatter_bufs_base_paddr[],
+	void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs,
+	uint32_t scatter_buf_size, uint32_t last_buf_end_offset,
+	uint32_t num_entries)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)halsoc;
+
+	hal_soc->ops->hal_setup_link_idle_list(halsoc, scatter_bufs_base_paddr,
+			scatter_bufs_base_vaddr, num_scatter_bufs,
+			scatter_buf_size, last_buf_end_offset,
+			num_entries);
+
+}
 #endif /* _HAL_APIH_ */

hal/wifi3.0/hal_api_mon.h

@@ -487,7 +487,15 @@ hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
 			HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
 }
 
-static void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
+/**
+ * hal_rx_proc_phyrx_other_receive_info_tlv()
+ *				    - process other receive info TLV
+ * @rx_tlv_hdr: pointer to TLV header
+ * @ppdu_info: pointer to ppdu_info
+ *
+ * Return: None
+ */
+static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
 						     void *rx_tlv_hdr,
 						     struct hal_rx_ppdu_info
 						     *ppdu_info)
@@ -504,884 +512,11 @@ static void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
  * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  */
 static inline uint32_t
-hal_rx_status_get_tlv_info(void *rx_tlv_hdr, struct hal_rx_ppdu_info *ppdu_info,
-			   struct hal_soc *hal)
+hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info,
+			   struct hal_soc *hal_soc)
 {
-	uint32_t tlv_tag, user_id, tlv_len, value;
-	uint8_t group_id = 0;
-	uint8_t he_dcm = 0;
-	uint8_t he_stbc = 0;
-	uint16_t he_gi = 0;
-	uint16_t he_ltf = 0;
-	void *rx_tlv;
-	bool unhandled = false;
-	bool is_no_payload_ppdu = false;
-
-	tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
-	user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
-	tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
-
-	rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
-	switch (tlv_tag) {
-
-	case WIFIRX_PPDU_START_E:
-		ppdu_info->com_info.ppdu_id =
-			HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
-				PHY_PPDU_ID);
-		/* channel number is set in PHY meta data */
-		ppdu_info->rx_status.chan_num =
-			HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
-				SW_PHY_META_DATA);
-		ppdu_info->com_info.ppdu_timestamp =
-			HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
-				PPDU_START_TIMESTAMP);
-		ppdu_info->rx_status.ppdu_timestamp =
-			ppdu_info->com_info.ppdu_timestamp;
-		ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
-		break;
-
-	case WIFIRX_PPDU_START_USER_INFO_E:
-		break;
-
-	case WIFIRX_PPDU_END_E:
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"[%s][%d] ppdu_end_e len=%d",
-				__func__, __LINE__, tlv_len);
-		/* This is followed by sub-TLVs of PPDU_END */
-		ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
-		break;
-
-	case WIFIRXPCU_PPDU_END_INFO_E:
-		ppdu_info->rx_status.tsft =
-			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
-				WB_TIMESTAMP_UPPER_32);
-		ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
-			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
-				WB_TIMESTAMP_LOWER_32);
-		ppdu_info->rx_status.duration =
-			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_8,
-				RX_PPDU_DURATION);
-		break;
-
-	case WIFIRX_PPDU_END_USER_STATS_E:
-	{
-		unsigned long tid = 0;
-		uint16_t seq = 0;
-
-		ppdu_info->rx_status.ast_index =
-				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
-						AST_INDEX);
-
-		tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
-				RECEIVED_QOS_DATA_TID_BITMAP);
-		ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8);
-
-		if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
-			ppdu_info->rx_status.tid = HAL_TID_INVALID;
-
-		ppdu_info->rx_status.tcp_msdu_count =
-			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
-					TCP_MSDU_COUNT) +
-			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
-					TCP_ACK_MSDU_COUNT);
-		ppdu_info->rx_status.udp_msdu_count =
-			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
-						UDP_MSDU_COUNT);
-		ppdu_info->rx_status.other_msdu_count =
-			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
-					OTHER_MSDU_COUNT);
-
-		ppdu_info->rx_status.frame_control_info_valid =
-			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
-					DATA_SEQUENCE_CONTROL_INFO_VALID);
-
-		seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
-					FIRST_DATA_SEQ_CTRL);
-		if (ppdu_info->rx_status.frame_control_info_valid)
-			ppdu_info->rx_status.first_data_seq_ctrl = seq;
-
-		ppdu_info->rx_status.preamble_type =
-			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
-						HT_CONTROL_FIELD_PKT_TYPE);
-		switch (ppdu_info->rx_status.preamble_type) {
-		case HAL_RX_PKT_TYPE_11N:
-			ppdu_info->rx_status.ht_flags = 1;
-			ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
-			break;
-		case HAL_RX_PKT_TYPE_11AC:
-			ppdu_info->rx_status.vht_flags = 1;
-			break;
-		case HAL_RX_PKT_TYPE_11AX:
-			ppdu_info->rx_status.he_flags = 1;
-			break;
-		default:
-			break;
-		}
-
-		ppdu_info->com_info.mpdu_cnt_fcs_ok =
-			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
-					MPDU_CNT_FCS_OK);
-		ppdu_info->com_info.mpdu_cnt_fcs_err =
-			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
-					MPDU_CNT_FCS_ERR);
-		if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
-			ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
-			ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
-		else
-			ppdu_info->rx_status.rs_flags &=
-				(~IEEE80211_AMPDU_FLAG);
-		break;
-	}
-
-	case WIFIRX_PPDU_END_USER_STATS_EXT_E:
-		break;
-
-	case WIFIRX_PPDU_END_STATUS_DONE_E:
-	{
-		if (is_no_payload_ppdu)
-			return HAL_TLV_STATUS_PPDU_NON_STD_DONE;
-		else
-			return HAL_TLV_STATUS_PPDU_DONE;
-	}
-
-	case WIFIDUMMY_E:
-		return HAL_TLV_STATUS_BUF_DONE;
-
-	case WIFIPHYRX_HT_SIG_E:
-	{
-		uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
-				HAL_RX_OFFSET(PHYRX_HT_SIG_0,
-				HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
-		value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
-				FEC_CODING);
-		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
-			1 : 0;
-		ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
-				HT_SIG_INFO_0, MCS);
-		ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
-				HT_SIG_INFO_0, CBW);
-		ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
-				HT_SIG_INFO_1, SHORT_GI);
-		break;
-	}
-
-	case WIFIPHYRX_L_SIG_B_E:
-	{
-		uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
-				HAL_RX_OFFSET(PHYRX_L_SIG_B_0,
-				L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
-
-		value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
-		ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
-		switch (value) {
-		case 1:
-			ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
-			break;
-		case 2:
-			ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
-			break;
-		case 3:
-			ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
-			break;
-		case 4:
-			ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
-			break;
-		case 5:
-			ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
-			break;
-		case 6:
-			ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
-			break;
-		case 7:
-			ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
-			break;
-		default:
-			break;
-		}
-		ppdu_info->rx_status.cck_flag = 1;
-	break;
-	}
-
-	case WIFIPHYRX_L_SIG_A_E:
-	{
-		uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
-				HAL_RX_OFFSET(PHYRX_L_SIG_A_0,
-				L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
-
-		value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
-		ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
-		switch (value) {
-		case 8:
-			ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
-			break;
-		case 9:
-			ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
-			break;
-		case 10:
-			ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
-			break;
-		case 11:
-			ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
-			break;
-		case 12:
-			ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
-			break;
-		case 13:
-			ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
-			break;
-		case 14:
-			ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
-			break;
-		case 15:
-			ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
-			break;
-		default:
-			break;
-		}
-		ppdu_info->rx_status.ofdm_flag = 1;
-	break;
-	}
-
-	case WIFIPHYRX_VHT_SIG_A_E:
-	{
-		uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
-				HAL_RX_OFFSET(PHYRX_VHT_SIG_A_0,
-				VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
-
-		value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
-				SU_MU_CODING);
-		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
-			1 : 0;
-		group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID);
-		ppdu_info->rx_status.vht_flag_values5 = group_id;
-		ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
-				VHT_SIG_A_INFO_1, MCS);
-		ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
-				VHT_SIG_A_INFO_1, GI_SETTING);
-
-		switch (hal->target_type) {
-		case TARGET_TYPE_QCA8074:
-		case TARGET_TYPE_QCA8074V2:
-			ppdu_info->rx_status.is_stbc =
-				HAL_RX_GET(vht_sig_a_info,
-					   VHT_SIG_A_INFO_0, STBC);
-			value =  HAL_RX_GET(vht_sig_a_info,
-					    VHT_SIG_A_INFO_0, N_STS);
-			if (ppdu_info->rx_status.is_stbc && (value > 0))
-				value = ((value + 1) >> 1) - 1;
-			ppdu_info->rx_status.nss =
-				((value & VHT_SIG_SU_NSS_MASK) + 1);
-
-			break;
-		case TARGET_TYPE_QCA6290:
-#if !defined(QCA_WIFI_QCA6290_11AX)
-			ppdu_info->rx_status.is_stbc =
-				HAL_RX_GET(vht_sig_a_info,
-					   VHT_SIG_A_INFO_0, STBC);
-			value =  HAL_RX_GET(vht_sig_a_info,
-					    VHT_SIG_A_INFO_0, N_STS);
-			if (ppdu_info->rx_status.is_stbc && (value > 0))
-				value = ((value + 1) >> 1) - 1;
-			ppdu_info->rx_status.nss =
-				((value & VHT_SIG_SU_NSS_MASK) + 1);
-#else
-			ppdu_info->rx_status.nss = 0;
-#endif
-			break;
-#ifdef QCA_WIFI_QCA6390
-		case TARGET_TYPE_QCA6390:
-			ppdu_info->rx_status.nss = 0;
-			break;
-#endif
-		default:
-			break;
-		}
-		ppdu_info->rx_status.vht_flag_values3[0] =
-				(((ppdu_info->rx_status.mcs) << 4)
-				| ppdu_info->rx_status.nss);
-		ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
-				VHT_SIG_A_INFO_0, BANDWIDTH);
-		ppdu_info->rx_status.vht_flag_values2 =
-			ppdu_info->rx_status.bw;
-		ppdu_info->rx_status.vht_flag_values4 =
-			HAL_RX_GET(vht_sig_a_info,
-				  VHT_SIG_A_INFO_1, SU_MU_CODING);
-
-		ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
-				VHT_SIG_A_INFO_1, BEAMFORMED);
-
-		break;
-	}
-	case WIFIPHYRX_HE_SIG_A_SU_E:
-	{
-		uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
-			HAL_RX_OFFSET(PHYRX_HE_SIG_A_SU_0,
-			HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
-		ppdu_info->rx_status.he_flags = 1;
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
-			FORMAT_INDICATION);
-		if (value == 0) {
-			ppdu_info->rx_status.he_data1 =
-				QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
-		} else {
-			 ppdu_info->rx_status.he_data1 =
-				 QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
-		}
-
-		/* data1 */
-		ppdu_info->rx_status.he_data1 |=
-			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
-			QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
-			QDF_MON_STATUS_HE_DL_UL_KNOWN |
-			QDF_MON_STATUS_HE_MCS_KNOWN |
-			QDF_MON_STATUS_HE_DCM_KNOWN |
-			QDF_MON_STATUS_HE_CODING_KNOWN |
-			QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
-			QDF_MON_STATUS_HE_STBC_KNOWN |
-			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
-			QDF_MON_STATUS_HE_DOPPLER_KNOWN;
-
-		/* data2 */
-		ppdu_info->rx_status.he_data2 =
-			QDF_MON_STATUS_HE_GI_KNOWN;
-		ppdu_info->rx_status.he_data2 |=
-			QDF_MON_STATUS_TXBF_KNOWN |
-			QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
-			QDF_MON_STATUS_TXOP_KNOWN |
-			QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
-			QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
-			QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
-
-		/* data3 */
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
-		ppdu_info->rx_status.he_data3 = value;
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
-		value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
-		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
-		ppdu_info->rx_status.mcs = value;
-		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_0, DCM);
-		he_dcm = value;
-		value = value << QDF_MON_STATUS_DCM_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_1, CODING);
-		value = value << QDF_MON_STATUS_CODING_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_1,
-				LDPC_EXTRA_SYMBOL);
-		value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_1, STBC);
-		he_stbc = value;
-		value = value << QDF_MON_STATUS_STBC_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		/* data4 */
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
-							SPATIAL_REUSE);
-		ppdu_info->rx_status.he_data4 = value;
-
-		/* data5 */
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
-		ppdu_info->rx_status.he_data5 = value;
-		ppdu_info->rx_status.bw = value;
-		value = HAL_RX_GET(he_sig_a_su_info,
-				HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
-		switch (value) {
-		case 0:
-				he_gi = HE_GI_0_8;
-				he_ltf = HE_LTF_1_X;
-				break;
-		case 1:
-				he_gi = HE_GI_0_8;
-				he_ltf = HE_LTF_2_X;
-				break;
-		case 2:
-				he_gi = HE_GI_1_6;
-				he_ltf = HE_LTF_2_X;
-				break;
-		case 3:
-				if (he_dcm && he_stbc) {
-					he_gi = HE_GI_0_8;
-					he_ltf = HE_LTF_4_X;
-				} else {
-					he_gi = HE_GI_3_2;
-					he_ltf = HE_LTF_4_X;
-				}
-				break;
-		}
-		ppdu_info->rx_status.sgi = he_gi;
-		value = he_gi << QDF_MON_STATUS_GI_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-		value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
-		value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
-		ppdu_info->rx_status.he_data5 |= value;
-
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
-							PACKET_EXTENSION_A_FACTOR);
-		value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
-		value = value << QDF_MON_STATUS_TXBF_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
-							PACKET_EXTENSION_PE_DISAMBIGUITY);
-		value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-
-		/* data6 */
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
-		value++;
-		ppdu_info->rx_status.nss = value;
-		ppdu_info->rx_status.he_data6 = value;
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
-							DOPPLER_INDICATION);
-		value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
-		ppdu_info->rx_status.he_data6 |= value;
-		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
-							TXOP_DURATION);
-		value = value << QDF_MON_STATUS_TXOP_SHIFT;
-		ppdu_info->rx_status.he_data6 |= value;
-
-		ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
-					HE_SIG_A_SU_INFO_1, TXBF);
-		break;
-	}
-	case WIFIPHYRX_HE_SIG_A_MU_DL_E:
-	{
-		uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
-			HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_DL_0,
-			HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
-
-		ppdu_info->rx_status.he_mu_flags = 1;
-
-		/* HE Flags */
-		/*data1*/
-		ppdu_info->rx_status.he_data1 =
-					QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
-		ppdu_info->rx_status.he_data1 |=
-			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
-			QDF_MON_STATUS_HE_DL_UL_KNOWN |
-			QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
-			QDF_MON_STATUS_HE_STBC_KNOWN |
-			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
-			QDF_MON_STATUS_HE_DOPPLER_KNOWN;
-
-		/* data2 */
-		ppdu_info->rx_status.he_data2 =
-			QDF_MON_STATUS_HE_GI_KNOWN;
-		ppdu_info->rx_status.he_data2 |=
-			QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
-			QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
-			QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
-			QDF_MON_STATUS_TXOP_KNOWN |
-			QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
-
-		/*data3*/
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
-		ppdu_info->rx_status.he_data3 = value;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
-		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_1,
-				LDPC_EXTRA_SYMBOL);
-		value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_1, STBC);
-		he_stbc = value;
-		value = value << QDF_MON_STATUS_STBC_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		/*data4*/
-		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
-							SPATIAL_REUSE);
-		ppdu_info->rx_status.he_data4 = value;
-
-		/*data5*/
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
-		ppdu_info->rx_status.he_data5 = value;
-		ppdu_info->rx_status.bw = value;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
-		switch (value) {
-		case 0:
-			he_gi = HE_GI_0_8;
-			he_ltf = HE_LTF_4_X;
-			break;
-		case 1:
-			he_gi = HE_GI_0_8;
-			he_ltf = HE_LTF_2_X;
-			break;
-		case 2:
-			he_gi = HE_GI_1_6;
-			he_ltf = HE_LTF_2_X;
-			break;
-		case 3:
-			he_gi = HE_GI_3_2;
-			he_ltf = HE_LTF_4_X;
-			break;
-		}
-		ppdu_info->rx_status.sgi = he_gi;
-		value = he_gi << QDF_MON_STATUS_GI_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-
-		value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				   HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS);
-		value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
-		ppdu_info->rx_status.he_data5 |= value;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
-				   PACKET_EXTENSION_A_FACTOR);
-		value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
-				   PACKET_EXTENSION_PE_DISAMBIGUITY);
-		value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-
-		/*data6*/
-		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
-							DOPPLER_INDICATION);
-		value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
-		ppdu_info->rx_status.he_data6 |= value;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
-							TXOP_DURATION);
-		value = value << QDF_MON_STATUS_TXOP_SHIFT;
-		ppdu_info->rx_status.he_data6 |= value;
-
-		/* HE-MU Flags */
-		/* HE-MU-flags1 */
-		ppdu_info->rx_status.he_flags1 =
-			QDF_MON_STATUS_SIG_B_MCS_KNOWN |
-			QDF_MON_STATUS_SIG_B_DCM_KNOWN |
-			QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
-			QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
-			QDF_MON_STATUS_RU_0_KNOWN;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
-		ppdu_info->rx_status.he_flags1 |= value;
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
-		value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
-		ppdu_info->rx_status.he_flags1 |= value;
-
-		/* HE-MU-flags2 */
-		ppdu_info->rx_status.he_flags2 =
-			QDF_MON_STATUS_BW_KNOWN;
-
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
-		ppdu_info->rx_status.he_flags2 |= value;
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
-		value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
-		ppdu_info->rx_status.he_flags2 |= value;
-		value = HAL_RX_GET(he_sig_a_mu_dl_info,
-				HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
-		value = value - 1;
-		value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
-		ppdu_info->rx_status.he_flags2 |= value;
-		break;
-	}
-	case WIFIPHYRX_HE_SIG_B1_MU_E:
-	{
-
-		uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
-			HAL_RX_OFFSET(PHYRX_HE_SIG_B1_MU_0,
-			HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
-
-		ppdu_info->rx_status.he_sig_b_common_known |=
-			QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
-		/* TODO: Check on the availability of other fields in
-		 * sig_b_common
-		 */
-
-		value = HAL_RX_GET(he_sig_b1_mu_info,
-				HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
-		ppdu_info->rx_status.he_RU[0] = value;
-		break;
-	}
-	case WIFIPHYRX_HE_SIG_B2_MU_E:
-	{
-		uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
-			HAL_RX_OFFSET(PHYRX_HE_SIG_B2_MU_0,
-			HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
-		/*
-		 * Not all "HE" fields can be updated from
-		 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
-		 * to populate rest of the "HE" fields for MU scenarios.
-		 */
-
-		/* HE-data1 */
-		ppdu_info->rx_status.he_data1 |=
-			QDF_MON_STATUS_HE_MCS_KNOWN |
-			QDF_MON_STATUS_HE_CODING_KNOWN;
-
-		/* HE-data2 */
-
-		/* HE-data3 */
-		value = HAL_RX_GET(he_sig_b2_mu_info,
-				HE_SIG_B2_MU_INFO_0, STA_MCS);
-		ppdu_info->rx_status.mcs = value;
-		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-
-		value = HAL_RX_GET(he_sig_b2_mu_info,
-				HE_SIG_B2_MU_INFO_0, STA_CODING);
-		value = value << QDF_MON_STATUS_CODING_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		/* HE-data4 */
-		value = HAL_RX_GET(he_sig_b2_mu_info,
-				HE_SIG_B2_MU_INFO_0, STA_ID);
-		value = value << QDF_MON_STATUS_STA_ID_SHIFT;
-		ppdu_info->rx_status.he_data4 |= value;
-
-		/* HE-data5 */
-
-		/* HE-data6 */
-		value = HAL_RX_GET(he_sig_b2_mu_info,
-				   HE_SIG_B2_MU_INFO_0, NSTS);
-		/* value n indicates n+1 spatial streams */
-		value++;
-		ppdu_info->rx_status.nss = value;
-		ppdu_info->rx_status.he_data6 |= value;
-
-		break;
-
-	}
-	case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
-	{
-		uint8_t *he_sig_b2_ofdma_info =
-		(uint8_t *)rx_tlv +
-		HAL_RX_OFFSET(PHYRX_HE_SIG_B2_OFDMA_0,
-		HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
-
-		/*
-		 * Not all "HE" fields can be updated from
-		 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
-		 * to populate rest of "HE" fields for MU OFDMA scenarios.
-		 */
-
-		/* HE-data1 */
-		ppdu_info->rx_status.he_data1 |=
-			QDF_MON_STATUS_HE_MCS_KNOWN |
-			QDF_MON_STATUS_HE_DCM_KNOWN |
-			QDF_MON_STATUS_HE_CODING_KNOWN;
-
-		/* HE-data2 */
-		ppdu_info->rx_status.he_data2 |=
-					QDF_MON_STATUS_TXBF_KNOWN;
-
-		/* HE-data3 */
-		value = HAL_RX_GET(he_sig_b2_ofdma_info,
-				HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
-		ppdu_info->rx_status.mcs = value;
-		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		value = HAL_RX_GET(he_sig_b2_ofdma_info,
-				HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
-		he_dcm = value;
-		value = value << QDF_MON_STATUS_DCM_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		value = HAL_RX_GET(he_sig_b2_ofdma_info,
-				HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
-		value = value << QDF_MON_STATUS_CODING_SHIFT;
-		ppdu_info->rx_status.he_data3 |= value;
-
-		/* HE-data4 */
-		value = HAL_RX_GET(he_sig_b2_ofdma_info,
-				HE_SIG_B2_OFDMA_INFO_0, STA_ID);
-		value = value << QDF_MON_STATUS_STA_ID_SHIFT;
-		ppdu_info->rx_status.he_data4 |= value;
-
-		/* HE-data5 */
-		value = HAL_RX_GET(he_sig_b2_ofdma_info,
-				   HE_SIG_B2_OFDMA_INFO_0, TXBF);
-		value = value << QDF_MON_STATUS_TXBF_SHIFT;
-		ppdu_info->rx_status.he_data5 |= value;
-
-		/* HE-data6 */
-		value = HAL_RX_GET(he_sig_b2_ofdma_info,
-				   HE_SIG_B2_OFDMA_INFO_0, NSTS);
-		/* value n indicates n+1 spatial streams */
-		value++;
-		ppdu_info->rx_status.nss = value;
-		ppdu_info->rx_status.he_data6 |= value;
-
-		break;
-	}
-	case WIFIPHYRX_RSSI_LEGACY_E:
-	{
-		uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
-			HAL_RX_OFFSET(PHYRX_RSSI_LEGACY_3,
-			RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS);
-
-		ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
-			PHYRX_RSSI_LEGACY_35, RSSI_COMB);
-		ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
-		ppdu_info->rx_status.he_re = 0;
-
-		ppdu_info->rx_status.reception_type = HAL_RX_GET(rx_tlv,
-				PHYRX_RSSI_LEGACY_0, RECEPTION_TYPE);
-
-		value = HAL_RX_GET(rssi_info_tlv,
-			RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"RSSI_PRI20_CHAIN0: %d", value);
-
-		value = HAL_RX_GET(rssi_info_tlv,
-			RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0);
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"RSSI_EXT20_CHAIN0: %d", value);
-
-		value = HAL_RX_GET(rssi_info_tlv,
-			RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0);
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"RSSI_EXT40_LOW20_CHAIN0: %d", value);
-
-		value = HAL_RX_GET(rssi_info_tlv,
-			RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0);
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"RSSI_EXT40_HIGH20_CHAIN0: %d", value);
-
-		value = HAL_RX_GET(rssi_info_tlv,
-			RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0);
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"RSSI_EXT80_LOW20_CHAIN0: %d", value);
-
-		value = HAL_RX_GET(rssi_info_tlv,
-			RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0);
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"RSSI_EXT80_LOW_HIGH20_CHAIN0: %d", value);
-
-		value = HAL_RX_GET(rssi_info_tlv,
-			RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0);
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"RSSI_EXT80_HIGH_LOW20_CHAIN0: %d", value);
-
-		value = HAL_RX_GET(rssi_info_tlv,
-				   RECEIVE_RSSI_INFO_1,
-				   RSSI_EXT80_HIGH20_CHAIN0);
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			"RSSI_EXT80_HIGH20_CHAIN0: %d", value);
-		break;
-	}
-	case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
-		hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
-								ppdu_info);
-		break;
-	case WIFIPHYRX_GENERATED_CBF_DETAILS_E:
-	{
-		/* This is a NDP frame, set no payload flag to true */
-		is_no_payload_ppdu = true;
-		break;
-	}
-	case WIFIRX_HEADER_E:
-		ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
-		ppdu_info->msdu_info.payload_len = tlv_len;
-		break;
-	case WIFIRX_MPDU_START_E:
-	{
-		uint8_t *rx_mpdu_start =
-			(uint8_t *)rx_tlv + HAL_RX_OFFSET(RX_MPDU_START_0,
-					RX_MPDU_INFO_RX_MPDU_INFO_DETAILS);
-		uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0,
-					      PHY_PPDU_ID);
-
-		ppdu_info->nac_info.fc_valid =
-			HAL_RX_GET(rx_mpdu_start,
-				   RX_MPDU_INFO_2,
-				   MPDU_FRAME_CONTROL_VALID);
-
-		ppdu_info->nac_info.to_ds_flag =
-			HAL_RX_GET(rx_mpdu_start,
-				   RX_MPDU_INFO_2,
-				   TO_DS);
-
-		ppdu_info->nac_info.mac_addr2_valid =
-			HAL_RX_GET(rx_mpdu_start,
-				   RX_MPDU_INFO_2,
-				   MAC_ADDR_AD2_VALID);
-
-		*(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
-			HAL_RX_GET(rx_mpdu_start,
-				   RX_MPDU_INFO_16,
-				   MAC_ADDR_AD2_15_0);
-
-		*(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
-			HAL_RX_GET(rx_mpdu_start,
-				   RX_MPDU_INFO_17,
-				   MAC_ADDR_AD2_47_16);
-
-		if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
-			ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
-			ppdu_info->rx_status.ppdu_len =
-				HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
-					   MPDU_LENGTH);
-		} else {
-			ppdu_info->rx_status.ppdu_len +=
-				HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
-				MPDU_LENGTH);
-		}
-		break;
-	}
-	case 0:
-		return HAL_TLV_STATUS_PPDU_DONE;
-
-	default:
-		unhandled = true;
-		break;
-	}
-
-	if (!unhandled)
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
-			  "%s TLV type: %d, TLV len:%d %s",
-			  __func__, tlv_tag, tlv_len,
-			  unhandled == true ? "unhandled" : "");
-
-	qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, rx_tlv, tlv_len);
-
-	return HAL_TLV_STATUS_PPDU_NOT_DONE;
+	return hal_soc->ops->hal_rx_status_get_tlv_info(rx_tlv_hdr,
+							ppdu_info, hal_soc);
 }
 
 static inline

hal/wifi3.0/hal_generic_api.h

@@ -0,0 +1,1460 @@
+/*
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef _HAL_GENERIC_API_H_
+#define _HAL_GENERIC_API_H_
+
+#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
+	((struct rx_msdu_desc_info *) \
+	_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
+UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
+/**
+ * hal_rx_msdu_desc_info_get_ptr_generic() - Get msdu desc info ptr
+ * @msdu_details_ptr - Pointer to msdu_details_ptr
+ * Return - Pointer to rx_msdu_desc_info structure.
+ *
+ */
+static void *hal_rx_msdu_desc_info_get_ptr_generic(void *msdu_details_ptr)
+{
+	return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
+}
+
+
+#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc)   \
+	((struct rx_msdu_details *) \
+	 _OFFSET_TO_BYTE_PTR((link_desc),\
+	UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
+/**
+ * hal_rx_link_desc_msdu0_ptr_generic - Get pointer to rx_msdu details
+ * @link_desc - Pointer to link desc
+ * Return - Pointer to rx_msdu_details structure
+ *
+ */
+
+static void *hal_rx_link_desc_msdu0_ptr_generic(void *link_desc)
+{
+	return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
+}
+
+/**
+ * hal_tx_comp_get_status() - TQM Release reason
+ * @hal_desc: completion ring Tx status
+ *
+ * This function will parse the WBM completion descriptor and populate in
+ * HAL structure
+ *
+ * Return: none
+ */
+#if defined(WCSS_VERSION) && \
+	((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
+	 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
+static inline void hal_tx_comp_get_status_generic(void *desc,
+		void *ts1)
+{
+	uint8_t rate_stats_valid = 0;
+	uint32_t rate_stats = 0;
+	struct hal_tx_completion_status *ts =
+		(struct hal_tx_completion_status *)ts1;
+
+	ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
+			TQM_STATUS_NUMBER);
+	ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
+			ACK_FRAME_RSSI);
+	ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU);
+	ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU);
+	ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
+			MSDU_PART_OF_AMSDU);
+
+	ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID);
+	ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID);
+	ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
+			TRANSMIT_COUNT);
+
+	rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5,
+			TX_RATE_STATS);
+
+	rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0,
+			TX_RATE_STATS_INFO_VALID, rate_stats);
+
+	ts->valid = rate_stats_valid;
+
+	if (rate_stats_valid) {
+		ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW,
+				rate_stats);
+		ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0,
+				TRANSMIT_PKT_TYPE, rate_stats);
+		ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0,
+				TRANSMIT_STBC, rate_stats);
+		ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC,
+				rate_stats);
+		ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI,
+				rate_stats);
+		ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS,
+				rate_stats);
+		ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION,
+				rate_stats);
+		ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU,
+				rate_stats);
+	}
+
+	ts->release_src = hal_tx_comp_get_buffer_source(desc);
+	ts->status = hal_tx_comp_get_release_reason(desc);
+
+	ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
+			TX_RATE_STATS_INFO_TX_RATE_STATS);
+}
+#else
+static inline void hal_tx_comp_get_status_generic(void *desc,
+		struct hal_tx_completion_status *ts)
+{
+
+	ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
+			TQM_STATUS_NUMBER);
+	ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
+			ACK_FRAME_RSSI);
+	ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU);
+	ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU);
+	ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
+			MSDU_PART_OF_AMSDU);
+
+	ts->release_src = hal_tx_comp_get_buffer_source(desc);
+	ts->status = hal_tx_comp_get_release_reason(desc);
+}
+#endif
+
+
+/**
+ * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
+ * @desc: Handle to Tx Descriptor
+ * @paddr: Physical Address
+ * @pool_id: Return Buffer Manager ID
+ * @desc_id: Descriptor ID
+ * @type: 0 - Address points to a MSDU buffer
+ *		1 - Address points to MSDU extension descriptor
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_buf_addr_generic(void *desc,
+		dma_addr_t paddr, uint8_t pool_id,
+		uint32_t desc_id, uint8_t type)
+{
+	/* Set buffer_addr_info.buffer_addr_31_0 */
+	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
+		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
+
+	/* Set buffer_addr_info.buffer_addr_39_32 */
+	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
+			 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
+		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
+		       (((uint64_t) paddr) >> 32));
+
+	/* Set buffer_addr_info.return_buffer_manager = pool id */
+	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
+			 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
+		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1,
+		       RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID));
+
+	/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
+	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
+			BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
+		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id);
+
+	/* Set  Buffer or Ext Descriptor Type */
+	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2,
+			BUF_OR_EXT_DESC_TYPE) |=
+		HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
+}
+
+/**
+ * hal_rx_status_get_tlv_info() - process receive info TLV
+ * @rx_tlv_hdr: pointer to TLV header
+ * @ppdu_info: pointer to ppdu_info
+ *
+ * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
+ */
+static inline uint32_t
+hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo,
+			   void *halsoc)
+{
+	struct hal_soc *hal = (struct hal_soc *)halsoc;
+	uint32_t tlv_tag, user_id, tlv_len, value;
+	uint8_t group_id = 0;
+	uint8_t he_dcm = 0;
+	uint8_t he_stbc = 0;
+	uint16_t he_gi = 0;
+	uint16_t he_ltf = 0;
+	void *rx_tlv;
+	bool unhandled = false;
+	struct hal_rx_ppdu_info *ppdu_info =
+			(struct hal_rx_ppdu_info *)ppduinfo;
+
+	tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
+	user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
+	tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
+
+	rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
+	switch (tlv_tag) {
+
+	case WIFIRX_PPDU_START_E:
+		ppdu_info->com_info.ppdu_id =
+			HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
+				PHY_PPDU_ID);
+		/* channel number is set in PHY meta data */
+		ppdu_info->rx_status.chan_num =
+			HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
+				SW_PHY_META_DATA);
+		ppdu_info->com_info.ppdu_timestamp =
+			HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
+				PPDU_START_TIMESTAMP);
+		ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
+		break;
+
+	case WIFIRX_PPDU_START_USER_INFO_E:
+		break;
+
+	case WIFIRX_PPDU_END_E:
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"[%s][%d] ppdu_end_e len=%d",
+				__func__, __LINE__, tlv_len);
+		/* This is followed by sub-TLVs of PPDU_END */
+		ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
+		break;
+
+	case WIFIRXPCU_PPDU_END_INFO_E:
+		ppdu_info->rx_status.tsft =
+			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
+				WB_TIMESTAMP_UPPER_32);
+		ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
+			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
+				WB_TIMESTAMP_LOWER_32);
+		ppdu_info->rx_status.duration =
+			HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
+				RX_PPDU_DURATION);
+		break;
+
+	case WIFIRX_PPDU_END_USER_STATS_E:
+	{
+		unsigned long tid = 0;
+		uint16_t seq = 0;
+
+		ppdu_info->rx_status.ast_index =
+				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
+						AST_INDEX);
+
+		tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
+				RECEIVED_QOS_DATA_TID_BITMAP);
+		ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8);
+
+		if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
+			ppdu_info->rx_status.tid = HAL_TID_INVALID;
+
+		ppdu_info->rx_status.tcp_msdu_count =
+			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
+					TCP_MSDU_COUNT) +
+			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
+					TCP_ACK_MSDU_COUNT);
+		ppdu_info->rx_status.udp_msdu_count =
+			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
+						UDP_MSDU_COUNT);
+		ppdu_info->rx_status.other_msdu_count =
+			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
+					OTHER_MSDU_COUNT);
+
+		ppdu_info->rx_status.frame_control_info_valid =
+			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
+					DATA_SEQUENCE_CONTROL_INFO_VALID);
+
+		seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
+					FIRST_DATA_SEQ_CTRL);
+		if (ppdu_info->rx_status.frame_control_info_valid)
+			ppdu_info->rx_status.first_data_seq_ctrl = seq;
+
+		ppdu_info->rx_status.preamble_type =
+			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
+						HT_CONTROL_FIELD_PKT_TYPE);
+		switch (ppdu_info->rx_status.preamble_type) {
+		case HAL_RX_PKT_TYPE_11N:
+			ppdu_info->rx_status.ht_flags = 1;
+			ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
+			break;
+		case HAL_RX_PKT_TYPE_11AC:
+			ppdu_info->rx_status.vht_flags = 1;
+			break;
+		case HAL_RX_PKT_TYPE_11AX:
+			ppdu_info->rx_status.he_flags = 1;
+			break;
+		default:
+			break;
+		}
+
+		ppdu_info->com_info.mpdu_cnt_fcs_ok =
+			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
+					MPDU_CNT_FCS_OK);
+		ppdu_info->com_info.mpdu_cnt_fcs_err =
+			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
+					MPDU_CNT_FCS_ERR);
+		if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
+			ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
+			ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
+		else
+			ppdu_info->rx_status.rs_flags &=
+				(~IEEE80211_AMPDU_FLAG);
+		break;
+	}
+
+	case WIFIRX_PPDU_END_USER_STATS_EXT_E:
+		break;
+
+	case WIFIRX_PPDU_END_STATUS_DONE_E:
+		return HAL_TLV_STATUS_PPDU_DONE;
+
+	case WIFIDUMMY_E:
+		return HAL_TLV_STATUS_BUF_DONE;
+
+	case WIFIPHYRX_HT_SIG_E:
+	{
+		uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
+				HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
+				HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
+		value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
+				FEC_CODING);
+		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
+			1 : 0;
+		ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
+				HT_SIG_INFO_0, MCS);
+		ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
+				HT_SIG_INFO_0, CBW);
+		ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
+				HT_SIG_INFO_1, SHORT_GI);
+		break;
+	}
+
+	case WIFIPHYRX_L_SIG_B_E:
+	{
+		uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
+				HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
+				L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
+
+		value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
+		switch (value) {
+		case 1:
+			ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
+			break;
+		case 2:
+			ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
+			break;
+		case 3:
+			ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
+			break;
+		case 4:
+			ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
+			break;
+		case 5:
+			ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
+			break;
+		case 6:
+			ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
+			break;
+		case 7:
+			ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
+			break;
+		default:
+			break;
+		}
+		ppdu_info->rx_status.cck_flag = 1;
+	break;
+	}
+
+	case WIFIPHYRX_L_SIG_A_E:
+	{
+		uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
+				HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
+				L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
+
+		value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
+		switch (value) {
+		case 8:
+			ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
+			break;
+		case 9:
+			ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
+			break;
+		case 10:
+			ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
+			break;
+		case 11:
+			ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
+			break;
+		case 12:
+			ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
+			break;
+		case 13:
+			ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
+			break;
+		case 14:
+			ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
+			break;
+		case 15:
+			ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
+			break;
+		default:
+			break;
+		}
+		ppdu_info->rx_status.ofdm_flag = 1;
+	break;
+	}
+
+	case WIFIPHYRX_VHT_SIG_A_E:
+	{
+		uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
+				HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
+				VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
+
+		value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
+				SU_MU_CODING);
+		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
+			1 : 0;
+		group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID);
+		ppdu_info->rx_status.vht_flag_values5 = group_id;
+		ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
+				VHT_SIG_A_INFO_1, MCS);
+		ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
+				VHT_SIG_A_INFO_1, GI_SETTING);
+
+		switch (hal->target_type) {
+		case TARGET_TYPE_QCA8074:
+		case TARGET_TYPE_QCA8074V2:
+			ppdu_info->rx_status.is_stbc =
+				HAL_RX_GET(vht_sig_a_info,
+					   VHT_SIG_A_INFO_0, STBC);
+			value =  HAL_RX_GET(vht_sig_a_info,
+					    VHT_SIG_A_INFO_0, N_STS);
+			if (ppdu_info->rx_status.is_stbc && (value > 0))
+				value = ((value + 1) >> 1) - 1;
+			ppdu_info->rx_status.nss =
+				((value & VHT_SIG_SU_NSS_MASK) + 1);
+
+			break;
+		case TARGET_TYPE_QCA6290:
+#if !defined(QCA_WIFI_QCA6290_11AX)
+			ppdu_info->rx_status.is_stbc =
+				HAL_RX_GET(vht_sig_a_info,
+					   VHT_SIG_A_INFO_0, STBC);
+			value =  HAL_RX_GET(vht_sig_a_info,
+					    VHT_SIG_A_INFO_0, N_STS);
+			if (ppdu_info->rx_status.is_stbc && (value > 0))
+				value = ((value + 1) >> 1) - 1;
+			ppdu_info->rx_status.nss =
+				((value & VHT_SIG_SU_NSS_MASK) + 1);
+#else
+			ppdu_info->rx_status.nss = 0;
+#endif
+			break;
+#ifdef QCA_WIFI_QCA6390
+		case TARGET_TYPE_QCA6390:
+			ppdu_info->rx_status.nss = 0;
+			break;
+#endif
+		default:
+			break;
+		}
+		ppdu_info->rx_status.vht_flag_values3[0] =
+				(((ppdu_info->rx_status.mcs) << 4)
+				| ppdu_info->rx_status.nss);
+		ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
+				VHT_SIG_A_INFO_0, BANDWIDTH);
+		ppdu_info->rx_status.vht_flag_values2 =
+			ppdu_info->rx_status.bw;
+		ppdu_info->rx_status.vht_flag_values4 =
+			HAL_RX_GET(vht_sig_a_info,
+				  VHT_SIG_A_INFO_1, SU_MU_CODING);
+
+		ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
+				VHT_SIG_A_INFO_1, BEAMFORMED);
+
+		break;
+	}
+	case WIFIPHYRX_HE_SIG_A_SU_E:
+	{
+		uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
+			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
+			HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
+		ppdu_info->rx_status.he_flags = 1;
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
+			FORMAT_INDICATION);
+		if (value == 0) {
+			ppdu_info->rx_status.he_data1 =
+				QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
+		} else {
+			 ppdu_info->rx_status.he_data1 =
+				 QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
+		}
+
+		/* data1 */
+		ppdu_info->rx_status.he_data1 |=
+			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
+			QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
+			QDF_MON_STATUS_HE_DL_UL_KNOWN |
+			QDF_MON_STATUS_HE_MCS_KNOWN |
+			QDF_MON_STATUS_HE_DCM_KNOWN |
+			QDF_MON_STATUS_HE_CODING_KNOWN |
+			QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
+			QDF_MON_STATUS_HE_STBC_KNOWN |
+			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
+			QDF_MON_STATUS_HE_DOPPLER_KNOWN;
+
+		/* data2 */
+		ppdu_info->rx_status.he_data2 =
+			QDF_MON_STATUS_HE_GI_KNOWN;
+		ppdu_info->rx_status.he_data2 |=
+			QDF_MON_STATUS_TXBF_KNOWN |
+			QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
+			QDF_MON_STATUS_TXOP_KNOWN |
+			QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
+			QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
+			QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
+
+		/* data3 */
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
+		ppdu_info->rx_status.he_data3 = value;
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
+		value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
+		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
+		ppdu_info->rx_status.mcs = value;
+		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_0, DCM);
+		he_dcm = value;
+		value = value << QDF_MON_STATUS_DCM_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_1, CODING);
+		value = value << QDF_MON_STATUS_CODING_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_1,
+				LDPC_EXTRA_SYMBOL);
+		value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_1, STBC);
+		he_stbc = value;
+		value = value << QDF_MON_STATUS_STBC_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		/* data4 */
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
+							SPATIAL_REUSE);
+		ppdu_info->rx_status.he_data4 = value;
+
+		/* data5 */
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
+		ppdu_info->rx_status.he_data5 = value;
+		ppdu_info->rx_status.bw = value;
+		value = HAL_RX_GET(he_sig_a_su_info,
+				HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
+		switch (value) {
+		case 0:
+				he_gi = HE_GI_0_8;
+				he_ltf = HE_LTF_1_X;
+				break;
+		case 1:
+				he_gi = HE_GI_0_8;
+				he_ltf = HE_LTF_2_X;
+				break;
+		case 2:
+				he_gi = HE_GI_1_6;
+				he_ltf = HE_LTF_2_X;
+				break;
+		case 3:
+				if (he_dcm && he_stbc) {
+					he_gi = HE_GI_0_8;
+					he_ltf = HE_LTF_4_X;
+				} else {
+					he_gi = HE_GI_3_2;
+					he_ltf = HE_LTF_4_X;
+				}
+				break;
+		}
+		ppdu_info->rx_status.sgi = he_gi;
+		value = he_gi << QDF_MON_STATUS_GI_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+		value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
+		value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
+		ppdu_info->rx_status.he_data5 |= value;
+
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
+						PACKET_EXTENSION_A_FACTOR);
+		value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
+		value = value << QDF_MON_STATUS_TXBF_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
+					PACKET_EXTENSION_PE_DISAMBIGUITY);
+		value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+
+		/* data6 */
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
+		value++;
+		ppdu_info->rx_status.nss = value;
+		ppdu_info->rx_status.he_data6 = value;
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
+							DOPPLER_INDICATION);
+		value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
+		ppdu_info->rx_status.he_data6 |= value;
+		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
+							TXOP_DURATION);
+		value = value << QDF_MON_STATUS_TXOP_SHIFT;
+		ppdu_info->rx_status.he_data6 |= value;
+
+		ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
+					HE_SIG_A_SU_INFO_1, TXBF);
+		break;
+	}
+	case WIFIPHYRX_HE_SIG_A_MU_DL_E:
+	{
+		uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
+			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
+			HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
+
+		ppdu_info->rx_status.he_mu_flags = 1;
+
+		/* HE Flags */
+		/*data1*/
+		ppdu_info->rx_status.he_data1 =
+					QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
+		ppdu_info->rx_status.he_data1 |=
+			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
+			QDF_MON_STATUS_HE_DL_UL_KNOWN |
+			QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
+			QDF_MON_STATUS_HE_STBC_KNOWN |
+			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
+			QDF_MON_STATUS_HE_DOPPLER_KNOWN;
+
+		/* data2 */
+		ppdu_info->rx_status.he_data2 =
+			QDF_MON_STATUS_HE_GI_KNOWN;
+		ppdu_info->rx_status.he_data2 |=
+			QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
+			QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
+			QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
+			QDF_MON_STATUS_TXOP_KNOWN |
+			QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
+
+		/*data3*/
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
+		ppdu_info->rx_status.he_data3 = value;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
+		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_1,
+				LDPC_EXTRA_SYMBOL);
+		value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_1, STBC);
+		he_stbc = value;
+		value = value << QDF_MON_STATUS_STBC_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		/*data4*/
+		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
+							SPATIAL_REUSE);
+		ppdu_info->rx_status.he_data4 = value;
+
+		/*data5*/
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
+		ppdu_info->rx_status.he_data5 = value;
+		ppdu_info->rx_status.bw = value;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
+		switch (value) {
+		case 0:
+			he_gi = HE_GI_0_8;
+			he_ltf = HE_LTF_4_X;
+			break;
+		case 1:
+			he_gi = HE_GI_0_8;
+			he_ltf = HE_LTF_2_X;
+			break;
+		case 2:
+			he_gi = HE_GI_1_6;
+			he_ltf = HE_LTF_2_X;
+			break;
+		case 3:
+			he_gi = HE_GI_3_2;
+			he_ltf = HE_LTF_4_X;
+			break;
+		}
+		ppdu_info->rx_status.sgi = he_gi;
+		value = he_gi << QDF_MON_STATUS_GI_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+
+		value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				   HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS);
+		value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
+		ppdu_info->rx_status.he_data5 |= value;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
+				   PACKET_EXTENSION_A_FACTOR);
+		value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
+				   PACKET_EXTENSION_PE_DISAMBIGUITY);
+		value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+
+		/*data6*/
+		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
+							DOPPLER_INDICATION);
+		value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
+		ppdu_info->rx_status.he_data6 |= value;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
+							TXOP_DURATION);
+		value = value << QDF_MON_STATUS_TXOP_SHIFT;
+		ppdu_info->rx_status.he_data6 |= value;
+
+		/* HE-MU Flags */
+		/* HE-MU-flags1 */
+		ppdu_info->rx_status.he_flags1 =
+			QDF_MON_STATUS_SIG_B_MCS_KNOWN |
+			QDF_MON_STATUS_SIG_B_DCM_KNOWN |
+			QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
+			QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
+			QDF_MON_STATUS_RU_0_KNOWN;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
+		ppdu_info->rx_status.he_flags1 |= value;
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
+		value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
+		ppdu_info->rx_status.he_flags1 |= value;
+
+		/* HE-MU-flags2 */
+		ppdu_info->rx_status.he_flags2 =
+			QDF_MON_STATUS_BW_KNOWN;
+
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
+		ppdu_info->rx_status.he_flags2 |= value;
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
+		value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
+		ppdu_info->rx_status.he_flags2 |= value;
+		value = HAL_RX_GET(he_sig_a_mu_dl_info,
+				HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
+		value = value - 1;
+		value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
+		ppdu_info->rx_status.he_flags2 |= value;
+		break;
+	}
+	case WIFIPHYRX_HE_SIG_B1_MU_E:
+	{
+
+		uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
+			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
+			HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
+
+		ppdu_info->rx_status.he_sig_b_common_known |=
+			QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
+		/* TODO: Check on the availability of other fields in
+		 * sig_b_common
+		 */
+
+		value = HAL_RX_GET(he_sig_b1_mu_info,
+				HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
+		ppdu_info->rx_status.he_RU[0] = value;
+		break;
+	}
+	case WIFIPHYRX_HE_SIG_B2_MU_E:
+	{
+		uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
+			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
+			HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
+		/*
+		 * Not all "HE" fields can be updated from
+		 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
+		 * to populate rest of the "HE" fields for MU scenarios.
+		 */
+
+		/* HE-data1 */
+		ppdu_info->rx_status.he_data1 |=
+			QDF_MON_STATUS_HE_MCS_KNOWN |
+			QDF_MON_STATUS_HE_CODING_KNOWN;
+
+		/* HE-data2 */
+
+		/* HE-data3 */
+		value = HAL_RX_GET(he_sig_b2_mu_info,
+				HE_SIG_B2_MU_INFO_0, STA_MCS);
+		ppdu_info->rx_status.mcs = value;
+		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+
+		value = HAL_RX_GET(he_sig_b2_mu_info,
+				HE_SIG_B2_MU_INFO_0, STA_CODING);
+		value = value << QDF_MON_STATUS_CODING_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		/* HE-data4 */
+		value = HAL_RX_GET(he_sig_b2_mu_info,
+				HE_SIG_B2_MU_INFO_0, STA_ID);
+		value = value << QDF_MON_STATUS_STA_ID_SHIFT;
+		ppdu_info->rx_status.he_data4 |= value;
+
+		/* HE-data5 */
+
+		/* HE-data6 */
+		value = HAL_RX_GET(he_sig_b2_mu_info,
+				   HE_SIG_B2_MU_INFO_0, NSTS);
+		/* value n indicates n+1 spatial streams */
+		value++;
+		ppdu_info->rx_status.nss = value;
+		ppdu_info->rx_status.he_data6 |= value;
+
+		break;
+
+	}
+	case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
+	{
+		uint8_t *he_sig_b2_ofdma_info =
+		(uint8_t *)rx_tlv +
+		HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
+		HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
+
+		/*
+		 * Not all "HE" fields can be updated from
+		 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
+		 * to populate rest of "HE" fields for MU OFDMA scenarios.
+		 */
+
+		/* HE-data1 */
+		ppdu_info->rx_status.he_data1 |=
+			QDF_MON_STATUS_HE_MCS_KNOWN |
+			QDF_MON_STATUS_HE_DCM_KNOWN |
+			QDF_MON_STATUS_HE_CODING_KNOWN;
+
+		/* HE-data2 */
+		ppdu_info->rx_status.he_data2 |=
+					QDF_MON_STATUS_TXBF_KNOWN;
+
+		/* HE-data3 */
+		value = HAL_RX_GET(he_sig_b2_ofdma_info,
+				HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
+		ppdu_info->rx_status.mcs = value;
+		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		value = HAL_RX_GET(he_sig_b2_ofdma_info,
+				HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
+		he_dcm = value;
+		value = value << QDF_MON_STATUS_DCM_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		value = HAL_RX_GET(he_sig_b2_ofdma_info,
+				HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
+		value = value << QDF_MON_STATUS_CODING_SHIFT;
+		ppdu_info->rx_status.he_data3 |= value;
+
+		/* HE-data4 */
+		value = HAL_RX_GET(he_sig_b2_ofdma_info,
+				HE_SIG_B2_OFDMA_INFO_0, STA_ID);
+		value = value << QDF_MON_STATUS_STA_ID_SHIFT;
+		ppdu_info->rx_status.he_data4 |= value;
+
+		/* HE-data5 */
+		value = HAL_RX_GET(he_sig_b2_ofdma_info,
+				   HE_SIG_B2_OFDMA_INFO_0, TXBF);
+		value = value << QDF_MON_STATUS_TXBF_SHIFT;
+		ppdu_info->rx_status.he_data5 |= value;
+
+		/* HE-data6 */
+		value = HAL_RX_GET(he_sig_b2_ofdma_info,
+				   HE_SIG_B2_OFDMA_INFO_0, NSTS);
+		/* value n indicates n+1 spatial streams */
+		value++;
+		ppdu_info->rx_status.nss = value;
+		ppdu_info->rx_status.he_data6 |= value;
+
+		break;
+	}
+	case WIFIPHYRX_RSSI_LEGACY_E:
+	{
+		uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
+			HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_3,
+			RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS);
+
+		ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
+			PHYRX_RSSI_LEGACY_35, RSSI_COMB);
+		ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
+		ppdu_info->rx_status.he_re = 0;
+
+		ppdu_info->rx_status.reception_type = HAL_RX_GET(rx_tlv,
+				PHYRX_RSSI_LEGACY_0, RECEPTION_TYPE);
+
+		value = HAL_RX_GET(rssi_info_tlv,
+			RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"RSSI_PRI20_CHAIN0: %d\n", value);
+
+		value = HAL_RX_GET(rssi_info_tlv,
+			RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0);
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"RSSI_EXT20_CHAIN0: %d\n", value);
+
+		value = HAL_RX_GET(rssi_info_tlv,
+			RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0);
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"RSSI_EXT40_LOW20_CHAIN0: %d\n", value);
+
+		value = HAL_RX_GET(rssi_info_tlv,
+			RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0);
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"RSSI_EXT40_HIGH20_CHAIN0: %d\n", value);
+
+		value = HAL_RX_GET(rssi_info_tlv,
+			RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0);
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"RSSI_EXT80_LOW20_CHAIN0: %d\n", value);
+
+		value = HAL_RX_GET(rssi_info_tlv,
+			RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0);
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value);
+
+		value = HAL_RX_GET(rssi_info_tlv,
+			RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0);
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value);
+
+		value = HAL_RX_GET(rssi_info_tlv,
+				   RECEIVE_RSSI_INFO_1,
+				   RSSI_EXT80_HIGH20_CHAIN0);
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			"RSSI_EXT80_HIGH20_CHAIN0: %d\n", value);
+		break;
+	}
+	case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
+		hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
+								ppdu_info);
+		break;
+	case WIFIRX_HEADER_E:
+		ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
+		ppdu_info->msdu_info.payload_len = tlv_len;
+		break;
+	case WIFIRX_MPDU_START_E:
+	{
+		uint8_t *rx_mpdu_start =
+			(uint8_t *)rx_tlv + HAL_RX_OFFSET(UNIFIED_RX_MPDU_START_0,
+					RX_MPDU_INFO_RX_MPDU_INFO_DETAILS);
+		uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0,
+					      PHY_PPDU_ID);
+
+		ppdu_info->nac_info.fc_valid =
+			HAL_RX_GET(rx_mpdu_start,
+				   RX_MPDU_INFO_2,
+				   MPDU_FRAME_CONTROL_VALID);
+
+		ppdu_info->nac_info.to_ds_flag =
+			HAL_RX_GET(rx_mpdu_start,
+				   RX_MPDU_INFO_2,
+				   TO_DS);
+
+		ppdu_info->nac_info.mac_addr2_valid =
+			HAL_RX_GET(rx_mpdu_start,
+				   RX_MPDU_INFO_2,
+				   MAC_ADDR_AD2_VALID);
+
+		*(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
+			HAL_RX_GET(rx_mpdu_start,
+				   RX_MPDU_INFO_16,
+				   MAC_ADDR_AD2_15_0);
+
+		*(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
+			HAL_RX_GET(rx_mpdu_start,
+				   RX_MPDU_INFO_17,
+				   MAC_ADDR_AD2_47_16);
+
+		if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
+			ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
+			ppdu_info->rx_status.ppdu_len =
+				HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
+					   MPDU_LENGTH);
+		} else {
+			ppdu_info->rx_status.ppdu_len +=
+				HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
+				MPDU_LENGTH);
+		}
+		break;
+	}
+	case 0:
+		return HAL_TLV_STATUS_PPDU_DONE;
+
+	default:
+		unhandled = true;
+		break;
+	}
+
+	if (!unhandled)
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+			  "%s TLV type: %d, TLV len:%d %s",
+			  __func__, tlv_tag, tlv_len,
+			  unhandled == true ? "unhandled" : "");
+
+	qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
+				rx_tlv, tlv_len);
+
+	return HAL_TLV_STATUS_PPDU_NOT_DONE;
+}
+/**
+ * hal_reo_status_get_header_generic - Process reo desc info
+ * @d - Pointer to reo descriptior
+ * @b - tlv type info
+ * @h1 - Pointer to hal_reo_status_header where info to be stored
+ *
+ * Return - none.
+ *
+ */
+static void hal_reo_status_get_header_generic(uint32_t *d, int b, void *h1)
+{
+
+	uint32_t val1 = 0;
+	struct hal_reo_status_header *h =
+			(struct hal_reo_status_header *)h1;
+
+	switch (b) {
+	case HAL_REO_QUEUE_STATS_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
+		break;
+	case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
+		break;
+	case HAL_REO_FLUSH_CACHE_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
+		break;
+	case HAL_REO_UNBLK_CACHE_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
+		break;
+	case HAL_REO_TIMOUT_LIST_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
+		break;
+	case HAL_REO_DESC_THRES_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
+		break;
+	case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
+		break;
+	default:
+		pr_err("ERROR: Unknown tlv\n");
+		break;
+	}
+	h->cmd_num =
+		HAL_GET_FIELD(
+			      UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
+			      val1);
+	h->exec_time =
+		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
+			      CMD_EXECUTION_TIME, val1);
+	h->status =
+		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
+			      REO_CMD_EXECUTION_STATUS, val1);
+	switch (b) {
+	case HAL_REO_QUEUE_STATS_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
+		break;
+	case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
+		break;
+	case HAL_REO_FLUSH_CACHE_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
+		break;
+	case HAL_REO_UNBLK_CACHE_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
+		break;
+	case HAL_REO_TIMOUT_LIST_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
+		break;
+	case HAL_REO_DESC_THRES_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
+		break;
+	case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
+		val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
+			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
+		break;
+	default:
+		pr_err("ERROR: Unknown tlv\n");
+		break;
+	}
+	h->tstamp =
+		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
+}
+
+/**
+ * hal_reo_setup - Initialize HW REO block
+ *
+ * @hal_soc: Opaque HAL SOC handle
+ * @reo_params: parameters needed by HAL for REO config
+ */
+static void hal_reo_setup_generic(void *hal_soc,
+	 void *reoparams)
+{
+	struct hal_soc *soc = (struct hal_soc *)hal_soc;
+	uint32_t reg_val;
+	struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
+
+	reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
+		SEQ_WCSS_UMAC_REO_REG_OFFSET));
+
+	reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |
+		HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |
+		HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK);
+
+	reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE,
+		FRAGMENT_DEST_RING, reo_params->frag_dst_ring) |
+		HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) |
+		HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1);
+
+	HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
+		SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val);
+
+	/* Other ring enable bits and REO_ENABLE will be set by FW */
+
+	/* TODO: Setup destination ring mapping if enabled */
+
+	/* TODO: Error destination ring setting is left to default.
+	 * Default setting is to send all errors to release ring.
+	 */
+
+	HAL_REG_WRITE(soc,
+		HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
+		SEQ_WCSS_UMAC_REO_REG_OFFSET),
+		HAL_DEFAULT_REO_TIMEOUT_MS * 1000);
+
+	HAL_REG_WRITE(soc,
+		HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
+		SEQ_WCSS_UMAC_REO_REG_OFFSET),
+		(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
+
+	HAL_REG_WRITE(soc,
+		HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
+		SEQ_WCSS_UMAC_REO_REG_OFFSET),
+		(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
+
+	HAL_REG_WRITE(soc,
+		HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
+		SEQ_WCSS_UMAC_REO_REG_OFFSET),
+		(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
+
+	/*
+	 * When hash based routing is enabled, routing of the rx packet
+	 * is done based on the following value: 1 _ _ _ _ The last 4
+	 * bits are based on hash[3:0]. This means the possible values
+	 * are 0x10 to 0x1f. This value is used to look-up the
+	 * ring ID configured in Destination_Ring_Ctrl_IX_* register.
+	 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
+	 * registers need to be configured to set-up the 16 entries to
+	 * map the hash values to a ring number. There are 3 bits per
+	 * hash entry – which are mapped as follows:
+	 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
+	 * 7: NOT_USED.
+	*/
+	if (reo_params->rx_hash_enabled) {
+		HAL_REG_WRITE(soc,
+			HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
+			SEQ_WCSS_UMAC_REO_REG_OFFSET),
+			reo_params->remap1);
+
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
+			FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"),
+			HAL_REG_READ(soc,
+			HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
+			SEQ_WCSS_UMAC_REO_REG_OFFSET)));
+
+		HAL_REG_WRITE(soc,
+			HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
+			SEQ_WCSS_UMAC_REO_REG_OFFSET),
+			reo_params->remap2);
+
+		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
+			FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"),
+			HAL_REG_READ(soc,
+			HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
+			SEQ_WCSS_UMAC_REO_REG_OFFSET)));
+	}
+
+
+	/* TODO: Check if the following registers shoould be setup by host:
+	 * AGING_CONTROL
+	 * HIGH_MEMORY_THRESHOLD
+	 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
+	 * GLOBAL_LINK_DESC_COUNT_CTRL
+	 */
+}
+
+/**
+ * hal_srng_src_hw_init - Private function to initialize SRNG
+ * source ring HW
+ * @hal_soc: HAL SOC handle
+ * @srng: SRNG ring pointer
+ */
+static inline void hal_srng_src_hw_init_generic(void *halsoc,
+	struct hal_srng *srng)
+{
+	struct hal_soc *hal = (struct hal_soc *)halsoc;
+	uint32_t reg_val = 0;
+	uint64_t tp_addr = 0;
+
+	HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id);
+
+	if (srng->flags & HAL_SRNG_MSI_INTR) {
+		SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB,
+			srng->msi_addr & 0xffffffff);
+		reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR),
+			(uint64_t)(srng->msi_addr) >> 32) |
+			SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB,
+			MSI1_ENABLE), 1);
+		SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
+		SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
+	}
+
+	SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
+	reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
+		((uint64_t)(srng->ring_base_paddr) >> 32)) |
+		SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE),
+		srng->entry_size * srng->num_entries);
+	SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val);
+
+#if defined(WCSS_VERSION) && \
+	((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
+	 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
+	reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size);
+#else
+	reg_val = SRNG_SM(SRNG_SRC_FLD(ID, RING_ID), srng->ring_id) |
+		SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size);
+#endif
+	SRNG_SRC_REG_WRITE(srng, ID, reg_val);
+
+	/**
+	 * Interrupt setup:
+	 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
+	 * if level mode is required
+	 */
+	reg_val = 0;
+
+	/*
+	 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be
+	 * programmed in terms of 1us resolution instead of 8us resolution as
+	 * given in MLD.
+	 */
+	if (srng->intr_timer_thres_us) {
+		reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0,
+			INTERRUPT_TIMER_THRESHOLD),
+			srng->intr_timer_thres_us);
+		/* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */
+	}
+
+	if (srng->intr_batch_cntr_thres_entries) {
+		reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0,
+			BATCH_COUNTER_THRESHOLD),
+			srng->intr_batch_cntr_thres_entries *
+			srng->entry_size);
+	}
+	SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val);
+
+	reg_val = 0;
+	if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) {
+		reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1,
+			LOW_THRESHOLD), srng->u.src_ring.low_threshold);
+	}
+
+	SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val);
+
+	/* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should
+	 * remain 0 to avoid some WBM stability issues. Remote head/tail
+	 * pointers are not required since this ring is completely managed
+	 * by WBM HW
+	 */
+	if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) {
+		tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
+			((unsigned long)(srng->u.src_ring.tp_addr) -
+			(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
+		SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff);
+		SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32);
+	}
+
+	/* Initilaize head and tail pointers to indicate ring is empty */
+	SRNG_SRC_REG_WRITE(srng, HP, 0);
+	SRNG_SRC_REG_WRITE(srng, TP, 0);
+	*(srng->u.src_ring.tp_addr) = 0;
+
+	reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ?
+			SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) |
+			((srng->flags & HAL_SRNG_RING_PTR_SWAP) ?
+			SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) |
+			((srng->flags & HAL_SRNG_MSI_SWAP) ?
+			SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0);
+
+	/* Loop count is not used for SRC rings */
+	reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1);
+
+	/*
+	 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1);
+	 * todo: update fw_api and replace with above line
+	 * (when SRNG_ENABLE field for the MISC register is available in fw_api)
+	 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
+	 */
+	reg_val |= 0x40;
+
+	SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
+
+}
+
+/**
+ * hal_srng_dst_hw_init - Private function to initialize SRNG
+ * destination ring HW
+ * @hal_soc: HAL SOC handle
+ * @srng: SRNG ring pointer
+ */
+static inline void hal_srng_dst_hw_init_generic(void *halsoc,
+	struct hal_srng *srng)
+{
+	struct hal_soc *hal = (struct hal_soc *)halsoc;
+	uint32_t reg_val = 0;
+	uint64_t hp_addr = 0;
+
+	HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id);
+
+	if (srng->flags & HAL_SRNG_MSI_INTR) {
+		SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB,
+			srng->msi_addr & 0xffffffff);
+		reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR),
+			(uint64_t)(srng->msi_addr) >> 32) |
+			SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB,
+			MSI1_ENABLE), 1);
+		SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
+		SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
+	}
+
+	SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
+	reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
+		((uint64_t)(srng->ring_base_paddr) >> 32)) |
+		SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE),
+		srng->entry_size * srng->num_entries);
+	SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val);
+
+	reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) |
+		SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size);
+	SRNG_DST_REG_WRITE(srng, ID, reg_val);
+
+
+	/**
+	 * Interrupt setup:
+	 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
+	 * if level mode is required
+	 */
+	reg_val = 0;
+	if (srng->intr_timer_thres_us) {
+		reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP,
+			INTERRUPT_TIMER_THRESHOLD),
+			srng->intr_timer_thres_us >> 3);
+	}
+
+	if (srng->intr_batch_cntr_thres_entries) {
+		reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP,
+			BATCH_COUNTER_THRESHOLD),
+			srng->intr_batch_cntr_thres_entries *
+			srng->entry_size);
+	}
+
+	SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val);
+	hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
+		((unsigned long)(srng->u.dst_ring.hp_addr) -
+		(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
+	SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff);
+	SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32);
+
+	/* Initilaize head and tail pointers to indicate ring is empty */
+	SRNG_DST_REG_WRITE(srng, HP, 0);
+	SRNG_DST_REG_WRITE(srng, TP, 0);
+	*(srng->u.dst_ring.hp_addr) = 0;
+
+	reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ?
+			SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) |
+			((srng->flags & HAL_SRNG_RING_PTR_SWAP) ?
+			SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) |
+			((srng->flags & HAL_SRNG_MSI_SWAP) ?
+			SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0);
+
+	/*
+	 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1);
+	 * todo: update fw_api and replace with above line
+	 * (when SRNG_ENABLE field for the MISC register is available in fw_api)
+	 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
+	 */
+	reg_val |= 0x40;
+
+	SRNG_DST_REG_WRITE(srng, MISC, reg_val);
+
+}
+#endif

hal/wifi3.0/hal_hw_headers.h

@@ -1,30 +1,19 @@
 /*
  * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 #ifndef _HAL_HW_INTERNAL_H_

hal/wifi3.0/hal_internal.h

@@ -1,30 +1,19 @@
 /*
  * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 #ifndef _HAL_INTERNAL_H_
@@ -274,6 +263,19 @@ struct hal_hw_srng_config {
 #define MAX_SHADOW_REGISTERS 36
 
 struct hal_hw_txrx_ops {
+
+	/* init and setup */
+	void (*hal_srng_dst_hw_init)(void *hal,
+		struct hal_srng *srng);
+	void (*hal_srng_src_hw_init)(void *hal,
+	struct hal_srng *srng);
+	void (*hal_reo_setup)(void *hal_soc, void *reoparams);
+	void (*hal_setup_link_idle_list)(void *hal_soc,
+	qdf_dma_addr_t scatter_bufs_base_paddr[],
+	void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs,
+	uint32_t scatter_buf_size, uint32_t last_buf_end_offset,
+	uint32_t num_entries);
+
 	/* tx */
 	void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
 	void (*hal_tx_set_dscp_tid_map)(void *hal_soc, uint8_t *map,
@@ -281,6 +283,9 @@ struct hal_hw_txrx_ops {
 	void (*hal_tx_update_dscp_tid)(void *hal_soc, uint8_t tid, uint8_t id,
 				       uint8_t dscp);
 	void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
+	 void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
+			uint8_t pool_id, uint32_t desc_id, uint8_t type);
+	void (*hal_tx_comp_get_status)(void *desc, void *ts);
 
 	/* rx */
 	uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
@@ -296,6 +301,12 @@ struct hal_hw_txrx_ops {
 	uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf);
 	uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf);
 	uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
+	void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr);
+	void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr);
+	void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h);
+	uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr,
+			void *ppdu_info,
+			void *hal);
 };
 
 /**

hal/wifi3.0/hal_reo.c

@@ -16,11 +16,233 @@
  * PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include "hal_api.h"
 #include "hal_hw_headers.h"
 #include "hal_reo.h"
 #include "hal_tx.h"
+#include "hal_rx.h"
 #include "qdf_module.h"
 
+/* TODO: See if the following definition is available in HW headers */
+#define HAL_REO_OWNED 4
+#define HAL_REO_QUEUE_DESC 8
+#define HAL_REO_QUEUE_EXT_DESC 9
+
+/* TODO: Using associated link desc counter 1 for Rx. Check with FW on
+ * how these counters are assigned
+ */
+#define HAL_RX_LINK_DESC_CNTR 1
+/* TODO: Following definition should be from HW headers */
+#define HAL_DESC_REO_OWNED 4
+
+/**
+ * hal_uniform_desc_hdr_setup - setup reo_queue_ext descritpro
+ * @owner - owner info
+ * @buffer_type - buffer type
+ */
+static inline void hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner,
+	uint32_t buffer_type)
+{
+	HAL_DESC_SET_FIELD(desc, UNIFORM_DESCRIPTOR_HEADER_0, OWNER,
+		owner);
+	HAL_DESC_SET_FIELD(desc, UNIFORM_DESCRIPTOR_HEADER_0, BUFFER_TYPE,
+		buffer_type);
+}
+
+#ifndef TID_TO_WME_AC
+#define WME_AC_BE 0 /* best effort */
+#define WME_AC_BK 1 /* background */
+#define WME_AC_VI 2 /* video */
+#define WME_AC_VO 3 /* voice */
+
+#define TID_TO_WME_AC(_tid) ( \
+	(((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
+	(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
+	(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
+	WME_AC_VO)
+#endif
+#define HAL_NON_QOS_TID 16
+
+/**
+ * hal_reo_qdesc_setup - Setup HW REO queue descriptor
+ *
+ * @hal_soc: Opaque HAL SOC handle
+ * @ba_window_size: BlockAck window size
+ * @start_seq: Starting sequence number
+ * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
+ * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
+ * @tid: TID
+ *
+ */
+void hal_reo_qdesc_setup(void *hal_soc, int tid, uint32_t ba_window_size,
+	uint32_t start_seq, void *hw_qdesc_vaddr, qdf_dma_addr_t hw_qdesc_paddr,
+	int pn_type)
+{
+	uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
+	uint32_t *reo_queue_ext_desc;
+	uint32_t reg_val;
+	uint32_t pn_enable;
+	uint32_t pn_size = 0;
+
+	qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
+
+	hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
+		HAL_REO_QUEUE_DESC);
+	/* Fixed pattern in reserved bits for debugging */
+	HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER_0,
+		RESERVED_0A, 0xDDBEEF);
+
+	/* This a just a SW meta data and will be copied to REO destination
+	 * descriptors indicated by hardware.
+	 * TODO: Setting TID in this field. See if we should set something else.
+	 */
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_1,
+		RECEIVE_QUEUE_NUMBER, tid);
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+		VLD, 1);
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+		ASSOCIATED_LINK_DESCRIPTOR_COUNTER, HAL_RX_LINK_DESC_CNTR);
+
+	/*
+	 * Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
+	 */
+
+	reg_val = TID_TO_WME_AC(tid);
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, AC, reg_val);
+
+	if (ba_window_size < 1)
+		ba_window_size = 1;
+
+	/* Set RTY bit for non-BA case. Duplicate detection is currently not
+	 * done by HW in non-BA case if RTY bit is not set.
+	 * TODO: This is a temporary War and should be removed once HW fix is
+	 * made to check and discard duplicates even if RTY bit is not set.
+	 */
+	if (ba_window_size == 1)
+		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, RTY, 1);
+
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, BA_WINDOW_SIZE,
+		ba_window_size - 1);
+
+	switch (pn_type) {
+	case HAL_PN_WPA:
+		pn_enable = 1;
+		pn_size = PN_SIZE_48;
+		break;
+	case HAL_PN_WAPI_EVEN:
+	case HAL_PN_WAPI_UNEVEN:
+		pn_enable = 1;
+		pn_size = PN_SIZE_128;
+		break;
+	default:
+		pn_enable = 0;
+		break;
+	}
+
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_CHECK_NEEDED,
+		pn_enable);
+
+	if (pn_type == HAL_PN_WAPI_EVEN)
+		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+			PN_SHALL_BE_EVEN, 1);
+	else if (pn_type == HAL_PN_WAPI_UNEVEN)
+		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+			PN_SHALL_BE_UNEVEN, 1);
+
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_HANDLING_ENABLE,
+		pn_enable);
+
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_SIZE,
+		pn_size);
+
+	/* TODO: Check if RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG need to be set
+	 * based on BA window size and/or AMPDU capabilities
+	 */
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+		IGNORE_AMPDU_FLAG, 1);
+
+	if (start_seq <= 0xfff)
+		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SSN,
+			start_seq);
+
+	/* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
+	 * but REO is not delivering packets if we set it to 1. Need to enable
+	 * this once the issue is resolved
+	 */
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SVLD, 0);
+
+	/* TODO: Check if we should set start PN for WAPI */
+
+#ifdef notyet
+	/* Setup first queue extension if BA window size is more than 1 */
+	if (ba_window_size > 1) {
+		reo_queue_ext_desc =
+			(uint32_t *)(((struct rx_reo_queue *)reo_queue_desc) +
+			1);
+		qdf_mem_zero(reo_queue_ext_desc,
+			sizeof(struct rx_reo_queue_ext));
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+	}
+	/* Setup second queue extension if BA window size is more than 105 */
+	if (ba_window_size > 105) {
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
+		qdf_mem_zero(reo_queue_ext_desc,
+			sizeof(struct rx_reo_queue_ext));
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+	}
+	/* Setup third queue extension if BA window size is more than 210 */
+	if (ba_window_size > 210) {
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
+		qdf_mem_zero(reo_queue_ext_desc,
+			sizeof(struct rx_reo_queue_ext));
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+	}
+#else
+	/* TODO: HW queue descriptors are currently allocated for max BA
+	 * window size for all QOS TIDs so that same descriptor can be used
+	 * later when ADDBA request is recevied. This should be changed to
+	 * allocate HW queue descriptors based on BA window size being
+	 * negotiated (0 for non BA cases), and reallocate when BA window
+	 * size changes and also send WMI message to FW to change the REO
+	 * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
+	 */
+	if (tid != HAL_NON_QOS_TID) {
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue *)reo_queue_desc) + 1);
+		qdf_mem_zero(reo_queue_ext_desc, 3 *
+			sizeof(struct rx_reo_queue_ext));
+		/* Initialize first reo queue extension descriptor */
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+		/* Fixed pattern in reserved bits for debugging */
+		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
+			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xADBEEF);
+		/* Initialize second reo queue extension descriptor */
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+		/* Fixed pattern in reserved bits for debugging */
+		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
+			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xBDBEEF);
+		/* Initialize third reo queue extension descriptor */
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+		/* Fixed pattern in reserved bits for debugging */
+		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
+			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xCDBEEF);
+	}
+#endif
+}
+qdf_export_symbol(hal_reo_qdesc_setup);
+
 #define BLOCK_RES_MASK		0xF
 static inline uint8_t hal_find_one_bit(uint8_t x)
 {
@@ -560,7 +782,8 @@ inline int hal_reo_cmd_update_rx_queue(void *reo_ring, struct hal_soc *soc,
 qdf_export_symbol(hal_reo_cmd_update_rx_queue);
 
 inline void hal_reo_queue_stats_status(uint32_t *reo_desc,
-			     struct hal_reo_queue_status *st)
+			     struct hal_reo_queue_status *st,
+			     struct hal_soc *hal_soc)
 {
 	uint32_t val;
 
@@ -569,7 +792,8 @@ inline void hal_reo_queue_stats_status(uint32_t *reo_desc,
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
 
 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_GET_QUEUE_STATS, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_QUEUE_STATS_STATUS_TLV,
+					&(st->header), hal_soc);
 
 	/* SSN */
 	val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_2, SSN)];
@@ -751,7 +975,8 @@ inline void hal_reo_queue_stats_status(uint32_t *reo_desc,
 qdf_export_symbol(hal_reo_queue_stats_status);
 
 inline void hal_reo_flush_queue_status(uint32_t *reo_desc,
-				    struct hal_reo_flush_queue_status *st)
+				    struct hal_reo_flush_queue_status *st,
+				    struct hal_soc *hal_soc)
 {
 	uint32_t val;
 
@@ -760,7 +985,8 @@ inline void hal_reo_flush_queue_status(uint32_t *reo_desc,
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
 
 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_QUEUE, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_FLUSH_QUEUE_STATUS_TLV,
+					&(st->header), hal_soc);
 
 	/* error bit */
 	val = reo_desc[HAL_OFFSET(REO_FLUSH_QUEUE_STATUS_2,
@@ -771,7 +997,8 @@ inline void hal_reo_flush_queue_status(uint32_t *reo_desc,
 qdf_export_symbol(hal_reo_flush_queue_status);
 
 inline void hal_reo_flush_cache_status(uint32_t *reo_desc, struct hal_soc *soc,
-				    struct hal_reo_flush_cache_status *st)
+				    struct hal_reo_flush_cache_status *st,
+				    struct hal_soc *hal_soc)
 {
 	uint32_t val;
 
@@ -780,7 +1007,8 @@ inline void hal_reo_flush_cache_status(uint32_t *reo_desc, struct hal_soc *soc,
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
 
 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_CACHE, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_FLUSH_CACHE_STATUS_TLV,
+					&(st->header), hal_soc);
 
 	/* error bit */
 	val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
@@ -834,7 +1062,8 @@ inline void hal_reo_unblock_cache_status(uint32_t *reo_desc,
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
 
 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_UNBLOCK_CACHE, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_UNBLK_CACHE_STATUS_TLV,
+					&(st->header), soc);
 
 	/* error bit */
 	val = reo_desc[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_2,
@@ -858,7 +1087,8 @@ qdf_export_symbol(hal_reo_unblock_cache_status);
 
 inline void hal_reo_flush_timeout_list_status(
 			 uint32_t *reo_desc,
-			 struct hal_reo_flush_timeout_list_status *st)
+			 struct hal_reo_flush_timeout_list_status *st,
+			 struct hal_soc *hal_soc)
 
 {
 	uint32_t val;
@@ -868,7 +1098,8 @@ inline void hal_reo_flush_timeout_list_status(
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
 
 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_TIMEOUT_LIST, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_TIMOUT_LIST_STATUS_TLV,
+					&(st->header), hal_soc);
 
 	/* error bit */
 	val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
@@ -902,7 +1133,8 @@ qdf_export_symbol(hal_reo_flush_timeout_list_status);
 
 inline void hal_reo_desc_thres_reached_status(
 			 uint32_t *reo_desc,
-			 struct hal_reo_desc_thres_reached_status *st)
+			 struct hal_reo_desc_thres_reached_status *st,
+			 struct hal_soc *hal_soc)
 {
 	uint32_t val;
 
@@ -911,8 +1143,9 @@ inline void hal_reo_desc_thres_reached_status(
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
 
 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc,
-			      REO_DESCRIPTOR_THRESHOLD_REACHED, st->header);
+	hal_reo_status_get_header(reo_desc,
+			      HAL_REO_DESC_THRES_STATUS_TLV,
+			      &(st->header), hal_soc);
 
 	/* threshold index */
 	val = reo_desc[HAL_OFFSET_DW(
@@ -959,15 +1192,17 @@ inline void hal_reo_desc_thres_reached_status(
 qdf_export_symbol(hal_reo_desc_thres_reached_status);
 
 inline void hal_reo_rx_update_queue_status(uint32_t *reo_desc,
-				      struct hal_reo_update_rx_queue_status *st)
+				      struct hal_reo_update_rx_queue_status *st,
+				      struct hal_soc *hal_soc)
 {
 	/* Offsets of descriptor fields defined in HW headers start
 	 * from the field after TLV header */
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
 
 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc,
-			      REO_UPDATE_RX_REO_QUEUE, st->header);
+	hal_reo_status_get_header(reo_desc,
+			      HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV,
+			      &(st->header), hal_soc);
 }
 qdf_export_symbol(hal_reo_rx_update_queue_status);
 

hal/wifi3.0/hal_reo.h

@@ -80,25 +80,6 @@
 /* dword offsets in REO cmd TLV */
 #define CMD_HEADER_DW_OFFSET	0
 
-#define HAL_REO_STATUS_GET_HEADER(d, b, h) do {				\
-	uint32_t val1 = d[HAL_OFFSET_DW(b ##_STATUS_0,			\
-			UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];	\
-	h.cmd_num =							\
-		HAL_GET_FIELD(						\
-			      UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, \
-			      val1);					\
-	h.exec_time =							\
-		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,		\
-			      CMD_EXECUTION_TIME, val1);		\
-	h.status =							\
-		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,		\
-			      REO_CMD_EXECUTION_STATUS, val1);		\
-	val1 = d[HAL_OFFSET_DW(b ##_STATUS_1,				\
-			   UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];   \
-	h.tstamp =							\
-		HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); \
-} while (0)
-
 /**
  * enum reo_unblock_cache_type: Enum for unblock type in REO unblock command
  * @UNBLOCK_RES_INDEX: Unblock a block resource
@@ -526,21 +507,27 @@ int hal_reo_cmd_update_rx_queue(void *reo_ring, struct hal_soc *soc,
 
 /* REO status ring routines */
 void hal_reo_queue_stats_status(uint32_t *reo_desc,
-				struct hal_reo_queue_status *st);
+				struct hal_reo_queue_status *st,
+				struct hal_soc *hal_soc);
 void hal_reo_flush_queue_status(uint32_t *reo_desc,
-				    struct hal_reo_flush_queue_status *st);
+				    struct hal_reo_flush_queue_status *st,
+				    struct hal_soc *hal_soc);
 void hal_reo_flush_cache_status(uint32_t *reo_desc, struct hal_soc *soc,
-				    struct hal_reo_flush_cache_status *st);
+				    struct hal_reo_flush_cache_status *st,
+				    struct hal_soc *hal_soc);
 void hal_reo_unblock_cache_status(uint32_t *reo_desc, struct hal_soc *soc,
 				      struct hal_reo_unblk_cache_status *st);
 void hal_reo_flush_timeout_list_status(
 			   uint32_t *reo_desc,
-			   struct hal_reo_flush_timeout_list_status *st);
+			   struct hal_reo_flush_timeout_list_status *st,
+			   struct hal_soc *hal_soc);
 void hal_reo_desc_thres_reached_status(
 				uint32_t *reo_desc,
-				struct hal_reo_desc_thres_reached_status *st);
+				struct hal_reo_desc_thres_reached_status *st,
+				struct hal_soc *hal_soc);
 void hal_reo_rx_update_queue_status(uint32_t *reo_desc,
-				    struct hal_reo_update_rx_queue_status *st);
+				    struct hal_reo_update_rx_queue_status *st,
+				    struct hal_soc *hal_soc);
 
 void hal_reo_init_cmd_ring(struct hal_soc *soc, void *hal_srng);
 

hal/wifi3.0/hal_rx.c

@@ -1,427 +0,0 @@
-/*
- * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "hal_api.h"
-#include "hal_hw_headers.h"
-#include "qdf_module.h"
-
-/* TODO: See if the following definition is available in HW headers */
-#define HAL_REO_OWNED 4
-#define HAL_REO_QUEUE_DESC 8
-#define HAL_REO_QUEUE_EXT_DESC 9
-
-/* TODO: Using associated link desc counter 1 for Rx. Check with FW on
- * how these counters are assigned
- */
-#define HAL_RX_LINK_DESC_CNTR 1
-/* TODO: Following definition should be from HW headers */
-#define HAL_DESC_REO_OWNED 4
-
-/* TODO: Move this to common header file */
-static inline void hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner,
-	uint32_t buffer_type)
-{
-	HAL_DESC_SET_FIELD(desc, UNIFORM_DESCRIPTOR_HEADER_0, OWNER,
-		owner);
-	HAL_DESC_SET_FIELD(desc, UNIFORM_DESCRIPTOR_HEADER_0, BUFFER_TYPE,
-		buffer_type);
-}
-
-#ifndef TID_TO_WME_AC
-#define WME_AC_BE 0 /* best effort */
-#define WME_AC_BK 1 /* background */
-#define WME_AC_VI 2 /* video */
-#define WME_AC_VO 3 /* voice */
-
-#define TID_TO_WME_AC(_tid) ( \
-	(((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
-	(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
-	(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
-	WME_AC_VO)
-#endif
-#define HAL_NON_QOS_TID 16
-
-/**
- * hal_reo_qdesc_setup - Setup HW REO queue descriptor
- *
- * @hal_soc: Opaque HAL SOC handle
- * @ba_window_size: BlockAck window size
- * @start_seq: Starting sequence number
- * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
- * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
- * @tid: TID
- *
- */
-void hal_reo_qdesc_setup(void *hal_soc, int tid, uint32_t ba_window_size,
-	uint32_t start_seq, void *hw_qdesc_vaddr, qdf_dma_addr_t hw_qdesc_paddr,
-	int pn_type)
-{
-	uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
-	uint32_t *reo_queue_ext_desc;
-	uint32_t reg_val;
-	uint32_t pn_enable;
-	uint32_t pn_size = 0;
-
-	qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
-
-	hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
-		HAL_REO_QUEUE_DESC);
-	/* Fixed pattern in reserved bits for debugging */
-	HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER_0,
-		RESERVED_0A, 0xDDBEEF);
-
-	/* This a just a SW meta data and will be copied to REO destination
-	 * descriptors indicated by hardware.
-	 * TODO: Setting TID in this field. See if we should set something else.
-	 */
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_1,
-		RECEIVE_QUEUE_NUMBER, tid);
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
-		VLD, 1);
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
-		ASSOCIATED_LINK_DESCRIPTOR_COUNTER, HAL_RX_LINK_DESC_CNTR);
-
-	/*
-	 * Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
-	 */
-
-	reg_val = TID_TO_WME_AC(tid);
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, AC, reg_val);
-
-	if (ba_window_size < 1)
-		ba_window_size = 1;
-	/*
-	 * WAR to get 2k exception in Non BA case.
-	 * Setting window size to 2 to get 2k jump exception
-	 * when we receive aggregates in Non BA case
-	 */
-	if (ba_window_size == 1)
-		ba_window_size++;
-	/* Set RTY bit for non-BA case. Duplicate detection is currently not
-	 * done by HW in non-BA case if RTY bit is not set.
-	 * TODO: This is a temporary War and should be removed once HW fix is
-	 * made to check and discard duplicates even if RTY bit is not set.
-	 */
-	if (ba_window_size == 1)
-		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, RTY, 1);
-
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, BA_WINDOW_SIZE,
-		ba_window_size - 1);
-
-	switch (pn_type) {
-	case HAL_PN_WPA:
-		pn_enable = 1;
-		pn_size = PN_SIZE_48;
-	case HAL_PN_WAPI_EVEN:
-	case HAL_PN_WAPI_UNEVEN:
-		pn_enable = 1;
-		pn_size = PN_SIZE_128;
-	default:
-		pn_enable = 0;
-	}
-
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_CHECK_NEEDED,
-		pn_enable);
-
-	if (pn_type == HAL_PN_WAPI_EVEN)
-		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
-			PN_SHALL_BE_EVEN, 1);
-	else if (pn_type == HAL_PN_WAPI_UNEVEN)
-		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
-			PN_SHALL_BE_UNEVEN, 1);
-
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_HANDLING_ENABLE,
-		pn_enable);
-
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_SIZE,
-		pn_size);
-
-	/* TODO: Check if RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG need to be set
-	 * based on BA window size and/or AMPDU capabilities
-	 */
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
-		IGNORE_AMPDU_FLAG, 1);
-
-	if (start_seq <= 0xfff)
-		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SSN,
-			start_seq);
-
-	/* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
-	 * but REO is not delivering packets if we set it to 1. Need to enable
-	 * this once the issue is resolved */
-	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SVLD, 0);
-
-	/* TODO: Check if we should set start PN for WAPI */
-
-#ifdef notyet
-	/* Setup first queue extension if BA window size is more than 1 */
-	if (ba_window_size > 1) {
-		reo_queue_ext_desc =
-			(uint32_t *)(((struct rx_reo_queue *)reo_queue_desc) +
-			1);
-		qdf_mem_zero(reo_queue_ext_desc,
-			sizeof(struct rx_reo_queue_ext));
-		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
-			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
-	}
-	/* Setup second queue extension if BA window size is more than 105 */
-	if (ba_window_size > 105) {
-		reo_queue_ext_desc = (uint32_t *)
-			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
-		qdf_mem_zero(reo_queue_ext_desc,
-			sizeof(struct rx_reo_queue_ext));
-		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
-			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
-	}
-	/* Setup third queue extension if BA window size is more than 210 */
-	if (ba_window_size > 210) {
-		reo_queue_ext_desc = (uint32_t *)
-			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
-		qdf_mem_zero(reo_queue_ext_desc,
-			sizeof(struct rx_reo_queue_ext));
-		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
-			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
-	}
-#else
-	/* TODO: HW queue descriptors are currently allocated for max BA
-	 * window size for all QOS TIDs so that same descriptor can be used
-	 * later when ADDBA request is recevied. This should be changed to
-	 * allocate HW queue descriptors based on BA window size being
-	 * negotiated (0 for non BA cases), and reallocate when BA window
-	 * size changes and also send WMI message to FW to change the REO
-	 * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
-	 */
-	if (tid != HAL_NON_QOS_TID) {
-		reo_queue_ext_desc = (uint32_t *)
-			(((struct rx_reo_queue *)reo_queue_desc) + 1);
-		qdf_mem_zero(reo_queue_ext_desc, 3 *
-			sizeof(struct rx_reo_queue_ext));
-		/* Initialize first reo queue extension descriptor */
-		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
-			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
-		/* Fixed pattern in reserved bits for debugging */
-		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
-			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xADBEEF);
-		/* Initialize second reo queue extension descriptor */
-		reo_queue_ext_desc = (uint32_t *)
-			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
-		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
-			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
-		/* Fixed pattern in reserved bits for debugging */
-		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
-			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xBDBEEF);
-		/* Initialize third reo queue extension descriptor */
-		reo_queue_ext_desc = (uint32_t *)
-			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
-		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
-			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
-		/* Fixed pattern in reserved bits for debugging */
-		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
-			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xCDBEEF);
-	}
-#endif
-}
-qdf_export_symbol(hal_reo_qdesc_setup);
-
-
-/**
- * hal_reo_setup - Initialize HW REO block
- *
- * @hal_soc: Opaque HAL SOC handle
- * @reo_params: parameters needed by HAL for REO config
- */
-void hal_reo_setup(void *hal_soc,
-	 struct hal_reo_params *reo_params)
-{
-	struct hal_soc *soc = (struct hal_soc *)hal_soc;
-	uint32_t reg_val;
-
-	reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
-		SEQ_WCSS_UMAC_REO_REG_OFFSET));
-
-	reg_val &= ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |
-		HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |
-		HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK);
-
-	reg_val |= HAL_SM(HWIO_REO_R0_GENERAL_ENABLE,
-		FRAGMENT_DEST_RING, reo_params->frag_dst_ring) |
-		HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_LIST_ENABLE, 1) |
-		HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, AGING_FLUSH_ENABLE, 1);
-
-	HAL_REG_WRITE(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
-		SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val);
-
-	/* Other ring enable bits and REO_ENABLE will be set by FW */
-
-	/* TODO: Setup destination ring mapping if enabled */
-
-	/* TODO: Error destination ring setting is left to default.
-	 * Default setting is to send all errors to release ring.
-	 */
-
-	HAL_REG_WRITE(soc,
-		HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
-		SEQ_WCSS_UMAC_REO_REG_OFFSET),
-		HAL_DEFAULT_REO_TIMEOUT_MS * 1000);
-
-	HAL_REG_WRITE(soc,
-		HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
-		SEQ_WCSS_UMAC_REO_REG_OFFSET),
-		(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
-
-	HAL_REG_WRITE(soc,
-		HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
-		SEQ_WCSS_UMAC_REO_REG_OFFSET),
-		(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
-
-	HAL_REG_WRITE(soc,
-		HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
-		SEQ_WCSS_UMAC_REO_REG_OFFSET),
-		(HAL_DEFAULT_REO_TIMEOUT_MS * 1000));
-
-	/*
-	 * When hash based routing is enabled, routing of the rx packet
-	 * is done based on the following value: 1 _ _ _ _ The last 4
-	 * bits are based on hash[3:0]. This means the possible values
-	 * are 0x10 to 0x1f. This value is used to look-up the
-	 * ring ID configured in Destination_Ring_Ctrl_IX_* register.
-	 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
-	 * registers need to be configured to set-up the 16 entries to
-	 * map the hash values to a ring number. There are 3 bits per
-	 * hash entry – which are mapped as follows:
-	 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
-	 * 7: NOT_USED.
-	*/
-	if (reo_params->rx_hash_enabled) {
-		HAL_REG_WRITE(soc,
-			HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
-			SEQ_WCSS_UMAC_REO_REG_OFFSET),
-			reo_params->remap1);
-
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
-			FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x"),
-			HAL_REG_READ(soc,
-			HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
-			SEQ_WCSS_UMAC_REO_REG_OFFSET)));
-
-		HAL_REG_WRITE(soc,
-			HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
-			SEQ_WCSS_UMAC_REO_REG_OFFSET),
-			reo_params->remap2);
-
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
-			FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x"),
-			HAL_REG_READ(soc,
-			HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
-			SEQ_WCSS_UMAC_REO_REG_OFFSET)));
-	}
-
-
-	/* TODO: Check if the following registers shoould be setup by host:
-	 * AGING_CONTROL
-	 * HIGH_MEMORY_THRESHOLD
-	 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
-	 * GLOBAL_LINK_DESC_COUNT_CTRL
-	 */
-}
-qdf_export_symbol(hal_reo_setup);
-
-/**
- * hal_get_ba_aging_timeout - Get BA Aging timeout
- *
- * @hal_soc: Opaque HAL SOC handle
- * @ac: Access category
- * @value: window size to get
- */
-void hal_get_ba_aging_timeout(void *hal_soc, uint8_t ac,
-			      uint32_t *value)
-{
-	struct hal_soc *soc = (struct hal_soc *)hal_soc;
-
-	switch (ac) {
-	case WME_AC_BE:
-		*value = HAL_REG_READ(soc,
-					HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
-					SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
-		break;
-	case WME_AC_BK:
-		*value = HAL_REG_READ(soc,
-					HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
-					SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
-		break;
-	case WME_AC_VI:
-		*value = HAL_REG_READ(soc,
-					HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
-					SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
-		break;
-	case WME_AC_VO:
-		*value = HAL_REG_READ(soc,
-					HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
-					SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
-		break;
-	default:
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
-			  "Invalid AC: %d\n", ac);
-	}
-}
-qdf_export_symbol(hal_get_ba_aging_timeout);
-
-/**
- * hal_set_ba_aging_timeout - Set BA Aging timeout
- *
- * @hal_soc: Opaque HAL SOC handle
- * @ac: Access category
- * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
- * @value: Input value to set
- */
-void hal_set_ba_aging_timeout(void *hal_soc, uint8_t ac,
-			      uint32_t value)
-{
-	struct hal_soc *soc = (struct hal_soc *)hal_soc;
-
-	switch (ac) {
-	case WME_AC_BE:
-		HAL_REG_WRITE(soc,
-				HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
-				SEQ_WCSS_UMAC_REO_REG_OFFSET),
-				value * 1000);
-		break;
-	case WME_AC_BK:
-		HAL_REG_WRITE(soc,
-				HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
-				SEQ_WCSS_UMAC_REO_REG_OFFSET),
-				value * 1000);
-		break;
-	case WME_AC_VI:
-		HAL_REG_WRITE(soc,
-				HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
-				SEQ_WCSS_UMAC_REO_REG_OFFSET),
-				value * 1000);
-		break;
-	case WME_AC_VO:
-		HAL_REG_WRITE(soc,
-				HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
-				SEQ_WCSS_UMAC_REO_REG_OFFSET),
-				value * 1000);
-		break;
-	default:
-		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
-			  "Invalid AC: %d\n", ac);
-	}
-}
-qdf_export_symbol(hal_set_ba_aging_timeout);

dp/wifi3.0/hal_rx.h → hal/wifi3.0/hal_rx.h

@@ -401,11 +401,6 @@ enum hal_rx_ret_buf_manager {
 	HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \
 	HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr))
 
-#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr)	\
-	((struct rx_msdu_desc_info *)			\
-	_OFFSET_TO_BYTE_PTR(msdu_details_ptr,		\
-RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
-
 
 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info)		\
 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
@@ -664,6 +659,7 @@ static inline uint8_t
 *hal_rx_padding0_get(uint8_t *buf)
 {
 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+
 	return pkt_tlvs->rx_padding0;
 }
 
@@ -703,6 +699,7 @@ hal_rx_print_pn(uint8_t *buf)
 	uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
 	uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
 	uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
+
 	QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
 		"PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ",
 			pn_127_96, pn_95_64, pn_63_32, pn_31_0);
@@ -1899,11 +1896,6 @@ hal_rx_mpdu_end_mic_err_get(uint8_t *buf)
  * RX REO ERROR APIS
  ******************************************************************************/
 
-#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc)	\
-	((struct rx_msdu_details *)		\
-		_OFFSET_TO_BYTE_PTR((link_desc),\
-		RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
-
 #define HAL_RX_NUM_MSDU_DESC 6
 #define HAL_RX_MAX_SAVED_RING_DESC 16
 
@@ -1919,8 +1911,37 @@ struct hal_buf_info {
 	uint32_t sw_cookie;
 };
 
+/**
+ * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details
+ * @msdu_link_ptr - msdu link ptr
+ * @hal - pointer to hal_soc
+ * Return - Pointer to rx_msdu_details structure
+ *
+ */
+static inline void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr, void *hal)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal;
+
+	return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr);
+}
+
+/**
+ * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr
+ * @msdu_details_ptr - Pointer to msdu_details_ptr
+ * @hal - pointer to hal_soc
+ * Return - Pointer to rx_msdu_desc_info structure.
+ *
+ */
+static inline void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr, void *hal)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal;
+
+	return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr);
+}
+
 /* This special cookie value will be used to indicate FW allocated buffers
- * received through RXDMA2SW ring for RXDMA WARs */
+ * received through RXDMA2SW ring for RXDMA WARs
+ */
 #define HAL_RX_COOKIE_SPECIAL 0x1fffff
 
 /**
@@ -1936,15 +1957,17 @@ struct hal_buf_info {
  *
  * Return: void
  */
-static inline void hal_rx_msdu_list_get(void *msdu_link_desc,
-		struct hal_rx_msdu_list *msdu_list, uint16_t *num_msdus)
+static inline void hal_rx_msdu_list_get(struct hal_soc *hal_soc,
+					void *msdu_link_desc,
+					struct hal_rx_msdu_list *msdu_list,
+					uint16_t *num_msdus)
 {
 	struct rx_msdu_details *msdu_details;
 	struct rx_msdu_desc_info *msdu_desc_info;
 	struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
 	int i;
 
-	msdu_details = HAL_RX_LINK_DESC_MSDU0_PTR(msdu_link);
+	msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
 
 	QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
 		"[%s][%d] msdu_link=%pK msdu_details=%pK",
@@ -1952,16 +1975,18 @@ static inline void hal_rx_msdu_list_get(void *msdu_link_desc,
 
 	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
 		/* num_msdus received in mpdu descriptor may be incorrect
-		 * sometimes due to HW issue. Check msdu buffer address also */
+		 * sometimes due to HW issue. Check msdu buffer address also
+		 */
 		if (HAL_RX_BUFFER_ADDR_31_0_GET(
 			&msdu_details[i].buffer_addr_info_details) == 0) {
 			/* set the last msdu bit in the prev msdu_desc_info */
 			msdu_desc_info =
-				HAL_RX_MSDU_DESC_INFO_GET(&msdu_details[i - 1]);
+				hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc);
 			HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
 			break;
 		}
-		msdu_desc_info = HAL_RX_MSDU_DESC_INFO_GET(&msdu_details[i]);
+		msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
+								hal_soc);
 
 		/* set first MSDU bit or the last MSDU bit */
 		if (!i)
@@ -1995,17 +2020,18 @@ static inline void hal_rx_msdu_list_get(void *msdu_link_desc,
  * Return: dst_ind (REO destination ring ID)
  */
 static inline uint32_t
-hal_rx_msdu_reo_dst_ind_get(void *msdu_link_desc)
+hal_rx_msdu_reo_dst_ind_get(struct hal_soc *hal_soc, void *msdu_link_desc)
 {
 	struct rx_msdu_details *msdu_details;
 	struct rx_msdu_desc_info *msdu_desc_info;
 	struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
 	uint32_t dst_ind;
 
-	msdu_details = HAL_RX_LINK_DESC_MSDU0_PTR(msdu_link);
+	msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
 
 	/* The first msdu in the link should exsist */
-	msdu_desc_info = HAL_RX_MSDU_DESC_INFO_GET(&msdu_details[0]);
+	msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0],
+							hal_soc);
 	dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info);
 	return dst_ind;
 }
@@ -2102,18 +2128,18 @@ enum hal_reo_error_code {
  *
  * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow
  * @ HAL_RXDMA_ERR_OVERFLOW      : MPDU frame is not complete due to a FIFO
- * 				   overflow
+ *                                 overflow
  * @ HAL_RXDMA_ERR_MPDU_LENGTH   : MPDU frame is not complete due to receiving
- * 				   incomplete
- * 		               	   MPDU from the PHY
+ *                                 incomplete
+ *                                 MPDU from the PHY
  * @ HAL_RXDMA_ERR_FCS           : FCS check on the MPDU frame failed
  * @ HAL_RXDMA_ERR_DECRYPT       : Decryption error
  * @ HAL_RXDMA_ERR_TKIP_MIC      : TKIP MIC error
  * @ HAL_RXDMA_ERR_UNENCRYPTED   : Received a frame that was expected to be
- * 			  	   encrypted but wasn’t
+ *                                 encrypted but wasn’t
  * @ HAL_RXDMA_ERR_MSDU_LEN      : MSDU related length error
  * @ HAL_RXDMA_ERR_MSDU_LIMIT    : Number of MSDUs in the MPDUs exceeded
- * 				   the max allowed
+ *                                 the max allowed
  * @ HAL_RXDMA_ERR_WIFI_PARSE    : wifi parsing error
  * @ HAL_RXDMA_ERR_AMSDU_PARSE   : Amsdu parsing error
  * @ HAL_RXDMA_ERR_SA_TIMEOUT    : Source Address search timeout
@@ -2379,7 +2405,7 @@ enum hal_rx_wbm_rxdma_push_reason {
 
 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc)		\
 	(((*(((uint32_t *) wbm_desc) +			\
-	(WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & 	\
+	(WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) &  \
 	WBM_RELEASE_RING_4_LAST_MSDU_MASK) >>		\
 	WBM_RELEASE_RING_4_LAST_MSDU_LSB)
 
@@ -3038,7 +3064,7 @@ void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr,
  * Returns: Number of processed msdus
  */
 static inline
-int hal_rx_chain_msdu_links(qdf_nbuf_t msdu,
+int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu,
 	struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info,
 	struct hal_rx_mpdu_desc_info *mpdu_desc_info)
 {
@@ -3047,7 +3073,7 @@ int hal_rx_chain_msdu_links(qdf_nbuf_t msdu,
 		&msdu_link_ptr_info->msdu_link;
 	struct rx_msdu_link *prev_msdu_link_ptr = NULL;
 	struct rx_msdu_details *msdu_details =
-		HAL_RX_LINK_DESC_MSDU0_PTR(msdu_link_ptr);
+		hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc);
 	uint8_t num_msdus = mpdu_desc_info->msdu_count;
 	struct rx_msdu_desc_info *msdu_desc_info;
 	uint8_t fragno, more_frag;
@@ -3056,7 +3082,8 @@ int hal_rx_chain_msdu_links(qdf_nbuf_t msdu,
 
 	for (j = 0; j < num_msdus; j++) {
 		msdu_desc_info =
-			HAL_RX_MSDU_DESC_INFO_GET(&msdu_details[j]);
+			hal_rx_msdu_desc_info_get_ptr(&msdu_details[j],
+							hal_soc);
 		msdu_list.msdu_info[j].msdu_flags =
 			HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
 		msdu_list.msdu_info[j].msdu_len =
@@ -3396,4 +3423,22 @@ static inline void hal_rx_dump_pkt_tlvs(struct hal_soc *hal_soc,
 	hal_rx_dump_pkt_hdr_tlv(pkt_hdr_tlv, dbg_level);
 }
 
+
+/**
+ * hal_reo_status_get_header_generic - Process reo desc info
+ * @d - Pointer to reo descriptior
+ * @b - tlv type info
+ * @h - Pointer to hal_reo_status_header where info to be stored
+ * @hal- pointer to hal_soc structure
+ * Return - none.
+ *
+ */
+static inline void hal_reo_status_get_header(uint32_t *d, int b,
+						void *h, void *hal)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal;
+
+	hal_soc->ops->hal_reo_status_get_header(d, b, h);
+}
+
 #endif /* _HAL_RX_H */

hal/wifi3.0/hal_srng.c

@@ -1,31 +1,21 @@
 /*
  * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
+
 #include "hal_hw_headers.h"
 #include "hal_api.h"
 #include "target_type.h"
@@ -37,6 +27,9 @@ void hal_qca6290_attach(struct hal_soc *hal);
 #ifdef QCA_WIFI_QCA8074
 void hal_qca8074_attach(struct hal_soc *hal);
 #endif
+#ifdef QCA_WIFI_QCA8074V2
+void hal_qca8074v2_attach(struct hal_soc *hal);
+#endif
 #ifdef QCA_WIFI_QCA6390
 void hal_qca6390_attach(struct hal_soc *hal);
 #endif
@@ -220,7 +213,6 @@ static void hal_target_based_configure(struct hal_soc *hal)
 	switch (hal->target_type) {
 #ifdef QCA_WIFI_QCA6290
 	case TARGET_TYPE_QCA6290:
-	case TARGET_TYPE_QCA6390:
 		hal->use_register_windowing = true;
 		hal_qca6290_attach(hal);
 	break;
@@ -236,6 +228,12 @@ static void hal_target_based_configure(struct hal_soc *hal)
 		hal_qca8074_attach(hal);
 	break;
 #endif
+
+#if defined(QCA_WIFI_QCA8074V2) && defined(CONFIG_WIN)
+	case TARGET_TYPE_QCA8074V2:
+		hal_qca8074v2_attach(hal);
+	break;
+#endif
 	default:
 	break;
 	}
@@ -369,121 +367,6 @@ extern void hal_detach(void *hal_soc)
 }
 qdf_export_symbol(hal_detach);
 
-/**
- * hal_srng_src_hw_init - Private function to initialize SRNG
- * source ring HW
- * @hal_soc: HAL SOC handle
- * @srng: SRNG ring pointer
- */
-static inline void hal_srng_src_hw_init(struct hal_soc *hal,
-	struct hal_srng *srng)
-{
-	uint32_t reg_val = 0;
-	uint64_t tp_addr = 0;
-
-	HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id);
-
-	if (srng->flags & HAL_SRNG_MSI_INTR) {
-		SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB,
-			srng->msi_addr & 0xffffffff);
-		reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR),
-			(uint64_t)(srng->msi_addr) >> 32) |
-			SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB,
-			MSI1_ENABLE), 1);
-		SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
-		SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
-	}
-
-	SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
-	reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
-		((uint64_t)(srng->ring_base_paddr) >> 32)) |
-		SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE),
-		srng->entry_size * srng->num_entries);
-	SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val);
-
-#if defined(WCSS_VERSION) && \
-	((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
-	 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
-	reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size);
-#else
-	reg_val = SRNG_SM(SRNG_SRC_FLD(ID, RING_ID), srng->ring_id) |
-		SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size);
-#endif
-	SRNG_SRC_REG_WRITE(srng, ID, reg_val);
-
-	/**
-	 * Interrupt setup:
-	 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
-	 * if level mode is required
-	 */
-	reg_val = 0;
-
-	/*
-	 * WAR - Hawkeye v1 has a hardware bug which requires timer value to be
-	 * programmed in terms of 1us resolution instead of 8us resolution as
-	 * given in MLD.
-	 */
-	if (srng->intr_timer_thres_us) {
-		reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0,
-			INTERRUPT_TIMER_THRESHOLD),
-			srng->intr_timer_thres_us);
-		/* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */
-	}
-
-	if (srng->intr_batch_cntr_thres_entries) {
-		reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0,
-			BATCH_COUNTER_THRESHOLD),
-			srng->intr_batch_cntr_thres_entries *
-			srng->entry_size);
-	}
-	SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val);
-
-	reg_val = 0;
-	if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) {
-		reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1,
-			LOW_THRESHOLD), srng->u.src_ring.low_threshold);
-	}
-
-	SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val);
-
-	/* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should
-	 * remain 0 to avoid some WBM stability issues. Remote head/tail
-	 * pointers are not required since this ring is completely managed
-	 * by WBM HW */
-	if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) {
-		tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
-			((unsigned long)(srng->u.src_ring.tp_addr) -
-			(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
-		SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff);
-		SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32);
-	}
-
-	/* Initilaize head and tail pointers to indicate ring is empty */
-	SRNG_SRC_REG_WRITE(srng, HP, 0);
-	SRNG_SRC_REG_WRITE(srng, TP, 0);
-	*(srng->u.src_ring.tp_addr) = 0;
-
-	reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ?
-			SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) |
-			((srng->flags & HAL_SRNG_RING_PTR_SWAP) ?
-			SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) |
-			((srng->flags & HAL_SRNG_MSI_SWAP) ?
-			SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0);
-
-	/* Loop count is not used for SRC rings */
-	reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1);
-
-	/*
-	 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1);
-	 * todo: update fw_api and replace with above line
-	 * (when SRNG_ENABLE field for the MISC register is available in fw_api)
-	 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
-	 */
-	reg_val |= 0x40;
-
-	SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
-
-}
 
 /**
  * hal_ce_dst_setup - Initialize CE destination ring registers
@@ -554,93 +437,6 @@ void hal_srng_dst_init_hp(struct hal_srng *srng,
 		*(srng->u.dst_ring.hp_addr));
 }
 
-/**
- * hal_srng_dst_hw_init - Private function to initialize SRNG
- * destination ring HW
- * @hal_soc: HAL SOC handle
- * @srng: SRNG ring pointer
- */
-static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
-	struct hal_srng *srng)
-{
-	uint32_t reg_val = 0;
-	uint64_t hp_addr = 0;
-
-	HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id);
-
-	if (srng->flags & HAL_SRNG_MSI_INTR) {
-		SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB,
-			srng->msi_addr & 0xffffffff);
-		reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR),
-			(uint64_t)(srng->msi_addr) >> 32) |
-			SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB,
-			MSI1_ENABLE), 1);
-		SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
-		SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
-	}
-
-	SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
-	reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
-		((uint64_t)(srng->ring_base_paddr) >> 32)) |
-		SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE),
-		srng->entry_size * srng->num_entries);
-	SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val);
-
-	reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) |
-		SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size);
-	SRNG_DST_REG_WRITE(srng, ID, reg_val);
-
-
-	/**
-	 * Interrupt setup:
-	 * Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
-	 * if level mode is required
-	 */
-	reg_val = 0;
-	if (srng->intr_timer_thres_us) {
-		reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP,
-			INTERRUPT_TIMER_THRESHOLD),
-			srng->intr_timer_thres_us >> 3);
-	}
-
-	if (srng->intr_batch_cntr_thres_entries) {
-		reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP,
-			BATCH_COUNTER_THRESHOLD),
-			srng->intr_batch_cntr_thres_entries *
-			srng->entry_size);
-	}
-
-	SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val);
-	hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
-		((unsigned long)(srng->u.dst_ring.hp_addr) -
-		(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
-	SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff);
-	SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32);
-
-	/* Initilaize head and tail pointers to indicate ring is empty */
-	SRNG_DST_REG_WRITE(srng, HP, 0);
-	SRNG_DST_REG_WRITE(srng, TP, 0);
-	*(srng->u.dst_ring.hp_addr) = 0;
-
-	reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ?
-			SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) |
-			((srng->flags & HAL_SRNG_RING_PTR_SWAP) ?
-			SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) |
-			((srng->flags & HAL_SRNG_MSI_SWAP) ?
-			SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0);
-
-	/*
-	 * reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1);
-	 * todo: update fw_api and replace with above line
-	 * (when SRNG_ENABLE field for the MISC register is available in fw_api)
-	 * (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
-	 */
-	reg_val |= 0x40;
-
-	SRNG_DST_REG_WRITE(srng, MISC, reg_val);
-
-}
-
 /**
  * hal_srng_hw_init - Private function to initialize SRNG HW
  * @hal_soc: HAL SOC handle

hal/wifi3.0/hal_tx.h

@@ -277,47 +277,6 @@ enum hal_tx_dscp_tid_table_id {
 /*---------------------------------------------------------------------------
   TCL Descriptor accessor APIs
   ---------------------------------------------------------------------------*/
-/**
- * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
- * @desc: Handle to Tx Descriptor
- * @paddr: Physical Address
- * @pool_id: Return Buffer Manager ID
- * @desc_id: Descriptor ID
- * @type: 0 - Address points to a MSDU buffer
- *		1 - Address points to MSDU extension descriptor
- *
- * Return: void
- */
-static inline void hal_tx_desc_set_buf_addr(void *desc,
-		dma_addr_t paddr, uint8_t pool_id,
-		uint32_t desc_id, uint8_t type)
-{
-	/* Set buffer_addr_info.buffer_addr_31_0 */
-	HAL_SET_FLD(desc, TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
-		HAL_TX_SM(BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
-
-	/* Set buffer_addr_info.buffer_addr_39_32 */
-	HAL_SET_FLD(desc, TCL_DATA_CMD_1,
-			 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
-		HAL_TX_SM(BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
-		       (((uint64_t) paddr) >> 32));
-
-	/* Set buffer_addr_info.return_buffer_manager = pool id */
-	HAL_SET_FLD(desc, TCL_DATA_CMD_1,
-			 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
-		HAL_TX_SM(BUFFER_ADDR_INFO_1,
-		       RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID));
-
-	/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
-	HAL_SET_FLD(desc, TCL_DATA_CMD_1,
-			BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
-		HAL_TX_SM(BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id);
-
-	/* Set  Buffer or Ext Descriptor Type */
-	HAL_SET_FLD(desc, TCL_DATA_CMD_2,
-			BUF_OR_EXT_DESC_TYPE) |=
-		HAL_TX_SM(TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
-}
 
 /**
  * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
@@ -830,90 +789,6 @@ static inline uint8_t hal_tx_comp_get_release_reason(void *hal_desc)
 		WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB;
 }
 
-/**
- * hal_tx_comp_get_status() - TQM Release reason
- * @hal_desc: completion ring Tx status
- *
- * This function will parse the WBM completion descriptor and populate in
- * HAL structure
- *
- * Return: none
- */
-#if defined(WCSS_VERSION) && \
-	((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
-	 (defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
-static inline void hal_tx_comp_get_status(void *desc,
-		struct hal_tx_completion_status *ts)
-{
-	uint8_t rate_stats_valid = 0;
-	uint32_t rate_stats = 0;
-
-	ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
-			TQM_STATUS_NUMBER);
-	ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
-			ACK_FRAME_RSSI);
-	ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU);
-	ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU);
-	ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
-			MSDU_PART_OF_AMSDU);
-
-	ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID);
-	ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID);
-	ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
-			TRANSMIT_COUNT);
-
-	rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5,
-			TX_RATE_STATS);
-
-	rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0,
-			TX_RATE_STATS_INFO_VALID, rate_stats);
-
-	ts->valid = rate_stats_valid;
-
-	if (rate_stats_valid) {
-		ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW,
-				rate_stats);
-		ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0,
-				TRANSMIT_PKT_TYPE, rate_stats);
-		ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0,
-				TRANSMIT_STBC, rate_stats);
-		ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC,
-				rate_stats);
-		ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI,
-				rate_stats);
-		ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS,
-				rate_stats);
-		ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION,
-				rate_stats);
-		ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU,
-				rate_stats);
-	}
-
-	ts->release_src = hal_tx_comp_get_buffer_source(desc);
-	ts->status = hal_tx_comp_get_release_reason(desc);
-
-	ts->tsf = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_6,
-			TX_RATE_STATS_INFO_TX_RATE_STATS);
-}
-#else
-static inline void hal_tx_comp_get_status(void *desc,
-		struct hal_tx_completion_status *ts)
-{
-
-	ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
-			TQM_STATUS_NUMBER);
-	ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
-			ACK_FRAME_RSSI);
-	ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU);
-	ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU);
-	ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
-			MSDU_PART_OF_AMSDU);
-
-	ts->release_src = hal_tx_comp_get_buffer_source(desc);
-	ts->status = hal_tx_comp_get_release_reason(desc);
-}
-#endif
-
 /**
  * hal_tx_comp_desc_sync() - collect hardware descriptor contents
  * @hal_desc: hardware descriptor pointer
@@ -1042,4 +917,42 @@ static inline void hal_tx_desc_set_lmac_id(struct hal_soc *hal_soc,
 {
 	hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id);
 }
+
+/**
+ * hal_tx_comp_get_status() - TQM Release reason
+ * @hal_desc: completion ring Tx status
+ *
+ * This function will parse the WBM completion descriptor and populate in
+ * HAL structure
+ *
+ * Return: none
+ */
+static inline void hal_tx_comp_get_status(void *desc, void *ts, void *hal)
+{
+	struct hal_soc *hal_soc = hal;
+
+	hal_soc->ops->hal_tx_comp_get_status(desc, ts);
+}
+
+
+/**
+ * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
+ * @desc: Handle to Tx Descriptor
+ * @paddr: Physical Address
+ * @pool_id: Return Buffer Manager ID
+ * @desc_id: Descriptor ID
+ * @type: 0 - Address points to a MSDU buffer
+ *		1 - Address points to MSDU extension descriptor
+ *
+ * Return: void
+ */
+static inline void hal_tx_desc_set_buf_addr(void *desc, dma_addr_t paddr,
+		uint8_t pool_id, uint32_t desc_id, uint8_t type, void *hal)
+{
+	struct hal_soc *hal_soc = hal;
+
+	hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id,
+						desc_id, type);
+
+}
 #endif /* HAL_TX_H */

hal/wifi3.0/hal_wbm.c → hal/wifi3.0/hal_wbm.h

@@ -16,10 +16,6 @@
  * PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "hal_api.h"
-#include "qdf_module.h"
-#include "hal_hw_headers.h"
-
 /**
  * hal_setup_link_idle_list - Setup scattered idle list using the
  * buffer list provided
@@ -33,7 +29,7 @@
  * @num_entries: Total entries of all scatter bufs
  *
  */
-void hal_setup_link_idle_list(void *hal_soc,
+static void hal_setup_link_idle_list_generic(void *hal_soc,
 	qdf_dma_addr_t scatter_bufs_base_paddr[],
 	void *scatter_bufs_base_vaddr[], uint32_t num_scatter_bufs,
 	uint32_t scatter_buf_size, uint32_t last_buf_end_offset,
@@ -156,4 +152,3 @@ void hal_setup_link_idle_list(void *hal_soc,
 		SEQ_WCSS_UMAC_WBM_REG_OFFSET),
 		0x40);
 }
-qdf_export_symbol(hal_setup_link_idle_list);

hal/wifi3.0/qca6290/hal_6290_srng.c → hal/wifi3.0/qca6290/hal_6290.c

@@ -1,32 +1,20 @@
 /*
  * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
-
 #include "qdf_types.h"
 #include "qdf_util.h"
 #include "qdf_types.h"
@@ -39,15 +27,101 @@
 #include "target_type.h"
 #include "wcss_version.h"
 #include "qdf_module.h"
+
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB
+#define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
+	PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
+	PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
+	PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
+	PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
+	PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
+	RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
+	RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
+#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
+	REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
+	UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
+#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
+	RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
+#define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
+	TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
+#define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
+	TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
+#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
+	BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
+	BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
+	BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
+	BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
+	BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
+	BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
+	BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
+	BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB
+
 #include "hal_6290_tx.h"
 #include "hal_6290_rx.h"
+#include <hal_generic_api.h>
+#include <hal_wbm.h>
 
 struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
+	/* init and setup */
+	hal_srng_dst_hw_init_generic,
+	hal_srng_src_hw_init_generic,
+	hal_reo_setup_generic,
+	hal_setup_link_idle_list_generic,
+
 	/* tx */
 	hal_tx_desc_set_dscp_tid_table_id_6290,
 	hal_tx_set_dscp_tid_map_6290,
 	hal_tx_update_dscp_tid_6290,
 	hal_tx_desc_set_lmac_id_6290,
+	hal_tx_desc_set_buf_addr_generic,
+	hal_tx_comp_get_status_generic,
 
 	/* rx */
 	hal_rx_msdu_start_nss_get_6290,
@@ -60,6 +134,10 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
 	hal_rx_mpdu_start_tid_get_6290,
 	hal_rx_msdu_start_reception_type_get_6290,
 	hal_rx_msdu_end_da_idx_get_6290,
+	hal_rx_msdu_desc_info_get_ptr_generic,
+	hal_rx_link_desc_msdu0_ptr_generic,
+	hal_reo_status_get_header_generic,
+	hal_rx_status_get_tlv_info_generic,
 };
 
 struct hal_hw_srng_config hw_srng_table_6290[] = {
@@ -501,6 +579,10 @@ int32_t hal_hw_reg_offset_qca6290[] = {
 	REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1),
 };
 
+/**
+ * hal_qca6290_attach() - Attach 6290 target specific hal_soc ops,
+ *			  offset and srng table
+ */
 void hal_qca6290_attach(struct hal_soc *hal_soc)
 {
 	hal_soc->hw_srng_table = hw_srng_table_6290;

hal/wifi3.0/qca6290/hal_6290_rx.h

@@ -1,30 +1,19 @@
 /*
- * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 #include "qdf_util.h"
 #include "qdf_types.h"

hal/wifi3.0/qca6290/hal_6290_tx.h

@@ -1,30 +1,19 @@
 /*
- * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 
 #include "tcl_data_cmd.h"

hal/wifi3.0/qca6390/hal_6390_srng.c → hal/wifi3.0/qca6390/hal_6390.c

@@ -1,32 +1,20 @@
 /*
  * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
-
 #include "qdf_types.h"
 #include "qdf_util.h"
 #include "qdf_types.h"
@@ -39,15 +27,101 @@
 #include "target_type.h"
 #include "wcss_version.h"
 #include "qdf_module.h"
+
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB
+#define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
+	PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
+	PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
+	PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
+	PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
+	PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
+	RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
+	RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
+#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
+	REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
+	UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
+#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
+	RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
+#define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
+	TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
+#define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
+	TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
+#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
+	BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
+	BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
+	BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
+	BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
+	BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
+	BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
+	BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
+	BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB
+
 #include "hal_6390_tx.h"
 #include "hal_6390_rx.h"
+#include <hal_generic_api.h>
+#include <hal_wbm.h>
 
 struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
+	/* init and setup */
+	hal_srng_dst_hw_init_generic,
+	hal_srng_src_hw_init_generic,
+	hal_reo_setup_generic,
+	hal_setup_link_idle_list_generic,
+
 	/* tx */
 	hal_tx_desc_set_dscp_tid_table_id_6390,
 	hal_tx_set_dscp_tid_map_6390,
 	hal_tx_update_dscp_tid_6390,
 	hal_tx_desc_set_lmac_id_6390,
+	hal_tx_desc_set_buf_addr_generic,
+	hal_tx_comp_get_status_generic,
 
 	/* rx */
 	hal_rx_msdu_start_nss_get_6390,
@@ -60,6 +134,10 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
 	hal_rx_mpdu_start_tid_get_6390,
 	hal_rx_msdu_start_reception_type_get_6390,
 	hal_rx_msdu_end_da_idx_get_6390,
+	hal_rx_msdu_desc_info_get_ptr_generic,
+	hal_rx_link_desc_msdu0_ptr_generic,
+	hal_reo_status_get_header_generic,
+	hal_rx_status_get_tlv_info_generic,
 };
 
 struct hal_hw_srng_config hw_srng_table_6390[] = {
@@ -505,6 +583,10 @@ int32_t hal_hw_reg_offset_qca6390[] = {
 	REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1),
 };
 
+/**
+ * hal_qca6390_attach() - Attach 6390 target specific hal_soc ops,
+ *			  offset and srng table
+ */
 void hal_qca6390_attach(struct hal_soc *hal_soc)
 {
 	hal_soc->hw_srng_table = hw_srng_table_6390;

hal/wifi3.0/qca6390/hal_6390_rx.h

@@ -1,30 +1,19 @@
 /*
- * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
 #include "qdf_util.h"
 #include "qdf_types.h"

hal/wifi3.0/qca6390/hal_6390_tx.h

@@ -1,32 +1,20 @@
 /*
- * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
-
 #include "tcl_data_cmd.h"
 #include "mac_tcl_reg_seq_hwioreg.h"
 #include "phyrx_rssi_legacy.h"

hal/wifi3.0/qca8074/hal_8074_srng.c → hal/wifi3.0/qca8074v1/hal_8074v1.c

@@ -1,47 +1,123 @@
 /*
- * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
-
 #include "hal_hw_headers.h"
 #include "hal_internal.h"
 #include "hal_api.h"
 #include "target_type.h"
 #include "wcss_version.h"
 #include "qdf_module.h"
-#include "hal_8074_tx.h"
-#include "hal_8074_rx.h"
+
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
+	RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB
+#define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
+	PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
+	PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
+	PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
+	PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET
+#define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
+	PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
+	RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
+	RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
+#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
+	REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
+	UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
+#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \
+	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
+#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
+	RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
+#define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
+	TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
+#define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
+	TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
+#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
+	BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
+	BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
+	BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
+	BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
+	BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
+	BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
+	BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
+	BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB
+
+#include "hal_8074v1_tx.h"
+#include "hal_8074v1_rx.h"
+#include <hal_generic_api.h>
+#include <hal_wbm.h>
+
 
 struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
+
+	/* init and setup */
+	hal_srng_dst_hw_init_generic,
+	hal_srng_src_hw_init_generic,
+	hal_reo_setup_generic,
+	hal_setup_link_idle_list_generic,
+
 	/* tx */
 	hal_tx_desc_set_dscp_tid_table_id_8074,
 	hal_tx_set_dscp_tid_map_8074,
 	hal_tx_update_dscp_tid_8074,
 	hal_tx_desc_set_lmac_id_8074,
+	hal_tx_desc_set_buf_addr_generic,
+	hal_tx_comp_get_status_generic,
 
 	/* rx */
 	hal_rx_msdu_start_nss_get_8074,
@@ -54,6 +130,10 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
 	hal_rx_mpdu_start_tid_get_8074,
 	hal_rx_msdu_start_reception_type_get_8074,
 	hal_rx_msdu_end_da_idx_get_8074,
+	hal_rx_msdu_desc_info_get_ptr_generic,
+	hal_rx_link_desc_msdu0_ptr_generic,
+	hal_reo_status_get_header_generic,
+	hal_rx_status_get_tlv_info_generic,
 };
 
 struct hal_hw_srng_config hw_srng_table_8074[] = {
@@ -498,6 +578,10 @@ int32_t hal_hw_reg_offset_qca8074[] = {
 	REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1),
 };
 
+/**
+ * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops,
+ *			  offset and srng table
+ */
 void hal_qca8074_attach(struct hal_soc *hal_soc)
 {
 	hal_soc->hw_srng_table = hw_srng_table_8074;

hal/wifi3.0/qca8074/hal_8074_rx.h → hal/wifi3.0/qca8074v1/hal_8074v1_rx.h

@@ -1,32 +1,20 @@
 /*
- * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
-
 #include "hal_hw_headers.h"
 #include "hal_internal.h"
 #include "cdp_txrx_mon_struct.h"

hal/wifi3.0/qca8074/hal_8074_tx.h → hal/wifi3.0/qca8074v1/hal_8074v1_tx.h

@@ -1,32 +1,20 @@
 /*
- * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above
- *       copyright notice, this list of conditions and the following
- *       disclaimer in the documentation and/or other materials provided
- *       with the distribution.
- *     * Neither the name of The Linux Foundation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
  *
- * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
- * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
- * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
- * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
  */
-
 #include "hal_hw_headers.h"
 #include "hal_internal.h"
 #include "cdp_txrx_mon_struct.h"

hal/wifi3.0/qca8074v2/hal_8074v2.c

@@ -0,0 +1,594 @@
+/*
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "hal_hw_headers.h"
+#include "hal_internal.h"
+#include "hal_api.h"
+#include "target_type.h"
+#include "wcss_version.h"
+#include "qdf_module.h"
+
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
+	RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
+	RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
+#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
+	RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
+#define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
+	PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
+#define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
+	PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
+#define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
+	PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
+#define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
+	PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
+#define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
+	PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
+#define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
+	PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
+#define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
+	RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
+#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
+	RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
+#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
+#define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
+#define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
+	REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
+#define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
+	STATUS_HEADER_REO_STATUS_NUMBER
+#define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
+	STATUS_HEADER_TIMESTAMP
+#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
+	RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
+#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
+	RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
+#define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
+	TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
+#define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
+	TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
+#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
+	BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
+	BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
+	BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
+	BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
+	BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
+	BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
+#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
+	BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
+#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
+	BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
+#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
+	TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
+#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
+	WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
+#include "hal_8074v2_tx.h"
+#include "hal_8074v2_rx.h"
+#include <hal_generic_api.h>
+#include <hal_wbm.h>
+
+struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
+
+	/* init and setup */
+	hal_srng_dst_hw_init_generic,
+	hal_srng_src_hw_init_generic,
+	hal_reo_setup_generic,
+	hal_setup_link_idle_list_generic,
+
+	/* tx */
+	hal_tx_desc_set_dscp_tid_table_id_8074v2,
+	hal_tx_set_dscp_tid_map_8074v2,
+	hal_tx_update_dscp_tid_8074v2,
+	hal_tx_desc_set_lmac_id_8074v2,
+	hal_tx_desc_set_buf_addr_generic,
+	hal_tx_comp_get_status_generic,
+
+	/* rx */
+	hal_rx_msdu_start_nss_get_8074v2,
+	hal_rx_mon_hw_desc_get_mpdu_status_8074v2,
+	hal_rx_get_tlv_8074v2,
+	hal_rx_proc_phyrx_other_receive_info_tlv_8074v2,
+	hal_rx_dump_msdu_start_tlv_8074v2,
+	hal_rx_dump_msdu_end_tlv_8074v2,
+	hal_get_link_desc_size_8074v2,
+	hal_rx_mpdu_start_tid_get_8074v2,
+	hal_rx_msdu_start_reception_type_get_8074v2,
+	hal_rx_msdu_end_da_idx_get_8074v2,
+	hal_rx_msdu_desc_info_get_ptr_generic,
+	hal_rx_link_desc_msdu0_ptr_generic,
+	hal_reo_status_get_header_generic,
+	hal_rx_status_get_tlv_info_generic,
+};
+
+struct hal_hw_srng_config hw_srng_table_8074v2[] = {
+	/* TODO: max_rings can populated by querying HW capabilities */
+	{ /* REO_DST */
+		.start_ring_id = HAL_SRNG_REO2SW1,
+		.max_rings = 4,
+		.entry_size = sizeof(struct reo_destination_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET),
+			HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET)
+		},
+		.reg_size = {
+			HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
+				HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
+			HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
+				HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
+		},
+		.max_size =
+			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_EXCEPTION */
+		/* Designating REO2TCL ring as exception ring. This ring is
+		 * similar to other REO2SW rings though it is named as REO2TCL.
+		 * Any of theREO2SW rings can be used as exception ring.
+		 */
+		.start_ring_id = HAL_SRNG_REO2TCL,
+		.max_rings = 1,
+		.entry_size = sizeof(struct reo_destination_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET),
+			HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET)
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+			HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_REINJECT */
+		.start_ring_id = HAL_SRNG_SW2REO,
+		.max_rings = 1,
+		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET),
+			HWIO_REO_R2_SW2REO_RING_HP_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET)
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
+				HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_CMD */
+		.start_ring_id = HAL_SRNG_REO_CMD,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct reo_get_queue_stats)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET),
+			HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_STATUS */
+		.start_ring_id = HAL_SRNG_REO_STATUS,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct reo_get_queue_stats_status)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET),
+			HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
+				SEQ_WCSS_UMAC_REO_REG_OFFSET),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_DATA */
+		.start_ring_id = HAL_SRNG_SW2TCL1,
+		.max_rings = 3,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct tcl_data_cmd)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
+				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
+			HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
+				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
+		},
+		.reg_size = {
+			HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
+				HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
+			HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
+				HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
+		},
+		.max_size =
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_CMD */
+		.start_ring_id = HAL_SRNG_SW2TCL_CMD,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct tcl_gse_cmd)) >> 2,
+		.lmac_ring =  FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
+				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
+			HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
+				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+			HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_STATUS */
+		.start_ring_id = HAL_SRNG_TCL_STATUS,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct tcl_status_ring)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
+				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
+			HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
+				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_SRC */
+		.start_ring_id = HAL_SRNG_CE_0_SRC,
+		.max_rings = 12,
+		.entry_size = sizeof(struct ce_src_desc) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
+		HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
+		},
+		.reg_size = {
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
+		},
+		.max_size =
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_DST */
+		.start_ring_id = HAL_SRNG_CE_0_DST,
+		.max_rings = 12,
+		.entry_size = 8 >> 2,
+		/*TODO: entry_size above should actually be
+		 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
+		 * of struct ce_dst_desc in HW header files
+		 */
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
+		HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
+		},
+		.reg_size = {
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
+		},
+		.max_size =
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_DST_STATUS */
+		.start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
+		.max_rings = 12,
+		.entry_size = sizeof(struct ce_stat_desc) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
+		HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
+		},
+			/* TODO: check destination status ring registers */
+		.reg_size = {
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
+		},
+		.max_size =
+		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* WBM_IDLE_LINK */
+		.start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
+		HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+			HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
+				HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* SW2WBM_RELEASE */
+		.start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_release_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
+		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* WBM2SW_RELEASE */
+		.start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
+		.max_rings = 4,
+		.entry_size = sizeof(struct wbm_release_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
+			HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
+		},
+		.reg_size = {
+			HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
+				HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
+			HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
+				HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
+		},
+		.max_size =
+			HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
+				HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* RXDMA_BUF */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
+#ifdef IPA_OFFLOAD
+		.max_rings = 3,
+#else
+		.max_rings = 2,
+#endif
+		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+	{ /* RXDMA_DST */
+		.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
+		.max_rings = 1,
+		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
+		.lmac_ring =  TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+	{ /* RXDMA_MONITOR_BUF */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+	{ /* RXDMA_MONITOR_STATUS */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+	{ /* RXDMA_MONITOR_DST */
+		.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
+		.max_rings = 1,
+		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+	{ /* RXDMA_MONITOR_DESC */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+	{ /* DIR_BUF_RX_DMA_SRC */
+		.start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
+		.max_rings = 1,
+		.entry_size = 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+#ifdef WLAN_FEATURE_CIF_CFR
+	{ /* WIFI_POS_SRC */
+		.start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
+		.max_rings = 1,
+		.entry_size = sizeof(wmi_oem_dma_buf_release_entry)  >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+#endif
+};
+
+int32_t hal_hw_reg_offset_qca8074v2[] = {
+	/* dst */
+	REG_OFFSET(DST, HP),
+	REG_OFFSET(DST, TP),
+	REG_OFFSET(DST, ID),
+	REG_OFFSET(DST, MISC),
+	REG_OFFSET(DST, HP_ADDR_LSB),
+	REG_OFFSET(DST, HP_ADDR_MSB),
+	REG_OFFSET(DST, MSI1_BASE_LSB),
+	REG_OFFSET(DST, MSI1_BASE_MSB),
+	REG_OFFSET(DST, MSI1_DATA),
+	REG_OFFSET(DST, BASE_LSB),
+	REG_OFFSET(DST, BASE_MSB),
+	REG_OFFSET(DST, PRODUCER_INT_SETUP),
+	/* src */
+	REG_OFFSET(SRC, HP),
+	REG_OFFSET(SRC, TP),
+	REG_OFFSET(SRC, ID),
+	REG_OFFSET(SRC, MISC),
+	REG_OFFSET(SRC, TP_ADDR_LSB),
+	REG_OFFSET(SRC, TP_ADDR_MSB),
+	REG_OFFSET(SRC, MSI1_BASE_LSB),
+	REG_OFFSET(SRC, MSI1_BASE_MSB),
+	REG_OFFSET(SRC, MSI1_DATA),
+	REG_OFFSET(SRC, BASE_LSB),
+	REG_OFFSET(SRC, BASE_MSB),
+	REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0),
+	REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1),
+};
+
+
+/**
+ * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops,
+ *			  offset and srng table
+ */
+void hal_qca8074v2_attach(struct hal_soc *hal_soc)
+{
+	hal_soc->hw_srng_table = hw_srng_table_8074v2;
+	hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2;
+	hal_soc->ops = &qca8074v2_hal_hw_txrx_ops;
+}
+
+
+

hal/wifi3.0/qca8074v2/hal_8074v2_rx.h

@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "hal_hw_headers.h"
+#include "hal_internal.h"
+#include "cdp_txrx_mon_struct.h"
+#include "qdf_trace.h"
+#include "hal_rx.h"
+#include "hal_tx.h"
+#include "dp_types.h"
+#include "hal_api_mon.h"
+
+#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
+	RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)),	\
+	RX_MSDU_START_5_MIMO_SS_BITMAP_MASK,		\
+	RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
+/*
+ * hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS
+ * Interval from rx_msdu_start
+ *
+ * @buf: pointer to the start of RX PKT TLV header
+ * Return: uint32_t(nss)
+ */
+static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_msdu_start *msdu_start =
+				&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
+	uint8_t mimo_ss_bitmap;
+
+	mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
+
+	return qdf_get_hweight8(mimo_ss_bitmap);
+}
+
+/**
+ * hal_rx_mon_hw_desc_get_mpdu_status_8074v2(): Retrieve MPDU status
+ *
+ * @ hw_desc_addr: Start address of Rx HW TLVs
+ * @ rs: Status for monitor mode
+ *
+ * Return: void
+ */
+static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr,
+						    struct mon_rx_status *rs)
+{
+	struct rx_msdu_start *rx_msdu_start;
+	struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
+	uint32_t reg_value;
+	const uint32_t sgi_hw_to_cdp[] = {
+		CDP_SGI_0_8_US,
+		CDP_SGI_0_4_US,
+		CDP_SGI_1_6_US,
+		CDP_SGI_3_2_US,
+	};
+
+	rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
+
+	HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
+
+	rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
+				RX_MSDU_START_5, USER_RSSI);
+	rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
+
+	reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
+	rs->sgi = sgi_hw_to_cdp[reg_value];
+	reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, PKT_TYPE);
+	switch (reg_value) {
+	case HAL_RX_PKT_TYPE_11N:
+		rs->ht_flags = 1;
+		break;
+	case HAL_RX_PKT_TYPE_11AC:
+		rs->vht_flags = 1;
+		reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5,
+				       RECEIVE_BANDWIDTH);
+		rs->vht_flag_values2 = reg_value;
+		break;
+	case HAL_RX_PKT_TYPE_11AX:
+		rs->he_flags = 1;
+		break;
+	default:
+		break;
+	}
+	reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
+	rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
+	/* TODO: rs->beamformed should be set for SU beamforming also */
+}
+
+#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
+static uint32_t hal_get_link_desc_size_8074v2(void)
+{
+	return LINK_DESC_SIZE;
+}
+
+/*
+ * hal_rx_get_tlv_8074v2(): API to get the tlv
+ *
+ * @rx_tlv: TLV data extracted from the rx packet
+ * Return: uint8_t
+ */
+static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv)
+{
+	return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
+}
+
+/**
+ * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2()
+ *				      -process other receive info TLV
+ * @rx_tlv_hdr: pointer to TLV header
+ * @ppdu_info: pointer to ppdu_info
+ *
+ * Return: None
+ */
+static
+void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr,
+						   void *ppdu_info)
+{
+}
+
+
+/**
+ * hal_rx_dump_msdu_start_tlv_8074v2() : dump RX msdu_start TLV in structured
+ *			     human readable format.
+ * @ msdu_start: pointer the msdu_start TLV in pkt.
+ * @ dbg_level: log level.
+ *
+ * Return: void
+ */
+static void hal_rx_dump_msdu_start_tlv_8074v2(void *msdustart,
+					    uint8_t dbg_level)
+{
+	struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
+
+	QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
+			"rx_msdu_start tlv - "
+			"rxpcu_mpdu_filter_in_category: %d "
+			"sw_frame_group_id: %d "
+			"phy_ppdu_id: %d "
+			"msdu_length: %d "
+			"ipsec_esp: %d "
+			"l3_offset: %d "
+			"ipsec_ah: %d "
+			"l4_offset: %d "
+			"msdu_number: %d "
+			"decap_format: %d "
+			"ipv4_proto: %d "
+			"ipv6_proto: %d "
+			"tcp_proto: %d "
+			"udp_proto: %d "
+			"ip_frag: %d "
+			"tcp_only_ack: %d "
+			"da_is_bcast_mcast: %d "
+			"ip4_protocol_ip6_next_header: %d "
+			"toeplitz_hash_2_or_4: %d "
+			"flow_id_toeplitz: %d "
+			"user_rssi: %d "
+			"pkt_type: %d "
+			"stbc: %d "
+			"sgi: %d "
+			"rate_mcs: %d "
+			"receive_bandwidth: %d "
+			"reception_type: %d "
+			"ppdu_start_timestamp: %d "
+			"sw_phy_meta_data: %d ",
+			msdu_start->rxpcu_mpdu_filter_in_category,
+			msdu_start->sw_frame_group_id,
+			msdu_start->phy_ppdu_id,
+			msdu_start->msdu_length,
+			msdu_start->ipsec_esp,
+			msdu_start->l3_offset,
+			msdu_start->ipsec_ah,
+			msdu_start->l4_offset,
+			msdu_start->msdu_number,
+			msdu_start->decap_format,
+			msdu_start->ipv4_proto,
+			msdu_start->ipv6_proto,
+			msdu_start->tcp_proto,
+			msdu_start->udp_proto,
+			msdu_start->ip_frag,
+			msdu_start->tcp_only_ack,
+			msdu_start->da_is_bcast_mcast,
+			msdu_start->ip4_protocol_ip6_next_header,
+			msdu_start->toeplitz_hash_2_or_4,
+			msdu_start->flow_id_toeplitz,
+			msdu_start->user_rssi,
+			msdu_start->pkt_type,
+			msdu_start->stbc,
+			msdu_start->sgi,
+			msdu_start->rate_mcs,
+			msdu_start->receive_bandwidth,
+			msdu_start->reception_type,
+			msdu_start->ppdu_start_timestamp,
+			msdu_start->sw_phy_meta_data);
+}
+
+/**
+ * hal_rx_dump_msdu_end_tlv_8074v2: dump RX msdu_end TLV in structured
+ *			     human readable format.
+ * @ msdu_end: pointer the msdu_end TLV in pkt.
+ * @ dbg_level: log level.
+ *
+ * Return: void
+ */
+static void hal_rx_dump_msdu_end_tlv_8074v2(void *msduend,
+					  uint8_t dbg_level)
+{
+	struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
+
+	QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
+			"rx_msdu_end tlv - "
+			"rxpcu_mpdu_filter_in_category: %d "
+			"sw_frame_group_id: %d "
+			"phy_ppdu_id: %d "
+			"ip_hdr_chksum: %d "
+			"tcp_udp_chksum: %d "
+			"key_id_octet: %d "
+			"cce_super_rule: %d "
+			"cce_classify_not_done_truncat: %d "
+			"cce_classify_not_done_cce_dis: %d "
+			"ext_wapi_pn_63_48: %d "
+			"ext_wapi_pn_95_64: %d "
+			"ext_wapi_pn_127_96: %d "
+			"reported_mpdu_length: %d "
+			"first_msdu: %d "
+			"last_msdu: %d "
+			"sa_idx_timeout: %d "
+			"da_idx_timeout: %d "
+			"msdu_limit_error: %d "
+			"flow_idx_timeout: %d "
+			"flow_idx_invalid: %d "
+			"wifi_parser_error: %d "
+			"amsdu_parser_error: %d "
+			"sa_is_valid: %d "
+			"da_is_valid: %d "
+			"da_is_mcbc: %d "
+			"l3_header_padding: %d "
+			"ipv6_options_crc: %d "
+			"tcp_seq_number: %d "
+			"tcp_ack_number: %d "
+			"tcp_flag: %d "
+			"lro_eligible: %d "
+			"window_size: %d "
+			"da_offset: %d "
+			"sa_offset: %d "
+			"da_offset_valid: %d "
+			"sa_offset_valid: %d "
+			"rule_indication_31_0: %d "
+			"rule_indication_63_32: %d "
+			"sa_idx: %d "
+			"msdu_drop: %d "
+			"reo_destination_indication: %d "
+			"flow_idx: %d "
+			"fse_metadata: %d "
+			"cce_metadata: %d "
+			"sa_sw_peer_id: %d ",
+			msdu_end->rxpcu_mpdu_filter_in_category,
+			msdu_end->sw_frame_group_id,
+			msdu_end->phy_ppdu_id,
+			msdu_end->ip_hdr_chksum,
+			msdu_end->tcp_udp_chksum,
+			msdu_end->key_id_octet,
+			msdu_end->cce_super_rule,
+			msdu_end->cce_classify_not_done_truncate,
+			msdu_end->cce_classify_not_done_cce_dis,
+			msdu_end->ext_wapi_pn_63_48,
+			msdu_end->ext_wapi_pn_95_64,
+			msdu_end->ext_wapi_pn_127_96,
+			msdu_end->reported_mpdu_length,
+			msdu_end->first_msdu,
+			msdu_end->last_msdu,
+			msdu_end->sa_idx_timeout,
+			msdu_end->da_idx_timeout,
+			msdu_end->msdu_limit_error,
+			msdu_end->flow_idx_timeout,
+			msdu_end->flow_idx_invalid,
+			msdu_end->wifi_parser_error,
+			msdu_end->amsdu_parser_error,
+			msdu_end->sa_is_valid,
+			msdu_end->da_is_valid,
+			msdu_end->da_is_mcbc,
+			msdu_end->l3_header_padding,
+			msdu_end->ipv6_options_crc,
+			msdu_end->tcp_seq_number,
+			msdu_end->tcp_ack_number,
+			msdu_end->tcp_flag,
+			msdu_end->lro_eligible,
+			msdu_end->window_size,
+			msdu_end->da_offset,
+			msdu_end->sa_offset,
+			msdu_end->da_offset_valid,
+			msdu_end->sa_offset_valid,
+			msdu_end->rule_indication_31_0,
+			msdu_end->rule_indication_63_32,
+			msdu_end->sa_idx,
+			msdu_end->msdu_drop,
+			msdu_end->reo_destination_indication,
+			msdu_end->flow_idx,
+			msdu_end->fse_metadata,
+			msdu_end->cce_metadata,
+			msdu_end->sa_sw_peer_id);
+}
+
+
+/*
+ * Get tid from RX_MPDU_START
+ */
+#define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info),	\
+		RX_MPDU_INFO_3_TID_OFFSET)),		\
+		RX_MPDU_INFO_3_TID_MASK,		\
+		RX_MPDU_INFO_3_TID_LSB))
+
+static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_mpdu_start *mpdu_start =
+			&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
+	uint32_t tid;
+
+	tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
+
+	return tid;
+}
+
+#define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),	\
+	RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)),	\
+	RX_MSDU_START_5_RECEPTION_TYPE_MASK,		\
+	RX_MSDU_START_5_RECEPTION_TYPE_LSB))
+
+/*
+ * hal_rx_msdu_start_reception_type_get(): API to get the reception type
+ * Interval from rx_msdu_start
+ *
+ * @buf: pointer to the start of RX PKT TLV header
+ * Return: uint32_t(reception_type)
+ */
+static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_msdu_start *msdu_start =
+		&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
+	uint32_t reception_type;
+
+	reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
+
+	return reception_type;
+}
+
+/* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */
+#define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end)		\
+	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end,		\
+		RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)),	\
+		RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK,	\
+		RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB))
+ /**
+ * hal_rx_msdu_end_da_idx_get_8074v2: API to get da_idx
+ * from rx_msdu_end TLV
+ *
+ * @ buf: pointer to the start of RX PKT TLV headers
+ * Return: da index
+ */
+static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf)
+{
+	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
+	struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
+	uint16_t da_idx;
+
+	da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
+
+	return da_idx;
+}
+

hal/wifi3.0/qca8074v2/hal_8074v2_tx.h

@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "hal_hw_headers.h"
+#include "hal_internal.h"
+#include "cdp_txrx_mon_struct.h"
+#include "qdf_trace.h"
+#include "hal_rx.h"
+#include "hal_tx.h"
+#include "dp_types.h"
+#include "hal_api_mon.h"
+
+/**
+ * hal_tx_desc_set_dscp_tid_table_id_8074v2() - Sets DSCP to TID conversion
+ *						table ID
+ * @desc: Handle to Tx Descriptor
+ * @id: DSCP to tid conversion table to be used for this frame
+ *
+ * Return: void
+ */
+
+static void hal_tx_desc_set_dscp_tid_table_id_8074v2(void *desc, uint8_t id)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_5,
+			DSCP_TID_TABLE_NUM) |=
+		HAL_TX_SM(TCL_DATA_CMD_5,
+				DSCP_TID_TABLE_NUM, id);
+}
+
+
+#define DSCP_TID_TABLE_SIZE 24
+#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
+/**
+ * hal_tx_set_dscp_tid_map_8074v2() - Configure default DSCP to TID map table
+ * @soc: HAL SoC context
+ * @map: DSCP-TID mapping table
+ * @id: mapping table ID - 0,1
+ *
+ * DSCP are mapped to 8 TID values using TID values programmed
+ * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0)
+ * and DSCP_TID2_MAP_<0 to 6> (id = 1)
+ * Each mapping register has TID mapping for 10 DSCP values
+ *
+ * Return: none
+ */
+
+static void hal_tx_set_dscp_tid_map_8074v2(void *hal_soc, uint8_t *map,
+					 uint8_t id)
+{
+	int i;
+	uint32_t addr, cmn_reg_addr;
+	uint32_t value = 0, regval;
+	uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
+
+	struct hal_soc *soc = (struct hal_soc *)hal_soc;
+
+	if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX)
+		return;
+
+	cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
+					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
+
+	addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
+				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
+				id * NUM_WORDS_PER_DSCP_TID_TABLE);
+
+	/* Enable read/write access */
+	regval = HAL_REG_READ(soc, cmn_reg_addr);
+	regval |=
+	(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
+
+	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
+
+	/* Write 8 (24 bits) DSCP-TID mappings in each interation */
+	for (i = 0; i < 64; i += 8) {
+		value = (map[i] |
+			(map[i + 1] << 0x3) |
+			(map[i + 2] << 0x6) |
+			(map[i + 3] << 0x9) |
+			(map[i + 4] << 0xc) |
+			(map[i + 5] << 0xf) |
+			(map[i + 6] << 0x12) |
+			(map[i + 7] << 0x15));
+
+		qdf_mem_copy(&val[cnt], (void *)&value, 3);
+		cnt += 3;
+	}
+
+	for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
+		regval = *(uint32_t *)(val + i);
+		HAL_REG_WRITE(soc, addr,
+			      (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
+		addr += 4;
+	}
+
+	/* Diasble read/write access */
+	regval = HAL_REG_READ(soc, cmn_reg_addr);
+	regval &=
+	~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
+
+	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
+}
+
+/**
+ * hal_tx_update_dscp_tid_8074v2() - Update the dscp tid map table as
+					updated by user
+ * @soc: HAL SoC context
+ * @map: DSCP-TID mapping table
+ * @id : MAP ID
+ * @dscp: DSCP_TID map index
+ *
+ * Return: void
+ */
+
+static void hal_tx_update_dscp_tid_8074v2(void *hal_soc, uint8_t tid,
+					uint8_t id, uint8_t dscp)
+{
+	int index;
+	uint32_t addr;
+	uint32_t value;
+	uint32_t regval;
+	struct hal_soc *soc = (struct hal_soc *)hal_soc;
+
+	addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
+			SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id);
+
+	index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
+	addr += 4 * (dscp / HAL_TX_NUM_DSCP_PER_REGISTER);
+	value = tid << (HAL_TX_BITS_PER_TID * index);
+
+	regval = HAL_REG_READ(soc, addr);
+	regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
+	regval |= value;
+
+	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
+}
+/**
+ * hal_tx_desc_set_lmac_id - Set the lmac_id value
+ * @desc: Handle to Tx Descriptor
+ * @lmac_id: mac Id to ast matching
+ *		     b00 – mac 0
+ *		     b01 – mac 1
+ *		     b10 – mac 2
+ *		     b11 – all macs (legacy HK way)
+ *
+ * Return: void
+ */
+static void hal_tx_desc_set_lmac_id_8074v2(void *desc, uint8_t lmac_id)
+{
+	HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
+		HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
+}
+

hif/src/hif_main.c

@@ -38,9 +38,7 @@
 #include "qdf_status.h"
 #include "hif_debug.h"
 #include "mp_dev.h"
-#ifdef QCA_WIFI_QCA8074
 #include "hal_api.h"
-#endif
 #include "hif_napi.h"
 #include "hif_unit_test_suspend_i.h"
 #include "qdf_module.h"