WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
HW macros used for hal_rx_wbm_err_info_get_generic_li are
different across chipset. Move this API to header file to
ensure chipset specific HAL is compiled with appropriate
HW headers
Change-Id: I053d243235f187d931048d1fd22293f9142a00c7
hal_reg_write_need_delay is invoked immediately after
q_elem->valid check. The first two instructions in
hal_reg_write_need_delay could be in the CPU instruction
pipeline which could result in possible loading and
dereferencing of NULL srng from an invalid q_elem.
Fix is to invoke hal_reg_write_need_delay just before
hal_process_reg_write_q_elem and also add NULL checks
to avoid the srng NULL pointer dereference.
Change-Id: I2de50b1e78782e3c91a9cb4477f28d91f9c29439
CRs-Fixed: 2973257
To fix the below compilation error, included "hal_be_rx_tlv.h" header file
in hal_be_generic_api.c file.
"cmn_dev/hal/wifi3.0/be/hal_be_generic_api.c:754:40: error:
'hal_rx_tlv_get_pn_num_be' undeclared (first use in this function);
did you mean 'hal_rx_tlv_get_pn_num'?"
Change-Id: I57074967dad8cee98fc8094c4eadc9289b7e7984
CRs-Fixed: 2974607
PN number get function handler is not initialized,
This lead to CFI assert. Add correct handlers for
differnt chipsets.
Change-Id: Ib8836af0d69380da597822d1755bb5dd2309c95f
CRs-Fixed: 2968223
Return LMAC start id also as part of hal_get_meminfo API.
This field is added to hal_mem_info struct.
Change-Id: I013d357cf4337702c06a91ed15e8337469865270
Refactor FISA packet history to not access "struct rx_pkt_tlvs". This is
because this structure may be different for Li and BE chips and should
not be accessed directly and only via hal_soc->ops in common code.
CRs-Fixed: 2888556
Change-Id: I0d9f2785a81c130a2dc506020a02ee5581c0bbd3
Implement core DP rx processing to functions in to corresponding
architecture specific be/li rx files. Keep common utility functions
in DP common files.
Change-Id: I40083e10772fd2b6ce2f1fa9e197f2ad92d0522a
CRs-Fixed: 2891021
Add the changes to the generic HAL APIs.
The APIs generic across lithium and beryllium
architecture are kept in common HAL code.
The APIs which are generic across lithium
chipsets are moved to lithium specific files.
The APIs which are generic across beryllium
chipsets are kept in beryllium specific files.
Change-Id: Ie5e28aca5de02aa42f63b4a13fcb1cb32ffa8a28
CRs-Fixed: 2891049
Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.
This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).
Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
Introduce intermediate EP voting state during this transition state
access the votes only if direct writes are not possible.
Change-Id: Ib4522aef2209b4797100ca84e4e230a00e14b654
CRs-Fixed: 2954903
While Rx buffers are getting umapped from net rx context if IPA
pipes are enabled at same time from MC thread context this is
leading to race condition and IPA map/unmap is going out of sync.
To fix this introducing IPA mapping lock and IPA mapping need to
be handled with lock held.
Change-Id: I9fa71bdb6d4e4aa93fc795cc5dd472a181325991
CRs-Fixed: 2945063
Even though HP/TP updates are posted writes at CPU level, they
are getting blocked until soc comes out retention which is hogging
CPU.
To avoid this if EP is in low power state update HP/TP writes from
delayed work context. In delayed work vote for EP awake wait till it
comes out low power state and then proceed to HP/TP update.
Change-Id: I61d5795f58f25f850b5a9ad4d30e3181dba23713
CRs-Fixed: 2913495
hal_get_entrysize_from_srng returns the entry size
in dwords but the caller expects in bytes. This results
in insufficient data to be recorded for CE event.
Fix is to left shift the entry size by two bits in
hal_get_entrysize_from_srng so that the entry size
value returned is in bytes.
Change-Id: If532da7abe5ce9c293969f0052455085f18b1926
CRs-Fixed: 2935196
Add iwpriv option 34 to dump the reo rx h/w descs
in DDR for debugging. This cmd will first send cache
flush cmd to REO for all rx tids and invalidate the h/w
cache. Henceforth ensuring that the reo status tlvs and
the DDR values are in sync.
iwpriv wlan0 txrx_stats 34 0
Add fix to ensure bar frame with 2k jump err code is
processed correctly using the REO error code instead of the
REO push reason.
Change-Id: Ia05be668343f3a5d4b3262b8d6a367a50875add5
CRs-Fixed: 2895965
When a msdu scattered across multiple nbufs is received
in REO2SW ring and the remaining nbufs are not yet
available in the ring, loop in dp_rx_process is exited
without resetting the invalid bit in the ring desc cookie.
This will result in an incorrect assertion failure when
the same entry is processed the next time.
Fix is to reset the invalid bit in ring desc cookie
when the loop is exited in the above msdu scattered
scenario.
Change-Id: Ie5cfa1fb8ea1db4b7a0a4837545ecbfdfbb8719a
CRs-Fixed: 2916296
To support IPA TX two pipes, WBM2SW4 is added as second WBM2IPA TX
transfer ring.
Change-Id: Id0762003c1d91e3614b15df2bc51f90e27add43c
CRs-Fixed: 2750073
Add support to update CE srngs HP/TP in delayed manner
for QCA6750 target. This avoids busy wait in register update.
Change-Id: Id825a6fdf709187765ff823cb3015db21a024af3
CRs-Fixed: 2894094
Add wbm head/tail pointer stats to dp_txrx_stats and ring
usage percentage for all SRC and DST rings.
Stats added to the following cmd: iwpriv wlan0 txrx_stats 26 0
CRs-Fixed: 2865996
Change-Id: I7d144d87c5f3485ec9ba85f50b036b69a64e53c6
For the minidump feature, the wlan_minidump_remove function
definition is modified. So, update the function parameters
accordingly at all instances of the wlan_minidump_remove function.
Change-Id: I5a346f6cdf423ece02fb08d68e4422251af54876
CRs-Fixed: 2860435
Enable force wake recipe feature DEVICE_FORCE_WAKE_ENABLE
and disable the generic shadow register write feature
GENERIC_SHADOW_REGISTER_ACCESS_ENABLE.
Force wake recipe will be used to write to the REO remap
control registers by waking up the UMAC instead of using
shadow register writes.
Assert soc wake reg and poll on the scratch reg to check
if UMAC is awake.
Enable HIF_REG_WINDOW_SUPPORT to enable windowed reg
read/write in HIF layer.
Change-Id: Ib696e27e19a07c0084c097b95b7780b56e643c8b
CRs-Fixed: 2850590
Add delayed SRNG register writes support for Tx Ring, also add
dedicated workqueue to do the delayed Tx SRNG register writes.
Change-Id: I8dd157d341f3035e988804eab50d1ca681ab789b
CRs-Fixed: 2868989
For hastings, it has two dma rx rings, and the first
one is for spectral scan, and the second one is for CFR.
So increase the max supported rings number from 1 to
2.
Change-Id: I85500bba366a4321ebc91e92f72146dd20311d03
CRs-Fixed:
Use macros like dp_cdp_debug, dp_cdp_err, dp_cdp_info to
print logs for QDF_MODULE_ID_CDP
Change-Id: I550eefa82c3417b8bf83378d4a9c6f382098fea6
CRs-Fixed: 2855937
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.
Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.
Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
mu code is not sending frequency in top 16 bits of tlv.
this check makes sure not to check for freq 0 and still be able to use
channel to generate freq.
Change-Id: If18c400e51bc41f8fec4fd50bdd180adfd79e578
