提交图

1817 次代码提交

作者 SHA1 备注 提交日期
Samantha Tran
bb6569b1ab disp: msm: gem_free_object removed from drm
Commit 1a9458aeb8eb ("drm: remove drm_driver::gem_free_object")
deprecates gem_free_object. This changes updates the msm driver
to call msm_gem_free_object from gem_free_object_unlocked.

Change-Id: If6bd6252232045975357e1bdfbeae6017b0f2ed5
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-17 09:49:19 -05:00
Samantha Tran
57c40f17c2 disp: msm: remove usage of DRM_DEBUG_DRIVER_RATELIMITED
Commit 7ff6ea0fd384 ("drm/print: Delete a few unused
shouting macros") removes the usage of
DRM_DEBUG_DRIVER_RATELIMITED. This changes updates
the relevant changes to the msm driver, printing through
DRM_DEBUG instead.

Change-Id: I910f0fe72d045e69dda966249437dcd004790f29
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-17 09:49:19 -05:00
Samantha Tran
b5784e4724 disp: msm: dp: renaming DP_TEST_PHY_PATTERN
Commit 4342f839ae7e ("drm/dp: get/set phy compliance pattern")
swaps TEST_PHY with PHY_TEST in drm_dp_helper header file. This
changes updates the relevant changes in the dp driver.

Change-Id: I5c24a100022277388af530c526f169a03c6df889
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2020-12-17 09:49:19 -05:00
Samantha Tran
6fa94ff382 disp: msm: rename drm_gem_object_put functions
Commit b5d250744ccc ("drm/gem: fold drm_gem_object_put_unlocked
and __drm_gem_object_put()"), commit eecd7fd8bf58 (drm/gem: add
_locked suffix to drm_gem_object_put", commit be6ee102341b ("drm:
remove _unlocked suffix in drm_object_put_unlocked") updates
the drm_gem_object_put call APIs. This change updates the relevant
changes to the msm driver.

Change-Id: I006b51b5f3d1f8b2e88ed7b4c73b5a98afcaf455
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-17 09:49:19 -05:00
Samantha Tran
640ada10b5 disp: msm: updates to msm_drv
Commit c368ec194dd0 ("drm/client: Rename _force to _locked"),
commit 4bdc0d676a64 ("remove ioremap_nocache and devm_ioremap_nocache") and
commit 595abbaff5db ("y2038: remove ktime to/from timespec/timeval
conversion") renames modeset_commit_force, renames devm_ioremap_nocache and
removes the usage of timespec. This changes updates the msm driver with
the relevant changes.

Change-Id: Ib7372b8b4e51cdf75771e5069be189be76c32ed4
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-16 17:28:03 -08:00
Samantha Tran
0c08cb1fb5 disp: msm: update parameters for drm_bridge_attach
Commit a25b988ff83f ("drm/bridge: Extend bridge API to
disable connector creation") and commit ee68c743f8d0 ("drm: Stop
including drm_bridge.h from drm_crtc.h) add additional input flags.
This change adds fixes to the drm bridge attach API and includes
relevant drm_bridge header files.

Change-Id: I85e84eaff7df2995243896108a217fae81716b63
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-16 17:27:46 -08:00
Samantha Tran
e68e102598 disp: msm: replace rpmh_flush with rpmh_write_sleep_and_wake
Commit d5e205079c34 ("drivers: qcom: rpmh: remove rpmh_flush export")
deprecates the rpmh_flush API. This change replaces the API with
rpmh_write_sleep_and_wake.

Change-Id: I1fb708b265d8abd981b099eb65b50d6cc73cc64d
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-16 17:26:04 -08:00
Samantha Tran
d2aea44026 disp: msm: dsi: drm_panel_init parameter change
Commit 6dbe0c4b0fc0 ("drm/panel: Initialise panel dev and funcs
through drm_panel_init()") and commit ba2fad4c9648 ("drm/panel:
Add and fill drm_panel type field") modify input parameters for
drm_panel_init. This change updates the relevant changes to the
dsi driver by passing in the device and panel type.

Change-Id: I76a271fea08190bd8633831442ca48882f8a97e6
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-16 17:25:54 -08:00
Samantha Tran
3d1a54ed8d disp: msm: dp: drm_dp_calc_pbn_mode includes dsc enable/disable bool
Commit dc48529fb14e ("drm/dp_mst: Add PBN calculation for DSC modes")
adds support for handling fractional bpp values for dsc usecases.
This change sets this to false since the driver uses unadjusted bpp.

Change-Id: I10b4a74fd512c5ffb333f8664effb5efb8ea6c4e
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-16 17:25:38 -08:00
Samantha Tran
16cc165833 disp: msm: obtain bridge from bridge chain
Commit 05193dc38197 ("drm/bridge: Make the bridge chain
a double-linked list") creates a bridge chain linked
list. This change updates the relevant changes to msm
driver to use the list to find the bridge associated to
the encoder.

Change-Id: I59eb2910be96f4fff7bdbeb040d6ad204c41d747
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-16 17:24:59 -08:00
Samantha Tran
4b150347fc disp: msm: dp: use full_pbn instead of available_pbn
Commit fcf463807596 ("drm/dp_mst: Use full_pbn instead of
available_pbn for bandwidth checks") changes bandwidth checks
to look at the Full PBN bandwidth rather than the available PBN.
This change updates the relevant changes to the dp driver.

Change-Id: I2a713a9b6fd10314bd768331dcea00950b6edf7f
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-16 17:20:53 -08:00
Samantha Tran
6d65c2b613 disp: msm: dsi: pass drm_display_info to mode_valid
Commit 12c683e12cd8 ("drm: bridge: Pass drm_display_info to
drm_bridge_funcs .mode_valid()") passes the drm_display_info to
mode valid. This change updates relevant changes to dsi display,
that will make it available during bridge validation.

Change-Id: I2772e9e3920de940f22341be5019213d562352ff
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-16 17:20:28 -08:00
Alisha Thapaliya
db23860b24 Merge remote-tracking branch 'origin/display-kernel.lnx.5.4' into display-kernel.lnx.5.10
* origin/display-kernel.lnx.5.4:
  disp: msm: dsi: move backlight operations to post kickoff
  disp: msm: sde: cleanup ctl/intf registers on cmd encoder disable
  disp: msm: dsi: enable DMA cmd scheduling for video mode panels
  disp: msm: dp: validate edid before dereferencing
  disp: msm: sde: update encoder atomic check during qsync usecase
  disp: msm: dp: handle link maintenance failures
  disp: msm: dp: fix page fault from hdcp buffer access
  disp: msm: dsi: Add support for 5nm C-PHY shadow clock
  disp: msm: dsi: trigger broadcast commands using DMA start window
  disp: msm: sde: flush all event thread work during CRTC disable
  disp: msm: sde: ignore HW recovery disable event
  disp: msm: dp: remove debug log output in isr
  drm: msm: Reset register when NoiseThresh disabled
  disp: msm: sde: use prepare_commit connector callback for DSI
  disp: msm: sde: retain ubwc settings during LA to LE transition
  disp: msm: sde: always enable prog fetch and fix prefill calculations
  disp: msm: dp: fix DSC and PPS version mismatch
  disp: msm: dp: add support for continuous PPS command
  disp: msm: sde: fix dsc 1_2 rate control parameter

Change-Id: I8f427b6ba706dd04de1b840952a41f2cc3598c2d
2020-12-15 11:24:33 -08:00
qctecmdr
554a3b8b06 Merge "disp: msm: dp: validate edid before dereferencing" 2020-12-14 09:56:07 -08:00
qctecmdr
e0695d4236 Merge "disp: msm: sde: cleanup ctl/intf registers on cmd encoder disable" 2020-12-12 22:39:19 -08:00
qctecmdr
93331df7d7 Merge "disp: msm: dsi: enable DMA cmd scheduling for video mode panels" 2020-12-11 09:49:33 -08:00
Rajeev Nandan
e60959b052 disp: msm: dsi: move backlight operations to post kickoff
This change moves the backlight update operation from
drm bridge enable to connector post kickoff.

When timing engine is enabled with programmable fetch
enabled, the timing engine will start counting from
the prog_fetch_start point (which is somewhere in VFP).
It’s a grey area from that point to the actual panel
vsync and SW should not trigger DMA command during that
time.

During display resume, sometimes the INTF timing engine
do not get enabled completely at the first vblank irq.
The backlight update cmd transfer trigger as part of the
drm bridge enable can also take place at the same time,
that may cause DSI cmd transfer failure.

Change-Id: I2722d3c23012ef0e7bcc7f728ec5658318ce4e60
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2020-12-11 12:14:54 +05:30
Veera Sundaram Sankaran
030e3f15a7 disp: msm: sde: cleanup ctl/intf registers on cmd encoder disable
The SDE RM determines the number of displays enabled in cont-splash by
checking the INTF_ACTIVE bits in the ctl. The trusted-vm relies on the
same cont-splash path during transitions and the stale ctl INTF_ACTIVE
on dual display usecases leads to wrong status check. Currently, only
video/wb encoders use the phys_encoder disable helper during encoder
disable to clear out few ctl/intf registers. Extend it for cmd encoder
as well to remove the stale entries.

Change-Id: I7f21ef46178ce3943ee85abdf29f7cdef93d7c52
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-10 18:37:34 -08:00
Rajeev Nandan
37b2f80ad4 disp: msm: dsi: enable DMA cmd scheduling for video mode panels
This change enables the DMA CMD scheduling as default for
video mode panels.

In video mode panel, if the DMA is triggered very close to
the beginning of the active window and the DMA transfer
happens in the last line of VBP, then the HW state will
stay in ‘wait’ and return to ‘idle’ in the first line of VFP.
But somewhere in the middle of the active window, if SW
disables DSI command mode engine while the HW is still
waiting and re-enable after timing engine is OFF. So the
HW never ‘sees’ another vblank line and hence it gets
stuck in the ‘wait’ state.
Scheduling the DMA cmd to the first line in VFP fixes
this issue.

Change-Id: If9e5bd1923c012f10dee50c791a2b2b001d97553
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
2020-12-10 04:19:33 -08:00
qctecmdr
5caf284ecc Merge "disp: msm: dp: handle link maintenance failures" 2020-12-08 04:44:42 -08:00
qctecmdr
a493aaf3a2 Merge "disp: msm: sde: flush all event thread work during CRTC disable" 2020-12-08 04:44:42 -08:00
qctecmdr
874ebfeeae Merge "disp: msm: dp: fix page fault from hdcp buffer access" 2020-12-08 04:44:42 -08:00
qctecmdr
285589db6a Merge "disp: msm: sde: update encoder atomic check during qsync usecase" 2020-12-07 23:37:28 -08:00
qctecmdr
59a266aa8e Merge "disp: msm: dsi: Add support for 5nm C-PHY shadow clock" 2020-12-07 17:09:16 -08:00
qctecmdr
ef242b391f Merge "disp: msm: dsi: trigger broadcast commands using DMA start window" 2020-12-07 17:09:16 -08:00
Sudarsan Ramesh
c6b636fe0b disp: msm: dp: validate edid before dereferencing
Currently, when using custom edid from debugfs, the
extensions data inside the edid block is not validated
before dereferencing the extension block.

The fix adds a edid validation function to validate
any custom edids before accessing any members in the
edid block.

Change-Id: I8a2cc45477416a8f8c4cff882bd53d14012e29f4
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
2020-12-07 10:02:42 -08:00
Yashwanth
d069726235 disp: msm: sde: update encoder atomic check during qsync usecase
During wb/cwb usecases, connectors_changed flag will be
set and needs modeset condition will be set to true. This
change updates qsync concurrency check with modeset to
fail atomic check only if there is seamless poms, dms or
dynamic clock scenario.

Change-Id: I1183f25cd45310fbd1d0b5ce67ee3d5dd3660fe0
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-12-07 16:15:23 +05:30
Sankeerth Billakanti
0386ae3a6b disp: msm: dp: handle link maintenance failures
Audio off is done before handling link maintenance
requests from sink or receiver. After handling the
link maintenance, audio is enabled without
verifying the success condition of the link
maintenance. If the link maintenance fails, then the
DP link will not be established and source will
not send video data. So, there is no need to
enable audio.

This change will skip the audio enable portion of
the code whenever the link maintenance fails. The
sink may eventually issue another irq_hpd to retry
the link training.

Change-Id: I1e9aab07d6465ab1b5e6f92717ef7288dc85068f
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-12-07 00:07:54 -08:00
Sankeerth Billakanti
656690c02f disp: msm: dp: fix page fault from hdcp buffer access
There are certain cases where the start_auth and cleanup
are scheduled to be executed consecutively on the
sde_hdcp_2x_main thread. When this scenario occurs, the
functions to facilitate hdcp authentication which are
scheduled to execute after the clean needs to be protected
from dereferencing the freed hdcp message buffers.

This change will add a check to prevent dereferencing the
hdcp message buffer after hdcp cleanup is executed.

Change-Id: I669d25b7a6ce751127b1c21228b751eed8da5b38
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
2020-12-07 00:07:46 -08:00
Satya Rama Aditya Pinapala
fcb453c0b8 disp: msm: dsi: Add support for 5nm C-PHY shadow clock
Add support for 5nm DSI PLL C-PHY shadow clocks, which
will be used during dynamic dsi clock switch.

Change-Id: I55b11f2d0cffd8494d4641e9b2de0b88e7229978
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2020-12-05 08:33:29 -08:00
Satya Rama Aditya Pinapala
ae5b602b4f disp: msm: dsi: trigger broadcast commands using DMA start window
As per the HW requirements it is highly recommended to use DMA start
window to trigger  broadcast commands. If not used then it can
result in a hardware hang with the DSI controllers going out
of sync. This behavior is even more prominent in cases of higher
refresh rates. As part of the change we change the default DMA
scheduling behavior to default to maximum possible DMA window
in case it is not specified in the panel device tree.

Change-Id: Ied4df9063664cedbc18ce009054d4e5ecae30ab2
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2020-12-04 20:01:55 -08:00
qctecmdr
348e9b397c Merge "disp: msm: dp: remove debug log output in isr" 2020-12-03 22:53:43 -08:00
qctecmdr
02e82d15e1 Merge "drm: msm: Reset register when NoiseThresh disabled" 2020-12-03 19:16:31 -08:00
qctecmdr
70df5208b0 Merge "disp: msm: sde: ignore HW recovery disable event" 2020-12-03 11:57:17 -08:00
Steve Cohen
2aaadbc5c7 disp: msm: sde: flush all event thread work during CRTC disable
The API to flush the event thread is only flushing the
frame_event work queued on that thread but during disable
the vblank work must also be flushed. Instead of flushing
only frame_events work, flush all work queued on the event
thread worker. Also rename the API to more accurately describe
what it's doing.

Change-Id: Iaf248a2b1bafc9b9a15ae9447b72cdff07509a91
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-12-03 11:26:00 -05:00
Veera Sundaram Sankaran
98c9ba6153 disp: msm: sde: ignore HW recovery disable event
The current SDE driver logic during MDP hang cases is to send a capture
event to user-mode if recovery custom event is registered. Otherwise, it
will enforce a device panic for debugging purpose. This might have a race
condition during the display tear-down sequence as user-mode unregisters
the recovery event when the last frame is in progress. If the last frame
causes any MDP hang, it will result in a device reset. Support only the
event registration to avoid this case, since HW recovery is not expected
to be changed dynamically.

Change-Id: I8a11e1060b239ac6827f1d078e3e396cff4c1325
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-12-02 15:29:19 -08:00
qctecmdr
ee8ad711e9 Merge "disp: msm: sde: use prepare_commit connector callback for DSI" 2020-12-02 15:02:46 -08:00
Tatenda Chipeperekwa
c90f535a24 disp: msm: dp: remove debug log output in isr
Remove all debug logs and replace them with event logs in the isr
path. This change will reduce the likelihood of an interrupt storm
causing a watchdog bark if display threads are being prevented
from completing execution due to debug logs holding the console
lock.

CRs-Fixed: 2810115
Change-Id: I906f19fb73a7501114fd0a62e9ae66c83dde4d5d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
2020-12-02 12:36:04 -08:00
qctecmdr
13c448e20f Merge "disp: msm: dp: add support for continuous PPS command" 2020-12-02 06:10:50 -08:00
Yuchao Ma
c1263308c7 drm: msm: Reset register when NoiseThresh disabled
The change reset register of noise thresh when disabled.

Change-Id: I2bb13167b52c6ba92e32c4fa9b4f0a57122164ab
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
2020-12-01 23:08:15 -08:00
qctecmdr
d9208128c7 Merge "disp: msm: sde: fix dsc 1_2 rate control parameter" 2020-12-01 21:38:54 -08:00
qctecmdr
7c8f6d1332 Merge "disp: msm: dp: fix DSC and PPS version mismatch" 2020-12-01 21:38:54 -08:00
qctecmdr
7d396c0c19 Merge "disp: msm: sde: always enable prog fetch and fix prefill calculations" 2020-12-01 09:15:53 -08:00
Steve Cohen
4eff2d1bce disp: msm: sde: use prepare_commit connector callback for DSI
Some DSI panels require qsync on/off DCS commands to be sent in
prepare commit phase. Add the hook for sending these commands
to the panel. If these commands are not present in the panel's
device tree node, it will be treated as a NO-OP.

Change-Id: Ida65512fe0214779dfa848f6c7b33644d3934afd
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-11-30 14:02:50 -05:00
Krishna Manikandan
6bf86dc2e5 disp: msm: sde: retain ubwc settings during LA to LE transition
Setting hbb value based on the ddr type of the target is
not supported in trusted vm environment. Add changes to
retain the ubwc configuration programmed by LA during the
transition to LE environment.

Change-Id: I1fa308ea99f815cfe4d1c75a22dbb6f89a806007
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-11-29 20:24:29 -08:00
Jayaprakash
ea5b9b3157 disp: msm: sde: always enable prog fetch and fix prefill calculations
Enabling and disabling programmable fetch dynamically
across different fps can cause dsi underflow/overflow followed
by underrun. Add changes to always enable prog fetch to handle
such cases. Fix needed_prefill_lines calculation for vfp method
of dfps since linetime is constant in this method and hence
prefill lines need to be based on max_fps. For panels whose
linetime varies with fps, the needed_prefill_lines calculation
remains unchanged.

Change-Id: Ib7b68b577ff903fc2359a8e8c4573d62d55c3828
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-11-26 14:43:43 +05:30
Amine Najahi
7a9e08de70 disp: msm: dp: fix DSC and PPS version mismatch
Currently, driver hardcodes the DSC version to use
to v1.1 in DP driver even if the sink reports v1.2 in
the DPCD DSC_ALGORITHM_REVISISON register. This causes
a mismatch between the source DSC hardware programming
and the PPS packet information sent to sink.

This change sets the PPS DSC version field to the one
reported by the sink and falls back to v1.1 in case of
DPCD parsing error.

Change-Id: I76fb55b7bf9b3925ae3f408008f3257fc85cef2c
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-11-25 13:16:37 -08:00
Abhinav Kumar
6db41ed532 disp: msm: dp: add support for continuous PPS command
Add support to send PPS command with every frame for DP.
This is needed to satisfy the requirement of certain bridge
chips which need the PPS to be sent every frame.

Change-Id: I8711dff41e60d8b1e1c515a5d34a370a2409ce14
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
2020-11-24 18:16:28 -05:00
Alisha Thapaliya
f9ce840444 Merge remote-tracking branch 'origin/display-kernel.lnx.5.4' into display-kernel.lnx.5.10
* origin/display-kernel.lnx.5.4:
  disp: msm: dsi: avoid TE status check based on rechecks count
  disp: msm: sde: move vm-ownership check to crtc custom events
  disp: msm: sde: remove HARD_RESET recovery event on frame-timeouts only
  disp: msm: read mdp intf line count and trigger dma accordingly
  disp: msm: sde: use drm mode set by user-mode in trusted-vm
  Revert "disp: msm: sde: use mdp scratch register to pass drm mode info"
  disp: msm: sde: request hard reset on vsync timeout
  disp: msm: sde: reset sw state on vm transition
  disp: msm: sde: add vblank mutex lock during irq unregister
  disp: msm: sde: move qsync validation to encoder atomic check
  disp: msm: sde: add check to fix null pointer dereference
  disp: msm: sde: add mutex lock to handle ppdone timeout usecases
  disp: msm: sde: cache encoder_mask for vblank_work
  disp: msm: sde: fix TUI CRTC selection for dual-display
  disp: msm: sde: bound crts and encoders for TUI displays
  disp: msm: dsi: avoid TE-based panel status check in Trusted-vm
  disp: msm: dsi: enable ESD trigger through debugfs in trsuted-vm
  disp: msm: dsi: parse & store gpio registers used by the host & panel
  disp: msm: sde: clear pending flushes after disable commit
  disp: msm: dsi: Add support for parsing mdp_intf base address from dt
  disp: msm: sde: fix missing error handling in VM ops
  disp: msm: sde: fix invalid dual-display TVM restriction check
  Revert "disp: msm: sde: fix race between disable commit and vblank work"
  disp: msm: dp: add error handling for host init failures
  disp: msm: hdcp: avoid sink message processing when hdcp is off
  disp: msm: dp: unify hpd event for sst and mst
  disp: msm: sde: use current crtc state during idle work scheduling
  disp: msm: dsi: recount drm mode count
  disp: msm: sde: add traces for lastclose
  disp: msm: sde: fix race between disable commit and vblank work
  disp: msm: dp: send hpd notification before updating mst_active
  disp: msm: avoid setting AMC and WAKE tage on icc vote

Change-Id: I690cba7c3c59e9d02a24160bd1b3d12660211405
2020-11-24 10:37:10 -08:00
qctecmdr
a2a3c5e864 Merge "disp: msm: sde: cache encoder_mask for vblank_work" 2020-11-24 06:44:04 -08:00