For KIWI target, 64-bit timestamp is reported
in the PHY TLVs. use the first 32-bits timestamp
value for the radiotap header.
Change-Id: Ia7d7a6913e4cdca3a1432cc5edbb0348ec8a6857
CRs-Fixed: 3096680
For Kiwi, if UMAC force wake is enabled, HIF window register
support is needed as well. currently hal_soc->init_phase just be
true for a very short periord, this lead to hif_force_wake_request
is called frequently when configure register during initialization,
this is not necessary as pld and device is not in power collapse
state during this period.
Enable HIF window register and increase init_phase true period
Change-Id: I0b5394bbc1ca73d20b2fcabbf2a261e6f8335626
CRs-Fixed: 3097991
In WCN7850, the tlv header width is 64-bit and the tlv header
start is 8-byte aligned inside the monitor status ring desc.
Add changes to parse the monitor status ring TLV according
to the TLV header width.
Change-Id: I19860b871abbc3037174b9d0ae5ed6e52b1eb736
CRs-Fixed: 3084443
Add 2 hal soc ops, hal_msdu_desc_info_set and
hal_mpdu_desc_info_se for berilliyum datapath.
Attach hal_rx_msdu_ext_desc_info_get_ptr_be to its function
pointer.
Get reo queue descriptor address as a 5 byte value as in
beryllium datapath it is being obtained from rx packet tlv.
Change-Id: Ia58597384e1a3d5eec493b865a88bab4f209502d
CRs-Fixed: 3084532
Use the tracepoints to trace delayed register write, ce
tasklet scheduling latency, tx, and rx packets.
Change-Id: I63a89276177a9d0466dcb0c831eeb8e938a2bf79
CRs-Fixed: 3081870
Use chip ID and destination peer to determine the target soc
and partner vdev for Intra-BSS in MLO case.
Change-Id: I709c52e74426c5e81b50c8063cad7669c0e7002d
HAL changes to populate agc gain, CFO, rx_start_ts, mcs_rate and
gi_type to CFR info for QCA6490.
Change-Id: I6f6f47c87d40bd661162f764fb3a360230a56457
CRs-Fixed: 3086667
Offsets used by host for HTT stats are not aligned as per the
structure declaration given in file htt.h .
Make change to use the correct offsets to get the correct stats.
Also make change for byte count computation.
Also make cleanup changes for FR65817.
Change-Id: I8bc6164cc4994c49536d7277779f25b258be1592
CRs-Fixed: 3082742
In BE architecture, HW provides basic vdev stats support for upto
48 vdevs. For each vdev, there is vdev_stats_id which represents the
id of this vdev on HW. This vdev_stats_id is assigned by host and
is conveyed to HW at the time of REO TID Queue setup for the peer.
Add logic for allocation and deallocation of vdev_stats_id and
convey this id to HW.
Change-Id: If5611bf54d057ccf71c6444b5c79a26eb28df87e
CRs-Fixed: 3067843
In hal_delayed_reg_write change the order of
hal_is_reg_write_tput_level_high and pld_is_device_awake check. This
ensures that throughput level is checked before checking for device
wake state. This is beneficial in saving CPU cycles in high throughput
scenarios.
Change-Id: I23d0bde46779df9dca4388bf67c9395999274f3a
CRs-Fixed: 3078096
Rx patch changes for multichip MLO
1. Create ini for rx ring mask for each chip
2. Configure hash based routing for each chip based
on lmac_peer_id_msb
3. Peer setup changes to configure lmac_peer_id_msb
to enable hash based routing
4. Rx Replenish changes to provide buffers back to owner
SOC of reo ring
Change-Id: Ibbe6e81f9e62d88d9bb289a082dd14b4362252c4
Changes needed for MLO soc attach to pass chip_id,
dp_ml_context from upper layer.
This change also takes care of assigning appropriate
RBM id for IDLE link descriptors based on chip_id.
Change-Id: I8f5f08c524d91942e6e458f048700b7bdd900107
Prefetch RX HW desc, SW desc and SKB in pipeline
fasion in the first loop of RX processing.
This has improved TPUT by 200Mbps and provided a
10% gain in CPU (single core)
PINE with other optimizations: 3960Mbps @ 100% core-3
PINE + pipeline prefetch: 4130Mbps @ 90% core-3
Change-Id: I47f351601b264eb3a2b50e4154229d55da738724
Added an API to do a batch invalidation of REO descs
saw an improvement of 40 to 45 Mbps.
Note: this change is applicable only for cached
descriptors
PINE with Default driver: 3189 @ 100% core-3
PINE with skb prefetch: 3469 @ 100% core-3
PINE with skb pre + batch inv: 3506 @ 100% core-3
Change-Id: Ic2cf294972acfe5765448a18bed7e903562836c3
Increase the max WBM2SW release rings for qca6750
when multiple tx ring pairs support is enabled.
Change-Id: Ifa3be25a7c9b7cb019165e76b3a71d3db9572334
CRs-Fixed: 3075392
tcp_proto is not set correctly from hal_rx_get_proto_params() API,
currently it is using HAL_RX_TLV_GET_IP_OFFSET, use
HAL_RX_TLV_GET_TCP_PROTO to fix it.
Change-Id: I1f3c6aa4b8f5420f176bda4aff158dcfa2a7ef5a
CRs-Fixed: 3073794
In WBM error processing read peer_id from peer_meta_data
instead of sw_peer_id.
This changes is needed because we need to process Rx packet
on ML peer. But in MLO case sw_peer_id field contains
link_peer_id where as peer_meta_data has ml_peer_id.
Change-Id: I3f469adfdf7efa88cb081e94fa9fe0c54c1fb078
The maximum WBM2SW rings in whunt for HSP is 5 and
the same could be 4 in wlan code which will result
in wcov failure for HSP. Use a maximum of 5 WBM2SW
rings for HSP based on FW_SIM config flag to address
this failure.
Change-Id: I8340cd094eb1e0cf842894e5c89174d410729028
CRs-Fixed: 3071662
Repurpose the IPA tx and tx completions rings for
normal use when IPA is disabled either via config
flag or ini.
Change-Id: Ia4b6a89c73d888a217bdef40e3c05435c3bb1bb2
CRs-Fixed: 3059730
Add fisa deletion support by invalidating the fisa
DDR entry when adding a new entry.
Change-Id: I02189e22e09ca0ef5e1fdb5952c7e72cd87d3673
CRs-Fixed: 2954060
Currently reg work is being cancelled in deinit path,
cancel work will remove all the pending work items
and wait for completion of current executing work.
But in reg work case even pending work items has to be
executed because we don't want to skip HP/TP values update.
To avoid this make sure all the pending reg work items are
flushed then disable the work for further queueing.
Change-Id: I2ba1e26cf41fb3b0c33ec584c56525cbfac94d8f
CRs-Fixed: 3065038
sw_exception bit will be marked in reo dest ring descriptor for
FW re-injected frame, get this bit and save it in skb->cb,
this bit value can be used for FISA further check.
there is no reo_dest_indication field in reo dest ring on beryllium,
so share same cb member for sw_exception and reo_dest_indication.
Change-Id: I2321121be7dda68ed19faca177d868c7e8ba1dbf
CRs-Fixed: 3056156
Add API to get dp peer authorize state.
Also modify dp_tx_get_rbm_id_li to update rbm for IPA offload
scenario
Change-Id: I0f8cca4623a1c3b840f336aa6d67740951cb6700
This FEATURE_HAL_DELAYED_REG_WRITE_V2 was added to fix the
Audio jank issue, but it could not resolve it completely,
so that was later fixed by existing delayed reg write
support with the help of SMP2P messages to communicate
with FW regarding PCIe link status. This code is not being
used, so removing it and cleaning up the redundant code.
Change-Id: Iada088e72a76b4c071c8a80ee945f36ac959670e
CRs-Fixed: 3056475
This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM
Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
The multicast echo check feature is moved to hardware in
Beryllium. Enable this hardware feature and also disable
the MEC handing code for Beryllium in the host.
Change-Id: I86d319963191f3ed77aba16dcccbc659906edd9f
In Beryllium the HW does the ast lookup and match
and sets the intra-bss bit in the msdu_desc_info
structure of reo_destination ring and WBM Rx release ring.
So, change the Beryllium code to make use of this
hardware assistance for intra-bss.
Change-Id: Ic7c89efc741fefe35603082309204fbe3c9a97c7
Add big endian version of rxtlv structure. THis is needed since
the structure members are directly accessed by name and hence reverse
order of bitfields have to be defined in case of Big endian mode.
Change-Id: I50ce4bdd482a336ee8d2f394ed2de1a7ddf0be57
