When display is left on from the bootloader, disp_cc driver will put a
proxy vote on clocks to maintain the hardware configuration of bootloader.
Once all the consumers have been probed, the dispcc driver will synchronize
the hardware state of the device to match the aggregated software state
requested by all the consumers using sync_state call.
If there is an idle power collapse or a suspend before sync state call,
branch clocks and in turn RCG will not get turned off during clocks
disable sequence because of the proxy vote of disp_cc driver. This can be
the case even if there is a vote from any other disp_cc consumers.
During a subsequent call to enable the clocks from DSI driver, we are
currently switching RCG parent to PLL and then turning on the PLL.
If the sync state call doesn't happen before we enable the clocks back,
we'll be setting PLL which is off as a parent to RCG that is on.
But ideally when RCG is on, both the old and new sources should be on
while switching the RCG parent.
Avoid this by turning on the PLL before switching RCG parent during clock
enable sequence.
Change-Id: I1597cf2c8095957cd2b2a20a72bf7199e0d61809
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Add support for localized CLK_CTRL access through LUTDMA
hardware block.
This change aggregates RD/WR LUTDMA CLK_CTRL in a single
ops.
Change-Id: Id5c24bebf7dfcd9f768b2a6f6fa03f8b01747354
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Log the vblank timestamp during vblank callback. This will be
useful in calculating the precise difference between the vsync
while debugging. As part of the change, remove the vblank
counter logging in sde_crtc as it floods the logs with 4 entries
for each vblank request.
Change-Id: I6b532ad657581fb2a34318541acbd81a44858819
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
On composer kill event, drm lastclose occurs during which suspend
commit gets triggered on primary. If secondary display is stuck in
continuous splash, then we do a early return without triggering
this suspend commit. On composer start, userspace waits for power on
event, but the drm_driver has never entered suspend state, so power
on event is never sent to userspace. This causes HWC deadlock side
effect and the current change triggers null_commit on secondary
display and then issues a suspend commit on both the displays to
avoid this deadlock issue.
Change-Id: I126f43ba3dd2c3bfa83346e8fd4678f35527893d
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Some of the display status changes such as re-enable
or re-disable are not critical errors and can be ignored.
This change downgrades such errors as warnings.
Change-Id: I6800e534fc7fb825a472f37bb78a928e2e78d63a
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Currently in an MST scenario, DSC resources are updated in
bookkeeping only when the corresponding stream is enabled.
This would lead to assigning already reserved DSC blocks to the
2nd stream, if 2nd stream is validated before the 1st stream is
enabled. This change would update the bookkeeping as soon as the
mode is validated.
Change-Id: I7f89a16639efcde3e5dfdf423715ed354e1de66a
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Pass the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag when attaching the
bridge so that the bridge driver would not create another
drm connector.
Change-Id: I838bd87c40d0eea3df36187befeb7195fb87d5b3
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
This change adds support for triggering output
hw fence upon programmable line count.
Change-Id: Ie4b8252e4f9a448a8c11d17696b9bb0ded81b04b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change updates the autorefresh disable sequence to manually
trigger output hw_fence during the transition. This is required
since on the last autorefresh frame HW will not trigger the output fence.
Change-Id: I6789fc6b51421524f88dcbdd1a063ae947646ae4
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change disables hw_fences when a mode switch
from video to command mode or command to video mode
is ongoing.
Change-Id: I6f99226b59b381c6d2ff34a85753f8608080f546
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds the value of hw-fence ready to
event logs for video and command modes.
Change-Id: I40a2e886a3b95e8853efcbdddf7fd9f6ce48eb9b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds one-to-one memory mapping for the hwfence
ipcc register memory needed for hw fence feature.
Change-Id: I0e264183e02d0ed5f2254b409cc5e776d670f0dc
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
remove the TARGET_BOARD_AUTO flag check to enable
the display driver msm_drm.ko packing for automotive builds.
Change-Id: I3eda4b3ecb497be71cbe156acb62a0731f12ccde
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
Change removes downstream parsing of deep color modes function
_sde_edid_update_dc_modes, which is presently parsed in upstream
function drm_parse_ycbcr420_deep_color_info in drm_edid file.
Change-Id: I4426e190cdc1e5f139a0c0439cc45f3cc7884c3d
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change collects the OPR, MISR values. If the values are
different than the previous then notify to client with custom event.
Change-Id: I2546439be1f665d90e6505d65283d28096bf7cdd
Signed-off-by: Akshay Ashtunkar <quic_akshayaa@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds reg dma support for vig DE lpf.
Change-Id: I9108046bb2afb987eec49224df4a45c37f9c27cd
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
This change updates vsync source as part of rc post modeset. For some
use cases like idlepc with DFPS, vsync could be configured for
previous fps and can cause timeouts during next frame.
Change-Id: I110fd958d2970eaca50ace0e72c4faea3fc64ce8
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Avoid various possible nullptr dereferences.
Addresses various issues highlighted by static analysis.
Change-Id: I36d34d610b37bf2799a7e34cd1de8b909b5c0ae4
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
To toggle error interrupts, we currently read the DSI_INT_CTRL register,
toggle the DSI_ERROR_MASK bit and write back to the register. While doing
so we are also writing back 1 to any status bits set by HW, thus clearing
the status interrupts. Clearing the status bits should always be done as
part of interrupt handling, which otherwise can lead to command transfer
failures.
Avoid clearing status interrupts while error interrupts are toggled.
Change-Id: Iaae10c279f2341269ed49074448167e68ab7e13c
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
The software mvid/nvid values represent the ratio of mode clock
to link clock. Currently we are converting the link clock to vco
clock, get the ratio of vco clock to mode clock and then adjust
the resulting values to get the ratio of link clock to mode clock.
This change simplifies this logic by directly using the link
clock to get the ratio and uses fixed point arithmetic to scale
the resulting mvid, nvid values to meet requirements.
Change-Id: Ifdfa27edb73d2db6381e592db219e75806d6bdc7
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Check the precise vsync feature bit in sde hw catalog features
bitmap for checking the precise vsync feature and remove the
obsolete has_precise_vsync_ts variable.
Change-Id: I1f0cfabe5dcf387358548e8ff5ea0d65d4d7cecf
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently only LLCC_DISP SCID is used to read and write to
system cache during static display use case.
This changes adds SCID LLCC_DISP_1 to allow each SCID to
have a dedicated function (read/write).
Change-Id: I5604ec1183d99a8492b005ec06ac94e5db60b5f7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently a boolean variable is used to track if the system
cache feature is enable for a particular SCID.
This change converts it to use a feature bit instead.
Change-Id: I8461fd9fb837b871c4ac5c67a9ab7613aadea7bb
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Merge reg_dump and dbgbus dump flag into dump_mode, and bring
back debugfs node "evtlog_dump" to keep flexible controlling
of evtlog.
Set in_mem option as default dump mode, since in_coredump
option will be enabled once HW recovery feature is enabled.
Change-Id: I75de1a69b01594b652479bf79201591ac0bf62e5
Signed-off-by: Bruce Hoo <quic_bingchua@quicinc.com>
Currently, when doze mode is enabled the encoder off work
worker is started 1 ms after idle power collapse because of
aggressive idle-pc feature. This causes the system cache
worker to start after the clocks and vsync interrupt are disabled.
This change independently enables clocks and interrupts during
system cache work thread to decouple it from the encoder
off work sequence.
Change-Id: I8ed172b0e7c5c8e4e270e768434301d972e90eb9
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
UBWC revision is in the expanded form, no need to process it again.
Change-Id: Ie4aafeea5459a76f325a07e58af1de5665fe45ba
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
