The offset for DP pixel clock configuration registers in disp_cc has
changed in waipio. Currently the driver is using incorrect offsets to
read M/N values to calculate SW MVID/NVID during MSA programming. This
results in a blank screen as the sink is not able to restore the pixel
clock.
This change fixes this issue by selecting the correct base address
based on dp core version.
Change-Id: I44214ce52c1bc346715362df0a138f1f8cc011e1
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
With the change in the clock names for newer targets, this fix
updates the driver to support different clock names per target.
Change-Id: I58c35fce34356f8c79adb0ac8a907e2fb60813ae
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
Currently the timing configuration for test pattern generator in DP
controller assumes that the widebus is disabled. This change adds the
check for widebus and adjusts timing configuration accordingly.
Change-Id: Id86601c910e88705a1a6d0ff4a4b38df6a843409
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Add support to send PPS command with every frame for DP.
This is needed to satisfy the requirement of certain bridge
chips which need the PPS to be sent every frame.
Change-Id: I8711dff41e60d8b1e1c515a5d34a370a2409ce14
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
Decrease the log level for messages that are typically printed from a
real time thread execution environment (such as the display commit
thread). This can help with cases where a console lock held during the
execution of these real time threads can result in RT throttling issues.
Change-Id: I41e1e4f171b5eee9966d8a7d26d64430a81bc6fc
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Update the DP controller and PHY programming to support different
values for pre-emp and voltage swing levels at different link rates.
Change-Id: I974c47cd1bf71b76dea4f270031a9cdfe320725e
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
Enable DP controller hardware feature to modulates the
data drain rate between DP and INTF to reduce chances
of MDP Underflow or DP Overflow.
Change-Id: I7214a2fff957ae35b31c660bafa1d0141eb50680
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Some Type-C multi-port adapters which do not support usb connection
are advertising the multi-functionality in DP alt mode. If
multi-functionality is preferred, the DP driver assumes the adapter
supports usb connection and USB phy driver will program the PHY mode
to DP+USB.
In source mode, usb PD driver checks for the peer_usb_connection
of the adapter. If it does not support usb then it will stop usb stack
and update the PHY MODE to USB only mode from phy_suspend path.
The result is, usb may program the combo PHY to usb only mode when DP
is already connected. This is causing AUX read/write timeouts when DP
is trying to access the phy registers.
To fix this issue, a flag in SVID connect handler in usbpd driver to
notify peer_usb_comm support to the DP driver. DP driver will read this
flag and program the phy mode.
Change-Id: I0164b239bf2832d480795d90f5e9fc221bcc12ba
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Clear the scrambler bypass bit while programming test pattern 4
for electrical compliance. This bit is only used for debugging
purposes and must be unset in order to get the correct test pattern
output from the controller.
Change-Id: If54ba17dc5bdd096899cf57cc4f276aab1837308
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Currently, for every DP hardware register read/write, there
is a string comparison to determine the execution mode. This
adds up an extra delay while powering up/down which does a
large number of register reads and writes. During stress
testing and automation, this can cause an issue resulting
in failures. Remove the unnecessary delays by using common
APIs for register reads and writes. Switch these APIs only
in case of execution mode change.
Change-Id: I9403873a29b3466c606297b2aa386d0885bb2dc7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Add the colorspace property for DP controller for MSM. Also, change
the default method to send the colorimetry information to the sink
from MISC bits of MSA to VSC SDP packets if the sink supports it. This
helps to avoid dynamic switches between the packet types for sending
the colorimetry information during BT2020 and DCI-P3 use-cases.
Change-Id: I7ddf879a187b023fcf7404d64028e4d19b031119
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Currently a lot of information is packed into the HDR data structure of
the catalog panel making it difficult to individually control the
parameters like colorimetry and other information sent using
VSC SDP packets.
Break up the structure into individual VSC SDP colorimetry, HDR
infoframe and DHDR VSIF packets.
This makes it easier to control each of these parameters independently.
For example, when only the colorspace is changed its sufficient to
update only the VSC SDP colorimetry packets.
Also align these packets with the upstream DP helper header defines.
Change-Id: Ia208f30a480fd203192624fe4f3d99c1c89350dc
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
DP specification mandate test pattern #4 for CTS 1.4a. Add
support for the same in link training #2 as per specification.
CRs-Fixed: 2490128
Change-Id: I2f72fec340b56270e7fd1c2940adafe1068bab43
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Adding prefixes for error, debug and info
messages in dp files. To enable debug logs
run "echo 0x100 > /sys/module/drm/parameters/debug"
CRs-Fixed: 2493739
Change-Id: Ibf509e837f527be6bff6b7a1c34b0cde2921b388
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Update the PLL and PHY power on and clock set sequence as per
the hardware recommendations. Move the post link clock phy enable
part to the catalog so that it can be programmed after enabling
link clock.
Change-Id: I9b3b49e5a9ac93bebcb1cb7da63b715a8d5ed85c
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Update the DP controller and PHY programming according to
the new hardware recommendations.
CRs-Fixed: 2458753
Change-Id: I1bce5915ba6ebbb250cc5c4aac907b0b287eece7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
