Added pre-sil implementation of icp hfi.
Hfi functions need to modify shared queue memory shared with FW
at byte level and frequently. Hence we redirect hfi function calls
to PCHost and have queue logic running directly on PCHost.
CRs-Fixed: 2932495
Change-Id: Ib3b92f998e5836b27573a2756f94f170d2827c82
Signed-off-by: Suraj Dongre <quic_sdongre@quicinc.com>
FF: Upto PC669: Merge tag 'camera-kernel.lnx.5.0-211101.1' into 6.0
* tag 'camera-kernel.lnx.5.0-211105':
msm: camera: isp: Enable line done config for SFE RDI0-2
msm: camera: smmu: Add support for 36 bit address space
msm: camera: cpas: Disable ICP QoS registers for kalama
msm: camera: isp: Update RM stride correctly at stream on
msm: camera: sensor: Add support for CSIPHY TPG 1.2
msm: camera: isp: Add header file VFE and CSID for Cape
msm: camera: cpas: Add support for Cape Camera
msm: camera: sensor: Add support for CSIPHY 2.1.1
msm: camera: common: Add path for ubwc and linear
msm: camera: common: Add Kalama make configuration
msm: camera: smmu: Moves custom smmu API's to cam_compat
msm: camera: common: Remove return from debugfs_create_bool
msm: camera: mem_mgr: Add dma_buf_vmap to cam_compat
msm: camera: custom: Move include to cam_compat
msm: camera: req_mgr: Update list_head to const
msm: camera: common: DDR type selection deprecation
msm: camera: csid: correction for printing long and short packet info
msm: camera: isp: Refactor csid get rdi format function
msm: camera: isp: Print additional debug info in case of csid errors
Change-Id: I46f3c1c34c2db76436ad02a30268e4c6f9a845b3
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
Due to interrupt delays, when VFE top processes the interrupt registers
it might see EPOCH and EOF of frame n along with SOF of frame n+1. The
current logic is based on IRQ controller priority and hence will report
SOF of frame n+1 before EPOCH of frame n. This can result in ISP context
reporting SOF timestamp of frame n+1 for both frame n and frame n+1.
In order to report the events in the order that they occurred, we
maintain a state machine in VFE top to keep track of the last seen
event. This helps detect any missing IRQs and also warn when such
interrupt delays are observed.
The state machine logic is only able to handle delays less than 1 frame.
For example, EPOCH of frame n+1 occurs before VFE top has read EPOCH of
frame n, there is no way to tell that this is the case from the
interrupt registers.
CRs-Fixed: 3067696
Change-Id: I061732c20ff23ca9394ae9844d50729476ad07b5
Signed-off-by: Anand Ravi <ananravi@codeaurora.org>
Remove regs reread of cdm_irq_status and top_irq_status
after finishing read poll of the regs to avoid false
errors in core reset of IPE and BPS.
CRs-Fixed: 3071147
Change-Id: Ie4d65a7b527b025b623d365c77361e3db9ae89be
Signed-off-by: sokchetra eung <eung@codeaurora.org>
QMAA flag check only applies in the Android build system.
It's primarily meant for controlling whether or not certain
UMD libraries are enabled in the compilation.
Change-Id: I295df2b02bbdf80b26783441908807f7309f148e
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
As part of HFI INIT ensure all CSR registers are configured prior
to setting INIT_REQUEST. Also monitor the INIT RESPONSE status
for 32 bits as opposed to 1 bit which will result in reading
a false value for FW error codes > 1.
CRs-Fixed: 3070374
Change-Id: Ib32f1cdf05c524072e5d6e55773351e95c9082a8
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
We will get wrong rdi only flag if we don't reset the flag.
So this change resets the rdi only flag during stopping resource.
CRs-Fixed: 3069713
Change-Id: If06ea32c3f9b5dbfa2f71da1496577c31b67b8c8
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Add support for new CSIPHY HW version 2.1.3.
Change-Id: I22e3658acc9a002e4323c0487e65f5ae0a495d6d
CRs-Fixed: 3068540
Signed-off-by: Anil Kumar Kanakanti <quic_akanakan@quicinc.com>
* tag 'camera-kernel.lnx.5.0-211101.1':
msm: camera: cdm: Fix incorrect condition in cdm code
msm: camera: isp: Add YUV format as supported format
msm: camera: isp: Force all IFE lite RDIs to line based
msm: camera: isp: Additional fixes for KMD internal recovery
msm: camera: cdm: handle dead lock scenario
msm: camera: sensor: Remove NULL set for regulator phandle
msm: camera: isp: Rearrange the rt-wrapper-base property
msm: camera: isp: Handle error event notification to HW manager
msm: camera: cdm: Fix cdm bl submit function
msm: camera: isp: Update right out resource for PDAF parsed outport
msm: camera: isp: Add SOF Retiming Disable Support
msm: camera: isp: Enable line smoothing in RDI path for CSID 780
msm: camera: isp: Add support for RDI LCR
msm: camera: isp: Add new CDM BL Type
msm: camera: csid: Fix excessive logging in CSID
msm: camera: common: Update the ctx memory request logic
msm: camera: csiphy: Add proper check for combo mode
msm: camera: common: Fix kernel code and add checks
msm: camera: isp: Add recovery support for custom AEB use-case
msm: camera: cre: add degug fs entry to update clock rate
msm: camera: core: Delete request from pending list in case of error
msm: camera: csiphy: Update the csiphy bringup sequence
msm: camera: csiphy: Enable PN9 infinite loop for test
msm: camera: isp: Update reapply field in config args
msm: camera: isp: Add common utility functions
msm: camera: isp: Split event handler based on HW type
msm: camera: isp: Apply scratch only on SOF trigger
msm: camera: common: Add wrapper for presil locking
msm: camera: isp: Fix BW voting corruption in top layer
msm: camera: isp: Handle RUP for enabled CSID CAMIF IRQs
msm: camera: reqmgr: Fix the crm driver
msm: camera: cdm: Fix cdm driver for bufffer excursion
msm: camera: common: fix map check failure for presil buffer send
msm: camera: cpas: Add support for Diwali Camera
msm: camera: uapi: Add new event causes
msm: camera: isp: Add bw info dump on clk/bw update error
msm: camera: common: Make msg_cb for cam_subdev generic
msm: camera: req_mgr: Rearrange state change sequence
msm: camera: isp: Add header file VFE and CSID for Diwali
msm: camera: csiphy: Extend CSIPHY hw block support
msm: camera: icp: send freq to ICP firmware
msm: camera: cci: Increase HW block support for CCI
msm: camera: isp: shdr enable pdaf occur overflow
msm: camera: cdm: Correct the CDM iommu handle
msm: camera: isp: Update last applied MUP for scratch
msm: camera: reqmgr: Only do self correction after initial sync
msm: camera: common: Add presil compilation and probe support
msm: camera: ife: Program image addr for once in RDI batch mode
msm: camera: icp: add mechanism to send/receive buffer for presil
Change-Id: Ib959b746db64825cc735fa80ddd5e79200c102a8
Signed-off-by: Abhijit Trivedi <abhijitt@codeaurora.org>
In case SOF interrupt is not received by the camera driver, we can
recover the missing SOF timestamp for the frame at epoch using the
previous and current SOF timestamps from CSID.
CRs-Fixed: 3067696
Change-Id: I25c8596132b99829d04ea38dbd3d904fc2a302c2
Signed-off-by: Anand Ravi <ananravi@codeaurora.org>
RDI0-2 clients are used in conjunction with fetch engine for
sHDR/FS enable line done for these clients. As opposed to
using WM index to enable this, update header to indicate
that this has to enabled for select clients.
CRs-Fixed: 3068277
Change-Id: I7ce4cbbddc9eb11174a39c4df93bc82e5413317f
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Add support for 36 bits wide smmu context bank for SM8550
target.
CRs-fixed: 3065594
Change-Id: Ib2953a3f4fe0bb9283719ce91dcef128cd63ab20
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
Disable cpas writing to ICP QoS registers, since they are in
ICP clock domain, which has not been enabled by the time cpas
probes to configure the registers.
CRs-Fixed: 3048249
Change-Id: Iaada5194a06408ecee69cb724eb94c6ffb7bfb95
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
When internal recovery is in progress skip notifying
SOF trigger to CRM. Also for AEB add a threshold check when
slave RDIs SOF is seen post IFE epoch, flag as fatal error
only on hitting this scenario on threshold number of
consecutive occasions.
CRs-Fixed: 3064736
Change-Id: Ibda10d3c42cff6ce128197221da298d2e88cb286
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
