Merge tag 'camera-kernel.lnx.5.0-211105' into camera-kernel.lnx.6.0

FF: Upto PC669: Merge tag 'camera-kernel.lnx.5.0-211101.1' into 6.0

* tag 'camera-kernel.lnx.5.0-211105':
  msm: camera: isp: Enable line done config for SFE RDI0-2
  msm: camera: smmu: Add support for 36 bit address space
  msm: camera: cpas: Disable ICP QoS registers for kalama
  msm: camera: isp: Update RM stride correctly at stream on
  msm: camera: sensor: Add support for CSIPHY TPG 1.2
  msm: camera: isp: Add header file VFE and CSID for Cape
  msm: camera: cpas: Add support for Cape Camera
  msm: camera: sensor: Add support for CSIPHY 2.1.1
  msm: camera: common: Add path for ubwc and linear
  msm: camera: common: Add Kalama make configuration
  msm: camera: smmu: Moves custom smmu API's to cam_compat
  msm: camera: common: Remove return from debugfs_create_bool
  msm: camera: mem_mgr: Add dma_buf_vmap to cam_compat
  msm: camera: custom: Move include to cam_compat
  msm: camera: req_mgr: Update list_head to const
  msm: camera: common: DDR type selection deprecation
  msm: camera: csid: correction for printing long and short packet info
  msm: camera: isp: Refactor csid get rdi format function
  msm: camera: isp: Print additional debug info in case of csid errors

Change-Id: I46f3c1c34c2db76436ad02a30268e4c6f9a845b3
Signed-off-by: Sridhar Gujje <[email protected]>

Kbuild

@@ -6,6 +6,10 @@ $(info "KERNEL_ROOT is: $(KERNEL_ROOT)")
 endif
 
 # Include Architecture configurations
+ifeq ($(CONFIG_ARCH_KALAMA), y)
+include $(CAMERA_KERNEL_ROOT)/config/kalama.mk
+endif
+
 ifeq ($(CONFIG_ARCH_WAIPIO), y)
 include $(CAMERA_KERNEL_ROOT)/config/waipio.mk
 endif
@@ -38,6 +42,10 @@ ifeq ($(CONFIG_ARCH_DIWALI), y)
 include $(CAMERA_KERNEL_ROOT)/config/diwali.mk
 endif
 
+ifeq ($(CONFIG_ARCH_CAPE), y)
+include $(CAMERA_KERNEL_ROOT)/config/cape.mk
+endif
+
 # List of all camera-kernel headers
 cam_include_dirs := $(shell dirname `find $(CAMERA_KERNEL_ROOT) -name '*.h'` | uniq)
 
@@ -202,6 +210,7 @@ camera-$(CONFIG_SPECTRA_SENSOR) += \
 	drivers/cam_sensor_module/cam_tpg/cam_tpg_core.o \
 	drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.o \
 	drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_0/tpg_hw_v_1_0.o \
+	drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_2/tpg_hw_v_1_2.o \
 	drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3.o \
 	drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.o \
 	drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.o \

config/cape.mk

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Settings for compiling cape camera architecture
+
+# Localized KCONFIG settings
+CONFIG_SPECTRA_ISP := y
+CONFIG_SPECTRA_ICP := y
+CONFIG_SPECTRA_JPEG := y
+CONFIG_SPECTRA_CUSTOM := y
+CONFIG_SPECTRA_SENSOR := y
+
+# Flags to pass into C preprocessor
+ccflags-y += -DCONFIG_SPECTRA_ISP=1
+ccflags-y += -DCONFIG_SPECTRA_ICP=1
+ccflags-y += -DCONFIG_SPECTRA_JPEG=1
+ccflags-y += -DCONFIG_SPECTRA_CUSTOM=1
+ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
+
+# External Dependencies
+KBUILD_CPPFLAGS += -DCONFIG_MSM_MMRM=1
+ifeq ($(CONFIG_QCOM_VA_MINIDUMP), y)
+KBUILD_CPPFLAGS += -DCONFIG_QCOM_VA_MINIDUMP=1
+endif

config/kalama.mk

@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# Localized KCONFIG settings
+CONFIG_SPECTRA_ISP := y
+CONFIG_SPECTRA_ICP := y
+CONFIG_SPECTRA_JPEG := y
+CONFIG_SPECTRA_CUSTOM := y
+CONFIG_SPECTRA_SENSOR := y
+
+# Flags to pass into C preprocessor
+ccflags-y += -DCONFIG_SPECTRA_ISP=1
+ccflags-y += -DCONFIG_SPECTRA_ICP=1
+ccflags-y += -DCONFIG_SPECTRA_JPEG=1
+ccflags-y += -DCONFIG_SPECTRA_CUSTOM=1
+ccflags-y += -DCONFIG_SPECTRA_SENSOR=1
+
+# External Dependencies
+ifeq ($(CONFIG_QCOM_VA_MINIDUMP), y)
+KBUILD_CPPFLAGS += -DCONFIG_QCOM_VA_MINIDUMP=1
+endif

drivers/cam_cpas/cam_cpas_hw.c

@@ -130,8 +130,8 @@ int cam_cpas_util_reg_update(struct cam_hw_info *cpas_hw,
 		value = reg_info->value;
 	}
 
-	CAM_DBG(CAM_CPAS, "Base[%d] Offset[0x%08x] Value[0x%08x]",
-		reg_base, reg_info->offset, value);
+	CAM_DBG(CAM_CPAS, "Base[%d]:[0x%08x] Offset[0x%08x] Value[0x%08x]",
+		reg_base, soc_info->reg_map[reg_base_index].mem_base, reg_info->offset, value);
 
 	cam_io_w_mb(value, soc_info->reg_map[reg_base_index].mem_base +
 		reg_info->offset);
@@ -2925,21 +2925,14 @@ static int cam_cpas_util_create_debugfs(struct cam_cpas *cpas_core)
 	/* Store parent inode for cleanup in caller */
 	cpas_core->dentry = dbgfileptr;
 
-	dbgfileptr = debugfs_create_bool("ahb_bus_scaling_disable", 0644,
+	debugfs_create_bool("ahb_bus_scaling_disable", 0644,
 		cpas_core->dentry, &cpas_core->ahb_bus_scaling_disable);
 
-	dbgfileptr = debugfs_create_bool("full_state_dump", 0644,
+	debugfs_create_bool("full_state_dump", 0644,
 		cpas_core->dentry, &cpas_core->full_state_dump);
 
-	dbgfileptr = debugfs_create_bool("smart_qos_dump", 0644,
+	debugfs_create_bool("smart_qos_dump", 0644,
 		cpas_core->dentry, &cpas_core->smart_qos_dump);
-
-	if (IS_ERR(dbgfileptr)) {
-		if (PTR_ERR(dbgfileptr) == -ENODEV)
-			CAM_WARN(CAM_CPAS, "DebugFS not enabled in kernel!");
-		else
-			rc = PTR_ERR(dbgfileptr);
-	}
 end:
 	return rc;
 }

drivers/cam_cpas/cam_cpas_hw.h

@@ -19,7 +19,7 @@
 #define CAM_CPAS_MAX_TREE_LEVELS             4
 #define CAM_CPAS_MAX_RT_WR_NIU_NODES         10
 #define CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT   32
-#define CAM_CPAS_PATH_DATA_MAX               40
+#define CAM_CPAS_PATH_DATA_MAX               41
 #define CAM_CPAS_TRANSACTION_MAX             2
 #define CAM_CAMNOC_FILL_LVL_REG_INFO_MAX     6
 

drivers/cam_cpas/cam_cpas_soc.c

@@ -229,6 +229,8 @@ static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core,
 		if (!level_node)
 			continue;
 
+		CAM_DBG(CAM_CPAS, "Parsing level %d nodes", level_idx);
+
 		camnoc_max_needed = of_property_read_bool(level_node,
 			"camnoc-max-needed");
 		for_each_available_child_of_node(level_node, curr_node) {
@@ -246,6 +248,9 @@ static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core,
 				return rc;
 			}
 
+			CAM_DBG(CAM_CPAS, "Parsing Node with cell index %d",
+					curr_node_ptr->cell_idx);
+
 			if (curr_node_ptr->cell_idx >=
 				CAM_CPAS_MAX_TREE_NODES) {
 				CAM_ERR(CAM_CPAS, "Invalid cell idx: %d",

drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

@@ -31,6 +31,7 @@
 #include "cpastop_v570_100.h"
 #include "cpastop_v570_200.h"
 #include "cpastop_v680_100.h"
+#include "cpastop_v680_110.h"
 #include "cpastop_v165_100.h"
 #include "cpastop_v780_100.h"
 #include "cam_req_mgr_workq.h"
@@ -140,7 +141,7 @@ static const uint32_t cam_cpas_hw_version_map
 	{
 		CAM_CPAS_TITAN_680_V100,
 		0,
-		0,
+		CAM_CPAS_TITAN_680_V110,
 		0,
 		0,
 		0,
@@ -737,6 +738,8 @@ static int cam_cpastop_print_poweron_settings(struct cam_hw_info *cpas_hw)
 				&camnoc_info->specific[i].ubwc_ctl);
 			cam_cpas_util_reg_read(cpas_hw, CAM_CPAS_REG_CAMNOC,
 				&camnoc_info->specific[i].flag_out_set0_low);
+			cam_cpas_util_reg_read(cpas_hw, CAM_CPAS_REG_CAMNOC,
+				&camnoc_info->specific[i].dynattr_mainctl);
 			cam_cpas_util_reg_read(cpas_hw, CAM_CPAS_REG_CAMNOC,
 				&camnoc_info->specific[i].qosgen_mainctl);
 			cam_cpas_util_reg_read(cpas_hw, CAM_CPAS_REG_CAMNOC,
@@ -776,6 +779,8 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
 				&camnoc_info->specific[i].ubwc_ctl);
 			cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
 				&camnoc_info->specific[i].flag_out_set0_low);
+			cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
+				&camnoc_info->specific[i].dynattr_mainctl);
 			cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
 				&camnoc_info->specific[i].qosgen_mainctl);
 			cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
@@ -955,6 +960,10 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw,
 		camnoc_info = &cam680_cpas100_camnoc_info;
 		qchannel_info = &cam680_cpas100_qchannel_info;
 		break;
+	case CAM_CPAS_TITAN_680_V110:
+		camnoc_info = &cam680_cpas110_camnoc_info;
+		qchannel_info = &cam680_cpas110_qchannel_info;
+		break;
 	case CAM_CPAS_TITAN_165_V100:
 		camnoc_info = &cam165_cpas100_camnoc_info;
 		break;

drivers/cam_cpas/cpas_top/cpastop_v680_110.h

@@ -0,0 +1,1296 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CPASTOP_V680_110_H_
+#define _CPASTOP_V680_110_H_
+
+#define TEST_IRQ_ENABLE 0
+
+static struct cam_camnoc_irq_sbm cam_cpas_v680_110_irq_sbm = {
+	.sbm_enable = {
+		.access_type = CAM_REG_TYPE_READ_WRITE,
+		.enable = true,
+		.offset = 0x2240, /* CAM_NOC_SBM_FAULTINEN0_LOW */
+		.value = 0x2 |    /* SBM_FAULTINEN0_LOW_PORT1_MASK */
+			0x04 |     /* SBM_FAULTINEN0_LOW_PORT2_MASK */
+			0x08 |     /* SBM_FAULTINEN0_LOW_PORT3_MASK */
+			0x10 |    /* SBM_FAULTINEN0_LOW_PORT4_MASK */
+			0x20 |    /* SBM_FAULTINEN0_LOW_PORT5_MASK */
+			(TEST_IRQ_ENABLE ?
+			0x80 :    /* SBM_FAULTINEN0_LOW_PORT7_MASK */
+			0x0),
+	},
+	.sbm_status = {
+		.access_type = CAM_REG_TYPE_READ,
+		.enable = true,
+		.offset = 0x2248, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */
+	},
+	.sbm_clear = {
+		.access_type = CAM_REG_TYPE_WRITE,
+		.enable = true,
+		.offset = 0x2280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
+		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+	}
+};
+
+static struct cam_camnoc_irq_err
+	cam_cpas_v680_110_irq_err[] = {
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
+		.enable = false,
+		.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x2008, /* CAM_NOC_ERL_MAINCTL_LOW */
+			.value = 1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x2010, /* CAM_NOC_ERL_ERRVLD_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x2018, /* CAM_NOC_ERL_ERRCLR_LOW */
+			.value = 1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x59A0, /* IFE_UBWC_NIU_ENCERREN_LOW */
+			.value = 0xF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x5990, /* IFE_UBWC_NIU_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x5998, /* IFE_UBWC_NIU_ENCERRCLR_LOW */
+			.value = 0X1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_BPS_UBWC_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x7A0, /* CAM_NOC_BPS_WR_NIU_ENCERREN_LOW */
+			.value = 0XF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x790, /* CAM_NOC_BPS_WR_NIU_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x798, /* CAM_NOC_BPS_WR_NIU_ENCERRCLR_LOW */
+			.value = 0X1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x5F20, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */
+			.value = 0xFF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x5F10, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x5F18, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */
+			.value = 0X1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE1_UBWC_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x6520, /* CAM_NOC_IPE_1_RD_NIU_DECERREN_LOW */
+			.value = 0XFF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x6510, /* CAM_NOC_IPE_1_RD_NIU_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x6518, /* CAM_NOC_IPE_1_RD_NIU_DECERRCLR_LOW */
+			.value = 0X1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x6BA0, /* CAM_NOC_IPE_WR_NIU_ENCERREN_LOW */
+			.value = 0XF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x6B90, /* CAM_NOC_IPE_WR_NIU_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x6B98, /* CAM_NOC_IPE_WR_NIU_ENCERRCLR_LOW */
+			.value = 0x1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
+		.enable = false,
+		.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x2288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
+			.value = 0x1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x2290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
+		.enable = TEST_IRQ_ENABLE ? true : false,
+		.sbm_port = 0x80, /* SBM_FAULTINSTATUS0_LOW_PORT7_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x2288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
+			.value = 0x5,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x2290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
+		},
+	},
+};
+
+static struct cam_camnoc_specific
+	cam_cpas_v680_110_camnoc_specific[] = {
+	{
+		.port_type = CAM_CAMNOC_IFE_UBWC,
+		.port_name = "IFE_UBWC",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5830, /* IFE_UBWC_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5834, /* IFE_UBWC_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5838, /* IFE_UBWC_URGENCY_LOW */
+			.value = 0x1E30,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5840, /* IFE_UBWC_DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5848, /* IFE_UBWC_SAFELUT_LOW */
+			.value = 0x000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5A08, /* IFE_UBWC_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5A20, /* IFE_UBWC_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5A24, /* IFE_UBWC_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5820, /* IFE_UBWC_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_RDI_WR,
+		.port_name = "IFE_RDI_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5230, /* IFE_RDI_WR_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5234, /* IFE_RDI_WR_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5238, /* IFE_RDI_WR_URGENCY_LOW */
+			.value = 0x1E30,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5240, /* IFE_RDI_WR_DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5248, /* IFE_RDI_WR_SAFELUT_LOW */
+			.value = 0x000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5408, /* IFE_RDI_WR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5420, /* IFE_RDI_WR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5424, /* IFE_RDI_WR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5220, /* IFE_RDI_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_PDAF,
+		.port_name = "IFE_PDAF",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4c30, /* IFE_PDAF_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4c34, /* IFE_PDAF_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4c38, /* IFE_PDAF_URGENCY_LOW */
+			.value = 0x1B30,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4c40, /* IFE_PDAF_DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4c48, /* IFE_PDAF_SAFELUT_LOW */
+			.value = 0x000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4e08, /* IFE_PDAF_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4e20, /* IFE_PDAF_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4e24, /* IFE_PDAF_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x4C20, /* IFE_PDAF_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_LINEAR_STATS,
+		.port_name = "IFE_LINEAR_STATS",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4030, /* IFE_LINEAR_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4034, /* IFE_LINEAR_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4038, /* IFE_LINEAR_URGENCY_LOW */
+			.value = 0x1B30,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4040, /* IFE_LINEAR_DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4048, /* IFE_LINEAR_SAFELUT_LOW */
+			.value = 0x000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4208, /* IFE_LINEAR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4220, /* IFE_LINEAR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4224, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x4020, /* IFE_LINEAR_STATS_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_LINEAR_STATS_1,
+		.port_name = "IFE_LINEAR_STATS_1",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8230, /* IFE_LINEAR_1_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8234, /* IFE_LINEAR_1_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8238, /* IFE_LINEAR_1_URGENCY_LOW */
+			.value = 0x1B30,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8240, /* IFE_LINEAR_1_DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8248, /* IFE_LINEAR_1_SAFELUT_LOW */
+			.value = 0x000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8408, /* IFE_LINEAR_1_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8420, /* IFE_LINEAR_1_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x8424, /* IFE_LINEAR_1_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x8220, /* IFE_LINEAR_STATS_1_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IFE_LITE,
+		.port_name = "IFE_LITE",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4630, /* IFE_LITE_PRIORITYLUT_LOW */
+			.value = 0x66665433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4634, /* IFE_LITE_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4638, /* IFE_LITE_URGENCY_LOW */
+			.value = 0x1B30,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4640, /* IFE_LITE_DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4648, /* IFE_LITE_SAFELUT_LOW */
+			.value = 0x000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4808, /* IFE_LITE_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4820, /* IFE_LITE_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4824, /* IFE_LITE_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x4620, /* IFE_LITE_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_SFE_RD,
+		.port_name = "SFE_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7030, /* SFE_RD_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7034, /* SFE_RD_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7038, /* SFE_RD_URGENCY_LOW */
+			.value = 0x4,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7040, /* SFE_RD_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7048, /* SFE_RD_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7208, /* SFE_RD_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7220, /* SFE_RD_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7224, /* SFE_RD_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IPE_WR,
+		.port_name = "IPE_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6a30, /* IPE_WR_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6a34, /* IPE_WR_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6a38, /* IPE_WR_URGENCY_LOW */
+			.value = 0x30,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6a40, /* IPE_WR_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6a48, /* IPE_WR_SAFELUT_LOW */
+			.value = 0xffff,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6c08, /* IPE_WR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6c20, /* IPE_WR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6c24, /* IPE_WR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x6A20, /* IPE_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_BPS_WR,
+		.port_name = "BPS_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x630, /* BPS_WR_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x634, /* BPS_WR_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x638, /* BPS_WR_URGENCY_LOW */
+			.value = 0x30,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x640, /* BPS_WR_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x648, /* BPS_WR_SAFELUT_LOW */
+			.value = 0xffff,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x808, /* BPS_WR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x820, /* BPS_WR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x824, /* BPS_WR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x620, /* BPS_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_BPS_RD,
+		.port_name = "BPS_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x30, /* BPS_RD_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x34, /* BPS_RD_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x38, /* BPS_RD_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x40, /* BPS_RD_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x48, /* BPS_RD_SAFELUT_LOW */
+			.value = 0xffff,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x208, /* BPS_RD_QOSGEN_MAINCTL */
+			.value = 0x2,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x220, /* BPS_RD_QOSGEN_SHAPING_LOW */
+			.value = 0x14141414,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x224, /* BPS_RD_QOSGEN_SHAPING_HIGH */
+			.value = 0x14141414,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7c30, /* JPEG_PRIORITYLUT_LOW */
+			.value = 0x22222222,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7c34, /* JPEG_PRIORITYLUT_HIGH */
+			.value = 0x22222222,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7c38, /* JPEG_URGENCY_LOW */
+			.value = 0x22,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7c40, /* JPEG_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7c48, /* JPEG_SAFELUT_LOW */
+			.value = 0xffff,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7e08, /* JPEG_QOSGEN_MAINCTL */
+			.value = 0x2,
+		},
+		.qosgen_shaping_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7e20, /* JPEG_QOSGEN_SHAPING_LOW */
+			.value = 0x10101010,
+		},
+		.qosgen_shaping_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7e24, /* JPEG_QOSGEN_SHAPING_HIGH */
+			.value = 0x10101010,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x7C20, /* JPEG_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IPE0_RD,
+		.port_name = "IPE0_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E30, /* IPE0_RD_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E34, /* IPE0_RD_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E38, /* IPE0_RD_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E40, /* IPE0_RD_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E48, /* IPE0_RD_SAFELUT_LOW */
+			.value = 0xffff,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5F08, /* IPE0_RD_DECCTL_LOW */
+			.value = 1,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6008, /* IPE0_RD_QOSGEN_MAINCTL */
+			.value = 0x2,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6020, /* IPE0_RD_QOSGEN_SHAPING_LOW */
+			.value = 0x29292929,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6024, /* IPE0_RD_QOSGEN_SHAPING_HIGH */
+			.value = 0x29292929,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_IPE1_RD,
+		.port_name = "IPE1_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6430, /* IPE1_RD_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6434, /* IPE1_RD_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6438, /* IPE1_RD_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6440, /* IPE1_RD_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6448, /* IPE1_RD_SAFELUT_LOW */
+			.value = 0xffff,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6608, /* IPE1_RD_QOSGEN_MAINCTL */
+			.value = 0x2,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6620, /* IPE1_RD_QOSGEN_SHAPING_LOW */
+			.value = 0x29292929,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6624, /* IPE1_RD_QOSGEN_SHAPING_HIGH */
+			.value = 0x29292929,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x3830, /* CDM_PRIORITYLUT_LOW */
+			.value = 0x0,
+		},
+		.priority_lut_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x3834, /* CDM_PRIORITYLUT_HIGH */
+			.value = 0x0,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x3838, /* CDM_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x3840, /* CDM_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x3848, /* CDM_SAFELUT_LOW */
+			.value = 0xffff,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x3a08, /* CDM_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x3a20, /* CDM_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x3a24, /* CDM_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
+		.enable = true,
+		.flag_out_set0_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_WRITE,
+			.masked_value = 0,
+			.offset = 0x2288,
+			.value = 0x100000,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x7688, /* ICP_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x76A0, /* ICP_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x76A4, /* ICP_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+};
+
+static struct cam_camnoc_err_logger_info cam680_cpas110_err_logger_offsets = {
+	.mainctrl     =  0x2008, /* ERRLOGGER_MAINCTL_LOW */
+	.errvld       =  0x2010, /* ERRLOGGER_ERRVLD_LOW */
+	.errlog0_low  =  0x2020, /* ERRLOGGER_ERRLOG0_LOW */
+	.errlog0_high =  0x2024, /* ERRLOGGER_ERRLOG0_HIGH */
+	.errlog1_low  =  0x2028, /* ERRLOGGER_ERRLOG1_LOW */
+	.errlog1_high =  0x202c, /* ERRLOGGER_ERRLOG1_HIGH */
+	.errlog2_low  =  0x2030, /* ERRLOGGER_ERRLOG2_LOW */
+	.errlog2_high =  0x2034, /* ERRLOGGER_ERRLOG2_HIGH */
+	.errlog3_low  =  0x2038, /* ERRLOGGER_ERRLOG3_LOW */
+	.errlog3_high =  0x203c, /* ERRLOGGER_ERRLOG3_HIGH */
+};
+
+static struct cam_cpas_hw_errata_wa_list cam680_cpas110_errata_wa_list = {
+	.camnoc_flush_slave_pending_trans = {
+		.enable = false,
+		.data.reg_info = {
+			.access_type = CAM_REG_TYPE_READ,
+			.offset = 0x2300, /* sbm_SenseIn0_Low */
+			.mask = 0xE0000, /* Bits 17, 18, 19 */
+			.value = 0, /* expected to be 0 */
+		},
+	},
+};
+
+static struct cam_camnoc_info cam680_cpas110_camnoc_info = {
+	.specific = &cam_cpas_v680_110_camnoc_specific[0],
+	.specific_size = ARRAY_SIZE(cam_cpas_v680_110_camnoc_specific),
+	.irq_sbm = &cam_cpas_v680_110_irq_sbm,
+	.irq_err = &cam_cpas_v680_110_irq_err[0],
+	.irq_err_size = ARRAY_SIZE(cam_cpas_v680_110_irq_err),
+	.err_logger = &cam680_cpas110_err_logger_offsets,
+	.errata_wa_list = &cam680_cpas110_errata_wa_list,
+};
+
+static struct cam_cpas_camnoc_qchannel cam680_cpas110_qchannel_info = {
+	.qchannel_ctrl   = 0x5C,
+	.qchannel_status = 0x60,
+};
+#endif /* _CPASTOP_V680_110_H_ */
+

drivers/cam_cpas/cpas_top/cpastop_v780_100.h

@@ -1141,7 +1141,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_name = "ICP_RD_WR",
-		.enable = true,
+		.enable = false,
 		.dynattr_mainctl = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -1150,7 +1150,7 @@ static struct cam_camnoc_specific
 			.value = 0x10,
 		},
 		.qosgen_mainctl = {
-			.enable = true,
+			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
 			.offset = 0x5608, /* ICP_RD_WR : NOC_XM_ICP_QOSGEN_MAINCTL */
@@ -1213,4 +1213,3 @@ static struct cam_cpas_camnoc_qchannel cam780_cpas100_qchannel_info = {
 	.qchannel_status = 0x60,
 };
 #endif /* _CPASTOP_V780_100_H_ */
-

drivers/cam_cpas/include/cam_cpas_api.h

@@ -147,6 +147,7 @@ enum cam_cpas_hw_version {
 	CAM_CPAS_TITAN_570_V100 = 0x570100,
 	CAM_CPAS_TITAN_570_V200 = 0x570200,
 	CAM_CPAS_TITAN_680_V100 = 0x680100,
+	CAM_CPAS_TITAN_680_V110 = 0x680110,
 	CAM_CPAS_TITAN_780_V100 = 0x780100,
 	CAM_CPAS_TITAN_MAX
 };

drivers/cam_cust/cam_custom_dev.c

@@ -7,7 +7,6 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/module.h>
-#include <linux/ion.h>
 #include <linux/iommu.h>
 #include <linux/timer.h>
 #include <linux/kernel.h>
@@ -20,6 +19,7 @@
 #include "cam_node.h"
 #include "cam_debug_util.h"
 #include "cam_smmu_api.h"
+#include "cam_compat.h"
 #include "camera_main.h"
 
 static struct cam_custom_dev g_custom_dev;

drivers/cam_icp/icp_hw/a5_hw/a5_core.c

@@ -12,6 +12,7 @@
 #include <linux/delay.h>
 #include <linux/timer.h>
 #include <media/cam_icp.h>
+
 #include "cam_io_util.h"
 #include "cam_a5_hw_intf.h"
 #include "cam_hw.h"
@@ -28,6 +29,7 @@
 #include "cam_debug_util.h"
 #include "cam_icp_utils.h"
 #include "cam_common_util.h"
+#include "cam_compat.h"
 
 #define PC_POLL_DELAY_US 100
 #define PC_POLL_TIMEOUT_US 10000
@@ -678,7 +680,7 @@ int cam_a5_process_cmd(void *device_priv, uint32_t cmd_type,
 
 		if (a5_soc->ubwc_config_ext) {
 			/* Invoke kernel API to determine DDR type */
-			ddr_type = of_fdt_get_ddrtype();
+			ddr_type = cam_get_ddr_type();
 			if ((ddr_type == DDR_TYPE_LPDDR5) ||
 				(ddr_type == DDR_TYPE_LPDDR5X))
 				index = 1;

drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c

@@ -1934,36 +1934,29 @@ static int cam_icp_hw_mgr_create_debugfs_entry(void)
 	/* Store parent inode for cleanup in caller */
 	icp_hw_mgr.dentry = dbgfileptr;
 
-	dbgfileptr = debugfs_create_bool("icp_pc", 0644, icp_hw_mgr.dentry,
+	debugfs_create_bool("icp_pc", 0644, icp_hw_mgr.dentry,
 		&icp_hw_mgr.icp_pc_flag);
 
-	dbgfileptr = debugfs_create_bool("ipe_bps_pc", 0644, icp_hw_mgr.dentry,
+	debugfs_create_bool("ipe_bps_pc", 0644, icp_hw_mgr.dentry,
 		&icp_hw_mgr.ipe_bps_pc_flag);
 
-	dbgfileptr = debugfs_create_file("icp_debug_clk", 0644,
+	debugfs_create_file("icp_debug_clk", 0644,
 		icp_hw_mgr.dentry, NULL, &cam_icp_debug_default_clk);
 
-	dbgfileptr = debugfs_create_bool("icp_jtag_debug", 0644,
+	debugfs_create_bool("icp_jtag_debug", 0644,
 		icp_hw_mgr.dentry, &icp_hw_mgr.icp_jtag_debug);
 
-	dbgfileptr = debugfs_create_file("icp_debug_type", 0644,
+	debugfs_create_file("icp_debug_type", 0644,
 		icp_hw_mgr.dentry, NULL, &cam_icp_debug_type_fs);
 
-	dbgfileptr = debugfs_create_file("icp_debug_lvl", 0644,
+	debugfs_create_file("icp_debug_lvl", 0644,
 		icp_hw_mgr.dentry, NULL, &cam_icp_debug_fs);
 
-	dbgfileptr = debugfs_create_file("icp_fw_dump_lvl", 0644,
+	debugfs_create_file("icp_fw_dump_lvl", 0644,
 		icp_hw_mgr.dentry, NULL, &cam_icp_debug_fw_dump);
 
-	dbgfileptr = debugfs_create_bool("disable_ubwc_comp", 0644,
+	debugfs_create_bool("disable_ubwc_comp", 0644,
 		icp_hw_mgr.dentry, &icp_hw_mgr.disable_ubwc_comp);
-
-	if (IS_ERR(dbgfileptr)) {
-		if (PTR_ERR(dbgfileptr) == -ENODEV)
-			CAM_WARN(CAM_ICP, "DebugFS not enabled in kernel!");
-		else
-			rc = PTR_ERR(dbgfileptr);
-	}
 end:
 	/* Set default hang dump lvl */
 	icp_hw_mgr.icp_fw_dump_lvl = HFI_FW_DUMP_ON_FAILURE;
@@ -6553,6 +6546,7 @@ int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl,
 		(camera_hw_version == CAM_CPAS_TITAN_570_V100) ||
 		(camera_hw_version == CAM_CPAS_TITAN_570_V200) ||
 		(camera_hw_version == CAM_CPAS_TITAN_680_V100) ||
+		(camera_hw_version == CAM_CPAS_TITAN_680_V110) ||
 		(camera_hw_version == CAM_CPAS_TITAN_780_V100)) {
 		if (cam_caps & CPAS_TITAN_IPE0_CAP_BIT)
 			icp_hw_mgr.ipe0_enable = true;

drivers/cam_icp/icp_hw/lx7_hw/lx7_core.c

@@ -20,6 +20,7 @@
 #include "lx7_reg.h"
 #include "lx7_soc.h"
 #include "cam_common_util.h"
+#include "cam_compat.h"
 
 #define TZ_STATE_SUSPEND 0
 #define TZ_STATE_RESUME  1
@@ -45,7 +46,7 @@ static int cam_lx7_ubwc_configure(struct cam_hw_soc_info *soc_info)
 
 	soc_priv = soc_info->soc_private;
 
-	ddr_type = of_fdt_get_ddrtype();
+	ddr_type = cam_get_ddr_type();
 	if (ddr_type == DDR_TYPE_LPDDR5 || ddr_type == DDR_TYPE_LPDDR5X)
 		i = 1;
 

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

@@ -12680,40 +12680,33 @@ static int cam_ife_hw_mgr_debug_register(void)
 	/* Store parent inode for cleanup in caller */
 	g_ife_hw_mgr.debug_cfg.dentry = dbgfileptr;
 
-	dbgfileptr = debugfs_create_file("ife_csid_debug", 0644,
+	debugfs_create_file("ife_csid_debug", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_csid_debug);
 	debugfs_create_u32("enable_recovery", 0644, g_ife_hw_mgr.debug_cfg.dentry,
 		&g_ife_hw_mgr.debug_cfg.enable_recovery);
-	dbgfileptr = debugfs_create_bool("enable_req_dump", 0644,
+	debugfs_create_bool("enable_req_dump", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry,
 		&g_ife_hw_mgr.debug_cfg.enable_req_dump);
 	debugfs_create_u32("enable_csid_recovery", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry,
 		&g_ife_hw_mgr.debug_cfg.enable_csid_recovery);
-	dbgfileptr = debugfs_create_file("ife_camif_debug", 0644,
+	debugfs_create_file("ife_camif_debug", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_camif_debug);
-	dbgfileptr = debugfs_create_bool("per_req_reg_dump", 0644,
+	debugfs_create_bool("per_req_reg_dump", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry,
 		&g_ife_hw_mgr.debug_cfg.per_req_reg_dump);
-	dbgfileptr = debugfs_create_bool("disable_ubwc_comp", 0644,
+	debugfs_create_bool("disable_ubwc_comp", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry,
 		&g_ife_hw_mgr.debug_cfg.disable_ubwc_comp);
-	dbgfileptr = debugfs_create_file("sfe_debug", 0644,
+	debugfs_create_file("sfe_debug", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_sfe_debug);
-	dbgfileptr = debugfs_create_file("sfe_sensor_diag_sel", 0644,
+	debugfs_create_file("sfe_sensor_diag_sel", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_sfe_sensor_diag_debug);
-	dbgfileptr = debugfs_create_bool("disable_ife_mmu_prefetch", 0644,
+	debugfs_create_bool("disable_ife_mmu_prefetch", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry,
 		&g_ife_hw_mgr.debug_cfg.disable_ife_mmu_prefetch);
-	dbgfileptr = debugfs_create_file("sfe_cache_debug", 0644,
+	debugfs_create_file("sfe_cache_debug", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_sfe_cache_debug);
-
-	if (IS_ERR(dbgfileptr)) {
-		if (PTR_ERR(dbgfileptr) == -ENODEV)
-			CAM_WARN(CAM_ISP, "DebugFS not enabled in kernel!");
-		else
-			rc = PTR_ERR(dbgfileptr);
-	}
 end:
 	g_ife_hw_mgr.debug_cfg.enable_csid_recovery = 1;
 	return rc;

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h

@@ -284,7 +284,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 	.phy_num_mask                    = 0x3,
 	.vc_mask                         = 0x7C00000,
 	.dt_mask                         = 0x3f0000,
-	.wc_mask                         = 0xffff0000,
+	.wc_mask                         = 0xffff,
 	.calc_crc_mask                   = 0xffff,
 	.expected_crc_mask               = 0xffff,
 	.ecc_correction_shift_en         = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170_200.h

@@ -365,7 +365,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 	.phy_num_mask                    = 0x7,
 	.vc_mask                         = 0x7C00000,
 	.dt_mask                         = 0x3f0000,
-	.wc_mask                         = 0xffff0000,
+	.wc_mask                         = 0xffff,
 	.calc_crc_mask                   = 0xffff,
 	.expected_crc_mask               = 0xffff,
 	.ecc_correction_shift_en         = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h

@@ -348,7 +348,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 	.phy_num_mask                    = 0x3,
 	.vc_mask                         = 0x7C00000,
 	.dt_mask                         = 0x3f0000,
-	.wc_mask                         = 0xffff0000,
+	.wc_mask                         = 0xffff,
 	.calc_crc_mask                   = 0xffff,
 	.expected_crc_mask               = 0xffff,
 	.ecc_correction_shift_en         = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h

@@ -367,7 +367,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 	.phy_num_mask                    = 0x7,
 	.vc_mask                         = 0x7C00000,
 	.dt_mask                         = 0x3f0000,
-	.wc_mask                         = 0xffff0000,
+	.wc_mask                         = 0xffff,
 	.calc_crc_mask                   = 0xffff,
 	.expected_crc_mask               = 0xffff,
 	.ecc_correction_shift_en         = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid480.h

@@ -404,7 +404,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 	.phy_num_mask                    = 0x7,
 	.vc_mask                         = 0x7C00000,
 	.dt_mask                         = 0x3f0000,
-	.wc_mask                         = 0xffff0000,
+	.wc_mask                         = 0xffff,
 	.calc_crc_mask                   = 0xffff,
 	.expected_crc_mask               = 0xffff,
 	.ecc_correction_shift_en         = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h

@@ -12,6 +12,7 @@
 #include "cam_ife_csid_common.h"
 #include "cam_ife_csid_hw_ver2.h"
 #include "cam_irq_controller.h"
+#include "cam_isp_hw_mgr_intf.h"
 
 #define CAM_CSID_VERSION_V680                 0x60080000
 
@@ -173,11 +174,15 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_680_path_irq_desc[] = {
 	},
 	{
 		.bitmask = BIT(13),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
 		.desc = "ERROR_PIX_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
 	},
 	{
 		.bitmask = BIT(14),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
 		.desc = "ERROR_LINE_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
 	},
 	{
 		.bitmask = BIT(15),
@@ -197,6 +202,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_680_path_irq_desc[] = {
 	},
 	{
 		.bitmask = BIT(19),
+		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
 		.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
 	},
 	{
@@ -234,6 +240,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_680_path_irq_desc[] = {
 	{
 		.bitmask = BIT(28),
 		.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
+		.err_handler = cam_ife_csid_hw_ver2_mup_mismatch_handler,
 	},
 	{
 		.bitmask = BIT(29),
@@ -1050,7 +1057,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.phy_num_mask                    = 0xf,
 		.vc_mask                         = 0x7C00000,
 		.dt_mask                         = 0x3f0000,
-		.wc_mask                         = 0xffff0000,
+		.wc_mask                         = 0xffff,
 		.calc_crc_mask                   = 0xffff,
 		.expected_crc_mask               = 0xffff,
 		.ecc_correction_shift_en         = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680_110.h

@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _CAM_IFE_CSID_680_110_H_
+#define _CAM_IFE_CSID_680_110_H_
+
+#include <linux/module.h>
+#include "cam_ife_csid_dev.h"
+#include "camera_main.h"
+#include "cam_ife_csid_common.h"
+#include "cam_ife_csid_hw_ver2.h"
+#include "cam_irq_controller.h"
+
+static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_110_reg_info = {
+	.irq_reg_info                         = &cam_ife_csid_680_irq_reg_info,
+	.cmn_reg                              = &cam_ife_csid_680_cmn_reg_info,
+	.csi2_reg                             = &cam_ife_csid_680_csi2_reg_info,
+	.buf_done_irq_reg_info                =
+				    &cam_ife_csid_680_buf_done_irq_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_IPP]   = &cam_ife_csid_680_ipp_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_PPP]   = &cam_ife_csid_680_ppp_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_680_rdi_0_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_1] = &cam_ife_csid_680_rdi_1_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_680_rdi_2_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_680_rdi_3_reg_info,
+	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_4] = &cam_ife_csid_680_rdi_4_reg_info,
+	.top_reg                              = &cam_ife_csid_680_top_reg_info,
+	.input_core_sel = {
+		{
+			0x0,
+			0x1,
+			0x2,
+			0x3,
+			0x8,
+			-1,
+			-1,
+		},
+		{
+			0x0,
+			0x1,
+			0x2,
+			0x3,
+			-1,
+			-1,
+			-1,
+		},
+		{
+			0x0,
+			0x1,
+			0x2,
+			0x3,
+			-1,
+			0x9,
+			-1,
+		},
+	},
+	.need_top_cfg = 0x1,
+	.csid_cust_node_map = {0x1, 0x0, 0x2},
+	.rx_irq_desc        = cam_ife_csid_680_rx_irq_desc,
+	.path_irq_desc      = cam_ife_csid_680_path_irq_desc,
+};
+#endif /*_CAM_IFE_CSID_680_110_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid780.h

@@ -122,7 +122,9 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_780_rx_irq_desc[] = {
 static const struct cam_ife_csid_irq_desc cam_ife_csid_780_path_irq_desc[] = {
 	{
 		.bitmask = BIT(0),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FATAL,
 		.desc = "ILLEGAL_PROGRAMMING",
+		.err_handler = cam_ife_csid_ver2_print_illegal_programming_irq_status,
 	},
 	{
 		.bitmask = BIT(1),
@@ -174,11 +176,15 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_780_path_irq_desc[] = {
 	},
 	{
 		.bitmask = BIT(13),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
 		.desc = "ERROR_PIX_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
 	},
 	{
 		.bitmask = BIT(14),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
 		.desc = "ERROR_LINE_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
 	},
 	{
 		.bitmask = BIT(15),
@@ -198,6 +204,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_780_path_irq_desc[] = {
 	},
 	{
 		.bitmask = BIT(19),
+		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
 		.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
 	},
 	{
@@ -235,6 +242,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_780_path_irq_desc[] = {
 	{
 		.bitmask = BIT(28),
 		.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
+		.err_handler = cam_ife_csid_hw_ver2_mup_mismatch_handler,
 	},
 	{
 		.bitmask = BIT(29),
@@ -266,6 +274,7 @@ static const struct cam_ife_csid_top_irq_desc cam_ife_csid_780_top_irq_desc[] =
 		.err_type = CAM_ISP_HW_ERROR_CSID_FIFO_OVERFLOW,
 		.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
 		.desc = "Two or more RDIs programmed to access the shared line buffer",
+		.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
 	},
 };
 
@@ -1110,7 +1119,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.phy_num_mask                    = 0xf,
 		.vc_mask                         = 0x7C00000,
 		.dt_mask                         = 0x3f0000,
-		.wc_mask                         = 0xffff0000,
+		.wc_mask                         = 0xffff,
 		.calc_crc_mask                   = 0xffff,
 		.expected_crc_mask               = 0xffff,
 		.ecc_correction_shift_en         = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c

@@ -96,10 +96,8 @@ int cam_ife_csid_is_pix_res_format_supported(
 	return rc;
 }
 
-int cam_ife_csid_get_format_rdi(
-	uint32_t in_format, uint32_t out_format,
-	struct cam_ife_csid_path_format *path_format, bool rpp,
-	bool mipi_unpacked)
+static int cam_ife_csid_validate_rdi_format(uint32_t in_format,
+	uint32_t out_format)
 {
 	int rc = 0;
 
@@ -107,239 +105,217 @@ int cam_ife_csid_get_format_rdi(
 	case CAM_FORMAT_MIPI_RAW_6:
 		switch (out_format) {
 		case CAM_FORMAT_MIPI_RAW_6:
-			path_format->decode_fmt = 0xf;
-			if (rpp) {
-				path_format->decode_fmt = 0x0;
-				path_format->packing_fmt = 0x1;
-			}
-
-			if (mipi_unpacked) {
-				path_format->decode_fmt = 0x0;
-				path_format->packing_fmt = 0x0;
-				path_format->plain_fmt = 0x0;
-			}
-			break;
 		case CAM_FORMAT_PLAIN8:
-			path_format->decode_fmt = 0x0;
-			path_format->plain_fmt = 0x0;
-			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
 			break;
 		}
-		path_format->bits_per_pxl = 6;
 		break;
 	case CAM_FORMAT_MIPI_RAW_8:
 		switch (out_format) {
 		case CAM_FORMAT_MIPI_RAW_8:
 		case CAM_FORMAT_PLAIN128:
-			path_format->decode_fmt = 0xf;
-			if (rpp) {
-				path_format->decode_fmt = 0x1;
-				path_format->packing_fmt = 0x1;
-			}
-
-			if (mipi_unpacked) {
-				path_format->decode_fmt = 0x1;
-				path_format->packing_fmt = 0x0;
-				path_format->plain_fmt = 0x0;
-			}
-			break;
 		case CAM_FORMAT_PLAIN8:
-			path_format->decode_fmt = 0x1;
-			path_format->packing_fmt = 0;
-			path_format->plain_fmt = 0x0;
 			break;
 		default:
 			rc = -EINVAL;
 			break;
 		}
-		path_format->bits_per_pxl = 8;
 		break;
 	case CAM_FORMAT_MIPI_RAW_10:
 		switch (out_format) {
 		case CAM_FORMAT_MIPI_RAW_10:
 		case CAM_FORMAT_PLAIN128:
-			path_format->decode_fmt = 0xf;
-			if (rpp) {
-				path_format->decode_fmt = 0x2;
-				path_format->packing_fmt = 0x1;
-			}
-
-			if (mipi_unpacked) {
-				path_format->decode_fmt = 0x2;
-				path_format->packing_fmt = 0x0;
-				path_format->plain_fmt = 0x1;
-			}
-			break;
 		case CAM_FORMAT_PLAIN16_10:
-			path_format->decode_fmt = 0x2;
-			path_format->plain_fmt = 0x1;
-			path_format->packing_fmt = 0;
+		case CAM_FORMAT_PLAIN16_16:
 			break;
 		default:
 			rc = -EINVAL;
 			break;
 		}
-		path_format->bits_per_pxl = 10;
 		break;
 	case CAM_FORMAT_MIPI_RAW_12:
 		switch (out_format) {
 		case CAM_FORMAT_MIPI_RAW_12:
-			path_format->decode_fmt = 0xf;
-			if (rpp) {
-				path_format->decode_fmt = 0x3;
-				path_format->packing_fmt = 0x1;
-			}
-
-			if (mipi_unpacked) {
-				path_format->decode_fmt = 0x3;
-				path_format->packing_fmt = 0x0;
-				path_format->plain_fmt = 0x1;
-			}
-			break;
 		case CAM_FORMAT_PLAIN16_12:
-			path_format->decode_fmt = 0x3;
-			path_format->plain_fmt = 0x1;
-			path_format->packing_fmt = 0;
+		case CAM_FORMAT_PLAIN16_16:
 			break;
 		default:
 			rc = -EINVAL;
 			break;
 		}
-		path_format->bits_per_pxl = 12;
 		break;
 	case CAM_FORMAT_MIPI_RAW_14:
 		switch (out_format) {
 		case CAM_FORMAT_MIPI_RAW_14:
-			path_format->decode_fmt = 0xf;
-			if (rpp) {
-				path_format->decode_fmt = 0x4;
-				path_format->packing_fmt = 0x1;
-			}
-
-			if (mipi_unpacked) {
-				path_format->decode_fmt = 0x4;
-				path_format->packing_fmt = 0x0;
-				path_format->plain_fmt = 0x1;
-			}
-			break;
 		case CAM_FORMAT_PLAIN16_14:
-			path_format->decode_fmt = 0x4;
-			path_format->plain_fmt = 0x1;
-			path_format->packing_fmt = 0;
+		case CAM_FORMAT_PLAIN16_16:
 			break;
 		default:
 			rc = -EINVAL;
 			break;
 		}
-		path_format->bits_per_pxl = 14;
 		break;
 	case CAM_FORMAT_MIPI_RAW_16:
 		switch (out_format) {
 		case CAM_FORMAT_MIPI_RAW_16:
-			path_format->decode_fmt = 0xf;
-			if (rpp) {
-				path_format->decode_fmt = 0x5;
-				path_format->packing_fmt = 0x1;
-			}
-
-			if (mipi_unpacked) {
-				path_format->decode_fmt = 0x5;
-				path_format->packing_fmt = 0x0;
-				path_format->plain_fmt = 0x1;
-			}
-			break;
 		case CAM_FORMAT_PLAIN16_16:
-			path_format->decode_fmt = 0x5;
-			path_format->plain_fmt = 0x1;
-			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
 			break;
 		}
-		path_format->bits_per_pxl = 16;
 		break;
 	case CAM_FORMAT_MIPI_RAW_20:
 		switch (out_format) {
 		case CAM_FORMAT_MIPI_RAW_20:
-			path_format->decode_fmt = 0xf;
-			if (rpp) {
-				path_format->decode_fmt = 0x6;
-				path_format->packing_fmt = 0x1;
-			}
-
-			if (mipi_unpacked) {
-				path_format->decode_fmt = 0x6;
-				path_format->packing_fmt = 0x0;
-				path_format->plain_fmt = 0x2;
-			}
-			break;
 		case CAM_FORMAT_PLAIN32_20:
-			path_format->decode_fmt = 0x6;
-			path_format->plain_fmt = 0x2;
-			path_format->packing_fmt = 0;
 			break;
 		default:
 			rc = -EINVAL;
 			break;
 		}
-		path_format->bits_per_pxl = 20;
 		break;
-	case CAM_FORMAT_DPCM_10_6_10:
-		path_format->decode_fmt  = 0x7;
-		path_format->plain_fmt = 0x1;
-		path_format->packing_fmt = 0;
+	case CAM_FORMAT_YUV422:
+		switch (out_format) {
+		case CAM_FORMAT_YUV422:
+			break;
+		default:
+			rc = -EINVAL;
+			break;
+		}
 		break;
-	case CAM_FORMAT_DPCM_10_8_10:
-		path_format->decode_fmt  = 0x8;
-		path_format->plain_fmt = 0x1;
-		path_format->packing_fmt = 0;
+	case CAM_FORMAT_YUV422_10:
+		switch (out_format) {
+		case CAM_FORMAT_YUV422_10:
+			break;
+		default:
+			rc = -EINVAL;
+			break;
+		}
 		break;
-	case CAM_FORMAT_DPCM_12_6_12:
-		path_format->decode_fmt  = 0x9;
-		path_format->plain_fmt = 0x1;
-		path_format->packing_fmt = 0;
+	default:
+		rc = -EINVAL;
 		break;
-	case CAM_FORMAT_DPCM_12_8_12:
-		path_format->decode_fmt  = 0xA;
-		path_format->plain_fmt = 0x1;
-		path_format->packing_fmt = 0;
+	}
+
+	if (rc)
+		CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d",
+			in_format, out_format);
+	return rc;
+}
+
+int cam_ife_csid_get_format_rdi(
+	uint32_t in_format, uint32_t out_format,
+	struct cam_ife_csid_path_format *path_format, bool mipi_pack_supported,
+	bool mipi_unpacked)
+{
+	int rc = 0;
+
+	rc = cam_ife_csid_validate_rdi_format(in_format, out_format);
+	if (rc)
+		goto err;
+
+	memset(path_format, 0, sizeof(*path_format));
+	/* if no packing supported and input is same as output dump the raw payload */
+	if (!mipi_pack_supported && (in_format == out_format)) {
+		path_format->decode_fmt = 0xf;
+		goto end;
+	}
+
+	/* Configure the incoming stream format types */
+	switch (in_format) {
+	case CAM_FORMAT_MIPI_RAW_6:
+		path_format->decode_fmt = 0x0;
+		path_format->bits_per_pxl = 6;
 		break;
-	case CAM_FORMAT_DPCM_14_8_14:
-		path_format->decode_fmt  = 0xB;
-		path_format->plain_fmt = 0x1;
-		path_format->packing_fmt = 0;
+	case CAM_FORMAT_MIPI_RAW_8:
+	case CAM_FORMAT_YUV422:
+		path_format->decode_fmt = 0x1;
+		path_format->bits_per_pxl = 8;
 		break;
-	case CAM_FORMAT_DPCM_14_10_14:
-		path_format->decode_fmt  = 0xC;
-		path_format->plain_fmt = 0x1;
-		path_format->packing_fmt = 0;
+	case CAM_FORMAT_MIPI_RAW_10:
+	case CAM_FORMAT_YUV422_10:
+		path_format->decode_fmt = 0x2;
+		path_format->bits_per_pxl = 10;
 		break;
-	case CAM_FORMAT_DPCM_12_10_12:
-		path_format->decode_fmt  = 0xD;
-		path_format->plain_fmt = 0x1;
-		path_format->packing_fmt = 0;
+	case CAM_FORMAT_MIPI_RAW_12:
+		path_format->decode_fmt = 0x3;
+		path_format->bits_per_pxl = 12;
 		break;
+	case CAM_FORMAT_MIPI_RAW_14:
+		path_format->decode_fmt = 0x4;
+		path_format->bits_per_pxl = 14;
+		break;
+	case CAM_FORMAT_MIPI_RAW_16:
+		path_format->decode_fmt = 0x5;
+		path_format->bits_per_pxl = 16;
+		break;
+	case CAM_FORMAT_MIPI_RAW_20:
+		path_format->decode_fmt = 0x6;
+		path_format->bits_per_pxl = 20;
+		break;
+	default:
+		rc = -EINVAL;
+		goto err;
+	}
+
+	/* Configure the out stream format types */
+	switch (out_format) {
+	case CAM_FORMAT_MIPI_RAW_6:
+	case CAM_FORMAT_MIPI_RAW_8:
 	case CAM_FORMAT_YUV422:
-		path_format->decode_fmt  = 0x1;
-		path_format->plain_fmt = 0x01;
+		if (mipi_unpacked)
+			path_format->plain_fmt = 0x0;
+		else
+			path_format->packing_fmt = 0x1;
+		break;
+	case CAM_FORMAT_PLAIN128:
+	case CAM_FORMAT_PLAIN8:
+		path_format->plain_fmt = 0x0;
 		break;
+	case CAM_FORMAT_MIPI_RAW_10:
+	case CAM_FORMAT_MIPI_RAW_12:
+	case CAM_FORMAT_MIPI_RAW_14:
+	case CAM_FORMAT_MIPI_RAW_16:
 	case CAM_FORMAT_YUV422_10:
-		path_format->decode_fmt  = 0x2;
-		path_format->plain_fmt = 0x01;
+		if (mipi_unpacked)
+			path_format->plain_fmt = 0x1;
+		else
+			path_format->packing_fmt = 0x1;
+		break;
+	case CAM_FORMAT_PLAIN16_10:
+	case CAM_FORMAT_PLAIN16_12:
+	case CAM_FORMAT_PLAIN16_14:
+	case CAM_FORMAT_PLAIN16_16:
+		path_format->plain_fmt = 0x1;
+		break;
+	case CAM_FORMAT_MIPI_RAW_20:
+		if (mipi_unpacked)
+			path_format->plain_fmt = 0x2;
+		else
+			path_format->packing_fmt = 0x1;
+		break;
+	case CAM_FORMAT_PLAIN32_20:
+		path_format->plain_fmt = 0x2;
 		break;
 	default:
 		rc = -EINVAL;
-		break;
+		goto err;
 	}
 
-	if (rc)
-		CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d",
-			in_format, out_format);
+end:
+	CAM_DBG(CAM_ISP,
+		"in %u out %u plain_fmt %u packing %u decode %u bpp %u unpack %u pack supported %u",
+		in_format, out_format, path_format->plain_fmt, path_format->packing_fmt,
+		path_format->decode_fmt, path_format->bits_per_pxl, mipi_unpacked,
+		mipi_pack_supported);
+	return rc;
 
+err:
+	CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d",
+		in_format, out_format);
 	return rc;
 }
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h

@@ -104,26 +104,33 @@ enum cam_ife_csid_irq_reg {
 /*
  * struct cam_ife_csid_irq_desc: Structure to hold IRQ description
  *
- * @bitmask  :       Bitmask of the IRQ
- * @irq_desc:        String to describe the IRQ bit
+ * @bitmask    :     Bitmask of the IRQ
+ * @err_type   :     Error type for ISP hardware event
+ * @irq_desc   :     String to describe the IRQ bit
+ * @err_handler:     Error handler which gets invoked if error IRQ bit set
  */
 struct cam_ife_csid_irq_desc {
 	uint32_t    bitmask;
+	uint32_t    err_type;
 	uint8_t    *desc;
+	void       (*err_handler)(void *csid_hw, void *res);
 };
 
 /*
  * struct cam_ife_csid_top_irq_desc: Structure to hold IRQ bitmask and description
  *
- * @bitmask  :        Bitmask of the IRQ
- * @err_name :        IRQ name
- * @desc     :        String to describe about the IRQ
+ * @bitmask    :        Bitmask of the IRQ
+ * @err_type   :        Error type for ISP hardware event
+ * @err_name   :        IRQ name
+ * @desc       :        String to describe about the IRQ
+ * @err_handler:        Error handler which gets invoked if error IRQ bit set
  */
 struct cam_ife_csid_top_irq_desc {
 	uint32_t    bitmask;
 	uint32_t    err_type;
 	char       *err_name;
 	char       *desc;
+	void       (*err_handler)(void *csid_hw);
 };
 
 /*
@@ -358,7 +365,7 @@ int cam_ife_csid_is_pix_res_format_supported(
 
 int cam_ife_csid_get_format_rdi(
 	uint32_t in_format, uint32_t out_format,
-	struct cam_ife_csid_path_format *path_format, bool rpp,
+	struct cam_ife_csid_path_format *path_format, bool mipi_pack_supported,
 	bool mipi_unpacked);
 
 int cam_ife_csid_get_format_ipp_ppp(

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c

@@ -2151,7 +2151,6 @@ static int cam_ife_csid_ver1_init_config_rdi_path(
 	uint32_t  val;
 	struct cam_ife_csid_ver1_path_cfg *path_cfg;
 	struct cam_ife_csid_cid_data *cid_data;
-	bool is_rpp = false;
 	void __iomem *mem_base;
 	struct cam_ife_csid_path_format path_format = {0};
 
@@ -2170,9 +2169,8 @@ static int cam_ife_csid_ver1_init_config_rdi_path(
 	path_cfg = (struct cam_ife_csid_ver1_path_cfg *)res->res_priv;
 	cid_data = &csid_hw->cid_data[path_cfg->cid];
 	mem_base = soc_info->reg_map[0].mem_base;
-	is_rpp = path_cfg->crop_enable || path_cfg->drop_enable;
 	rc = cam_ife_csid_get_format_rdi(path_cfg->in_format,
-		path_cfg->out_format, &path_format, is_rpp, false);
+		path_cfg->out_format, &path_format, path_reg->mipi_pack_supported, false);
 	if (rc)
 		return rc;
 
@@ -2306,7 +2304,6 @@ static int cam_ife_csid_ver1_init_config_udi_path(
 	uint32_t  val;
 	struct cam_ife_csid_ver1_path_cfg *path_cfg;
 	struct cam_ife_csid_cid_data *cid_data;
-	bool is_rpp = false;
 	void __iomem *mem_base;
 	struct cam_ife_csid_path_format path_format = {0};
 	uint32_t id;
@@ -2328,9 +2325,8 @@ static int cam_ife_csid_ver1_init_config_udi_path(
 	path_cfg = (struct cam_ife_csid_ver1_path_cfg *)res->res_priv;
 	cid_data = &csid_hw->cid_data[path_cfg->cid];
 	mem_base = soc_info->reg_map[0].mem_base;
-	is_rpp = path_cfg->crop_enable || path_cfg->drop_enable;
 	rc = cam_ife_csid_get_format_rdi(path_cfg->in_format,
-		path_cfg->out_format, &path_format, is_rpp, false);
+		path_cfg->out_format, &path_format, path_reg->mipi_pack_supported, false);
 	if (rc)
 		return rc;
 
@@ -3801,8 +3797,8 @@ static int cam_ife_csid_ver1_handle_rx_debug_event(
 		CAM_INFO_RATE_LIMIT(CAM_ISP,
 			"Csid :%d Long pkt VC: %d DT: %d WC: %d",
 			csid_hw->hw_intf->hw_idx,
-			val & csi2_reg->vc_mask,
-			val & csi2_reg->dt_mask,
+			(val & csi2_reg->vc_mask) >> 22,
+			(val & csi2_reg->dt_mask) >> 16,
 			val & csi2_reg->wc_mask);
 
 		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
@@ -3825,16 +3821,16 @@ static int cam_ife_csid_ver1_handle_rx_debug_event(
 		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
 			csi2_reg->captured_short_pkt_0_addr);
 		CAM_INFO_RATE_LIMIT(CAM_ISP,
-			"Csid :%d Long pkt VC: %d DT: %d LC: %d",
+			"Csid :%d Short pkt VC: %d DT: %d LC: %d",
 			csid_hw->hw_intf->hw_idx,
-			val & csi2_reg->vc_mask,
-			val & csi2_reg->dt_mask,
+			(val & csi2_reg->vc_mask) >> 22,
+			(val & csi2_reg->dt_mask) >> 16,
 			val & csi2_reg->wc_mask);
 
 		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
 			csi2_reg->captured_short_pkt_1_addr);
 		CAM_INFO_RATE_LIMIT(CAM_ISP,
-			"Csid :%d Long pkt ECC: %d",
+			"Csid :%d Short pkt ECC: %d",
 			csid_hw->hw_intf->hw_idx, val);
 		break;
 	case IFE_CSID_VER1_RX_CPHY_PKT_HDR_CAPTURED:
@@ -3844,8 +3840,8 @@ static int cam_ife_csid_ver1_handle_rx_debug_event(
 		CAM_INFO_RATE_LIMIT(CAM_ISP,
 			"Csid :%d CPHY pkt VC: %d DT: %d LC: %d",
 			csid_hw->hw_intf->hw_idx,
-			val & csi2_reg->vc_mask,
-			val & csi2_reg->dt_mask,
+			(val & csi2_reg->vc_mask) >> 22,
+			(val & csi2_reg->dt_mask) >> 16,
 			val & csi2_reg->wc_mask);
 		break;
 	case IFE_CSID_VER1_RX_UNMAPPED_VC_DT:

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -794,8 +794,8 @@ static int cam_ife_csid_ver2_handle_rx_debug_event(
 		CAM_INFO_RATE_LIMIT(CAM_ISP,
 			"Csid :%d Long pkt VC: %d DT: %d WC: %d",
 			csid_hw->hw_intf->hw_idx,
-			val & csi2_reg->vc_mask,
-			val & csi2_reg->dt_mask,
+			(val & csi2_reg->vc_mask) >> 22,
+			(val & csi2_reg->dt_mask) >> 16,
 			val & csi2_reg->wc_mask);
 
 		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
@@ -818,16 +818,16 @@ static int cam_ife_csid_ver2_handle_rx_debug_event(
 		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
 			csi2_reg->captured_short_pkt_0_addr);
 		CAM_INFO_RATE_LIMIT(CAM_ISP,
-			"Csid :%d Long pkt VC: %d DT: %d LC: %d",
+			"Csid :%d Short pkt VC: %d DT: %d LC: %d",
 			csid_hw->hw_intf->hw_idx,
-			val & csi2_reg->vc_mask,
-			val & csi2_reg->dt_mask,
+			(val & csi2_reg->vc_mask) >> 22,
+			(val & csi2_reg->dt_mask) >> 16,
 			val & csi2_reg->wc_mask);
 
 		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
 			csi2_reg->captured_short_pkt_1_addr);
 		CAM_INFO_RATE_LIMIT(CAM_ISP,
-			"Csid :%d Long pkt ECC: %d",
+			"Csid :%d Short pkt ECC: %d",
 			csid_hw->hw_intf->hw_idx, val);
 		break;
 	case IFE_CSID_VER2_RX_CPHY_PKT_HDR_CAPTURED:
@@ -837,8 +837,8 @@ static int cam_ife_csid_ver2_handle_rx_debug_event(
 		CAM_INFO_RATE_LIMIT(CAM_ISP,
 			"Csid :%d CPHY pkt VC: %d DT: %d LC: %d",
 			csid_hw->hw_intf->hw_idx,
-			val & csi2_reg->vc_mask,
-			val & csi2_reg->dt_mask,
+			(val & csi2_reg->vc_mask) >> 22,
+			(val & csi2_reg->dt_mask) >> 16,
 			val & csi2_reg->wc_mask);
 		break;
 	case IFE_CSID_VER2_RX_UNMAPPED_VC_DT:
@@ -1159,10 +1159,67 @@ end:
 	return 0;
 }
 
-static void cam_ife_csid_ver2_print_illegal_programming_irq_status(
-	struct cam_ife_csid_ver2_hw *csid_hw,
-	struct cam_isp_resource_node    *res)
+void cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler(
+	void *csid)
+{
+	struct cam_ife_csid_ver2_hw       *csid_hw  = csid;
+	struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg;
+	struct cam_hw_soc_info            *soc_info = &csid_hw->hw_info->soc_info;
+	void __iomem                      *base =
+		soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
+	const struct cam_ife_csid_ver2_path_reg_info *path_reg;
+	uint32_t i = 0, rdi_cfg = 0;
+	uint8_t *log_buf = NULL;
+	size_t len = 0;
+
+	for (i = CAM_IFE_PIX_PATH_RES_RDI_0; i < CAM_IFE_PIX_PATH_RES_RDI_4;
+		i++) {
+		path_reg = csid_reg->path_reg[i - CAM_IFE_PIX_PATH_RES_RDI_0];
+
+		if (!(path_reg->capabilities &
+			CAM_IFE_CSID_CAP_LINE_SMOOTHING_IN_RDI))
+			continue;
+
+		rdi_cfg = cam_io_r_mb(base + path_reg->cfg1_addr);
+
+		if (rdi_cfg & path_reg->pix_store_en_shift_val)
+			CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
+				"LINE BUFFER ENABLED for RDI%d", (i - CAM_IFE_PIX_PATH_RES_RDI_0));
+	}
+
+	if (len)
+		CAM_ERR(CAM_ISP, "CSID[%d] %s", csid_hw->hw_intf->hw_idx, log_buf);
+
+}
+
+void cam_ife_csid_hw_ver2_mup_mismatch_handler(
+	void *csid, void *resource)
+{
+	struct cam_ife_csid_ver2_hw       *csid_hw = csid;
+        struct cam_isp_resource_node      *res = resource;
+	struct cam_ife_csid_ver2_path_cfg *path_cfg =
+		(struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
+	struct cam_ife_csid_cid_data      *cid_data = &csid_hw->cid_data[path_cfg->cid];
+
+	CAM_INFO(CAM_ISP, "CSID:%d Last MUP value 0x%x programmed for res [id: %d name: %s]",
+		csid_hw->hw_intf->hw_idx, csid_hw->rx_cfg.mup, res->res_id, res->res_name);
+
+	if (cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].valid) {
+		CAM_INFO(CAM_ISP, "vc0 %d vc1 %d" ,
+			cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].vc,
+			cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_1].vc);
+	} else {
+		CAM_ERR(CAM_ISP, "Multi-VCDT is not enabled, vc0 %d" ,
+			cid_data->vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_0].vc);
+	}
+
+}
+
+void cam_ife_csid_ver2_print_illegal_programming_irq_status(
+	void *csid, void *resource)
 {
+	struct cam_ife_csid_ver2_hw       *csid_hw = csid;
+        struct cam_isp_resource_node      *res = resource;
 	struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg;
 	struct cam_ife_csid_ver2_path_cfg *path_cfg =
 		(struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
@@ -1279,7 +1336,8 @@ static void cam_ife_csid_ver2_print_debug_reg_status(
 }
 
 static int cam_ife_csid_ver2_parse_path_irq_status(
-	struct cam_ife_csid_ver2_hw *csid_hw,
+	struct cam_ife_csid_ver2_hw  *csid_hw,
+	struct cam_isp_resource_node *res,
 	uint32_t                     index,
 	uint32_t                     err_mask,
 	uint32_t                     irq_status)
@@ -1287,7 +1345,7 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
 	const uint8_t                          **irq_reg_tag;
 	const struct cam_ife_csid_ver2_reg_info *csid_reg;
 	uint32_t                                 bit_pos = 0;
-	uint32_t                                 status;
+	uint32_t                                 status, err_type = 0;
 	uint32_t                                 sof_irq_debug_en = 0;
 	size_t                                   len = 0;
 	uint8_t                                 *log_buf = NULL;
@@ -1302,9 +1360,14 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
 
 	status = irq_status & err_mask;
 	while (status) {
-		if (status & 0x1 )
+		if (status & 0x1 ) {
 			CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, "%s",
 				csid_reg->path_irq_desc[bit_pos].desc);
+			if (csid_reg->path_irq_desc[bit_pos].err_type)
+				err_type |=  csid_reg->path_irq_desc[bit_pos].err_type;
+			if (csid_reg->path_irq_desc[bit_pos].err_handler)
+				csid_reg->path_irq_desc[bit_pos].err_handler(csid_hw, res);
+		}
 		bit_pos++;
 		status >>= 1;
 	}
@@ -1340,7 +1403,7 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
 		}
 	}
 
-	return 0;
+	return err_type;
 }
 
 static int cam_ife_csid_ver2_top_err_irq_bottom_half(
@@ -1379,6 +1442,8 @@ static int cam_ife_csid_ver2_top_err_irq_bottom_half(
 			CAM_ERR(CAM_ISP, "%s %s",
 				csid_reg->top_irq_desc[i].err_name,
 				csid_reg->top_irq_desc[i].desc);
+			if (csid_reg->top_irq_desc[i].err_handler)
+				csid_reg->top_irq_desc[i].err_handler(csid_hw);
 			event_type |= csid_reg->top_irq_desc[i].err_type;
 		}
 	}
@@ -1394,16 +1459,17 @@ static int cam_ife_csid_ver2_top_err_irq_bottom_half(
 	return 0;
 }
 
-static void cam_ife_csid_ver2_print_format_measure_info(
-	struct cam_ife_csid_ver2_hw *csid_hw,
-	struct cam_isp_resource_node *res)
+void cam_ife_csid_ver2_print_format_measure_info(
+	void *csid, void *resource)
 {
-	uint32_t expected_frame = 0, actual_frame = 0;
+	struct cam_ife_csid_ver2_hw       *csid_hw = csid;
+        struct cam_isp_resource_node      *res = resource;
 	struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg;
 	const struct cam_ife_csid_ver2_path_reg_info *path_reg =
 		csid_reg->path_reg[res->res_id];
 	struct cam_hw_soc_info *soc_info = &csid_hw->hw_info->soc_info;
 	void __iomem *base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
+	uint32_t expected_frame = 0, actual_frame = 0;
 
 	actual_frame = cam_io_r_mb(base + path_reg->format_measure0_addr);
 	expected_frame = cam_io_r_mb(base + path_reg->format_measure_cfg1_addr);
@@ -1504,36 +1570,11 @@ static int cam_ife_csid_ver2_ipp_bottom_half(
 		goto unlock;
 	}
 
-	cam_ife_csid_ver2_parse_path_irq_status(
-		csid_hw,
+	err_type = cam_ife_csid_ver2_parse_path_irq_status(
+		csid_hw, res,
 		CAM_IFE_CSID_IRQ_REG_IPP,
 		err_mask, irq_status_ipp);
 
-
-	if (irq_status_ipp & IFE_CSID_VER2_PATH_ERROR_ILLEGAL_PROGRAM) {
-		if (path_reg->fatal_err_mask &
-			IFE_CSID_VER2_PATH_ERROR_ILLEGAL_PROGRAM) {
-			CAM_ERR(CAM_ISP, "CSID[%u] Illegal Programming for IPP status:0x%x",
-				csid_hw->hw_intf->hw_idx,irq_status_ipp);
-			cam_ife_csid_ver2_print_illegal_programming_irq_status(
-				csid_hw, res);
-		} else {
-			CAM_ERR(CAM_ISP, "Illegal Programming IRQ is not supported");
-			CAM_INFO(CAM_ISP, "CSID[%u]: status:0x%x",
-				csid_hw->hw_intf->hw_idx, irq_status_ipp);
-		}
-		err_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
-	}
-
-	if (irq_status_ipp & IFE_CSID_VER2_PATH_RECOVERY_OVERFLOW)
-		err_type |= CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW;
-
-	if (irq_status_ipp & (IFE_CSID_VER2_PATH_ERROR_PIX_COUNT |
-		IFE_CSID_VER2_PATH_ERROR_LINE_COUNT)) {
-		cam_ife_csid_ver2_print_format_measure_info(csid_hw, res);
-		err_type |= CAM_ISP_HW_ERROR_CSID_FRAME_SIZE;
-	}
-
 	if (err_type)
 		cam_ife_csid_ver2_handle_event_err(csid_hw,
 			irq_status_ipp,
@@ -1604,34 +1645,10 @@ static int cam_ife_csid_ver2_ppp_bottom_half(
 			csid_hw->hw_intf->hw_idx);
 		goto unlock;
 	}
-	cam_ife_csid_ver2_parse_path_irq_status(
-		csid_hw, CAM_IFE_CSID_IRQ_REG_PPP,
+	err_type = cam_ife_csid_ver2_parse_path_irq_status(
+		csid_hw, res, CAM_IFE_CSID_IRQ_REG_PPP,
 		err_mask, irq_status_ppp);
 
-	if (irq_status_ppp & IFE_CSID_VER2_PATH_ERROR_ILLEGAL_PROGRAM) {
-		if (path_reg->fatal_err_mask &
-			IFE_CSID_VER2_PATH_ERROR_ILLEGAL_PROGRAM) {
-			CAM_ERR(CAM_ISP, "CSID[%u] Illegal Programming for PPP status:0x%x",
-				csid_hw->hw_intf->hw_idx,irq_status_ppp);
-			cam_ife_csid_ver2_print_illegal_programming_irq_status(
-				csid_hw, res);
-		} else {
-			CAM_ERR(CAM_ISP, "Illegal Programming IRQ is not supported");
-			CAM_INFO(CAM_ISP, "CSID[%u]: status:0x%x",
-				csid_hw->hw_intf->hw_idx, irq_status_ppp);
-		}
-		err_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
-	}
-
-	if (irq_status_ppp & (IFE_CSID_VER2_PATH_ERROR_PIX_COUNT |
-		IFE_CSID_VER2_PATH_ERROR_LINE_COUNT)) {
-		cam_ife_csid_ver2_print_format_measure_info(csid_hw, res);
-		err_type |= CAM_ISP_HW_ERROR_CSID_FRAME_SIZE;
-	}
-
-	if (irq_status_ppp & IFE_CSID_VER2_PATH_RECOVERY_OVERFLOW)
-		err_type |= CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW;
-
 	if (err_type)
 		cam_ife_csid_ver2_handle_event_err(csid_hw,
 			irq_status_ppp,
@@ -1711,36 +1728,10 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 		goto end;
 	}
 
-	cam_ife_csid_ver2_parse_path_irq_status(csid_hw,
+	err_type = cam_ife_csid_ver2_parse_path_irq_status(csid_hw, res,
 		path_cfg->irq_reg_idx,
 		err_mask, irq_status_rdi);
 
-	if (irq_status_rdi & IFE_CSID_VER2_PATH_ERROR_ILLEGAL_PROGRAM) {
-		if (rdi_reg->fatal_err_mask &
-			IFE_CSID_VER2_PATH_ERROR_ILLEGAL_PROGRAM) {
-			CAM_ERR(CAM_ISP, "CSID[%u]: Illegal Programming for RDI:%d status:0x%x",
-				csid_hw->hw_intf->hw_idx,
-				res->res_id, irq_status_rdi);
-			cam_ife_csid_ver2_print_illegal_programming_irq_status(
-				csid_hw, res);
-		} else {
-			CAM_ERR(CAM_ISP, "Illegal Programming IRQ is not supported");
-			CAM_INFO(CAM_ISP, "CSID[%u]: RDI:%d status:0x%x",
-				csid_hw->hw_intf->hw_idx,
-				res->res_id, irq_status_rdi);
-		}
-		err_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
-	}
-
-	if (irq_status_rdi & IFE_CSID_VER2_PATH_RECOVERY_OVERFLOW)
-		err_type |= CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW;
-
-	if (irq_status_rdi & (IFE_CSID_VER2_PATH_ERROR_PIX_COUNT |
-				IFE_CSID_VER2_PATH_ERROR_LINE_COUNT)) {
-		cam_ife_csid_ver2_print_format_measure_info(csid_hw, res);
-		err_type |= CAM_ISP_HW_ERROR_CSID_FRAME_SIZE;
-	}
-
 	spin_unlock(&csid_hw->lock_state);
 	if (err_type) {
 
@@ -2181,7 +2172,6 @@ static int cam_ife_csid_hw_ver2_config_path_data(
 	uint32_t cid)
 {
 	int rc = 0, i = 0;
-	bool is_rpp = false;
 	const struct cam_ife_csid_ver2_reg_info *csid_reg =
 		(struct cam_ife_csid_ver2_reg_info *)csid_hw->core_info->csid_reg;
 	struct cam_ife_csid_cid_data *cid_data = &csid_hw->cid_data[cid];
@@ -2258,7 +2248,6 @@ static int cam_ife_csid_hw_ver2_config_path_data(
 	case CAM_IFE_PIX_PATH_RES_RDI_2:
 	case CAM_IFE_PIX_PATH_RES_RDI_3:
 	case CAM_IFE_PIX_PATH_RES_RDI_4:
-		is_rpp = path_cfg->crop_enable || path_cfg->drop_enable;
 		/*
 		 * if csid gives unpacked out, packing needs to be done at
 		 * WM side if needed, based on the format the decision is
@@ -2270,7 +2259,7 @@ static int cam_ife_csid_hw_ver2_config_path_data(
 			path_cfg->in_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0],
 			path_cfg->out_format,
 			&path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_0],
-			is_rpp, reserve->use_wm_pack);
+			path_reg->mipi_pack_supported, reserve->use_wm_pack);
 		if (rc)
 			goto end;
 
@@ -2281,7 +2270,7 @@ static int cam_ife_csid_hw_ver2_config_path_data(
 				path_cfg->in_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1],
 				path_cfg->out_format,
 				&path_cfg->path_format[CAM_IFE_CSID_MULTI_VC_DT_GRP_1],
-				is_rpp, reserve->use_wm_pack);
+				path_reg->mipi_pack_supported, reserve->use_wm_pack);
 			if (rc)
 				goto end;
 		}

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h

@@ -623,5 +623,9 @@ int cam_ife_csid_hw_ver2_init(struct cam_hw_intf  *csid_hw_intf,
 	bool is_custom);
 
 int cam_ife_csid_hw_ver2_deinit(struct cam_hw_info *hw_priv);
+void cam_ife_csid_ver2_print_illegal_programming_irq_status(void *csid_hw, void *res);
+void cam_ife_csid_ver2_print_format_measure_info(void *csid_hw, void *res);
+void cam_ife_csid_hw_ver2_mup_mismatch_handler(void *csid_hw, void *res);
+void cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler(void *csid_hw);
 
 #endif

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h

@@ -10,6 +10,7 @@
 #include "cam_ife_csid_dev.h"
 #include "cam_ife_csid_hw_ver2.h"
 #include "cam_irq_controller.h"
+#include "cam_isp_hw_mgr_intf.h"
 
 static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_rx_irq_desc[] = {
 	{
@@ -169,11 +170,15 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_path_irq_desc[]
 	},
 	{
 		.bitmask = BIT(13),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
 		.desc = "ERROR_PIX_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
 	},
 	{
 		.bitmask = BIT(14),
-		.desc = "ERROR_LINE_COUNT",
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
+		.desc = "ERROR_PIX_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
 	},
 	{
 		.bitmask = BIT(15),
@@ -193,6 +198,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_path_irq_desc[]
 	},
 	{
 		.bitmask = BIT(19),
+		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
 		.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
 	},
 	{
@@ -230,6 +236,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_path_irq_desc[]
 	{
 		.bitmask = BIT(28),
 		.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
+		.err_handler = cam_ife_csid_hw_ver2_mup_mismatch_handler,
 	},
 	{
 		.bitmask = BIT(29),
@@ -424,7 +431,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.phy_num_mask                         = 0xf,
 		.vc_mask                              = 0x7C00000,
 		.dt_mask                              = 0x3f0000,
-		.wc_mask                              = 0xffff0000,
+		.wc_mask                              = 0xffff,
 		.calc_crc_mask                        = 0xffff,
 		.expected_crc_mask                    = 0xffff,
 		.ecc_correction_shift_en              = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite780.h

@@ -118,7 +118,9 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_rx_irq_desc[] =
 static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_path_irq_desc[] = {
 	{
 		.bitmask = BIT(0),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FATAL,
 		.desc = "ILLEGAL_PROGRAMMING",
+		.err_handler = cam_ife_csid_ver2_print_illegal_programming_irq_status,
 	},
 	{
 		.bitmask = BIT(1),
@@ -170,11 +172,15 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_path_irq_desc[]
 	},
 	{
 		.bitmask = BIT(13),
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
 		.desc = "ERROR_PIX_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
 	},
 	{
 		.bitmask = BIT(14),
-		.desc = "ERROR_LINE_COUNT",
+		.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
+		.desc = "ERROR_PIX_COUNT",
+		.err_handler = cam_ife_csid_ver2_print_format_measure_info,
 	},
 	{
 		.bitmask = BIT(15),
@@ -194,6 +200,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_path_irq_desc[]
 	},
 	{
 		.bitmask = BIT(19),
+		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
 		.desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
 	},
 	{
@@ -231,6 +238,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_path_irq_desc[]
 	{
 		.bitmask = BIT(28),
 		.desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
+		.err_handler = cam_ife_csid_hw_ver2_mup_mismatch_handler,
 	},
 	{
 		.bitmask = BIT(29),
@@ -262,6 +270,7 @@ static const struct cam_ife_csid_top_irq_desc cam_ife_csid_lite_780_top_irq_desc
 		.err_type = CAM_ISP_HW_ERROR_CSID_FIFO_OVERFLOW,
 		.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
 		.desc = "Two or more RDIs programmed to access the shared line buffer",
+		.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
 	},
 };
 
@@ -459,7 +468,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.phy_num_mask                         = 0xf,
 		.vc_mask                              = 0x7C00000,
 		.dt_mask                              = 0x3f0000,
-		.wc_mask                              = 0xffff0000,
+		.wc_mask                              = 0xffff,
 		.calc_crc_mask                        = 0xffff,
 		.expected_crc_mask                    = 0xffff,
 		.ecc_correction_shift_en              = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.c

@@ -64,6 +64,10 @@ static const struct of_device_id cam_ife_csid_lite_dt_match[] = {
 		.compatible = "qcom,csid-lite680",
 		.data = &cam_ife_csid_lite_680_hw_info,
 	},
+	{
+		.compatible = "qcom,csid-lite680_110",
+		.data = &cam_ife_csid_lite_680_hw_info,
+	},
 	{
 		.compatible = "qcom,csid-lite780",
 		.data = &cam_ife_csid_lite_780_hw_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c

@@ -17,6 +17,7 @@
 #include "cam_ife_csid570.h"
 #include "cam_ife_csid580.h"
 #include "cam_ife_csid680.h"
+#include "cam_ife_csid680_110.h"
 #include "cam_ife_csid780.h"
 
 #define CAM_CSID_DRV_NAME                    "csid"
@@ -66,6 +67,11 @@ static struct cam_ife_csid_core_info cam_ife_csid680_hw_info = {
 	.sw_version  = CAM_IFE_CSID_VER_2_0,
 };
 
+static struct cam_ife_csid_core_info cam_ife_csid680_110_hw_info = {
+	.csid_reg = &cam_ife_csid_680_reg_info,
+	.sw_version  = CAM_IFE_CSID_VER_2_0,
+};
+
 static struct cam_ife_csid_core_info cam_ife_csid780_hw_info = {
 	.csid_reg = &cam_ife_csid_780_reg_info,
 	.sw_version  = CAM_IFE_CSID_VER_2_0,
@@ -109,6 +115,10 @@ static const struct of_device_id cam_ife_csid_dt_match[] = {
 		.compatible = "qcom,csid680",
 		.data = &cam_ife_csid680_hw_info,
 	},
+	{
+		.compatible = "qcom,csid680_110",
+		.data = &cam_ife_csid680_110_hw_info,
+	},
 	{
 		.compatible = "qcom,csid780",
 		.data = &cam_ife_csid780_hw_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe680.h

@@ -948,6 +948,7 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.mid[0]        = 25,
 			.num_wm        = 1,
 			.wm_idx        = 8,
+			.en_line_done  = 1,
 			.name          = "RDI_0",
 		},
 		{
@@ -958,6 +959,7 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.mid[0]        = 26,
 			.num_wm        = 1,
 			.wm_idx        = 9,
+			.en_line_done  = 1,
 			.name          = "RDI_1",
 		},
 		{
@@ -968,6 +970,7 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.mid[0]        = 27,
 			.num_wm        = 1,
 			.wm_idx        = 10,
+			.en_line_done  = 1,
 			.name          = "RDI_2",
 		},
 		{

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe780.h

@@ -1295,6 +1295,7 @@ static struct cam_sfe_bus_wr_hw_info sfe780_bus_wr_hw_info = {
 			.mid[0]        = 45,
 			.num_wm        = 1,
 			.wm_idx        = 11,
+			.en_line_done  = 1,
 			.name          = "RDI_0",
 		},
 		{
@@ -1305,6 +1306,7 @@ static struct cam_sfe_bus_wr_hw_info sfe780_bus_wr_hw_info = {
 			.mid[0]        = 46,
 			.num_wm        = 1,
 			.wm_idx        = 12,
+			.en_line_done  = 1,
 			.name          = "RDI_1",
 		},
 		{
@@ -1315,6 +1317,7 @@ static struct cam_sfe_bus_wr_hw_info sfe780_bus_wr_hw_info = {
 			.mid[0]        = 47,
 			.num_wm        = 1,
 			.wm_idx        = 13,
+			.en_line_done  = 1,
 			.name          = "RDI_2",
 		},
 		{

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.c

@@ -456,7 +456,7 @@ static int cam_sfe_bus_start_rm(struct cam_isp_resource_node *rm_res)
 		rm_data->hw_regs->buf_width);
 	cam_io_w_mb(rm_data->height, common_data->mem_base +
 		rm_data->hw_regs->buf_height);
-	cam_io_w_mb(rm_data->width, common_data->mem_base +
+	cam_io_w_mb(rm_data->stride, common_data->mem_base +
 		rm_data->hw_regs->stride);
 	cam_io_w_mb(rm_data->unpacker_cfg, common_data->mem_base +
 		rm_data->hw_regs->unpacker_cfg);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c

@@ -141,6 +141,7 @@ struct cam_sfe_bus_wr_wm_resource_data {
 	bool                 init_cfg_done;
 	bool                 hfr_cfg_done;
 	bool                 use_wm_pack;
+	bool                 en_line_done;
 };
 
 struct cam_sfe_bus_wr_comp_grp_data {
@@ -863,8 +864,7 @@ static int cam_sfe_bus_start_wm(struct cam_isp_resource_node *wm_res)
 		common_data->mem_base + rsrc_data->hw_regs->packer_cfg);
 
 	/* configure line_done_cfg for RDI0-2 */
-	if ((rsrc_data->index >= 8) &&
-		(rsrc_data->index <= 10)) {
+	if (rsrc_data->en_line_done) {
 		CAM_DBG(CAM_SFE, "configure line_done_cfg 0x%x for WM: %d",
 			rsrc_data->common_data->line_done_cfg,
 			rsrc_data->index);
@@ -944,7 +944,8 @@ static int cam_sfe_bus_init_wm_resource(uint32_t index,
 	struct cam_sfe_bus_wr_priv      *bus_priv,
 	struct cam_sfe_bus_wr_hw_info   *hw_info,
 	struct cam_isp_resource_node    *wm_res,
-	uint8_t                         *wm_name)
+	uint8_t                         *wm_name,
+	bool                             en_line_done)
 {
 	struct cam_sfe_bus_wr_wm_resource_data *rsrc_data;
 
@@ -957,6 +958,7 @@ static int cam_sfe_bus_init_wm_resource(uint32_t index,
 	wm_res->res_priv = rsrc_data;
 
 	rsrc_data->index = index;
+	rsrc_data->en_line_done = en_line_done;
 	rsrc_data->hw_regs = &hw_info->bus_client_reg[index];
 	rsrc_data->common_data = &bus_priv->common_data;
 
@@ -1943,7 +1945,8 @@ static int cam_sfe_bus_init_sfe_out_resource(
 			hw_info->sfe_out_hw_info[index].wm_idx,
 			bus_priv, hw_info,
 			&rsrc_data->wm_res[i],
-			hw_info->sfe_out_hw_info[index].name);
+			hw_info->sfe_out_hw_info[index].name,
+			hw_info->sfe_out_hw_info[index].en_line_done);
 	if (rc < 0) {
 		CAM_ERR(CAM_SFE, "SFE:%d init WM:%d failed rc:%d",
 			bus_priv->common_data.core_index, i, rc);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.h

@@ -138,6 +138,7 @@ struct cam_sfe_bus_sfe_out_hw_info {
 	uint32_t                            mid[CAM_SFE_BUS_MAX_MID_PER_PORT];
 	uint32_t                            num_wm;
 	uint32_t                            wm_idx;
+	uint32_t                            en_line_done;
 	uint8_t                            *name;
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c

@@ -12,6 +12,7 @@
 #include "cam_vfe570.h"
 #include "cam_vfe580.h"
 #include "cam_vfe680.h"
+#include "cam_vfe680_110.h"
 #include "cam_vfe780.h"
 #include "cam_vfe_lite17x.h"
 #include "cam_vfe_lite48x.h"
@@ -55,6 +56,10 @@ static const struct of_device_id cam_vfe_dt_match[] = {
 		.compatible = "qcom,vfe680",
 		.data = &cam_vfe680_hw_info,
 	},
+	{
+		.compatible = "qcom,vfe680_110",
+		.data = &cam_vfe680_110_hw_info,
+	},
 	{
 		.compatible = "qcom,vfe780",
 		.data = &cam_vfe780_hw_info,
@@ -83,6 +88,10 @@ static const struct of_device_id cam_vfe_dt_match[] = {
 		.compatible = "qcom,vfe-lite680",
 		.data = &cam_vfe_lite68x_hw_info,
 	},
+	{
+		.compatible = "qcom,vfe-lite680_110",
+		.data = &cam_vfe_lite68x_hw_info,
+	},
 	{
 		.compatible = "qcom,vfe-lite780",
 		.data = &cam_vfe_lite78x_hw_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe680_110.h

@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _CAM_VFE680_110_H_
+#define _CAM_VFE680_110_H_
+#include "cam_vfe_top_ver4.h"
+#include "cam_vfe_core.h"
+#include "cam_vfe_bus_ver3.h"
+#include "cam_irq_controller.h"
+
+#define CAM_VFE_680_110_NUM_DBG_REG              17
+
+static struct cam_vfe_top_ver4_reg_offset_common vfe680_110_top_common_reg = {
+	.hw_version               = 0x00000000,
+	.hw_capability            = 0x00000004,
+	.lens_feature             = 0x00000008,
+	.stats_feature            = 0x0000000C,
+	.color_feature            = 0x00000010,
+	.zoom_feature             = 0x00000014,
+	.core_cfg_0               = 0x00000024,
+	.core_cfg_1               = 0x00000028,
+	.core_cfg_2               = 0x0000002C,
+	.global_reset_cmd         = 0x00000030,
+	.diag_config              = 0x00000050,
+	.diag_sensor_status_0     = 0x00000054,
+	.diag_sensor_status_1     = 0x00000058,
+	.diag_frm_cnt_status_0    = 0x0000005C,
+	.diag_frm_cnt_status_1    = 0x00000060,
+	.ipp_violation_status     = 0x00000064,
+	.pdaf_violation_status    = 0x00000404,
+	.core_cfg_3               = 0x00000068,
+	.core_cgc_ovd_0           = 0x00000018,
+	.core_cgc_ovd_1           = 0x0000001C,
+	.ahb_cgc_ovd              = 0x00000020,
+	.dsp_status               = 0x0000006C,
+	.stats_throttle_cfg_0     = 0x00000070,
+	.stats_throttle_cfg_1     = 0x00000074,
+	.stats_throttle_cfg_2     = 0x00000078,
+	.core_cfg_4               = 0x00000080,
+	.core_cfg_5               = 0x00000084,
+	.core_cfg_6               = 0x00000088,
+	.period_cfg               = 0x0000008C,
+	.irq_sub_pattern_cfg      = 0x00000090,
+	.epoch0_pattern_cfg       = 0x00000094,
+	.epoch1_pattern_cfg       = 0x00000098,
+	.epoch_height_cfg         = 0x0000009C,
+	.bus_violation_status     = 0x00000C64,
+	.bus_overflow_status      = 0x00000C68,
+	.top_debug_cfg            = 0x000000FC,
+	.num_top_debug_reg        = CAM_VFE_680_110_NUM_DBG_REG,
+	.top_debug = {
+		0x000000A0,
+		0x000000A4,
+		0x000000A8,
+		0x000000AC,
+		0x000000B0,
+		0x000000B4,
+		0x000000B8,
+		0x000000BC,
+		0x000000C0,
+		0x000000C4,
+		0x000000C8,
+		0x000000CC,
+		0x000000D0,
+		0x000000D4,
+		0x000000D8,
+		0x000000DC,
+		0x000000E0,
+	},
+};
+
+struct cam_vfe_ver4_path_hw_info
+	vfe680_110_rdi_hw_info_arr[CAM_VFE_RDI_VER2_MAX] = {
+	{
+		.common_reg     = &vfe680_110_top_common_reg,
+		.reg_data       = &vfe680_vfe_full_rdi_reg_data[0],
+	},
+	{
+		.common_reg     = &vfe680_110_top_common_reg,
+		.reg_data       = &vfe680_vfe_full_rdi_reg_data[1],
+	},
+	{
+		.common_reg     = &vfe680_110_top_common_reg,
+		.reg_data       = &vfe680_vfe_full_rdi_reg_data[2],
+	},
+};
+
+static struct cam_vfe_top_ver4_hw_info vfe680_110_top_hw_info = {
+	.common_reg = &vfe680_110_top_common_reg,
+	.vfe_full_hw_info = {
+		.common_reg     = &vfe680_110_top_common_reg,
+		.reg_data       = &vfe_pp_common_reg_data,
+	},
+	.pdlib_hw_info = {
+		.common_reg     = &vfe680_110_top_common_reg,
+		.reg_data       = &vfe680_pdlib_reg_data,
+	},
+	.rdi_hw_info[0] = &vfe680_110_rdi_hw_info_arr[0],
+	.rdi_hw_info[1] = &vfe680_110_rdi_hw_info_arr[1],
+	.rdi_hw_info[2] = &vfe680_110_rdi_hw_info_arr[2],
+	.wr_client_desc         = vfe680_wr_client_desc,
+	.ipp_module_desc        = vfe680_ipp_mod_desc,
+	.num_mux = 5,
+	.mux_type = {
+		CAM_VFE_CAMIF_VER_4_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_PDLIB_VER_1_0,
+	},
+	.num_path_port_map = 2,
+	.path_port_map = {
+		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_2PD},
+		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PREPROCESS_2PD}
+	},
+	.num_top_errors                  = ARRAY_SIZE(vfe680_top_irq_err_desc),
+	.top_err_desc                    = vfe680_top_irq_err_desc,
+	.num_pdaf_violation_errors       = ARRAY_SIZE(vfe680_pdaf_violation_desc),
+	.pdaf_violation_desc             = vfe680_pdaf_violation_desc,
+	.debug_reg_info                  = &vfe680_dbg_reg_info,
+};
+
+static struct cam_vfe_hw_info cam_vfe680_110_hw_info = {
+	.irq_hw_info                  = &vfe680_irq_hw_info,
+
+	.bus_version                   = CAM_VFE_BUS_VER_3_0,
+	.bus_hw_info                   = &vfe680_bus_hw_info,
+
+	.top_version                   = CAM_VFE_TOP_VER_4_0,
+	.top_hw_info                   = &vfe680_110_top_hw_info,
+};
+
+#endif /* _CAM_VFE680_110_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

@@ -25,6 +25,7 @@
 #include "cam_trace.h"
 #include "cam_smmu_api.h"
 #include "cam_common_util.h"
+#include "cam_compat.h"
 
 static const char drv_name[] = "vfe_bus";
 
@@ -1881,7 +1882,7 @@ static int cam_vfe_bus_ver3_init_comp_grp(uint32_t index,
 		rsrc_data->comp_grp_type != CAM_VFE_BUS_VER3_COMP_GRP_1)
 		rsrc_data->ubwc_static_ctrl = 0;
 	else {
-		ddr_type = of_fdt_get_ddrtype();
+		ddr_type = cam_get_ddr_type();
 		if ((ddr_type == DDR_TYPE_LPDDR5) ||
 			(ddr_type == DDR_TYPE_LPDDR5X))
 			rsrc_data->ubwc_static_ctrl =

drivers/cam_req_mgr/cam_mem_mgr.c

@@ -23,6 +23,7 @@
 #include "cam_trace.h"
 #include "cam_common_util.h"
 #include "cam_presil_hw_access.h"
+#include "cam_compat.h"
 
 #define CAM_MEM_SHARED_BUFFER_PAD_4K (4 * 1024)
 
@@ -37,13 +38,13 @@ static int cam_mem_mgr_get_dma_heaps(void);
 #ifdef CONFIG_CAM_PRESIL
 static inline void cam_mem_mgr_reset_presil_params(int idx)
 {
-        tbl.bufq[idx].presil_params.fd_for_umd_daemon = -1;
-        tbl.bufq[idx].presil_params.refcount = 0;
+	tbl.bufq[idx].presil_params.fd_for_umd_daemon = -1;
+	tbl.bufq[idx].presil_params.refcount = 0;
 }
 #else
 static inline void cam_mem_mgr_reset_presil_params(int idx)
 {
-        return;
+	return;
 }
 #endif
 
@@ -109,12 +110,9 @@ static int cam_mem_util_get_dma_dir(uint32_t flags)
 	return rc;
 }
 
-static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
-	uintptr_t *vaddr,
-	size_t *len)
+static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf, uintptr_t *vaddr, size_t *len)
 {
 	int rc = 0;
-	void *addr;
 
 	/*
 	 * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
@@ -126,24 +124,20 @@ static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
 		return rc;
 	}
 
-	addr = dma_buf_vmap(dmabuf);
-	if (!addr) {
-		CAM_ERR(CAM_MEM, "kernel map fail");
-		*vaddr = 0;
+	rc = cam_compat_util_get_dmabuf_va(dmabuf, vaddr);
+	if (rc) {
+		CAM_ERR(CAM_MEM, "kernel vmap failed: rc = %d", rc);
 		*len = 0;
-		rc = -ENOSPC;
-		goto fail;
+		dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
+	}
+	else {
+		*len = dmabuf->size;
+		CAM_DBG(CAM_MEM, "vaddr = %llu, len = %zu", *vaddr, *len);
 	}
 
-	*vaddr = (uint64_t)addr;
-	*len = dmabuf->size;
-
-	return 0;
-
-fail:
-	dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
 	return rc;
 }
+
 static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
 	uint64_t vaddr)
 {
@@ -185,14 +179,8 @@ static int cam_mem_mgr_create_debug_fs(void)
 	/* Store parent inode for cleanup in caller */
 	tbl.dentry = dbgfileptr;
 
-	dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
+	debugfs_create_bool("alloc_profile_enable", 0644,
 		tbl.dentry, &tbl.alloc_profile_enable);
-	if (IS_ERR(dbgfileptr)) {
-		if (PTR_ERR(dbgfileptr) == -ENODEV)
-			CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
-		else
-			rc = PTR_ERR(dbgfileptr);
-	}
 end:
 	return rc;
 }

drivers/cam_req_mgr/cam_req_mgr_debug.c

@@ -126,20 +126,14 @@ int cam_req_mgr_debug_register(struct cam_req_mgr_core_device *core_dev)
 	/* Store parent inode for cleanup in caller */
 	debugfs_root = dbgfileptr;
 
-	dbgfileptr = debugfs_create_file("sessions_info", 0644, debugfs_root,
+	debugfs_create_file("sessions_info", 0644, debugfs_root,
 		core_dev, &session_info);
-	dbgfileptr = debugfs_create_file("bubble_recovery", 0644,
+	debugfs_create_file("bubble_recovery", 0644,
 		debugfs_root, core_dev, &bubble_recovery);
-	dbgfileptr = debugfs_create_bool("recovery_on_apply_fail", 0644,
+	debugfs_create_bool("recovery_on_apply_fail", 0644,
 		debugfs_root, &core_dev->recovery_on_apply_fail);
 	debugfs_create_u32("delay_detect_count", 0644, debugfs_root,
 		&cam_debug_mgr_delay_detect);
-	if (IS_ERR(dbgfileptr)) {
-		if (PTR_ERR(dbgfileptr) == -ENODEV)
-			CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
-		else
-			rc = PTR_ERR(dbgfileptr);
-	}
 end:
 	return rc;
 }

drivers/cam_req_mgr/cam_req_mgr_dev.c

@@ -17,7 +17,6 @@
 #include <media/v4l2-ioctl.h>
 #include <media/cam_req_mgr.h>
 #include <media/cam_defs.h>
-#include <linux/list_sort.h>
 
 #include "cam_req_mgr_dev.h"
 #include "cam_req_mgr_util.h"
@@ -28,6 +27,7 @@
 #include "cam_common_util.h"
 #include "cam_compat.h"
 #include "cam_cpas_hw.h"
+#include "cam_compat.h"
 
 #define CAM_REQ_MGR_EVENT_MAX 30
 
@@ -685,24 +685,6 @@ void cam_subdev_notify_message(u32 subdev_type,
 }
 EXPORT_SYMBOL(cam_subdev_notify_message);
 
-
-static int cam_req_mgr_ordered_list_cmp(void *priv,
-	struct list_head *head_1, struct list_head *head_2)
-{
-	struct cam_subdev *entry_1 =
-		list_entry(head_1, struct cam_subdev, list);
-	struct cam_subdev *entry_2 =
-		list_entry(head_2, struct cam_subdev, list);
-	int ret = -1;
-
-	if (entry_1->close_seq_prior > entry_2->close_seq_prior)
-		return 1;
-	else if (entry_1->close_seq_prior < entry_2->close_seq_prior)
-		return ret;
-	else
-		return 0;
-}
-
 bool cam_req_mgr_is_open(void)
 {
 	bool crm_status = false;

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -401,6 +401,7 @@ static int32_t cam_csiphy_update_secure_info(
 	case CSIPHY_VERSION_V123:
 	case CSIPHY_VERSION_V124:
 	case CSIPHY_VERSION_V210:
+	case CSIPHY_VERSION_V211:
 		phy_mask_len =
 		(csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) ?
 		(CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES) :

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

@@ -14,6 +14,7 @@
 #include "include/cam_csiphy_1_2_5_hwreg.h"
 #include "include/cam_csiphy_2_0_hwreg.h"
 #include "include/cam_csiphy_2_1_0_hwreg.h"
+#include "include/cam_csiphy_2_1_1_hwreg.h"
 
 /* Clock divide factor for CPHY spec v1.0 */
 #define CSIPHY_DIVISOR_16                    16
@@ -472,6 +473,23 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 		csiphy_dev->clk_lane = 0;
 		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_1_0;
 		csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_0;
+	} else if (of_device_is_compatible(soc_info->dev->of_node,
+		"qcom,csiphy-v2.1.1")) {
+		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_1_1_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v2_1_1_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_1_1_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
+		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_1_1;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_1_1;
+		csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_enter_reg_2_1_1;
+		csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = csiphy_reset_exit_reg_2_1_1;
+		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_1_1;
+		csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;
+		csiphy_dev->hw_version = CSIPHY_VERSION_V211;
+		csiphy_dev->is_divisor_32_comp = true;
+		csiphy_dev->clk_lane = 0;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_1_1;
+		csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_1;
 	} else {
 		CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",
 			csiphy_dev->hw_version);

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h

@@ -31,6 +31,7 @@
 #define CSIPHY_VERSION_V20                        0x20
 #define CSIPHY_VERSION_V201                       0x201
 #define CSIPHY_VERSION_V210                       0x210
+#define CSIPHY_VERSION_V211                       0x211
 
 /**
  * @csiphy_dev: CSIPhy device structure

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_1_hwreg.h

@@ -0,0 +1,1051 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CAM_CSIPHY_2_1_1_HWREG_H_
+#define _CAM_CSIPHY_2_1_1_HWREG_H_
+
+#include "../cam_csiphy_dev.h"
+
+struct cam_cphy_dphy_status_reg_params_t status_regs_2_1_1 = {
+	.csiphy_3ph_status0_offset = 0x0340,
+	.csiphy_2ph_status0_offset = 0x00C0,
+	.cphy_lane_status = {0x0358, 0x0758, 0x0B58},
+	.csiphy_3ph_status_size = 24,
+	.csiphy_2ph_status_size = 20,
+};
+
+struct csiphy_reg_parms_t csiphy_v2_1_1 = {
+	.mipi_csiphy_interrupt_status0_addr = 0x10B0,
+	.status_reg_params = &status_regs_2_1_1,
+	.size_offset_betn_lanes = 0x400,
+	.mipi_csiphy_interrupt_clear0_addr = 0x1058,
+	.mipi_csiphy_glbl_irq_cmd_addr = 0x1028,
+	.csiphy_common_array_size = 4,
+	.csiphy_reset_enter_array_size = 2,
+	.csiphy_reset_exit_array_size = 3,
+	.csiphy_2ph_config_array_size = 23,
+	.csiphy_3ph_config_array_size = 37,
+	.csiphy_2ph_clock_lane = 0x1,
+	.csiphy_2ph_combo_ck_ln = 0x10,
+	.csiphy_interrupt_status_size = 11,
+	.csiphy_num_common_status_regs = 20,
+	.aon_sel_params = NULL,
+};
+
+struct csiphy_reg_t csiphy_common_reg_2_1_1[] = {
+	{0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE},
+	{0x1084, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1018, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x101C, 0x7A, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
+struct csiphy_reg_t csiphy_reset_enter_reg_2_1_1[] = {
+	{0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE},
+	{0x1000, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},
+};
+
+struct csiphy_reg_t csiphy_reset_exit_reg_2_1_1[] = {
+	{0x1000, 0x02, 0x00, CSIPHY_2PH_REGS},
+	{0x1000, 0x00, 0x00, CSIPHY_2PH_COMBO_REGS},
+	{0x1000, 0x0E, 0xBE8, CSIPHY_3PH_REGS},
+};
+
+struct csiphy_reg_t csiphy_irq_reg_2_1_1[] = {
+	{0x102c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1030, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1034, 0xfb, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1038, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x103c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1040, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1044, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1048, 0xef, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x104c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1050, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+	{0x1054, 0xff, 0x64, CSIPHY_DEFAULT_PARAMS},
+};
+
+struct csiphy_reg_t csiphy_2ph_v2_1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
+	{
+		{0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E94, 0xD7, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+	},
+	{
+		{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0828, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x080C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C28, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C00, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C0C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x0C5C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0C60, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+};
+
+struct csiphy_reg_t
+	csiphy_2ph_v2_1_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
+	{
+		{0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0E94, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+	},
+	{
+		{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x080C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0828, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
+		{0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL},
+		{0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL},
+		{0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
+	},
+	{
+		{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
+		{0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C28, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0C94, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+		{0x0C64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+	},
+};
+
+struct csiphy_reg_t csiphy_3ph_v2_1_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
+	{
+		{0x0268, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0294, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02F8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02FC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02F0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
+		{0x02F0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0294, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0204, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x020C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+		{0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0218, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x021C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0220, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0224, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x022C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0264, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0244, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0310, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x02BC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0230, 0x94, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0234, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0238, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x023C, 0xA6, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0258, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0254, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x025C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0248, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x024C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0240, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0260, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
+	},
+	{
+		{0x0668, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0694, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06F8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06FC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06F0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
+		{0x06F0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0694, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0604, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x060C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+		{0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0618, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x061C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0620, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0624, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x062C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0664, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0644, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0710, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x06BC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0630, 0x94, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0634, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0638, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x063C, 0xA6, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0658, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0654, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x065C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0648, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x064C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0640, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0660, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
+	},
+	{
+		{0x0A68, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AF4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AF8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AFC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AF0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
+		{0x0AF0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
+		{0x0A94, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A0C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+		{0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+		{0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AE4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AE8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0AEC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A18, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A1C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A20, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A24, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A28, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A2C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A64, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A44, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0B10, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0ABC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A30, 0x94, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A34, 0x31, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A38, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A3C, 0xA6, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A58, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A54, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A48, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A4C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A40, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A60, 0xA8, 0x64, CSIPHY_DEFAULT_PARAMS},
+	},
+};
+struct csiphy_reg_t bist_arr_2_1_1[] = {
+	/* 3Phase BIST CONFIGURATION REG SET */
+	{0x02D4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x02D8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0250, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0244, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0240, 0x85, 0x00, CSIPHY_3PH_REGS},
+	{0x06D4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x06D8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0650, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0644, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0640, 0x85, 0x00, CSIPHY_3PH_REGS},
+	{0x0AD4, 0x64, 0x00, CSIPHY_3PH_REGS},
+	{0x0AD8, 0x3E, 0x00, CSIPHY_3PH_REGS},
+	{0x0A50, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0A44, 0xB1, 0x00, CSIPHY_3PH_REGS},
+	{0x0A40, 0x85, 0x00, CSIPHY_3PH_REGS},
+};
+
+struct csiphy_reg_t bist_status_arr_2_1_1[] = {
+
+	{0x0344, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0744, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x0B44, 0x00, 0x00, CSIPHY_3PH_REGS},
+	{0x00C0, 0x00, 0x00, CSIPHY_2PH_REGS},
+	{0x04C0, 0x00, 0x00, CSIPHY_2PH_REGS},
+	{0x08C0, 0x00, 0x00, CSIPHY_2PH_REGS},
+	{0x0CC0, 0x00, 0x00, CSIPHY_2PH_REGS},
+};
+
+struct bist_reg_settings_t bist_setting_2_1_1 = {
+	.error_status_val_3ph = 0x10,
+	.error_status_val_2ph = 0x10,
+	.set_status_update_3ph_base_offset = 0x0240,
+	.set_status_update_2ph_base_offset = 0x0050,
+	.bist_status_3ph_base_offset = 0x0344,
+	.bist_status_2ph_base_offset = 0x00C0,
+	.bist_sensor_data_3ph_status_base_offset = 0x0340,
+	.bist_counter_3ph_base_offset = 0x0348,
+	.bist_counter_2ph_base_offset = 0x00C8,
+	.number_of_counters = 2,
+	.num_data_settings = ARRAY_SIZE(bist_arr_2_1_1),
+	.bist_arry = bist_arr_2_1_1,
+	.num_status_reg = ARRAY_SIZE(bist_status_arr_2_1_1),
+	.bist_status_arr = bist_status_arr_2_1_1,
+};
+
+struct data_rate_settings_t data_rate_delta_table_2_1_1 = {
+	.num_data_rate_settings = 12,
+	.data_rate_settings = {
+		{
+			/* ((1.2 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 2736000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x0C, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x0C, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x70, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x11, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((1.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 3420000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((1.7 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 3876000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2.1 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 4788000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2.35 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 5358000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2.6 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 5928000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2.8 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 6384000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((3.3 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 7524000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((3.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 7980000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((4 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 9120000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((4.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 10260000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((5.0 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 11400000000,
+			.data_rate_reg_array_size = 8,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0278, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x026C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0678, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x066C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DNP_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A78, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A6C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x108C, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+	},
+};
+
+#endif /* _CAM_CSIPHY_2_1_1_HWREG_H_ */

drivers/cam_sensor_module/cam_tpg/cam_tpg_dev.c

@@ -7,6 +7,7 @@
 #include "cam_tpg_core.h"
 #include "camera_main.h"
 #include "tpg_hw/tpg_hw_v_1_0/tpg_hw_v_1_0_data.h"
+#include "tpg_hw/tpg_hw_v_1_2/tpg_hw_v_1_2_data.h"
 #include "tpg_hw/tpg_hw_v_1_3/tpg_hw_v_1_3_data.h"
 
 static int cam_tpg_subdev_close(struct v4l2_subdev *sd,
@@ -369,6 +370,10 @@ static const struct of_device_id cam_tpg_dt_match[] = {
 		.compatible = "qcom,cam-tpg101",
 		.data = &tpg_v_1_0_hw_info,
 	},
+	{
+		.compatible = "qcom,cam-tpg102",
+		.data = &tpg_v_1_2_hw_info,
+	},
 	{
 		.compatible = "qcom,cam-tpg103",
 		.data = &tpg_v_1_3_hw_info,

drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.c

@@ -379,6 +379,7 @@ int tpg_hw_start(struct tpg_hw *hw)
 		if (hw->hw_info->ops->start)
 			hw->hw_info->ops->start(hw, NULL);
 		break;
+	case TPG_HW_VERSION_1_2:
 	case TPG_HW_VERSION_1_3:
 		if (hw->hw_info->ops->start)
 			hw->hw_info->ops->start(hw, NULL);
@@ -405,6 +406,7 @@ int tpg_hw_stop(struct tpg_hw *hw)
 	switch (hw->hw_info->version) {
 	case TPG_HW_VERSION_1_0:
 	case TPG_HW_VERSION_1_1:
+	case TPG_HW_VERSION_1_2:
 	case TPG_HW_VERSION_1_3:
 		if (hw->hw_info->ops->stop)
 			rc = hw->hw_info->ops->stop(hw, NULL);
@@ -433,6 +435,7 @@ int tpg_hw_acquire(struct tpg_hw *hw,
 	switch (hw->hw_info->version) {
 	case TPG_HW_VERSION_1_0:
 	case TPG_HW_VERSION_1_1:
+	case TPG_HW_VERSION_1_2:
 	case TPG_HW_VERSION_1_3:
 		// Start Cpas and enable required clocks
 		break;
@@ -456,6 +459,7 @@ int tpg_hw_release(struct tpg_hw *hw)
 	switch (hw->hw_info->version) {
 	case TPG_HW_VERSION_1_0:
 	case TPG_HW_VERSION_1_1:
+	case TPG_HW_VERSION_1_2:
 	case TPG_HW_VERSION_1_3:
 		break;
 	default:
@@ -480,6 +484,7 @@ static int tpg_hw_configure_init_settings(
 	switch (hw->hw_info->version) {
 	case TPG_HW_VERSION_1_0:
 	case TPG_HW_VERSION_1_1:
+	case TPG_HW_VERSION_1_2:
 	case TPG_HW_VERSION_1_3:
 		rc = tpg_hw_soc_enable(hw, CAM_SVS_VOTE);
 		if (hw->hw_info->ops->init)

drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw.h

@@ -14,6 +14,7 @@
 #include <media/cam_sensor.h>
 #define TPG_HW_VERSION_1_0 0x10000000
 #define TPG_HW_VERSION_1_1 0x10000001
+#define TPG_HW_VERSION_1_2 0x10000002
 #define TPG_HW_VERSION_1_3 0x10000003
 
 

drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_2/tpg_hw_v_1_2.c

@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "tpg_hw_v_1_2.h"
+
+/* TPG HW IDs */
+enum cam_tpg_hw_id {
+    CAM_TPG_0 = 13,
+    CAM_TPG_1,
+    CAM_TPG_MAX,
+};
+
+static struct cam_tpg_ver_1_2_reg_offset cam_tpg102_reg = {
+	.tpg_hw_version = 0x0,
+	.tpg_hw_status = 0x4,
+	.tpg_module_cfg = 0x60,
+	.tpg_cfg0 = 0x68,
+	.tpg_cfg1 = 0x6C,
+	.tpg_cfg2 = 0x70,
+	.tpg_cfg3 = 0x74,
+	.tpg_spare = 0x1FC,
+
+	/* configurations */
+	.major_version = 1,
+	.minor_version = 0,
+	.version_incr = 2,
+	.tpg_en_shift = 0,
+	.tpg_hbi_shift = 20,
+	.tpg_dt_shift = 11,
+	.tpg_rotate_period_shift = 5,
+	.tpg_split_en_shift = 4,
+	.top_mux_reg_offset = 0x90,
+	.tpg_mux_sel_tpg_0_shift = 0,
+	.tpg_mux_sel_tpg_1_shift = 8,
+};
+
+static int configure_global_configs(
+	struct tpg_hw *hw,
+	int num_vcs,
+	struct tpg_global_config_t *configs)
+{
+	uint32_t val;
+	struct cam_hw_soc_info *soc_info = NULL;
+	struct cam_tpg_ver_1_2_reg_offset *tpg_reg = &cam_tpg102_reg;
+
+	if (!hw) {
+		CAM_ERR(CAM_TPG, "invalid params");
+		return -EINVAL;
+	}
+	soc_info = hw->soc_info;
+
+	if (num_vcs <= 0) {
+		CAM_ERR(CAM_TPG, "Invalid vc count");
+		return -EINVAL;
+	}
+
+	/* Program number of frames */
+	val = 0xFFFFF;
+	cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_cfg3);
+	CAM_DBG(CAM_TPG, "TPG[%d] cfg3=0x%x",
+			hw->hw_idx, val);
+
+	val = cam_io_r_mb(soc_info->reg_map[1].mem_base +
+			tpg_reg->top_mux_reg_offset);
+
+	if (hw->hw_idx == CAM_TPG_0)
+		val |= 1 << tpg_reg->tpg_mux_sel_tpg_0_shift;
+	else if (hw->hw_idx == CAM_TPG_1)
+		val |= 1 << tpg_reg->tpg_mux_sel_tpg_1_shift;
+
+	cam_io_w_mb(val,
+			soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset);
+	CAM_INFO(CAM_TPG, "TPG[%d] Set CPAS top mux: 0x%x",
+			hw->hw_idx, val);
+
+	val = (1 << tpg_reg->tpg_en_shift);
+	cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_module_cfg);
+	CAM_DBG(CAM_TPG, "TPG[%d] tpg_module_cfg=0x%x", hw->hw_idx, val);
+
+	return 0;
+}
+
+static int configure_dt(
+	struct tpg_hw *hw,
+	uint32_t       vc_slot,
+	uint32_t       dt_slot,
+	struct tpg_stream_config_t *stream)
+{
+	uint32_t val;
+	struct cam_hw_soc_info *soc_info = NULL;
+	struct cam_tpg_ver_1_2_reg_offset *tpg_reg = &cam_tpg102_reg;
+	if (!hw) {
+		CAM_ERR(CAM_TPG, "invalid params");
+		return -EINVAL;
+	}
+
+	soc_info = hw->soc_info;
+	CAM_DBG(CAM_TPG, "TPG[%d] slot(%d,%d) <= dt:%d",
+			hw->hw_idx,
+			vc_slot,
+			dt_slot,
+			stream->dt);
+
+	val = (((stream->stream_dimension.width & 0xFFFF) << 16) |
+			(stream->stream_dimension.height & 0xFFFF));
+	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
+			tpg_reg->tpg_cfg0);
+	CAM_DBG(CAM_TPG, "TPG[%d] cfg0=0x%x",
+			hw->hw_idx, val);
+
+	val = stream->dt << tpg_reg->tpg_dt_shift;
+	cam_io_w_mb(val,
+			soc_info->reg_map[0].mem_base +
+			tpg_reg->tpg_cfg2);
+	CAM_DBG(CAM_TPG, "TPG[%d] cfg2=0x%x",
+			hw->hw_idx, val);
+
+	return 0;
+}
+
+static int configure_vc(
+	struct tpg_hw *hw,
+	uint32_t       vc_slot,
+	int            num_dts,
+	struct tpg_stream_config_t *stream)
+{
+	uint32_t val = 0;
+	struct cam_hw_soc_info *soc_info = NULL;
+	struct cam_tpg_ver_1_2_reg_offset *tpg_reg = &cam_tpg102_reg;
+	if (!hw) {
+		CAM_ERR(CAM_TPG, "invalid params");
+		return -EINVAL;
+	}
+
+	soc_info = hw->soc_info;
+	if (stream->cb_mode == TPG_COLOR_BAR_MODE_SPLIT)
+		val |= (1 << tpg_reg->tpg_split_en_shift);
+
+	CAM_DBG(CAM_TPG, "TPG[%d] period: %d", hw->hw_idx, stream->rotate_period);
+	val |= ((stream->rotate_period & 0x3F) <<
+			tpg_reg->tpg_rotate_period_shift);
+	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
+			tpg_reg->tpg_cfg2);
+	CAM_DBG(CAM_TPG, "TPG[%d] cfg2=0x%x",
+			hw->hw_idx, val);
+
+	val = stream->hbi << tpg_reg->tpg_hbi_shift | stream->vbi;
+	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
+			tpg_reg->tpg_cfg1);
+	CAM_DBG(CAM_TPG, "TPG[%d] cfg1=0x%x",
+			hw->hw_idx, val);
+
+	return 0;
+}
+
+static int tpg_hw_v_1_2_reset(
+	struct tpg_hw *hw, void *data)
+{
+	struct cam_hw_soc_info *soc_info = NULL;
+	uint32_t val;
+	struct cam_tpg_ver_1_2_reg_offset *tpg_reg = &cam_tpg102_reg;
+	if (!hw) {
+		CAM_ERR(CAM_TPG, "invalid params");
+		return -EINVAL;
+	}
+
+	soc_info = hw->soc_info;
+
+	/* Clear out tpg_module_cfg before reset */
+	cam_io_w_mb(0, soc_info->reg_map[0].mem_base + tpg_reg->tpg_module_cfg);
+
+	/* Read the version */
+	val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+			tpg_reg->tpg_hw_version);
+	CAM_INFO(CAM_TPG, "TPG[%d] TPG HW version: 0x%x started",
+			hw->hw_idx, val);
+	return 0;
+}
+
+int tpg_hw_v_1_2_process_cmd(
+	struct tpg_hw *hw,
+	uint32_t       cmd,
+	void          *arg)
+{
+	int rc = 0;
+	if (hw == NULL) {
+		CAM_ERR(CAM_TPG, "invalid argument");
+		return -EINVAL;
+	}
+
+	CAM_DBG(CAM_TPG, "TPG[%d] Cmd opcode:0x%x", hw->hw_idx, cmd);
+	switch(cmd) {
+	case TPG_CONFIG_VC:
+	{
+		struct vc_config_args *vc_config =
+			(struct vc_config_args *)arg;
+
+		if (vc_config == NULL) {
+			CAM_ERR(CAM_TPG, "invalid argument");
+			return -EINVAL;
+		}
+		rc = configure_vc(hw,
+			vc_config->vc_slot,
+			vc_config->num_dts,
+			vc_config->stream);
+	}
+	break;
+	case TPG_CONFIG_DT:
+	{
+		struct dt_config_args *dt_config =
+			(struct dt_config_args *)arg;
+
+		if (dt_config == NULL) {
+			CAM_ERR(CAM_TPG, "invalid argument");
+			return -EINVAL;
+		}
+		rc = configure_dt(hw,
+			dt_config->vc_slot,
+			dt_config->dt_slot,
+			dt_config->stream);
+	}
+	break;
+	case TPG_CONFIG_CTRL:
+	{
+		struct global_config_args *global_args =
+			(struct global_config_args *)arg;
+		rc = configure_global_configs(hw,
+				global_args->num_vcs,
+				global_args->globalconfig);
+	}
+	break;
+	default:
+		CAM_ERR(CAM_TPG, "invalid argument");
+		break;
+	}
+	return rc;
+}
+
+int tpg_hw_v_1_2_start(struct tpg_hw *hw, void *data)
+{
+	CAM_DBG(CAM_TPG, "TPG V1.2 HWL start");
+	return 0;
+}
+
+int tpg_hw_v_1_2_stop(struct tpg_hw *hw, void *data)
+{
+	CAM_DBG(CAM_TPG, "TPG V1.2 HWL stop");
+	tpg_hw_v_1_2_reset(hw, data);
+	return 0;
+}
+
+int tpg_hw_v_1_2_dump_status(struct tpg_hw *hw, void *data)
+{
+	struct cam_hw_soc_info *soc_info = NULL;
+	uint32_t val;
+	struct cam_tpg_ver_1_2_reg_offset *tpg_reg = &cam_tpg102_reg;
+
+	if (!hw) {
+		CAM_ERR(CAM_TPG, "invalid params");
+		return -EINVAL;
+	}
+
+	soc_info = hw->soc_info;
+	CAM_DBG(CAM_TPG, "TPG V1.2 HWL status dump");
+	/* Read the version */
+	val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
+			tpg_reg->tpg_hw_status);
+	CAM_INFO(CAM_TPG, "TPG[%d] TPG HW status: 0x%x started",
+			hw->hw_idx, val);
+
+	return 0;
+}
+
+int tpg_hw_v_1_2_init(struct tpg_hw *hw, void *data)
+{
+	CAM_DBG(CAM_TPG, "TPG V1.2 HWL init");
+	tpg_hw_v_1_2_reset(hw, data);
+	return 0;
+}

drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_2/tpg_hw_v_1_2.h

@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __TPG_HW_V_1_2_H__
+#define __TPG_HW_V_1_2_H__
+
+#include "../tpg_hw.h"
+
+struct cam_tpg_ver_1_2_reg_offset {
+	uint32_t tpg_hw_version;
+	uint32_t tpg_hw_status;
+	uint32_t tpg_module_cfg;
+	uint32_t tpg_cfg0;
+	uint32_t tpg_cfg1;
+	uint32_t tpg_cfg2;
+	uint32_t tpg_cfg3;
+	uint32_t tpg_spare;
+
+	/* configurations */
+	uint32_t major_version;
+	uint32_t minor_version;
+	uint32_t version_incr;
+	uint32_t tpg_en_shift;
+	uint32_t tpg_hbi_shift;
+	uint32_t tpg_dt_shift;
+	uint32_t tpg_rotate_period_shift;
+	uint32_t tpg_split_en_shift;
+	uint32_t top_mux_reg_offset;
+	uint32_t tpg_mux_sel_tpg_0_shift;
+	uint32_t tpg_mux_sel_tpg_1_shift;
+};
+
+
+/**
+ * @brief initialize the tpg hw instance
+ *
+ * @param hw   : tpg hw instance
+ * @param data : argument for initialize
+ *
+ * @return     : 0 on success
+ */
+int tpg_hw_v_1_2_init(struct tpg_hw *hw, void *data);
+
+/**
+ * @brief start tpg hw
+ *
+ * @param hw    : tpg hw instance
+ * @param data  : tpg hw instance data
+ *
+ * @return      : 0 on success
+ */
+int tpg_hw_v_1_2_start(struct tpg_hw *hw, void *data);
+
+/**
+ * @brief stop tpg hw
+ *
+ * @param hw   : tpg hw instance
+ * @param data : argument for tpg hw stop
+ *
+ * @return     : 0 on success
+ */
+int tpg_hw_v_1_2_stop(struct tpg_hw *hw, void *data);
+
+/**
+ * @brief process a command send from hw layer
+ *
+ * @param hw  : tpg hw instance
+ * @param cmd : command to process
+ * @param arg : argument corresponding to command
+ *
+ * @return    : 0 on success
+ */
+int tpg_hw_v_1_2_process_cmd(struct tpg_hw *hw,
+		uint32_t cmd, void *arg);
+
+/**
+ * @brief  dump hw status registers
+ *
+ * @param hw   : tpg hw instance
+ * @param data : argument for status dump
+ *
+ * @return     : 0 on sucdess
+ */
+int tpg_hw_v_1_2_dump_status(struct tpg_hw *hw, void *data);
+
+#endif

drivers/cam_sensor_module/cam_tpg/tpg_hw/tpg_hw_v_1_2/tpg_hw_v_1_2_data.h

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __TPG_HW_V_1_2_DATA_H__
+#define __TPG_HW_V_1_2_DATA_H__
+
+#include "../tpg_hw.h"
+#include "tpg_hw_v_1_2.h"
+
+struct tpg_hw_ops tpg_hw_v_1_2_ops = {
+	.start = tpg_hw_v_1_2_start,
+	.stop  = tpg_hw_v_1_2_stop,
+	.init = tpg_hw_v_1_2_init,
+	.process_cmd = tpg_hw_v_1_2_process_cmd,
+	.dump_status = tpg_hw_v_1_2_dump_status,
+};
+
+struct tpg_hw_info tpg_v_1_2_hw_info = {
+	.version = TPG_HW_VERSION_1_2,
+	.max_vc_channels = 1,
+	.max_dt_channels_per_vc = 1,
+	.ops = &tpg_hw_v_1_2_ops,
+};
+
+#endif

drivers/cam_smmu/cam_smmu_api.c

@@ -3863,11 +3863,9 @@ static int cam_smmu_setup_cb(struct cam_context_bank_info *cb,
 			goto end;
 		}
 
-		iommu_dma_enable_best_fit_algo(dev);
-
-		if (cb->discard_iova_start)
-			iommu_dma_reserve_iova(dev, cb->discard_iova_start,
-				cb->discard_iova_len);
+		/* Enable custom iommu features, if applicable */
+		cam_smmu_util_iommu_custom(dev, cb->discard_iova_start,
+			cb->discard_iova_len);
 
 		cb->state = CAM_SMMU_ATTACH;
 	} else {
@@ -3987,6 +3985,10 @@ static int cam_smmu_get_memory_regions_info(struct device_node *of_node,
 	int rc = 0;
 	struct device_node *mem_map_node = NULL;
 	struct device_node *child_node = NULL;
+	dma_addr_t region_start = 0;
+	size_t region_len = 0;
+	uint32_t region_id;
+	uint32_t qdss_region_phy_addr;
 	const char *region_name;
 	int num_regions = 0;
 
@@ -4010,12 +4012,10 @@ static int cam_smmu_get_memory_regions_info(struct device_node *of_node,
 	}
 
 	for_each_available_child_of_node(mem_map_node, child_node) {
-		uint32_t region_start;
-		uint32_t region_len;
-		uint32_t region_id;
-		uint32_t qdss_region_phy_addr = 0;
+		qdss_region_phy_addr = 0;
 
 		num_regions++;
+
 		rc = of_property_read_string(child_node,
 			"iova-region-name", &region_name);
 		if (rc < 0) {
@@ -4024,24 +4024,40 @@ static int cam_smmu_get_memory_regions_info(struct device_node *of_node,
 			return -EINVAL;
 		}
 
-		rc = of_property_read_u32(child_node,
-			"iova-region-start", &region_start);
-		if (rc < 0) {
-			of_node_put(mem_map_node);
-			CAM_ERR(CAM_SMMU, "Failed to read iova-region-start");
-			return -EINVAL;
-		}
+		if (iommu_cb_set.is_expanded_memory) {
+			rc = of_property_read_u64(child_node, "iova-region-start", &region_start);
+			if (rc < 0) {
+				of_node_put(mem_map_node);
+				CAM_ERR(CAM_SMMU, "Failed to read iova-region-start");
+				return -EINVAL;
+			}
 
-		rc = of_property_read_u32(child_node,
-			"iova-region-len", &region_len);
-		if (rc < 0) {
-			of_node_put(mem_map_node);
-			CAM_ERR(CAM_SMMU, "Failed to read iova-region-len");
-			return -EINVAL;
+			rc = of_property_read_u64(child_node, "iova-region-len",
+				(uint64_t *)&region_len);
+			if (rc < 0) {
+				of_node_put(mem_map_node);
+				CAM_ERR(CAM_SMMU, "Failed to read iova-region-len");
+				return -EINVAL;
+			}
+		} else {
+			rc = of_property_read_u32(child_node, "iova-region-start",
+				(uint32_t *)&region_start);
+			if (rc < 0) {
+				of_node_put(mem_map_node);
+				CAM_ERR(CAM_SMMU, "Failed to read iova-region-start");
+				return -EINVAL;
+			}
+
+			rc = of_property_read_u32(child_node, "iova-region-len",
+				(uint32_t *)&region_len);
+			if (rc < 0) {
+				of_node_put(mem_map_node);
+				CAM_ERR(CAM_SMMU, "Failed to read iova-region-len");
+				return -EINVAL;
+			}
 		}
 
-		rc = of_property_read_u32(child_node,
-			"iova-region-id", &region_id);
+		rc = of_property_read_u32(child_node, "iova-region-id", &region_id);
 		if (rc < 0) {
 			of_node_put(mem_map_node);
 			CAM_ERR(CAM_SMMU, "Failed to read iova-region-id");
@@ -4443,16 +4459,10 @@ static int cam_smmu_create_debug_fs(void)
 	/* Store parent inode for cleanup in caller */
 	iommu_cb_set.dentry = dbgfileptr;
 
-	dbgfileptr = debugfs_create_bool("cb_dump_enable", 0644,
+	debugfs_create_bool("cb_dump_enable", 0644,
 		iommu_cb_set.dentry, &iommu_cb_set.cb_dump_enable);
-	dbgfileptr = debugfs_create_bool("map_profile_enable", 0644,
+	debugfs_create_bool("map_profile_enable", 0644,
 		iommu_cb_set.dentry, &iommu_cb_set.map_profile_enable);
-	if (IS_ERR(dbgfileptr)) {
-		if (PTR_ERR(dbgfileptr) == -ENODEV)
-			CAM_WARN(CAM_SMMU, "DebugFS not enabled in kernel!");
-		else
-			rc = PTR_ERR(dbgfileptr);
-	}
 end:
 	return rc;
 }

drivers/cam_sync/cam_sync.c

@@ -1077,14 +1077,9 @@ static int cam_sync_create_debugfs(void)
 	/* Store parent inode for cleanup in caller */
 	sync_dev->dentry = dbgfileptr;
 
-	dbgfileptr = debugfs_create_bool("trigger_cb_without_switch", 0644,
+	debugfs_create_bool("trigger_cb_without_switch", 0644,
 		sync_dev->dentry, &trigger_cb_without_switch);
-	if (IS_ERR(dbgfileptr)) {
-		if (PTR_ERR(dbgfileptr) == -ENODEV)
-			CAM_WARN(CAM_SYNC, "DebugFS not enabled in kernel!");
-		else
-			rc = PTR_ERR(dbgfileptr);
-	}
+
 end:
 	return rc;
 }

drivers/cam_utils/cam_compat.c

@@ -248,7 +248,7 @@ end:
 	return rc;
 }
 
-#if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
 #include <linux/qcom-iommu-util.h>
 void cam_check_iommu_faults(struct iommu_domain *domain,
 	struct cam_smmu_pf_info *pf_info)
@@ -281,4 +281,89 @@ void cam_check_iommu_faults(struct iommu_domain *domain,
 	pf_info->pid = fault_ids.pid;
 	pf_info->mid = fault_ids.mid;
 }
+#endif
+
+static int inline cam_subdev_list_cmp(struct cam_subdev *entry_1, struct cam_subdev *entry_2)
+{
+	if (entry_1->close_seq_prior > entry_2->close_seq_prior)
+		return 1;
+	else if (entry_1->close_seq_prior < entry_2->close_seq_prior)
+		return -1;
+	else
+		return 0;
+}
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)
+void cam_smmu_util_iommu_custom(struct device *dev,
+	dma_addr_t discard_start, size_t discard_length)
+{
+	return;
+}
+
+int cam_req_mgr_ordered_list_cmp(void *priv,
+	const struct list_head *head_1, const struct list_head *head_2)
+{
+	return cam_subdev_list_cmp(list_entry(head_1, struct cam_subdev, list),
+		list_entry(head_2, struct cam_subdev, list));
+}
+
+int cam_compat_util_get_dmabuf_va(struct dma_buf *dmabuf, uintptr_t *vaddr)
+{
+	struct dma_buf_map mapping;
+	int error_code = dma_buf_vmap(dmabuf, &mapping);
+
+	if (error_code)
+		*vaddr = 0;
+	else
+		*vaddr = (mapping.is_iomem) ?
+			(uintptr_t)mapping.vaddr_iomem : (uintptr_t)mapping.vaddr;
+
+	return error_code;
+}
+
+int cam_get_ddr_type(void)
+{
+	/* We assume all chipsets running kernel version 5.15+
+	 * to be using only DDR5 based memory.
+	 */
+	return DDR_TYPE_LPDDR5;
+}
+#else
+void cam_smmu_util_iommu_custom(struct device *dev,
+	dma_addr_t discard_start, size_t discard_length)
+{
+	iommu_dma_enable_best_fit_algo(dev);
+
+	if (discard_start)
+		iommu_dma_reserve_iova(dev, discard_start, discard_length);
+
+	return;
+}
+
+int cam_req_mgr_ordered_list_cmp(void *priv,
+	struct list_head *head_1, struct list_head *head_2)
+{
+	return cam_subdev_list_cmp(list_entry(head_1, struct cam_subdev, list),
+		list_entry(head_2, struct cam_subdev, list));
+}
+
+int cam_compat_util_get_dmabuf_va(struct dma_buf *dmabuf, uintptr_t *vaddr)
+{
+	int error_code = 0;
+	void *addr = dma_buf_vmap(dmabuf);
+
+	if (!addr) {
+		*vaddr = 0;
+		error_code = -ENOSPC;
+	} else {
+		*vaddr = (uintptr_t)addr;
+	}
+
+	return error_code;
+}
+
+int cam_get_ddr_type(void)
+{
+	return of_fdt_get_ddrtype();
+}
 #endif

drivers/cam_utils/cam_compat.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_COMPAT_H_
@@ -9,36 +9,25 @@
 #include <linux/version.h>
 #include <linux/platform_device.h>
 #include <linux/component.h>
+#include <linux/iommu.h>
+#include <linux/qcom_scm.h>
+#include <linux/list_sort.h>
+#include <linux/dma-iommu.h>
 
 #include "cam_csiphy_dev.h"
 #include "cam_cpastop_hw.h"
 #include "cam_smmu_api.h"
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 7, 0)
-
-#define VFL_TYPE_VIDEO VFL_TYPE_GRABBER
-
-#endif
-
-#if KERNEL_VERSION(5, 4, 0) <= LINUX_VERSION_CODE
-
-#include <linux/msm_ion.h>
-#include <linux/iommu.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)
 #include <linux/ion.h>
-#include <linux/qcom_scm.h>
-
-#else
-
 #include <linux/msm_ion.h>
-#include <linux/ion_kernel.h>
-#include <soc/qcom/scm.h>
-
+#define VFL_TYPE_VIDEO VFL_TYPE_GRABBER
 #endif
 
-#if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
-
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) && \
+	LINUX_VERSION_CODE < KERNEL_VERSION(5, 15, 0)
+#include <soc/qcom/of_common.h>
 #include <linux/qcom-dma-mapping.h>
-
 #endif
 
 struct cam_fw_alloc_info {
@@ -58,5 +47,17 @@ int cam_csiphy_notify_secure_mode(struct csiphy_device *csiphy_dev,
 void cam_free_clear(const void *);
 void cam_check_iommu_faults(struct iommu_domain *domain,
 	struct cam_smmu_pf_info *pf_info);
+int cam_get_ddr_type(void);
+int cam_compat_util_get_dmabuf_va(struct dma_buf *dmabuf, uintptr_t *vaddr);
+void cam_smmu_util_iommu_custom(struct device *dev,
+	dma_addr_t discard_start, size_t discard_length);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0)
+int cam_req_mgr_ordered_list_cmp(void *priv,
+	const struct list_head *head_1, const struct list_head *head_2);
+#else
+int cam_req_mgr_ordered_list_cmp(void *priv,
+	struct list_head *head_1, struct list_head *head_2);
+#endif
 
 #endif /* _CAM_COMPAT_H_ */

dt-bindings/msm-camera.h

@@ -64,6 +64,8 @@
 #define CAM_CPAS_PATH_DATA_IFE_UBWC (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 6)
 #define CAM_CPAS_PATH_DATA_IFE_LINEAR_STATS \
 	(CAM_CPAS_PATH_DATA_CONSO_OFFSET + 7)
+#define CAM_CPAS_PATH_DATA_IFE_UBWC_LINEAR \
+	(CAM_CPAS_PATH_DATA_CONSO_OFFSET + 8)
 
 /* IPE Consolidated paths */
 #define CAM_CPAS_PATH_DATA_IPE_WR_VID_DISP (CAM_CPAS_PATH_DATA_CONSO_OFFSET + 1)