This changes takes pitches into account for alignment check
of destination writeback fb. As per HW recommendation
the stride needs to be a multiple of 256 bits.
Change-Id: Ib823a8d309f7ed579d701a4bf56772ce318fb1f5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
The splash memory initialized by the bootloader needs
to be released after the first frame update. Add
memblock_free() call to release this memory that was
reserved during the kernel boot.
Change-Id: I463139a3f930dd9284d3ba9516714ead0c77cc02
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change avoids sde error during fal10_veto override enablement
for targets with uidle disabled and early returns in such case.
Change-Id: I491952615d7b3cbd70d35b4a90ee8d27ab56c2ad
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Update the DSI debugbus logging to print correct offsets for
DSI0/DSI1. Change the VBIF logging to reflect the actual register
value written for block-id instead of BIT value. Update the register
dump format to match the logging style across all dumping methods.
Change-Id: Id862c47e3fb77e1518327dad550a55df1825df89
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Kalama adds support for uidle fill level scaling to allow
fal10 mode for 90 and above fps use cases.
Pre-Kalama, the fill levels are clamped at 4-bit values supported
by the threshold registers. But to achieve the targeted 50us idle
time on fal10 modes with higher FPS use cases, we need fill levels
higher than 15 (max for 4 bit). The hardware change in Kalama
achieves by using a 5 bit scale factor in combination with the
programmed threshold values.
Change-Id: I638705355c03910a83e7d922b6fe48ab11c120a8
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Destination scaler0 and scaler1 when operated in independent mode,
by two built-in independent displays the op_mode gets modified
concurrently and HW flushes new config. This leads to underruns
on both the displays. This change programs the op_mode
correctly to operate ds0 and ds1 independently.
Change-Id: I01a3d4a986e0e7166f8a38b4cf35981d3e434686
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Changes include support to update necessary copyright
information to dp file for 4nm target.
Change-Id: Iebb2cc542f7b9262073936f12d55eb1be788e757
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Expand the DS enum and increase the DS max number
to support DS2 and DS3.
Change-Id: Iff8d591fece20528e30449c228db5cb2047cdded
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
This reverts commit 6547137f7b.
This change can cause negative mdp_transfer_time_us for the panels with
VFP as big as panel active height.
Change-Id: Ibebfcacd9c4eddf80749fa55509821b332fba4cf
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Add support for detecting UBWC decoder version and program
UBWC configuration to hardware.
Change-Id: Ibe753d35ca46b069de8392c65a3b06131b7e238a
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
During link training, after the swing/preemphasis is updated, the driver
is supposed to poll the link status on the sink and quit once the
LINK_STATUS_UPDATED bit is set and also latch the next set of
swing/preemphasis requested by the sink. But currently, the driver is
exiting the loop only when the LINK_STATUS_UPDATED bit is cleared. So,
it also latches the swing/emphasis request from the second read.
Typically, the SW read is slow enough that the bit is set on the first
read. The driver then reads the second time and exits the loop, since
the bit would be cleared then. In most cases, this doesn't affect
the training sequence, since the swing/preemphasis request for next
attempt is retained on the second read. But, atleast in one
specific case, it was observed that the swing/emphasis request
gets reset along with LINK_STATUS_UPDATED and so the driver ends
up missing the actual request and latches incorrect values instead.
This causes link training to fail as it keep retrying with the
same values that it starts with.
This change fixes the exit condition check so the driver quits the loop
as soon as the LINK_STATUS_UPDATED bit is set.
Change-Id: I7f5d9c6b30d48e113aef628d2ab2c1bd972fe743
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
This change updates vreg_ctrl_0 and vreg_ctrl_1 settings for
cape DPHY as per the HW recommendation.
Change-Id: Ide66c62d980b57de1f826ed24d1c0747d8fb6c77
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
This change fails the drm_atomic_commit and avoids S2 translation
fault if drm_gem_object is found attached to a secure context bank
during non secure session. In the current codeflow, we are detaching
the gem object from secure CB and reattaching it to non secure CB,
but only S1 pagetables entries get modified and S2 pagetables entries
are not corrected since hyp_unassign is not called with CP_PIXEL
VMID which can only be done by client when buffer gets allocated.
Change-Id: I62302064f96276ef82044ee88fb89e295fb96b4b
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Changes include updated register writes for DP PLL
as per 4nm target.
Change-Id: I2d8ddbf4af5c2c6d885c73b7c888f31ce45f4cbf
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Remove unnecessary register block size < REG_DUMP_ALIGN check during
the sde_dbg registration of a HW blcok. This avoids the registration
failures for few smaller hw blocks. The register size is padded later
according to REG_DUMP_ALIGN during the hw block register dump time.
Change-Id: I36474720a630f1c3e96072b1d6d8743018fcaeec
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
In an effort to reset the DP controller states on a disconnect, the
driver is issuing a SW reset to the controller. But SW reset on
the controller doesn't necessarily restore the controller to its
full reset state. It only resets part of the logic. So if for some
reason the MST streams were not disabled properly, ie. the slot
allocations were not reset properly in the controller, then a SW
reset would result in the DP controller raising state interrupts.
Since this SW reset is issued in the tail end of the disconnect
processing, the driver turns off all the clocks and also
removes the irq handler. This results in an interrupt storm at
the MDSS top level.
This change removes the SW reset on the disconnect path and
relies on the SW reset that already exists in the connect path
to restore controller state.
Change-Id: Ie7115e17d3c50c46c83c6f0e333da5cb534b8227
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
MST driver is incorrectly using maximum bw_code while initializing
MST topology manager instead of maximum link clock in KHz. This
prevents the topology manager to set MST state on a subsequent MST
plug in causing all MST cases to fail.
Change-Id: I9fc4e0326fe0c7a6c9b81af8810b7098fa8ba967
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During link training, after the swing/preemphasis is updated, the driver
is supposed to poll the link status on the sink and quit once the
LINK_STATUS_UPDATED bit is set and also latch the next set of
swing/preemphasis requested by the sink. But currently, the driver is
exiting the loop only when the LINK_STATUS_UPDATED bit is cleared. So,
it also latches the swing/emphasis request from the second read.
Typically, the SW read is slow enough that the bit is set on the first
read. The driver then reads the second time and exits the loop, since
the bit would be cleared then. In most cases, this doesn't affect
the training sequence, since the swing/preemphasis request for next
attempt is retained on the second read. But, atleast in one
specific case, it was observed that the swing/emphasis request
gets reset along with LINK_STATUS_UPDATED and so the driver ends
up missing the actual request and latches incorrect values instead.
This causes link training to fail as it keep retrying with the
same values that it starts with.
This change fixes the exit condition check so the driver quits the loop
as soon as the LINK_STATUS_UPDATED bit is set.
Change-Id: I7f5d9c6b30d48e113aef628d2ab2c1bd972fe743
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Decouple the configuration and parsing of aux switches with the
parsing and configuration of HPD sources. HPD notification can come from
either GPIO based approach or a PD module through a SW interface. The
presence of AUX switch on the board should have no bearing in deciding
which configuration for HPD detection is used. Update the implementation
to allow for flexibility in selecting any combination of the HPD source
and aux switches.
Change-Id: I96d558f1d88a359d523fae6dc746045393884d5a
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
