fa1f3fab80
In an effort to reset the DP controller states on a disconnect, the driver is issuing a SW reset to the controller. But SW reset on the controller doesn't necessarily restore the controller to its full reset state. It only resets part of the logic. So if for some reason the MST streams were not disabled properly, ie. the slot allocations were not reset properly in the controller, then a SW reset would result in the DP controller raising state interrupts. Since this SW reset is issued in the tail end of the disconnect processing, the driver turns off all the clocks and also removes the irq handler. This results in an interrupt storm at the MDSS top level. This change removes the SW reset on the disconnect path and relies on the SW reset that already exists in the connect path to restore controller state. Change-Id: Ie7115e17d3c50c46c83c6f0e333da5cb534b8227 Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com> Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>