This change adds a check for the length of the buffer
before copying it to avoid a buffer overflow.
Change-Id: I9af9d422e0b3cf02c8d6662af3310337a9861a7a
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Limit clock rate of shadow VCO clock as normal VCO clock.
For larger bit clock rate gap between switched ones, the clock switching
would fail due to mismatched VCO clock rate between normal VCO clock and
shadow one.
Change-Id: I9d68725de360ac28c243a3ce1800bfb139f39757
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
CRTC client type is wrongly identified as RT_CLIENT
for WB as the API considers only RT and RT_RSC. Resolve
it by adding a new API to check for RT CTRC.
Change-Id: I1f216f60a18215426e594d0f8b09852af376799d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change adds a check for the length of the buffer
before copying it to avoid a buffer overflow.
Change-Id: I146895660be4060d9896706636257a57c6aef94f
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Helper function is returning the width of single mixer. During
atomic crtc check, the number of destination scaler is not
considered before width check and can fail possible higher
resolutions. The mixerwidth should be taken as a multiple of
num_ds_enabled.
Change-Id: Id9e5e0ccf0cebb54d2a242e039d8dc3676b3729f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Update the minimum encryption level only when there is a request
to do so coming from the DRM framework. This will ensure that any
previously set value will not be overwritten while processing
other commands. Failure to preserve the minimum encryption level
can result in secure content playback failure if the sink device
is not updated with the correct value.
Change-Id: Ie9a555a57617096fbdb9e46dd29a973b9223e237
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Adding debug, info and error prefix for log messages
in dsi files. To enable debug logs
run "echo 0x1 > /sys/module/drm/parameters/debug"
Change-Id: I438ac16954bd1d39450f8adeb7fb17f9ea6f8140
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Break the host initialization and de-initialization to
create late initialization and early de-initialization.
Call host init/deinit on physical connect/disconnect only
As attention messages from sink doesn't change the physical
cable configurations, call only late init/early deinit in
this case to avoid unnecessary hardware resources
re-initialization.
CRs-Fixed: 2490128
Change-Id: Ib930d250724ab3ea811a7388c7ad0aeae1164e21
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
This GPIO is a input signal, so need to set it
to input mode, or it will lead leakage in RBC.
This change is only to fix the power issue.
Change-Id: I87716f646c75dac2f1350a2ea55188829a4ccc9e
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
This pin is a output pin from panel. Panel can
output signal of internal VSYNC and ERR_FLAG.
Change-Id: Ib8e661ca1fdb33bb7060935edb9bc1f1a858c4b3
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Change calculates and updates correct pclk that is being
used to drm modes in kilo hertz.
Change-Id: I7aab10c08689697120d4d7c152f30993defd36d3
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Partial update commands are using static memory. For dual dsi,
both dsi's can manipulate on same memory, if partial update is enabled
on both of them. Change removes the static configuration.
Change-Id: I0ca16324a27427d13deaa9d18e3ab4f47fe1cc21
Signed-off-by: Vara Reddy <varar@codeaurora.org>
CWB, DP and WB displays tear down sequence must reset
3d_merge, ctl, pingpong_binding, etc. MDP HW
blocks. This change fixes the tear down
sequence register programming. It also moves flush
sw reset before encoder_disable call. That allows
CWB tear down to update the flush configuration
on primary ctl path.
Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change updates the DSI PHY sequence for Kona target as
per latest HW team recommendation.
Change-Id: I20f6a81bb1112e9e976acae595b985dad7ad4b7a
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change updates the DSI PHY PLL programming for kona target
as per the hardware recommendation.
Change-Id: I706169fb635e72bd0ccd3057107ea749408733d0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Currently trace always shows up on same process as caller, add
an additional function to allow attaching trace to any process.
Change-Id: I8fc124f9d1cfae28d1868a9a3067d0e92eda934e
Signed-off-by: Adrian Salido <salidoa@google.com>
(cherry picked from commit 52ba2d3585eb49c5d5b90b3cd75e0abe5c984dad)
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Trace counter is not properly showing up on trace as is. Replace it with
proper format by refactoring existing trace to be more generic.
Bug: 119295905
Change-Id: I50abb593cd67c10ceed115380ac0e9d2177f0963
Signed-off-by: Adrian Salido <salidoa@google.com>
(cherry picked from commit 89ac1949eaa1524e4e2bbd2ad8c8b6513ae594dd)
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Unpaired trace "sde_power_resource_enable" caused tracer parse
incorrect trace points and display weird state on Chrome. Make
trace "sde_power_resource_enable" pair to fix it.
Bug: 122510119
Test: Checked sde trace can be displayed correctly on Chrome
Change-Id: I938b5648a09e00eaea59070af31a2e6469763087
Signed-off-by: Midas Chien <midaschieh@google.com>
(cherry picked from commit 3a335059bf7a200977e8f4e0a4aa5c6ceca3863a)
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Change updates connector edid node with proper panel physical
dimensions based on panel device tree file.
Change-Id: I36db9c3e5b5aee926a0d029ae742166fc8c7591c
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Highest bank bit property is read from device-tree, else set
to default value based on DDR type.
Change-Id: I8b31d957e29071b599a7f983cbf8300e293e9e36
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
When there is a change in resolution or FPS, a new clock rate is
calculated. During such a Dynamic Mode Switch, the clock rate
change pending flag needs to be set after it has been calculated.
This flag is later checked before kickoff and the clocks are updated
accordingly.
Change-Id: Iec102796d5c61d01c567f0b6676e9a6d4ed94268
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
When secondary display preference is determined and 2 layer
mixers are required, the preference must check LM pair mask
to meet hw restrictions.
Change-Id: I22845be84f95659a58be98ff11afa4e652fb16e3
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Update the PLL and PHY power on and clock set sequence as per
the hardware recommendations. Move the post link clock phy enable
part to the catalog so that it can be programmed after enabling
link clock.
Change-Id: I9b3b49e5a9ac93bebcb1cb7da63b715a8d5ed85c
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
