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@@ -204,8 +204,6 @@ void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
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u32 vreg_ctrl_0 = 0;
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u32 glbl_str_swi_cal_sel_ctrl = 0;
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u32 glbl_hstx_str_ctrl_0 = 0;
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- u32 glbl_rescode_top_ctrl = 0;
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- u32 glbl_rescode_bot_ctrl = 0;
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if (dsi_phy_hw_v4_0_is_pll_on(phy))
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pr_warn("PLL turned on before configuring PHY\n");
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@@ -218,22 +216,17 @@ void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
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return;
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}
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- /* Alter PHY configurations if data rate less than 1.5GHZ*/
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- if (cfg->bit_clk_rate_hz <= 1500000000)
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- less_than_1500_mhz = true;
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-
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if (phy->version == DSI_PHY_VERSION_4_1) {
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- vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
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- glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00;
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- glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
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+ vreg_ctrl_0 = 0x58;
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glbl_str_swi_cal_sel_ctrl = 0x00;
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glbl_hstx_str_ctrl_0 = 0x88;
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} else {
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+ /* Alter PHY configurations if data rate less than 1.5GHZ*/
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+ if (cfg->bit_clk_rate_hz < 1500000000)
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+ less_than_1500_mhz = true;
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vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
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glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
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glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
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- glbl_rescode_top_ctrl = 0x03;
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- glbl_rescode_bot_ctrl = 0x3c;
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}
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/* de-assert digital and pll power down */
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@@ -263,10 +256,8 @@ void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
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glbl_str_swi_cal_sel_ctrl);
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DSI_W32(phy, DSIPHY_CMN_GLBL_HSTX_STR_CTRL_0, glbl_hstx_str_ctrl_0);
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DSI_W32(phy, DSIPHY_CMN_GLBL_PEMPH_CTRL_0, 0x00);
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- DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
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- glbl_rescode_top_ctrl);
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- DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
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- glbl_rescode_bot_ctrl);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL, 0x03);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL, 0x3c);
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DSI_W32(phy, DSIPHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
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/* Remove power down from all blocks */
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qctecmdr