Some monitors seem to be not enabling Sink CRC capability on first plugin
and therefore the CRC read returns all zeros. But on subsequent plugins
the capability is set properly and CRC values are calculated. To
workaround this quirk on the sink side, this change reenables sink CRC
if the values are read as zeros.
Change-Id: I67ace5c064b2b56d03732a78f334ea6b1b649608
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Starting pineapple, the output_fence trigger_sel register is updated to be
more controllable. Instead of hardware choosing the output fence timing
based on detecting if panel is in video/cmd mode, this is explicitly set
by software. Add support in display driver for to correctly write to
trigger_sel register for video mode.
Change-Id: I76d8cfb644cebfd2f34f3017fc779b87fc52db1a
Signed-off-by: Grace An <quic_gracan@quicinc.com>
While same spinlock can be used to protect a critical section
in both irq-handler and in non-irq context, in non-irq context
it is mandatory to use irqsave version of locking api to disable
irqs locally on the particular cpu. Otherwise, this could lead
to a deadlock if a non-irq thread holding the spinlock and irq
handler is scheduled on same cpu.
This change replaces physical encoder spinlock locking with
irqsave version of locking api in the non-irq context.
Change-Id: If73b4c995b75e9499d79fbe969d426427fd3a9d1
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Update tracking of layer mixer resources to prevent valid modes
from being skipped during DP topology validation.
Change-Id: Id88337094c4113b721f307d24583a3ca30157216
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Add check to avoid programming the color processing HW if sde_crtc is
not enabled.
Change-Id: I7ffd341147f0caebefb647486a139df5c0aeab31
Signed-off-by: Ping Li <quic_pingli@quicinc.com>
sg_dma_address returns the iova address when virtual address is invloved
and physical address when S2-only or physical address is used. Replace
sg_phys with this to support in all cases.
Change-Id: Ibffe9b5cd5f4b24c1bbff92d2d95f2d16a564160
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
During the gem prime_fd_to_handle, attach the drm device to the
secure camera preview buffers. For CSF 2.5 solution, the DRM device
DT will have a special entry as indication to memory driver based on
which the buffer is handled differently. For older solution, the
attaching DRM device has no impact as the secure camera preview
buffer would be S2-only buffer.
Change-Id: I18646dd947476827819b7d83504ea0af55070a55
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
If the event thread worker processing vblank_notify_work is
scheduled out while holding spinlock to process the ctl-done
interrupt, it will result in a deadlock as the
frame_event_callback requires the same spinlock.
This change updates vblank notify work to use spin lock irqsave &
irqrestore to ensure we don't hit this case.
Change-Id: I96bcb3b21bf9426016f5b3ae43f7d1f8581a8483
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
MDSS 10.0 onwards, hw supports programming of pingpong
latency buffer size based on the resolution of display.
In prior targets full size of the latency buffer is used.
This change adds required support in sde driver to program
the pingpong buffer size based on systems recommended
latency lines requirement and the display resolution.
Change-Id: I172b19e5b397eb86190de57fed36f24cd67d2207
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Add case tags in eventlogs in cmd_prepare_for_kickoff to
help in differentiating the logs in this function.
Change-Id: Idce10e715c77340175d124ec3ef7ecc30c95a0af
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, hdcp wait loops uses the wait_event() macro which sets the
status of the thread to WAIT_UNINTERRUPTIBLE and contributes to system
load. The macro wait_event_idle() polls for a changing condition in the
same way but instead sets the thread status to WAIT_IDLE which does not
contribute to system load. This prevents hdcp threads from appearing as
hung threads in system load summaries while still properly polling for
status changes.
Change-Id: Ie6991881d912ba6fca6bb0fd9558633b1fb83492
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
Enable the Expected Present Time feature through the FPS for cmd
mode panels in pineapple target.
Change-Id: Ib1e3c7aaf5329004ffdf89672e919228931468ee
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Introduce a new connector property called “EPT_FPS” for the cmd
mode panels. User space will set the “EPT_FPS” based on the
intended content fps, relative to the last retire fence timestamp
as calculated by Surface flinger. Program start window based
on the Expected Present Time fps.
Change-Id: I24b93e0f941af9fb2422b2484328254d04a1acbe
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add capability to read avr step for each timing mode. This will
be in addition to the existing avr-step-list which is defined
when dfps is enabled. Expose the avr-step as part of each
mode in connector caps to user-mode.
Additionally, change the avr_step connector property to enum
to give usermode just the capability to enable/disable avr-step
and not alter the step value as its fixed from the device tree.
Change-Id: I6d7f8e9fcf03f98abef7640fc741e5e1be8597a1
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
clear cached rectangles when PU ROI is set to avoid incorrect
cached rois when two subsequent state duplications occur due
to timing. This will lead to commit N and commit N+1 to have
same cached ROIs as commit N-1. This results in issues when
commit N-1 is PU, N is full frame and N+1 is PU with same
ROI as N-1.
Change-Id: I3bb9390e500d327e703e41d64f7aaae5e5f1b4f2
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Currently, QSYNC sim panels are not fully emulating panel
side logic to allow different refresh rate depending on when
the frame is received by the panel.
This change adds the logic to reconfigure the TE watchdog at
different frame rate depending on when the frame is sent to the
simulated QSYNC panel.
Change-Id: I3f0de73976a0fc5748a76c4f7ab00205d1af9a1b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Install volatile enum and range properties for UCSC IGC, GC, UNMULT
and ALPHA_DITHER. This will mark the force dirty property data as
true, and will avoid caching in driver by always applying the
property values set by userspace, rather than checking for modified
values.
Change-Id: Ib8132165fb58ddc829bf8610657e302e0798d72f
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
Add debug log to dump qtimer information after the input hw-fence
signal configuration.
Change-Id: I7617b1a6bae3db1e003c42bfe306dbe7f552ad83
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Add display event log for the display input hw-fence.
Change-Id: Id0fc19565c7b83c8009ab518dae7323db534b66e
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Force vbif axi halt on all the power-collapse with/without RSC.
This will keep the logic simple for all targets.
Change-Id: I5a4956cbc1f5875d923d5cf818016fba7ed2c8f7
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
When precise vsync timestamp feature is enabled, move the vblank
signaling from interrupt context to event thread. This helps in
freeing up the interrupt context soon. The precise vsync timestamp
feature along with DRM hooks to get the vblank timestamp will get
the correct timestamp though the event thread is scheduled later.
Change-Id: I77002913f222ff422b6118f9fc952533065c07aa
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Enable the Expected Present Time feature in sde catalog
for pineapple target.
Change-Id: I12a6abb00e8792564fad390be1d49e3217f88517
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Time the flush bit setting to match with the expected frame
rate. To achieve this, introduce a new connector property called
“Expected_Present_Time”. User space will set it based on the
intended content fps and AVR step, relative to the last retire
fence timestamp as calculated by user space. Delay the frame
trigger to match with the EPT.
Change-Id: I0b86caaa53ee2e37671167acdffd22ec62b4e9ae
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Modify the default INTF TE sync threshold config in cmd-mode to
32-bit max based on the INTF TE 32-bit support.
Change-Id: I963ffa8ae37bce0e85deb335609857c17e32d6b0
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the
trigger window to be out of sync when power is restored
until the next vsync is received.
This change reads the panel read pointer and overrrides
the internal register to allow a frame to be picked up in
the current vsync cycle, but defers it to next vsync if it
comes later than the safe trigger window.
Change-Id: I741a91edcddc105eda34d875e8e1c32933b83d71
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add DCS command to read the panel scan line value and associated
time stamp in nano-seconds.
Change-Id: I06a76d3a6c5ad7a2e7681413c741e5b97b34d73f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Current driver prints error messages when it fails
registration for the display clients with the hw-fence
driver, however, this is not an error as currently
feature is disabled by default in hw-fence driver,
which as result will fail registration for clients.
Therefore, silent the error messages for a failed
registration.
Change-Id: I13b872db3452a57a885c73cc8f1cf512be986dd0
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
