Currently get vcpi info call is returning wrong slot info since update
payload function is called afterwards. The latter function is calculating
the slot info which is read back by get vcpi call. This change reorders
these function calls. Also, this change sets start_slot to be always 1.
This is the value expected by upstream driver for atomic drivers.
This is a follow up change for the commit 19a9abf064
("disp: msm: dp: update MST first link slot information").
Change-Id: I620125a2d73afb7537a3540ee129e2a4eb0c488c
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Increase the log level of the prink statements to dev_err
when a register dump is triggered. This will allow user to
capture the values independently of the target default log level.
Change-Id: I67f8c854a274b70d1595e74136095ef91584ca90
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Update the LUT DMA register range registration to target
specific ranges of valid registers instead of the full
memory region of the LUT DMA module. This ensures that
unused LUT DMA register regions are not dumped.
Change-Id: I3739692ae7fcfd5777bb8774dd34c16ab87c3ae1
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
This change adds support for enabling the system cache
slices with staling. This allows back to back static display
cache usecases to self evict prior to using cache.
Change-Id: Iea71da26a8f7a450822624305dc20a3bab323d4b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Pipe csc configuration is being cached in the sde plane which can cause
race conditions between hardware programming and caching.
All drm properties should be cached in sde plane state to avoid race
conditions. Change moves caching to sde plane state.
Change-Id: I22470a82b2fc2812f8c526ababc2b517db13a3ce
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
This change avoid programming of legacy bit fields which
are conflicting with TE alignment feature bit fields
of split control register of peripheral top block.
Change-Id: Ib9f519ec82ee3b3885351dff960b176c99dcf08d
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Currently, num of 3dmux used is incremented or decremented based
on LM allotment. This was leading to wrong bookkeeping in few
corner cases. This change maintains a 3d mux mask to track the
usage and update the count accordingly.
Change-Id: Idf25eff827462f3f0263d01a1aa733a1cbaf0a83
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change adds a device-tree configurable property to define
the ipcc client id of the dpu used for registers access and
configuration. Starting pineapple, this is the ipcc client physical
id, distinct from the ipcc client virtual id.
Change-Id: Icb59111c85c7132c0efd7b207eaa5417cca013eb
Signed-off-by: Grace An <quic_gracan@quicinc.com>
For calculating bit rate in cphy, we multiply bit rate by a factor of
7/16 where 7 is the number of symbols and 16 is the bits per symbol.
But we are currently not considering the 7/16 factor while calculating
minimum bit clk value for command mode which is resulting in a smaller
bit rate value than the minimum bit clk.
Bit rate should always be greater than the minimum bit clk which otherwise
can lead to discrepancies. Correct minimum bit clk calculation for command
mode, by multiplying a factor of 7/16 if cphy.
Change-Id: I39b202dcafe60e2047549f84ff9388b46ae490a5
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
This change fixes the incorrect calculation of VCO rate for
stream clocks. This issue was introduced because of a previous
commit e4e277ad36 ("disp: msm: dp: Convert clock operations to byte2 ops").
Change-Id: I2886f98a95fd7c166edabec3fc023dc9846c201d
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change adds support for updating danger, safe and creq LUT
configuration for WB rotation use case.
Change-Id: I01784be4ea4ac5b027258df2907f3ba745a05850
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Add support for demura v2 by adding demura blocks
2 and 3 for pineapple target.
Change-Id: I9e6107480ab44853ca49e6396787378c5c70557a
Signed-off-by: Mitika Dodiya <quic_mdodiya@quicinc.com>
This change adds support for the device tree entry parsing and
programming of VBIF Qos remap settings in WB rotate use case.
Change-Id: I729abc3562b70bf85217130aebeeeabc2fca04da
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
As per DP HPG recommendation, controller flush mode is
set to be synchronous with a vsync. This requires a
peripheral flush to be issued for HDR SDP to be processed.
Currently in a static HDR use case, since the peripheral
flush is not issued after queueing an HDR SDP, it never
gets sent to the sink and it stays in SDR mode. This change
issues a peripheral flush on every DP commit, so that
any pending SDPs are flushed.
Change-Id: I0ed82b6cd8df33539a3067c6ad9827f74de2ed51
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
When using the TU calculator for SST DSC usecase, the calculator
expects the bpp to be 24 irrespective of the actual panel bpp.
Change-Id: Ifdab2c00a2a99b4d7d7dea7eadb33bc34e3cfa8b
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
When calculating the Rate Governor parameters for MST, if the
stream is compressed, the calculator expects the input bpp to be
the compressed bpp, but currently the driver is passing uncompressed
bpp. This change updates the driver to pass compressed bpp to the
calculator.
Change-Id: Iac51d75843bd0072bbe07142ac4533d841f795f5
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Add extra display driver debug events for input and output
hw-fences.
Change-Id: I32be1d25d98c510ebba5d39f8aff2a0c54144ba1
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Current display driver sets the hw-fences as valid even when
the speculative fence is empty. Avoid this issue by doing a
positive check and only create hw-fences if all the fences in
the speculative fence are valid.
Change-Id: Iec9636641ac9146eb651be08615e2478994c2508
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Move print message from error to debug for a failure that is not fatal
but can be expected when a crtc doesn't have a hw ctl, in this case
driver will handle the output fence as a sw-fence.
Change-Id: I908135dce4336b0c9ec3fa388dc9211c6df97f68
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Files used for HDCP ops in the driver are not included
under compile flag for HDCP. This change includes
these files under this condition which will enable DP
driver to be built even with HDCP disabled.
Change-Id: Iff3d9468d007da4342011b8e0e52f3f995425a0b
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change fixes printk arguments in display driver which is
found with additional compilation flags and adds the compile
flags too.
Change-Id: Ic653591db49b49b9ce1ce04e7df89216772d0e71
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
New SID registers are added from display MDSS 10.0.0.
Changes are made to program these lutdma related SID
registers.
Change-Id: I691c234d4968f0fd0f603f07360364ec9cf15f52
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Enable trusted vm flag for pineapple target.
Change-Id: I40165162c504d0de675899ae791d58e36da3f5fe
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Fix debug message arguments in sde which are found with
-Wformat-extra-args and -Wstrict-prototypes compilation
flag and add compile flags to msm compilation.
Change-Id: Ic7f30e0cab3ea16b7f2a34658262b6f51da259e9
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Introduce support for SPR V2 features. Full validation
has been performed.
Change-Id: Ia83c06b30729fef12cae014ee5ce4792236a0a8a
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
Add functionality to change which aux switch is used
at compile time for different targets. Add wcd939x
switch support.
Change-Id: Iced3b11733009680063790dfa8f180b19002f963
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Currently, RC is using displayh and displayv variables
which are pointing to the LM dimension on a full frame
setting. If DS is enable and HW RC was not disabled the
the full frame ROI will not match the panel resolution
and cause an invalid hardware configuration.
This change uses the height and width values coming
from the mode information when a full frame ROI is
detected.
Change-Id: I274d15cbca61076ea7e95a984f907201e97b76ec
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Current code creates an output hw fence for any virtual
connector with a retire fence attached. This is a problem
for CWB, where the output-fence should be handled as a
sw-fence as current hw can only support a single hw-fence
per ctl path.
Fix this issue by adding a check to only create a retire
output hw-fence for virtual connectors that are not CWB.
Change-Id: I5863282d24ef8940b1f45c1fbd7584f91d28f0b8
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
In MST atomic check function, add a check to ensure it's a disable call
before releasing vcpi slots to ensure atomic_release_vcpi_slots() and
atomic_find_vcpi_slots() are never called in the same atomic check
as mentioned in the kernel docs.
Change-Id: I36cf689b4d3bf9d2469a6c402b6377a667f01c12
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
