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@@ -5840,7 +5840,7 @@ static int __reg_dmav1_setup_demurav1_cfg0(struct sde_hw_dspp *ctx,
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goto quit;
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}
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- width = hw_cfg->panel_width >> 1;
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+ width = hw_cfg->panel_width >> ((dcfg->flags & DEMURA_FLAG_1) ? 2 : 1);
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DRM_DEBUG_DRIVER("0x80: value %x\n", width);
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REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x80,
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&width, sizeof(width), REG_SINGLE_WRITE, 0, 0, 0);
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@@ -6044,7 +6044,7 @@ static bool __reg_dmav1_valid_hfc_en_cfg(struct drm_msm_dem_cfg *dcfg,
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h = hw_cfg->num_ds_enabled ? hw_cfg->panel_height : hw_cfg->displayv;
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w = hw_cfg->panel_width;
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- temp = hw_cfg->panel_width / 2;
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+ temp = hw_cfg->panel_width / (2 * ((dcfg->flags & DEMURA_FLAG_1) ? 2 : 1));
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if (dcfg->pentile) {
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w = dcfg->c0_depth * (temp / 2) + dcfg->c1_depth * temp +
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dcfg->c2_depth * (temp / 2);
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