Changes include support to update necessary copyright
information to dp file for 4nm target.
Change-Id: Iebb2cc542f7b9262073936f12d55eb1be788e757
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Expand the DS enum and increase the DS max number
to support DS2 and DS3.
Change-Id: Iff8d591fece20528e30449c228db5cb2047cdded
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
This reverts commit 6547137f7b.
This change can cause negative mdp_transfer_time_us for the panels with
VFP as big as panel active height.
Change-Id: Ibebfcacd9c4eddf80749fa55509821b332fba4cf
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Add support for detecting UBWC decoder version and program
UBWC configuration to hardware.
Change-Id: Ibe753d35ca46b069de8392c65a3b06131b7e238a
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
During link training, after the swing/preemphasis is updated, the driver
is supposed to poll the link status on the sink and quit once the
LINK_STATUS_UPDATED bit is set and also latch the next set of
swing/preemphasis requested by the sink. But currently, the driver is
exiting the loop only when the LINK_STATUS_UPDATED bit is cleared. So,
it also latches the swing/emphasis request from the second read.
Typically, the SW read is slow enough that the bit is set on the first
read. The driver then reads the second time and exits the loop, since
the bit would be cleared then. In most cases, this doesn't affect
the training sequence, since the swing/preemphasis request for next
attempt is retained on the second read. But, atleast in one
specific case, it was observed that the swing/emphasis request
gets reset along with LINK_STATUS_UPDATED and so the driver ends
up missing the actual request and latches incorrect values instead.
This causes link training to fail as it keep retrying with the
same values that it starts with.
This change fixes the exit condition check so the driver quits the loop
as soon as the LINK_STATUS_UPDATED bit is set.
Change-Id: I7f5d9c6b30d48e113aef628d2ab2c1bd972fe743
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
This change updates vreg_ctrl_0 and vreg_ctrl_1 settings for
cape DPHY as per the HW recommendation.
Change-Id: Ide66c62d980b57de1f826ed24d1c0747d8fb6c77
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
This change fails the drm_atomic_commit and avoids S2 translation
fault if drm_gem_object is found attached to a secure context bank
during non secure session. In the current codeflow, we are detaching
the gem object from secure CB and reattaching it to non secure CB,
but only S1 pagetables entries get modified and S2 pagetables entries
are not corrected since hyp_unassign is not called with CP_PIXEL
VMID which can only be done by client when buffer gets allocated.
Change-Id: I62302064f96276ef82044ee88fb89e295fb96b4b
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Changes include updated register writes for DP PLL
as per 4nm target.
Change-Id: I2d8ddbf4af5c2c6d885c73b7c888f31ce45f4cbf
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Remove unnecessary register block size < REG_DUMP_ALIGN check during
the sde_dbg registration of a HW blcok. This avoids the registration
failures for few smaller hw blocks. The register size is padded later
according to REG_DUMP_ALIGN during the hw block register dump time.
Change-Id: I36474720a630f1c3e96072b1d6d8743018fcaeec
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
In an effort to reset the DP controller states on a disconnect, the
driver is issuing a SW reset to the controller. But SW reset on
the controller doesn't necessarily restore the controller to its
full reset state. It only resets part of the logic. So if for some
reason the MST streams were not disabled properly, ie. the slot
allocations were not reset properly in the controller, then a SW
reset would result in the DP controller raising state interrupts.
Since this SW reset is issued in the tail end of the disconnect
processing, the driver turns off all the clocks and also
removes the irq handler. This results in an interrupt storm at
the MDSS top level.
This change removes the SW reset on the disconnect path and
relies on the SW reset that already exists in the connect path
to restore controller state.
Change-Id: Ie7115e17d3c50c46c83c6f0e333da5cb534b8227
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
MST driver is incorrectly using maximum bw_code while initializing
MST topology manager instead of maximum link clock in KHz. This
prevents the topology manager to set MST state on a subsequent MST
plug in causing all MST cases to fail.
Change-Id: I9fc4e0326fe0c7a6c9b81af8810b7098fa8ba967
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During link training, after the swing/preemphasis is updated, the driver
is supposed to poll the link status on the sink and quit once the
LINK_STATUS_UPDATED bit is set and also latch the next set of
swing/preemphasis requested by the sink. But currently, the driver is
exiting the loop only when the LINK_STATUS_UPDATED bit is cleared. So,
it also latches the swing/emphasis request from the second read.
Typically, the SW read is slow enough that the bit is set on the first
read. The driver then reads the second time and exits the loop, since
the bit would be cleared then. In most cases, this doesn't affect
the training sequence, since the swing/preemphasis request for next
attempt is retained on the second read. But, atleast in one
specific case, it was observed that the swing/emphasis request
gets reset along with LINK_STATUS_UPDATED and so the driver ends
up missing the actual request and latches incorrect values instead.
This causes link training to fail as it keep retrying with the
same values that it starts with.
This change fixes the exit condition check so the driver quits the loop
as soon as the LINK_STATUS_UPDATED bit is set.
Change-Id: I7f5d9c6b30d48e113aef628d2ab2c1bd972fe743
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Decouple the configuration and parsing of aux switches with the
parsing and configuration of HPD sources. HPD notification can come from
either GPIO based approach or a PD module through a SW interface. The
presence of AUX switch on the board should have no bearing in deciding
which configuration for HPD detection is used. Update the implementation
to allow for flexibility in selecting any combination of the HPD source
and aux switches.
Change-Id: I96d558f1d88a359d523fae6dc746045393884d5a
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Add a new function in Kalama to support implementation of sixzone
using single buffer LUTDMA. Since there is a hw delta from previous
target, we are updating the major version.
Change-Id: I1078e4e6f351c6894367c5457f3415a7432f55b5
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
DP PHY version is changed for kalama. This change
initializes the catalog structure for this new
version.
Change-Id: Ib89293cb874c61c6276f49573266822570e715bb
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Certain pll variables and function signatures are
obsolete and hence removing the header file
declaration containing these.
Change-Id: I93d4ff096ff253f21d67660287d6d3baa857cca1
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change updates framedata event and ubwc stats API to
align with userspace handling and expectations.
This change adds the empty irq event handler required to register
the frame data event.
This change also adds handling to the crtc event notify to provide
the payload pointer directly, required for the buffer object,
ensuring pointers are not mismatched while sending drm events.
This change also updates the ubwc roi plane property to process the
uapi defined roi.
Change-Id: I209f2b7418a0ec33aa0488119eb3fdb8ae94e8ba
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Cape uses phy version 4.3 but requires programming of
different values for vreg_ctrl_0 and vreg_ctrl_1 to
configure LDO setting. Add new phy compatible string
to distinguish cape from other chipsets and program
the registers accordingly.
Change-Id: I68b266cc6e179d211ee0fd05584a605f39b4d31d
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
This change adds Detail Enhancer LPF blend support from MDSS 9.0.
Support is added for qseed block in both SSPP and Destination Scaler.
Change-Id: Ic8e3732059498a156f51fb93c5fd6638bd731c57
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Create a common config function to be used by newer
versions of sixzone to avoid code repetitions.
Change-Id: I570cc625715880c325d257e2594d8a7688a040bc
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
In Kalama for sixzone there are 2 new lut entries for saturation
high and saturation medium. There is also a new saturation
adjustment curve, and a SV enable feature.
Add entries in uapi to accomodate the corresponding programming
for these 4 new registers.
Change-Id: Ib9a8a4e233da25de90480c09c40536546f614a01
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
When cwb is enabled enable software override for fal10 veto to
block fal10 entry as MDSS can keep asserting uidle if there
are no fetch clients like dim layer only usecase.
Change-Id: Ief51499d370c20fcbdda79576aee0179578650fd
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Update LTM merge mode setting for kailua since
merge control has its own register.
Change-Id: Ieaacd1e12f410def18a0fce11a77c94832c416f5
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
Some of the DPU hardware can have LTM2/LTM3 blocks.
Change adds register DMA to support LTM2/3 blocks.
Change-Id: I5703872994156b42decaaf6d383f8aded218c117
Signed-off by: Alisha Thapaliya <quic_athapali@quicinc.com>
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
During msm_drm_bind if one of the sub components fails
to bind and defers the probe, it used to clear the device
platform device private structures which are created as
part of msm_pdev_probe. When sub devices try to bind as
part of probe sequence it will try to bringup master
msm_drm and accesses invalid address leading to crash.
This change updates the cleanup procedure which avoids
such crash.
Change-Id: I2d5c94cfafa3c5ec23b81bb0a080ad6e0e5b02ad
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
