Link descriptor were getting freed by the pointer
of the previous freed link descriptor. This patch
fixes by copying the address of the current in a
local descriptor info and using it to free the
current.
Change-Id: I95e137ba5b1f0ad21b0e6fb39f6671e1d5b65ba6
CRs-Fixed: 2577624
Block ack and ack frame is composed and sent to up
layer after a unicast packet to AP is received for
tx capture feature.
Change-Id: I4b6bb35fa093432539d15d09a93f85a8ec700b34
As per the REO logic, if a packet is received with
SN <= current SN, then it will be treated as a 2K jump
error or OOR and the packet in consideration will be
dropped by REO. For NON-BA case this case will be
treated as 2k-jump error.
For the NON-BA case, the packets with SN <= current SN
should not be dropped.
The current REO configuration, sets the BA window size
to 2 for NON-BA case, which in turn enables 2k-jump
detection.
For configuring the REO to not drop packets with previous
SN, we need not set the BA window size to 2, thereby
disabling the 2k-jump check for NON-BA case.
A. SN = 1, 2, 3, 4, 2096, …
(good case, as long as the SN is within 2K range)
B. SN = 3, 5, 2
(3, 5 are good packet, 2 is bad packet and will
be dropped to ‘2K error’ with error code = 2K error.)
(note that this is for non-BA session, for BA session,
we detect SN as either
2K error or OOR error based on SN and window size).
After this change, we will treat this as a good packet.
C. SN = 1, 1, 1, 1, with duplicate detect enabled – these are duplicate
packets and will be dropped to ‘DD queue’ with
error code = DD
(No change)
D. SN = 1, 1, 1, 1, with duplicate detect disabled – packets will be
dropped to ‘2K error’ with error code = 2K error.
After this change, we will treat this as a good packet.
Skip the setting of BA window size to 2 for aggregated
packets in NON BA case.
CRs-Fixed: 2580605
Change-Id: I19d5eced7c8730a9c3820fd6fc69923d2a98263a
sw_frame_group_id decides process for frame. USER_STATS tlv case uses
sw_frame_group_id to add qos_null frame control to rx_status.
Change-Id: Ia3da8dbe4fc4c2d0f21fa8864e6b4e87170ba8f6
When SAP do connection with first Ref-STA or dis-connection with
last Ref_STA, wlan host need to re-configure REO Dst ring control
register. one of the register offset is 0xA38004, host need to write
remap window register (offset 0x310C) with value 0x14 first, but
sometimes this remap window writing not work, so just use the remap
window value 0x3F left by last writing, final Dst register offset will
be 0x1FB8004 which is out of valid range.
Find that if we read back the remap window after writing is done,
remap window writing failure issue is gone. as a WAR, check register
writing result for this specific register REO_R0_DST_RING_CTRL_IX_0
always before root caused.
Change-Id: I8d385a0f974ff37bdd867d2ec946f2f46f6eff32
CRs-Fixed: 2570728
Write into hal register using three floating windows instead of one.
This change is done to avoid frequent window changes for writing into
DP and CE registers. Instead 3 windows are used. One window is statically
mapped to CE block and another window is mapped statically to DP block.
Due to this design there is no need to change the window register to
write into these blocks and write can be done on corresponding window
with single iowrite32. Similar loginc is used for ioread32.
Also modified the hp_addr and tp_addr in initialisation stage so that
hal_write will not have multiple if checks.
Change-Id: Ibb99ec4da7f63323082e46a28afbe90e1f555545
CRs-fixed: 2507441
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
Increase the force wake timeout to 100ms for
debug builds as mhi requires 100ms to
wake up.
Change-Id: Ida0b1287a86a5a97fd2d9c80fee4e677eea86cbe
CRs-Fixed: 2552815
a. Add new macro HAL_REG_WRITE_CONFIRM to check register writing result,
enable register writing result check when do REO DST ring remap for
IPA.
b. only enable register writing result check when macro
HAL_REGISTER_WRITE_DEBUG is configured.
Change-Id: Ib52e6b0d689ccf714876b3978fa8e356f652d25e
CRs-Fixed: 2557252
Add debugging infrastructure to record every event posted to reo
command ring. The infrastructure maintains the record of the last
64 events posted to the ring.
Change-Id: Id56fc352050eb664a64b0abb767f3b4a6b4c3aa3
CRs-Fixed: 2552822
Added change to modify ce flags for Pine.
Also made changes in window enable bit
Change-Id: Id080be53d14450cb6d9376fc810177bce26a2869
CRs-fixed: 2507441
The reo destination ctrl registers
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR and
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR are used for mapping
msdu packets to different reo rings.
For QCA6390,
reo remap values varied from 0 - 7 so every 3 bits in
the register were used to map to a particular reo ring.
For QCA6490,
reo remap values vary from 0 - 9 as two extra reo rings are
added so we are using 4 bits in the register to map to a
particular reo ring.
Use the macros directly provided in the header files
to map reo rings.
Change-Id: I6d64266d3b388b3453b7df959048e3d693cf0a40
CRs-Fixed: 2544102
If CNSS platform driver and wlan host driver try to write
window register at the same time, conflict happened which then
register write failed.
Use the window register lock shared from CNSS driver to avoid
the conflict.
Change-Id: Iccc4e60e4f5eed995ec6aa53b024f3f96a2619a0
CRs-Fixed: 2534408
Check if REO ring is near full at the end of dp_rx_process. In case the
ring is near full, reap the packets in the ring (and replenish, send to
upper layer) until the quota allows. Ignore the HIF yield time
limit in such cases.
This change is needed to prevent back pressure from the REO ring(in case
it gets full). Backpressure from REO ring (to LMAC) may lead to a
watchdog and eventually a FW crash. Hence, avoid such a scenario by
reaping as many packets as the 'quota' allows when the REO ring is in
aforementioned condition.
A sid-effect of this change would be that at times the RX softirq may run
longer (till the quota limit) than the configured HIF yield time.
However, this logic is not expected to kick-in in perf builds. The issue
is reported for a defconfig build where lots debug options are enabled
in the kernel which can slow the processing down.
Change-Id: I2eb6544c159ec5957d10386b1750fd96473fe13a
CRs-Fixed: 2540964
During hal write register first device force wakeup
request is done. If force wakeup request fails register
write is not done and the execution continues. This leads
to NOC erros in REO ramap register cases. As in later point
of time packets will be coming on wrong reo2sw ring and at
the destination side channels are not enabled. When NOC error
happens the current system is of no help to root cause as the
write fail happened way before. So do panic if pci wake request
fails which help to root cause the reason for failure.
Change-Id: I30d3f0a7858f3d4af96a80f69ba59764c9a7c8e9
CRs-Fixed: 2541061
When txrx_stats 28 is issued we post messages to reo command ring
to receive reo queue stats on the reo status ring.
This leads to acces accessing reo_cmd_ring head pointer shadow
register when runtime pm is suspended. Perform
a hif_pm_runtime_get to resume the apps before accessing
the shadow register.
Change-Id: Ie6df817fc114bd4c8ba7783df1fe3bd770deec40
CRs-Fixed: 2544174
Add hal_rx_get_rx_sequence API to retrieve
rx sequence value based on the chipset.
Change-Id: I8377b96dfe04e9695a183482d9fcc4a804f845e0
CRs-Fixed: 2522133
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Implement hal_rx_tlv_get_tcp_chksum API
to retrieve tcp_udp_checksum value
based on the chipset.
Change-Id: Ifab970f10af06f8c0cdbd14d57cb66b49bae1648
CRs-Fixed: 2522133
Implement hal_rx_msdu_get_flow_params API
per chipset as the macro
to retrieve the flow parameters is
chipset dependent.
Change-Id: I6ef83232ebdf7497871a7fc588e082d14cdc9e75
CRs-Fixed: 2522133
Implement hal_rx_msdu_cce_metadata API per
chipset as the macro to retrieve the cce_metadata
value is chipset dependent.
Change-Id: Icd87d4ac32be78d69b24da106381a7669c86ada6
CRs-Fixed: 2522133
Implement hal_rx_msdu_fse_metadata API per
chipset as the macro to retrieve the fse_metadata
value is chipset dependent.
Change-Id: Iae7f532460b5203af2f95c504a6941c0b18b665e
CRs-Fixed: 2522133
Implement hal_rx_msdu_flow_idx_timeout API
per chipset as the macro
to retrieve the flow_idx_timeout value is
chipset dependent.
Change-Id: I03030e3763b3c4a9099699a2d24b8110961610cf
CRs-Fixed: 2522133
Implement hal_rx_msdu_flow_idx_invalid API
per chipset as the macro
to retrieve the flow_idx_invalid value is
chipset dependent.
Change-Id: I5b8622eb896456b7388016a16657048d0da4e970
CRs-Fixed: 2522133
Implement hal_rx_msdu_flow_idx_get API
per chipset as the macro
to retrieve the flow_idx value is
chipset dependent.
Change-Id: I75131d7c048f5b67489ed25fbd52bfcf01bab782
CRs-Fixed: 2522133
Add the following macros:
1. HAL_REO_CONFIG
2. HAL_RX_MSDU_DESC_INFO_GET
3. HAL_RX_LINK_DESC_MSDU0_PTR
Add the relevant function pointers to
retrieve the descriptor info from the
above mentioned macros based on a
given chipset.
Change-Id: If44ae3d91397f1b1b0c36a49ce56a2c5e719434e
CRs-Fixed: 2522133
Add the following macros:
1. HAL_RX_GET_FC_VALID
2. HAL_RX_GET_TO_DS_FLAG
3. HAL_RX_GET_MAC_ADDR2_VALID
4. HAL_RX_GET_FILTER_CATEGORY
5. HAL_RX_GET_PPDU_ID
Also add function pointers to
retrieve the flags from the above
macros.
Change-Id: I334b198588ceba77cd30bdde7ebc500cdbe18358
CRs-Fixed: 2522133
Add the following HAL macros:
1. HAL_RX_MSDU0_BUFFER_ADDR_LSB
2. HAL_RX_MSDU_DESC_INFO_PTR_GET
3. HAL_ENT_MPDU_DESC_INFO
4. HAL_DST_MPDU_DESC_INFO
Add relevant function pointers to retrieve
descriptor info from the macros based
on chipsets.
Change-Id: I99ce7566a668180c7849eedea915b6f23a8dbf35
CRs-Fixed: 2522133
Implement hal_tx_desc_set_mesh_en API
based on the chipset as
the macro to set mesh_en value is
chipset dependent.
Change-Id: I43c85e4ed6fd4f9992de5b71857cdb8becd1dd36
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_sa_sw_peer_id API
based on the chipset as
the macro to retrieve sa_sw_peer_id value is
chipset dependent.
Change-Id: I2efd1f851539bbffc8f75c7662045c1f4a3c4469
CRs-Fixed: 2522133
Implement hal_rx_mpdu_start_mpdu_qos_control_valid
API based on the chipset as
the macro to retrieve mpdu_qos_control value is
chipset dependent.
Change-Id: I61449ff5afc958f1a1f93013b0c5ab56d38cc833
CRs-Fixed: 2522133
Implement hal_reo_status_get_header_generic
based on the chipset as the macro to retrieve
reo_status value is chipset dependent.
Change-Id: I43bd624bec37fb051f33b4828fcf7cd3e4b2a61e
CRs-Fixed: 2522133
Implement hal_rx_hw_desc_get_ppduid API based
on the chipset as the macro to retrieve
ppduid value is chipset dependent.
Change-Id: I7d3457d731ea486f04367f98f9f18d3f1c0fcfd7
CRs-Fixed: 2522133
Implement hal_rx_tid_get API based on
the chipset as the macro to retrieve
tid value is chipset dependent.
Change-Id: I37eab3f3c1c2bbba6094b9ddb24d72712b819f73
CRs-Fixed: 2522133
Implement hal_rx_is_unicase API based
on the chipset as the macro to retrieve
is_unicast bit value is chipset dependent.
Change-Id: I38807f478c295309adf2a07ce9010b1bc04c734e
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_sequence_control_valid
API based on the chipset as
the macro to retrieve sequence control valid
value is chipset dependent.
Change-Id: I01a006094d0330060e9ff1a91200c48c2426f38d
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr4 API based
on the chipset as the macro to retrieve
addr4 value is chipset dependent.
Change-Id: Ie35d01de1619a8ab540bb1b2019a15b436efb7d4
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr3 API
based on the chipset as
the macro to retrieve addr3 value is
chipset dependent.
Change-Id: I3983599b656e82170de5905c08daee3ec164e7a0
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr2 API
based on the chipset as
the macro to retrieve addr2 value is
chipset dependent.
Change-Id: I4026db892d4f2f41db72c50f780ba898b8a17fa7
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr1 API
based on the chipset as the macro to
retrieve addr1 value is
chipset dependent.
Change-Id: I7ed88f2243d397c9d605a08d3b93e17f0004c63d
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_frame_control_valid API
based on the chipset as the macro to retrieve
frame control valid value is chipset dependent.
Change-Id: I49d16ae44b2e9567ff746d2088058f0c1025ea40
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_fr_ds API
based on the chipset as the macro to
retrieve for_ds value is chipset
dependent.
Change-Id: I6d41d02ac50cae752567d98645f0447cc122a84f
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_to_ds API based
on the chipset as the macro to retrieve
to_ds bit value is chipset dependent.
Change-Id: I36d9d14e226bcc604b91d8aecbe52836c5a12272
CRs-Fixed: 2522133
Implement hal_rx_mpdu_start_sw_peer_id API
based on the chipset as the macro to retrieve
sw_peer_id value is chipset dependent.
Change-Id: Ifebaf2430731f5e0593dde4789d721e9fe7ce7c1
CRs-Fixed: 2522133
