Adjust pll pclk rate to support non 1/1 dispcc MND
divider values by updating pclk div calculation.
Change-Id: I1972b536a109b97978e843f046b1db4ad6813a51
Signed-off-by: Srihitha Tangudu <tangudu@codeaurora.org>
Creating a generic api that can be used with the driver
for read poll timeouts. This allows for easy overriding
of the function, if necessary.
Change-Id: I7bc5176ebabe782089b1a4d6e94c17ad3eb9ada4
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Michael Ru <mru@codeaurora.org>
The change ensures that for the slave PLL the PHY post divider
always needs to be configured to 0x1.
Change-Id: I481b4fd206d9f8e05af724687beb2e89fd6c2ea6
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Define 64 bit variables as unsigned long long to ensure
8 bytes in 32 bit builds.
Change-Id: I723ae0c4ba6a0de07c92d14eeef95bde095c8e3d
Signed-off-by: Venkata Prahlad Valluru <vvalluru@codeaurora.org>
Change fixes issues with the recalculation and DSI PHY PLL
toggle sequences while using continuous splash.
Change-Id: I6e63dd176e3ad5160b4df9f2da6d981951b696ab
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change avoids hardcoding the PLL_LOCKDET_RATE_1 register
value, rather using the variable with the same name that has
been initialized in dsi_pll_regs.
Change-Id: Ideb2c2b593156a4361feeb071df41f65e52c3beb
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
While recalculating VCO rate, currently the frac_bits value
is being hardcoded. The change instead uses the initialized
value from the 5nm PLL configuration.
Change-Id: I245574f4810a7b036d512ff1a347aa7e296702d1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change updates the pclk divider calculation to ensure
more accurate pclk rate for DSI.
Change-Id: Iaf3a5b6e4b10ac751b3a80e2c3041ab8260b21e5
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change avoids clock framework APIs to configure the DSI PHY
PLL. It follows HW recommendation to set the byte and pclk
dividers.
Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add support for 5nm DSI PLL C-PHY shadow clocks, which
will be used during dynamic dsi clock switch.
Change-Id: I55b11f2d0cffd8494d4641e9b2de0b88e7229978
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Currently, PLL_CFG1(1:0) register is updated with cached values
in dsi_pll_enable. This can create issue when UEFI and kernel
cfg1 programming is not same. To fix it, return cached value
of cfg1 when its read in pclk_mux_read, so that pclk_mux_write
is called and cached value is updated.
Change-Id: I1e45ff0685797bf4dd2e3a52af4753425f31edfc
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Panels supporting Cphy use a specific divider
blocks. Add additional divider blocks for byte
and pixel clock output to support DSI CPHY.
Change-Id: I74b3ee2bdd22ae8fa20567fe837e03915537c4fb
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
The clock framework nulls the clock hardware init data, after a variant
of clk_register is called on the clk_hw pointer. This results in a null
pointer dereference when we try to call set rate in the PLL prepare
function. The call can be a direct call to the function rather than
trying to access through the init_data pointer of the clk_hw.
Change-Id: I3613eea915d4f5620d7f0258ae391ad2ac624148
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
DSI PLL is tightly coupled with DSI PHY. This change removes
separate DSI pll driver and makes DSI pll as a subnode to DSI
PHY which is an accurate way of representation. In addition, this
change adds support for 5nm DSI ctrl and PHY revisions and adds
DSI pll support for 5nm. Remove support for older DSI pll revisions
such as 7nm, 10nm, 14nm, 20nm, 28nm.
Change-Id: Ic8b886a9fe24b906e4ec5130720600efa1e59b68
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
