On reclaim error, mem handle is still valid and reclaim
should be retried on next commit. This change keeps the
mem_handle valid.
Change-Id: Ie3e0cc3d37c7f1f260a7655f48a6aadece65a1ca
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Commit b67da33a6307 ("trigger tx_wait if panel
resolution switch") increases the mode switch latency.
Alternatively, single buffer tear check registers can be
updated when vsync_in is disabled. It allows mode switch
frame trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Wait for asynchronous DSI DCS command transfers to complete
before disabling DSI interrupts during pre-release. This is
required to resolve a race condition where dsi worker threads
can trigger HW access while a VM lend/release is occurring on
the CRTC commit thread.
Change-Id: Ia1f153a2cd008c617dba274473e7678b01a38d29
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The ROI commands are sent with an asynchronous command transfer wait.
If the queued CMD DMA wait for done gets scheduled before the DSI
controller timing engine programming, the later will be blocked waiting
on the ctrl_lock, which was acquired by the queued DMA wait for done work.
This effectively negates any advantage of having the async wait flag for
ROI commands blocking the main commit thread.
The change swaps this order to ensure that such a scenario never happens.
Change-Id: I8a971c0c7733eea3d435b637ca41b34fa60adfc1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
During display encoder disable, reset the dsc control
mux configuration during null commit to ensure dsc hw
blocks are cleanly freed up.
Change-Id: I02e2f074450e4d7b49dc8fec14777f380786c63e
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
While hw resources allocation for an active display during modeset, avoid
dsc hw allocation switch by finding which dsc encoders are allocated
previously and allocate same dsc hw encoders. This helps in fixing underrun
issues in below scenario of dual display power ON/OFF.
Use case: Dual DSI display setup, both are DSC enabled, primary in video mode.
--> when both displays are in powered off, all hw block are free.
--> enable second dsi display
Since LM 0/1 marked for primary, LM 2/3 allocated along with DSC 0/1
--> enable primary display
LM 0/1 allocated with DSC 2/3 encoders
--> Now power off secondary DSI
DSC 0/1 are freed up
--> Immediate modeset on primary, DSC allocation switched
LM 0/1 and DSC 0/1 allocated. DSC 2/3 are freed up as per RM but
decoupling DSC 2/3 blocks with respective pingpong or intf is not done.
This is causing underruns on primary.
Tracking which DSC blocks are freed during resource switch and programming the
respective DSC control mux configuration is not feasible and not scalable as
any other display can allocate those blocks and would require synchronizing
across display threads. So approach taken is avoid dsc resource switch itself.
Change-Id: I7f740722a52266740c4b168edc0c619e3cf68989
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Adjust pll pclk rate to support non 1/1 dispcc MND
divider values by updating pclk div calculation.
Change-Id: I1972b536a109b97978e843f046b1db4ad6813a51
Signed-off-by: Srihitha Tangudu <tangudu@codeaurora.org>
Add new properties to support dynamically turning on and off digital
dimming and setting new minimum backlight.
Change-Id: I3b94190877d556768ba2c92ec59432dec44de0de
Signed-off-by: Ping Li <pingli@codeaurora.org>
Trigger tx_wait if command mode panel resolution
switches during mode switch to avoid early single buffer
tear check programming.
Change-Id: Ib747df8250c714248a44b596c2c8aeef006ea4fc
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Userspace module may not trigger the atomic check and it
can cause the commit failure. In such case, always reserve
the minimum core clock rate on mmrm module for built-in
displays to avoid the power ON failure.
Change-Id: Iafd92a7b7d1b35befe70b041cbedaec2add40de4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Reorder registration of various display drivers in the order of
dependency.
Change-Id: Idfa0616d3133f3b03c713e3c15a4fd3956ec2594
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
If an external display, such as DP, requests for the available
resources, resource manager (RM) will provide a count of all unused
mixers. If the primary/secondary display(s) are not active, the RM
will report the associated preferred mixers as free resources.
However, RM will not allow preferred mixers to be allocated to other
displays. DP driver could look at these available resources and assume
a high resolution mode is possible and fail during resource allocation.
This change updates the available resources info API to account for
primary/secondary preferences while exposing available resources.
Change-Id: I134a1047f24ac9f1fcee695aa14a1d3e43c1571f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.
Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Commit Ie972a2e140adfd81c4e68df8e7bc69feaaca22e1 updated the dp
driver to extract the drm mode clock from timing parameters
instead of using the clock value provided by EDID to align the
behavior with DSI driver. But this results in incorrect clock
value if the refresh rate is not an integer value. For rates
such as 59.94 or 29.97, the calculated mode clock value would
be different from what is stipulated by EDID. This change
reverts the mode clock calculation to use the clock value
from EDID.
Change-Id: I3e192ef09d2456fbb1d22a0bf9474ac25ba86c72
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
Noise and attenuation layers are full screen layers. Top left coordinates
are not cleared in some use cases when same blend stage is assigned to
noise and attenuation layers. This change sets top left coordinates of noise
and attenuation layers.
Change-Id: I6af7a38d011d0bb642dc3d8a4aff338075524906
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
Power on reset value of DPTX_CONFIGURATION_CTRL.ASSR (alternate scrambler
seed reset) is high. Which will cause link training 2 to fail with TPS4 pattern.
Change disables this before link training starts.
Change-Id: Iee95de04625658254b242afdcbba6db24a52606d
Signed-off-by: Vara Reddy <varar@codeaurora.org>
DP driver is requesting USB to release SS lanes very early
during bootup even before USB has fully initialized. As a
result USB driver is returning -11 which will abort DP state
machine. This change will allow DP driver to retry USB request
whenever this error code is received.
Change-Id: I144d16ef4b07016569ba9c04df15610fe3b5e6fc
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
When disabling an encoder with multiple physical encoders, the
intf mux must be cleared on all interfaces. Currently only the master
physical encoder is being cleared, leading to possible DSI
underflow errors. This change ensures that the mux is cleared
on all interface blocks.
Change-Id: Idb1b96fd65545e3599100e70ace22bc3837d7233
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
In the event when msm_gem_delayed_import returns an error, reset
the obj_dirty property to true to allow the buffer to detach and
attach again.
Change-Id: Ib8da8f237c5a4ab696675cbcf66f1a3dfae02639
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
In sim mode, the dp driver is not checking for the aux state before
processing an aux request. This ends up causing the drm framework to
unnecessarily wait for 4 seconds while destroying a stream.
This change adds the check for aux state to align with the behavior
of a real sink.
Change-Id: I81900018ac1b403bb1e03fe26206e145694fefbd
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
In the current code for finding the qsync min fps for a
mode, entire mode list is iterated which involves acquiring
dsi display_lock. During conn tx debugfs commands, if
qsync min fps is required, we try to acquire dsi
display_lock twice which results in hang state. This change
adds qsync min fps value in dsi_display_mode_priv_info
struct in order to get the qsync fps from the
msm_display_mode present in connector state instead of
looping through all the modes to find the mode qsync fps.
Change-Id: Ifded40d1f12462bb50fc7bdafb746ae5b8d9512a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Change adds support to notify TZ ops TA for any HDCP 1.4
authentication state changes, so that TZ can optimize their
code for better performance.
Change-Id: I62f47e2e3fc102cb51cf695daa5f6b798f65781a
Signed-off-by: Vara Reddy <varar@codeaurora.org>
This change adds support for reading the byte at specific DPCD
addresses for physical monitors, similar to the way it is already done in
sim mode.
The read address is taken to be the last written address. Reads return a
single byte unless the address is 0, in which case 20 bytes are returned
to preserve the original functionality.
Change-Id: I43c44d81758c156257bd5dba6bb8f9c08ac948eb
Signed-off-by: Alex Danila <eadanila@codeaurora.org>
