Add srng disable function for 5332. This is required for
umac reset feature. Also, Avoid srng disable for lmac
rings.
Change-Id: Ieccc86134ee4d1cc3cd8a31a62f8fdf3afd5faf9
CRs-Fixed: 3599325
1. Check Tx halt during umac reset and avoid halt if set already.
2. Perform SRNG disable only in case of umac reset
Change-Id: Id364a6460a64e83002b5c96e08031ad2a0bc8fd7
CRs-Fixed: 3459427
setup to correct value by shifting intr_timer_thres_us
by 3 for interrupt timer to take less time.
Change-Id: I0eb799bf3a3443a7ca4a43512b7ec03444da81bc
CRs-Fixed: 3439468
Add generic HAL APIs changes for Rhine architecture under
hal/wifi3.0/rh/ which are generic across Rhine chipsets.
Add wcn6450 specific HAL API changes under hal/wifi3.0/wcn6450.
Change-Id: I0964e0f610faa402c00fb68e4c6e901a92f6d7a7
CRs-Fixed: 3383304
The kernel-doc script identified a number of kernel-doc issues in the
hal/wifi3.0 folder, so fix them.
Note that there are a number of instances where public functions have
their implementation documented in addition to having their interface
documented, so remove the duplicate documentation since only the
interfaces should be documented.
Change-Id: Ic238c0f53658e8754882c83204ffae5ad713ec6b
CRs-Fixed: 3410624
Retain ds ring indices across wifi restart to avoid
edma hang. Fetch the indices from ds module and set
the corresponding ds ring indices.
Change-Id: Ia299a7006166aef096c7d2c1f65f6bef65415a37
CRs-Fixed: 3332152
The MSI address and data information for Direct Link
copy engines will be available once the WiFi driver
on LPASS is initialized. Add support to configure the
IPCC address and data values into Direct Link copy
engines at runtime.
Change-Id: I5e7dff90c2f1ff764462c235deb5795ed019a16b
CRs-Fixed: 3316679
Hal layer changes to handle Umac post reset
and post reset complete events from firmware.
Change-Id: Ib25427930aab25650731c87b38e2ef7e47ae98d9
CRs-Fixed: 3267222
Add function pointers to free buffer address stored in status buffer
and support tx monitor in legacy and Waikiki flow.
Change-Id: I28612d388009292ff751fe514183fb801909f485
Currently the hardware srng register offset is statically
assigned to the handle. This can lead to incorrect index access
when targets (eg: wcn7850) is added which require additional
register offsets to be stored in the hw srng register offset table.
Move to the index based assignment of the srng register offset.
Change-Id: I8e38bdd0c28068029a0267fce706edf4378b9df8
CRs-Fixed: 2965081
WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
Add the changes to the generic HAL APIs.
The APIs generic across lithium and beryllium
architecture are kept in common HAL code.
The APIs which are generic across lithium
chipsets are moved to lithium specific files.
The APIs which are generic across beryllium
chipsets are kept in beryllium specific files.
Change-Id: Ie5e28aca5de02aa42f63b4a13fcb1cb32ffa8a28
CRs-Fixed: 2891049
Use macros like dp_cdp_debug, dp_cdp_err, dp_cdp_info to
print logs for QDF_MODULE_ID_CDP
Change-Id: I550eefa82c3417b8bf83378d4a9c6f382098fea6
CRs-Fixed: 2855937
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.
Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.
Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
mu code is not sending frequency in top 16 bits of tlv.
this check makes sure not to check for freq 0 and still be able to use
channel to generate freq.
Change-Id: If18c400e51bc41f8fec4fd50bdd180adfd79e578
Add reo ring descrptor swap in case of big endian platform.
Convert msi_data into little endian format before writing into
MSI_DATA register. Also change into little endian format while accessing
the shared LMAC registers.
Change-Id: I07f4ae4e6df4608201b63d325c2cbc37436d1592
When matching ppdu_id is detected during HAL processing, then print the
error message instead of going for assert.
Change-Id: I8f58359a66fbeaf2ebc98477f65bab446c0a784b
CRs-Fixed: 2747953
In monitor mode, radiotap header contains VHT/HE information in management
and control frames after association of STA to AP.For this,reset of
ppdu_info is required before processing of ppdu in order to avoid reuse
of ppdu_info.
Change-Id: Ia36ec2664f79d645ff76db016f986dfb92ec8bbd
CRs-Fixed: 2734804
When an AP operates on a 6G channel. The channel frequency in the
radiotap header, in the beacon frame, shows an incorrect 6G frequency.
This is because, the function hal_rx_radiotap_num_to_freq is not updated
to handle the 6G channelization spec update ( IEEE 802.11 11AX Draft 6.1).
To fix this issue, update the function hal_rx_radiotap_num_to_freq to
handle the 6G channelization spec update (increase the 6G frequencies by
an offset of 10MHz).
Change-Id: I342dcb46b2627b3a2c3f12524077e63d811a5feb
CRs-Fixed: 2733367
On Lahaina platform it is seen that WBM IDLE ring init is failing,
Write to WBM_IDLE link ring LSB write is failing.
Add temporary WAR to do back to back write of WBM IDLE link ring
LSB address config register.
Change-Id: If0c20da06bafa3037845e9806934f9e4dfbd1c1c
CRs-Fixed: 2690495
MPDU start TLV structure is different across pine and hk/cyp. The
access to individual members of this structure is already taken care
in HAL APIs.
Tha addition of offset is redundant and wrongly defined offset values
led to wrong interpretation of mpdu start tlv fields like RSSI in
QCN9000.
Change-Id: I3c0daa1c9117eecd1566a1d52d794e92dc292fa4
CRs-Fixed: 2682570
make sure both PCIe and device are force woken for the register
writes for hsp, or write may fail.
Earlier WAR is not required as we have root caused it.
Change-Id: I350b810a6cef8eec46428e57f5b779f888552c1b
CRs-Fixed: 2677342
rts full destination address is needed to be able to do check on mac
to be able to recreate cts frame correspondingly.
Change-Id: I3ec7e765bb4a0645a1495b4ca42d81fd3134cc5d
Currently, mcopy mode delivers first msdu(fcs_passed 128 bytes) per-ppdu
to upper layer, add support for Extended mcopy mode to deliver first
msdu(128 bytes) per-MPDU(fcs_passed).
Change-Id: Ib345fc14a8d468788b9de78516d27e8dff24caa4
CRs-Fixed: 2644175
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
On Lahaina platform it is seen that WBM IDLE ring init is failing,
Write to WBM_IDLE link ring LSB write is failing.
Add temporary WAR to do back to back write of WBM IDLE link ring
LSB address config register.
Change-Id: I7f72abb7226e1d7beee127ebda88488172147f21
CRs-Fixed: 2647762
Enable SW2TCL_CMD ring for data on QCN9000, QCA8074 V2/V1
and IPQ6018 targets.
Enabled 4th Tx ring for data enqueue to HW.
Transmit completions for packets from CPU0 and CPU3 are routed to
WBM2SW Completion ring 2.
WB2SW completion ring2 is mapped to CPU3.
Change-Id: Ied4c4704e1f8623e909ad45c547a611de26c7ec5
Function added to convert given channel number to correct
channel frequency using the Channel center frequency and
populate it correctly inside the radiotap header
Change-Id: Iea2a9ee7d496b2aa0dbf8d6741a32d2dbfa3503d
CRs-fixed: 2637424
The HE GI and HE LTF values are obtained from phy
TLVs in monitor path. The stats used in host have an
enum defined used by other upper layer code.
The radiotap spec defines different set of enums.
Add translation function to convert host stats enum
to radiotap defined enum for sniffer capture purpose.
Change-Id: I8c76adb42b0623e83958f7a37147b74e72b1ce74
CRs-Fixed: 2636051
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
Initial changes for ipq5018 compilation.
Added device ID and target type checks for ipq5018 traget.
Change-Id: Ib86a371fbe66749fcb6d114e7a4a9931b684e03d
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
fix the issue for block ack/ack for tx capture mode.
1. Hanndle BAR frame.
2. set rate for ACK frame.
3. Check block ack session and use block ack if block
ack session is established.
4. no ACK for broadcast probe request.
5. not ack if the ack policy is set to no ack in qos control.
Change-Id: I4f22c1c976334978fb971b42319fb3a6e43a00c2
Add monitor mode support to capture packets over 6GHz frequencies by
getting capture frequency from pdev.
Change freq type to qdf_freq_t.
Change-Id: I7b6edc43e254dc98a3c2939c369874bec9d16ddd
CRs-Fixed: 2568970
the current HAL API is to read the WBM internal error
bit from the wbm release ring descriptor is always taking
HKv1 HW structure. But the wbm_internal_error bit
placement has changed from HKv2, for this reason we have
to use target specific HAL API.
Change-Id: I44789180754ca21ae59650b6d8620321a1f12569
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers.
Change-Id: I3662b60375cb8886447a2fba3efead6a1ef3a98d
CRs-Fixed: 2593408
sw_frame_group_id decides process for frame. USER_STATS tlv case uses
sw_frame_group_id to add qos_null frame control to rx_status.
Change-Id: Ia3da8dbe4fc4c2d0f21fa8864e6b4e87170ba8f6
The reo destination ctrl registers
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR and
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR are used for mapping
msdu packets to different reo rings.
For QCA6390,
reo remap values varied from 0 - 7 so every 3 bits in
the register were used to map to a particular reo ring.
For QCA6490,
reo remap values vary from 0 - 9 as two extra reo rings are
added so we are using 4 bits in the register to map to a
particular reo ring.
Use the macros directly provided in the header files
to map reo rings.
Change-Id: I6d64266d3b388b3453b7df959048e3d693cf0a40
CRs-Fixed: 2544102
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Implement hal_rx_msdu_get_flow_params API
per chipset as the macro
to retrieve the flow parameters is
chipset dependent.
Change-Id: I6ef83232ebdf7497871a7fc588e082d14cdc9e75
CRs-Fixed: 2522133
