qcacmn: Data path changes for big endian platform

Add reo ring descrptor swap in case of big endian platform.
Convert msi_data into little endian format before writing into
MSI_DATA register. Also change into little endian format while accessing
the shared LMAC registers.

Change-Id: I07f4ae4e6df4608201b63d325c2cbc37436d1592

dp/wifi3.0/dp_htt.c

@@ -1028,7 +1028,7 @@ int htt_srng_setup(struct htt_soc *soc, int mac_id,
 	msg_word++;
 	*msg_word = 0;
 	HTT_SRING_SETUP_RING_MSI_DATA_SET(*msg_word,
-		srng_params.msi_data);
+		qdf_cpu_to_le32(srng_params.msi_data));
 
 	/* word 11 */
 	msg_word++;
@@ -1304,9 +1304,6 @@ int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id,
 	HTT_RX_RING_SELECTION_CFG_STATUS_TLV_SET(*msg_word,
 		!!(srng_params.flags & HAL_SRNG_MSI_SWAP));
 
-	HTT_RX_RING_SELECTION_CFG_PKT_TLV_SET(*msg_word,
-		!!(srng_params.flags & HAL_SRNG_DATA_TLV_SWAP));
-
 	HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_SET(*msg_word,
 						htt_tlv_filter->offset_valid);
 

hal/wifi3.0/hal_api.h

@@ -1942,9 +1942,11 @@ hal_srng_access_end_unlocked(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
 		 * hence written to a shared memory location that is read by FW
 		 */
 		if (srng->ring_dir == HAL_SRNG_SRC_RING) {
-			*(srng->u.src_ring.hp_addr) = srng->u.src_ring.hp;
+			*srng->u.src_ring.hp_addr =
+				qdf_cpu_to_le32(srng->u.src_ring.hp);
 		} else {
-			*(srng->u.dst_ring.tp_addr) = srng->u.dst_ring.tp;
+			*srng->u.dst_ring.tp_addr =
+				qdf_cpu_to_le32(srng->u.dst_ring.tp);
 		}
 	} else {
 		if (srng->ring_dir == HAL_SRNG_SRC_RING)

hal/wifi3.0/hal_generic_api.h

@@ -1642,6 +1642,22 @@ hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo,
 	return HAL_TLV_STATUS_PPDU_NOT_DONE;
 }
 
+static void hal_setup_reo_swap(struct hal_soc *soc)
+{
+	uint32_t reg_val;
+
+	reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
+		SEQ_WCSS_UMAC_REO_REG_OFFSET));
+
+	reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1);
+	reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1);
+
+#if defined(QDF_BIG_ENDIAN_MACHINE)
+	HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
+		SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val);
+#endif
+}
+
 /**
  * hal_reo_setup - Initialize HW REO block
  *
@@ -1666,6 +1682,9 @@ static void hal_reo_setup_generic(struct hal_soc *soc,
 	 * Default setting is to send all errors to release ring.
 	 */
 
+	/* Set the reo descriptor swap bits in case of BIG endian platform */
+	hal_setup_reo_swap(soc);
+
 	HAL_REG_WRITE(soc,
 		HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
 		SEQ_WCSS_UMAC_REO_REG_OFFSET),
@@ -1813,7 +1832,8 @@ void hal_srng_src_hw_init_generic(struct hal_soc *hal,
 			SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB,
 			MSI1_ENABLE), 1);
 		SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
-		SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
+		SRNG_SRC_REG_WRITE(srng, MSI1_DATA,
+				   qdf_cpu_to_le32(srng->msi_data));
 	}
 
 	SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
@@ -1928,7 +1948,8 @@ void hal_srng_dst_hw_init_generic(struct hal_soc *hal,
 			SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB,
 			MSI1_ENABLE), 1);
 		SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
-		SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
+		SRNG_DST_REG_WRITE(srng, MSI1_DATA,
+				   qdf_cpu_to_le32(srng->msi_data));
 	}
 
 	SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);

hal/wifi3.0/hal_tx.h

@@ -32,6 +32,9 @@
 #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE    0
 #define HAL_WBM_RELEASE_RING_2_DESC_TYPE      1
 
+#define HAL_TX_DESC_TLV_TAG_OFFSET 1
+#define HAL_TX_DESC_TLV_LEN_OFFSET 10
+
 /*---------------------------------------------------------------------------
   Preprocessor definitions and constants
   ---------------------------------------------------------------------------*/
@@ -45,8 +48,10 @@
 
 #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \
 do {                                            \
-	((struct tlv_32_hdr *) desc)->tlv_tag = (tag); \
-	((struct tlv_32_hdr *) desc)->tlv_len = (len); \
+	uint32_t temp = 0; \
+	temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \
+	temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \
+	(*(uint32_t *)desc) = temp; \
 } while (0)
 
 #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E