The original BA window size given from CP might > max DP supported,
add sanity check based on HAL target allowed.
Change-Id: Ibadaddeffe65165a89d580d8a5cbf5f7c724c809
CRs-Fixed: 3193852
Bifurcate the hal_get_reo_qdesc_size to corresponding lithium
or Berillium platforms.
This can handle difference, if any between them and later enhance
to set the qdesc size based on peer negotiation.
Currently for NON_QOS_TID, the BA window size is hardcoded as
256 for Li and 1024 for Be.
Also modify hal_reo_cmd_update_queue_params to accommodate higher
Block-Ack Window size. For this steal bits from pn_size and use
pn_size values as macros PN_SIZE_XX which is only 3 bits,
instead of 8bits.
Change-Id: If310175da579aa3a47a8b031a1774c6c8982d4b2
CRs-Fixed: 3125986
Changes needed for MLO soc attach to pass chip_id,
dp_ml_context from upper layer.
This change also takes care of assigning appropriate
RBM id for IDLE link descriptors based on chip_id.
Change-Id: I8f5f08c524d91942e6e458f048700b7bdd900107
WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
Adding write/read APIs for accessing the CMEM.
Currently in QCA6750, UMAC and CE windows are statically mapped,
a new static window for CMEM is added for CMEM transactions.
Change-Id: Ie10b33a6f468c6e4db314ea85856414962ef29e3
CRs-Fixed: 2771193
If reo_dst_ctrl register writing failed, this is a fatal error for
IPA pipe going to down case as RX frames will still be routed to
IPA rings then hit NOC error. retry register writing to see any
chance to write successfully, if fail always, trigger SSR or panic.
Change-Id: I3c03faa28e6cc93f396944579a360d5405c8138e
CRs-Fixed: 2774789
Add prefetch_timer configuration for CE rings.
Set prefetch_timer=1 configuration for qca6490 destination CEs,
prefetch_timer=0 configuration for other targets CEs.
Basically setting to 1us asking CE hw to update ring tail pointer to
update within 1us. FW side CE SW sets all rings to 1us already.
Idea behind this change is, we have seen pre-silicon issue where SRC
ring TP read by SW was not seen updated value when prefetch was set
to 8us. Changing prefetch timer value to 1us helps to resolve
pre-silicon issue.
So host side rings need to update the prefetch timer to 1us.
Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741
CRs-Fixed: 2669762
Fix macro name to enable delayed register writes.
Donot use delayed register writes for non fastpath access.
Change-Id: I235116ab3df5cb26bbfbb72de4ac6ed4b363a13a
CRs-Fixed: 2645865
As a part of enabling IPA pipes, the WBM2SW2 head
pointer register is written with the number of
buffers which have been allocated initially. This
register write is a critical one and failure in
writing this register can be fatal.
Confirm the written value, when initializing
the HP register for WBM2SW2 (for IPA).
Change-Id: Ib2da3a7aa6096375cf64857721619f47c50658de
CRs-Fixed: 2620750
In case the bus is in low power mode, the register writes (followed by a
memory barrier) may take a long time (~4ms). This can cause the caller
to block till the PCIe write is completed. Thus, even though PCI
writes are posted, it can still block the caller.
Hence, in case the bus is in low power mode (not in M0), or not in high
throughput scenarios, queue the register write in a workqueue. The
register write will happen in the delayed work context. In other cases,
i.e ,when the bus is not in low power mode or in high thoughput
scenarios, do the register writes in caller context.
Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e
CRs-Fixed: 2602029
Link descriptor were getting freed by the pointer
of the previous freed link descriptor. This patch
fixes by copying the address of the current in a
local descriptor info and using it to free the
current.
Change-Id: I95e137ba5b1f0ad21b0e6fb39f6671e1d5b65ba6
CRs-Fixed: 2577624
When SAP do connection with first Ref-STA or dis-connection with
last Ref_STA, wlan host need to re-configure REO Dst ring control
register. one of the register offset is 0xA38004, host need to write
remap window register (offset 0x310C) with value 0x14 first, but
sometimes this remap window writing not work, so just use the remap
window value 0x3F left by last writing, final Dst register offset will
be 0x1FB8004 which is out of valid range.
Find that if we read back the remap window after writing is done,
remap window writing failure issue is gone. as a WAR, check register
writing result for this specific register REO_R0_DST_RING_CTRL_IX_0
always before root caused.
Change-Id: I8d385a0f974ff37bdd867d2ec946f2f46f6eff32
CRs-Fixed: 2570728
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
a. Add new macro HAL_REG_WRITE_CONFIRM to check register writing result,
enable register writing result check when do REO DST ring remap for
IPA.
b. only enable register writing result check when macro
HAL_REGISTER_WRITE_DEBUG is configured.
Change-Id: Ib52e6b0d689ccf714876b3978fa8e356f652d25e
CRs-Fixed: 2557252
Add hal_rx_get_rx_sequence API to retrieve
rx sequence value based on the chipset.
Change-Id: I8377b96dfe04e9695a183482d9fcc4a804f845e0
CRs-Fixed: 2522133
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Add code to replace usage of void pointers from
HAL layer and instead use appropriate opaque pointers
Change-Id: Id950bd9130a99014305738937aed736cf0144aca
CRs-Fixed: 2487250
Modify aging timout in reo based on access category
to match cascade.
For BE, BK, VI use 100ms and VO uses 40ms.
Change-Id: I09267b6540460a13728bddc92a7e72157d6ce569
Crs-fixed: 2418294
To avoid race conditions where BA window size can change, always
flush entire REO descriptor from HW cache irrespective of current
BA window size.
Change-Id: I608996722e7dc2dc6acfd145b8c190b58ce09822
CRs-Fixed: 2251811
- Change the SR mapping address for QCA6390
- Use ring direction field from HAL ring config instead of HAL ring
directly as ring is not yet initialized here.
Change-Id: I900b2329367cc02ae2f9d7f164e5f867d8253d90
CRs-Fixed: 2299919
HE format in radiotap header are not being updated for HE_TRIG
frames. Add support for it. This is to support MU-OFDMA frames of
UL.
CRs-Fixed: 2223635
Change-Id: If0a93f6047185bcc51948b613d48d13ecb5e16cd
Some of the macro names defined in qca8074v1, are defined with
a slightly different name in qca8074v2, and few macros have the
same name in both headers but are defined with different values.
Fixed the same.
Change-Id: I5e948baf5326d1d8fdfa2bd7ee8aa072c710d17c
Create separate individual hal_srng_table and hal register
offset in target specific source files. Create separate
functions for qca6290 and qca8074 for few hal rx tx
functions as the macro value differs between the chipsets.
Assign target specific hal tx, rx ops as part of hal_attach
and call respective hal tx, rx ops through callbacks.
Change-Id: Ibbf490c678c39fdd9d54191aad7aaec786db30ec
