During display disable, ensure source pipes are detached
from control path in the disable commit itself. Otherwise,
if other display acquire these pipes immediately it can hang
as these pipes are still staged on current display ctl path.
Change-Id: Idc376051908676c74bc26394372a92316a674e3b
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Add a new clear_flush_mask ops in sde_hw_ctl_ops.
Flush mask update to cancel the fence error frame with
the new ops.
Change-Id: I8d03d8e83a05a652789fb38e885a3c8497e4d262
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
While clearing all blend stages, avoid writing blend config
registers for invalid dummy layer mixers introduced for dcwb.
These dummy mixers are SW only representation, these mixers
do not have respective blend config register space defined in HW.
Currently blend stage clear logic clears other undefined and
some valid registers like CTL_x_SW_RESET_OVERRIDE which is not
intended. This change limits accessing blend config registers
based on actual HW layer mixer count by ignoring dummy mixers.
Change-Id: I3a61fb6d5522b041fd6f10305b84dae449b4f2c7
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change adds hardware programming that will update the
txq wr_ptr upon output fence firing.
Change-Id: I79ff0ea5fb2b7f73a48bd70e3c8e71ea69fead95
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
add memory barrier before and after last command to avoid
out of order packet queuing to lut dma packet queue.
add memory barrier after ctrl flush to ensure lut dma
trigger, dspp flush and ctrl flush all are written to dpu
before control start.
Change-Id: I7e1613034af8407d55529cf3f95c70994334af82
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Update the hardware blocks and corresponding APIs
to configure new D-CWB data path. Add new hardware
pingpong blocks that are dedicated for second DCWB.
Change-Id: I529c24ac5aa483f30b6c9e7653eb1713c6b8fb8a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This change disables hw-fencing for the last commit before
vm transition. This avoids configuration issues if hw-fencing is
disabled in the incoming VM.
Change-Id: I573b7d1665f8cef442168bd0ab83a4b2b6cebbb6
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change updates the autorefresh disable sequence to manually
trigger output hw_fence during the transition. This is required
since on the last autorefresh frame HW will not trigger the output fence.
Change-Id: I6789fc6b51421524f88dcbdd1a063ae947646ae4
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds the value of hw-fence ready to
event logs for video and command modes.
Change-Id: I40a2e886a3b95e8853efcbdddf7fd9f6ce48eb9b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds the programming of the master interface
register for single interface configurations.
Setting this register is required by hw-fencing feature
to distinguish primary interfaces vs wb.
Change-Id: I84936ebd6a9f2d67cf98c19a51ce3a132c648a2d
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Ensure SDE_ERROR error log print function name and line number.
Add a macro DISP_DEV_ERR as a wrapper of dev_err to ensure origin dev_err
will print function name and line number.
This would help with analysis of errors reported with automated testing.
Expected display error log format:
[FUNCTION_NAME:line] ERROR_MESSAGE
Change-Id: I354f45b492059d5ba2bb110d56443fd338add7ad
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.
Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the cwb block offset and stride values for kalama
target in sde hw catalog. As part of the change, allow the
ctl wb-flush bit for cwb to be set based on the wb idx used.
Change-Id: Ibf7ccda88cbb47bddacf53b5af9841d381a4766c
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add sde ctl hw changes to support downscale blur. The ctl flush/active
bits for downscale blur are part of the writeback flush/active bits.
Add a new ops to update the dnsc_blur flush mask.
Change-Id: I29483ab399c5503ef4cfe5804d25cd26ad6265b2
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Expand various SSPP and CTL related data structures
to support DMA 4,5.
Change-Id: I0ce052b6a2f1599a9b6eb82ce8e4f34f4c68333d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
This change enables support for wb1 in ctl path and
adds irq support.
Change-Id: Iebbe35725aa279b8e02217ea93ba1b481f5e869f
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
The sde_hw_blk was meant to be a generic base object for all
SDE HW blocks, however, it enforces using a common set of ops
which is not practical when blocks have different capabilities.
Since this object was never used as intended and is not doing
anything functional today, remove the dead weight.
Change-Id: If76006c1ae5c62e8d7d77b100837dbaf6c661bd3
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Align the HW catalog to use common naming amongst the "revision"
and "version" structure members.
Change-Id: Ib6c81aee6cb49208b0699db4a75b4eb9dc79e800
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
This change fixes the continuos splash logic that identifies the
pipes staged by bootloader. The same code flow is used in trusted ui
handover as well. Existing logic was counting the pipes twice if the pipe
is staged on both the layer mixers. This change simplifies the pipes
already staged before handover by using the pipe index to convey if
it is staged or not.
Change-Id: Idb255f2077161dc3553114ac5d04e0ef743bb5ea
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Continuous splash setup checks the CTL configuration to determine and
log all planes that have been enabled for continuous splash boot.
This logic currently only checks the planes mapped to each LM on
a given control path, resulting in data planes being missed.
Update the boot plane enumeration logic to additionally check the CTL
fetch active registers to detect and log missed planes. This logic
checks against all planes found through the original enumeration path
to avoid logging the same plane twice. Note that planes found via the
fetch registers are assumed to be used across both rectangles due to
hardware logging limitations.
Change-Id: Ic1f4aaba94111fe096ba9764eeaef242beb6adf5
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Add new capture/tap point as CRTC property for
D-CWB feature. Update the hardware blocks and
corresponding APIs to configure D-CWB data path.
Add new hardware pingpong blocks that
are dedicated for CWB.
Change-Id: I22576df1768b50f9f47d8527f62913b01ff4d9a7
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Clean up ctl set up blend stages op to be more robust by
relying on global sspp stage register mapping.
Change-Id: I6d1594d52c275b6d848f51597a8f2411a8711b95
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This change replaces kzfree with kfree as kzfree has been
renamed.
While moving to the latest 5.10 tip, additional small changes
were required to resolve compilation issues:
set_dma_ops has moved from dma-mapping to dma-map-ops header.
This change includes the new header file required.
drm_panel_add returns void, this change removes the expected
return value check.
drm_prime_pages_to_sg takes an additional parameter. This change
passes in the drm_device pointer the function is looking for.
Remove an unused variable in sde_crtc vblank function.
Change-Id: I47c085c0cb64432873c2e750ae64cbdc2b5340da
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change disables the border color on the layer mixer,
based on the caller's request. This is required to totally
disconnect the layer mixer hardware when it is not
participating in blending the pixels. Having empty blendstage
but border color enabled, allows Layer mixer hw to produce
border pixels even when blend stage is empty.
Change-Id: I8e84aeedffbd42ad793a167a6cc5a3a653864c1a
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Add smmu cache hint at during the msm gem prime import
to ensure memory is cacheable. Ensure sys cache feature
is added to all sspp, not just vig.
Change-Id: Icc10468ad8d3e7c6aabd437776cde99eb627375a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Setup blendstages is done per LM but FETCH_PIPE_ACTIVE is per CTL.
Overloading mixer blendstage setup with fetch pipe logic can lead
to HW programming errors. Refactor the logic for setting
FETCH_PIPE_ACTIVE by adding a new op that allows caller to provide
a bitmask of all pipes required to be active on this CTL. This new
logic includes support for:
- 4LM use-cases, staging pipes for all LMs within a CRTC
- Demura fetch-pipe without need for tracking via active_cfg (removed)
Also, lower the cyclomatic complexity in setup_blendstages by moving
the logic for obtaining the mixer config settings in to a helper
function.
Change-Id: I2907b359ffad5734be5b06f44919b5ddb1ef3f7c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Store full or partial static image in system cache (L3 cache)
for video mode primary display. Added additional commit to
crtc commit thread to transition to read cache state.
The change also updates llcc APIs to support generic functionality.
Change-Id: I6b2a45da946d7e0e0b326da9d214be3f01a9420e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Some of the features in the DPU hardware needs planes to be staged but
it should not be blended in the layer mixer. Change adds support for drm
driver client to set the blend type on the plane and updates driver code
to skip staging the plane.
Change-Id: I1e8c7f6ce5617820ea8b24419e0d4d27b481819b
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Add support to stage layer with zorder 0 as base
layer and stage borderfill only during null commit.
Change-Id: I54356c1b7834227cc3da00c211e71ac5816ce51a
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Using individual flush functions for each active hw blk
is not scable-able for future use. Clean up the ops to merge
all flush functions into one and manage HW block id
with same API.
Change-Id: I62afbc51fa7d345b3a1f5721e5e09661a4215f7a
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Defines should always have a single space between #define and
the keyword to allow for searching where these definitions are
located using grep.
Change-Id: I38778e789b12df8a7a22c22dd27152a5ab047405
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add support to configure the DPU pipeline to support VDC-m
topologies.
Change-Id: Ib8ce9a0eaeaa838759fb09cb2ee164d4765e4989
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This change adds support for dsc using the 3d mux hw block.
The 3d_mux hw block merges the input from layer mixer before passing to
dsc block for compression.
Change-Id: I21544c33fff2c1e604c0ae712a036a127d25afcf
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Certain sub-blocks need to be enabled disabled dynamically on a
seemless mode switch (for ex. partial update) CWB is another example
where control path interface configuration needs to be dynamically
changed on enable/disable of concurrent writeback. Similarly
3d mux needs to be enabled/disabled for partial update use cases.
This change modfies the current api update_cwb_cfg and makes it
more generic and adds support to enable/disable only the 3d mux.
Change-Id: I5e5a6e78b0599f689cb2f83d0d626a5f392eff6e
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change introduces new ctl path api read_active_status to check
if a particular hw block is active or not in the current control path.
This is specially required in continuous splash use case when bootloader
has programmed certain blocks and the kernel driver tries to find
out the same configuration. This is used to ascertain which DSC block
is active in continuous splash case since DSC blocks are not tied to
mixer blocks.
Change-Id: I8dd590aa2dc764bd340727c166e1133ef9ce7af5
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
SDE HW from lahaina has moved the DSPP flush bits from CTL_FLUSH
to new CTL_DSPP_x_FLUSH registers. This change brings in
support for programming the new DSPP flush registers which
allow more fine-grained control over what sub-blocks within
each DSPP get flushed.
Change-Id: Ie16c9b153d607bd7627ba02480813ab588bbe2ea
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
New required programming in CTL. Fetch active informs the HW
of the active fetch pipes. Group ID informs HW of which VM owns
that CTL. Force this group ID to default/disabled until
virtualization support is enabled in SW.
Change-Id: Id9d68ae725a640893a4e347b69ad2b506a998f25
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
While disabling merge3d block, pending flush mask
needs to be set for merge3d.
Change-Id: Ic7baea278ac62ac1203aad8a33c40874704c85a1
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
CWB, DP and WB displays tear down sequence must reset
3d_merge, ctl, pingpong_binding, etc. MDP HW
blocks. This change fixes the tear down
sequence register programming. It also moves flush
sw reset before encoder_disable call. That allows
CWB tear down to update the flush configuration
on primary ctl path.
Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This snapshot ports changes from 4.14 to 4.19 into
the msm and sde layer. Snapshot was taken as of
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").
Change-Id: I59b799a78319c2db6930a2a10bc38976f8c09898
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Get controller scheduler status at each vsync to verify
pending frame status.
Change-Id: I01401a57b68828294299977a7be7e796d07c7472
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
