This change fixes an issue, where in CTL_2 was programmed for
secondary display and handoff was not done as the list traversal
logic was restricting it.
Change-Id: Icd945cfb3401ecc9c9c33059f5208a87979ada77
Signed-off-by: Yojana <quic_yjuadi@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
The issue scenario is as follows:
1. User space issues CWB commit N-1, frame got picked up and wr_ptr_irq
is received.
2. Next commit N CWB disable commit is programmed waits for N-1 wb_done
irq.
3. The kickoff count is decremented on wb_done_irq of commit N-1
and wb wait_for_idle is exited.
4. wb_frame_done irq thread execution stalled before populating fences
and commit thread execution continues.
5. wb_reset disables in_clone_mode flag, the stalled wb_done_irq thread
resumes its execution and signals the release fences on primary crtc.
6. Commit N-1 frame_done irq is received and release fences is
signaled again.
Made changes to avoid the race between irq thread and commit thread
over in_clone_mode flag, by adding a lock over wb physical encoder.
Change-Id: Iba9b6613c49d413239c9603228fe16b0d64c0ab6
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
When poms supported panel is booting up with video mode
rsc timers are not configured. Made changes to update rsc
timers configuration during bootup with video mode as well,
to avoid rsc stuck issues during poms switch.
Change-Id: I8c03b3e5483c17f73e3d8c6b57bd8d3eabb33b10
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
In the case of DMS the dsi phy timings get updated in
dsi_display_set_mode() and the clock in pre_kickoff().
This brings a mismatch between phy timing and the clock between the
above two operations. For example, during dsi_display_enable(),
the HW is programmed with the new phy timings but the clock is still
running at the older rate. This mismatch can lead to screen flicker
or error.
Update the phy timings and clocks together during pre_kickoff().
Change-Id: I30198e91aba5879b1773103c088d94175639790c
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
During suspend-resume in a dual-display scenario with primary
display topology <2 2 1> and secondary display topology <1 1 1>
with 3 DSC instances, allocating DSC block 1 to the secondary
display results in DSC blocks 2 and 3 being assigned to the
primary display. However, as DSC block 2 is not a peer of DSC
block 3, it triggers an atomic check failure as a part of the RM
reservation failure. While reserving the DSC resources, prefer non
pairable DSC if the topology requests for single DSC instance. If
there are no non pairable DSCs available, then select one of the
available DSC.
Change-Id: I3e3f7ec343b5bc99aa23786a3cb65cf7bbbd7275
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Clear internally tracked total number of lm blocks in
use when there are zero active streams.
This is required to have an accurate count of lm blocks
in use in a mst scenario.
Change-Id: Ida5d509bab60b3b6a4c0ace07c7c68380d28a0dd
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Dither, unsharp should not be enable when VLUT
is disabled. This change ties dither, unsharp to VLUT
enable/disable and not during init property.
Change-Id: Idfad899a13252b22104c9746c86f4e158d9b0980
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Anti aging requires cwb capture for algorithm. This change adds
support for cwb capture with downscale. Dnsc block needs to be
disabled when cwb is disabled.
Change-Id: I52e3eb4442440e6c59eb96566b0f6af1fd10c973
Signed-off-by: Mitika Dodiya <quic_mdodiya@quicinc.com>
Changes to select particular dp_aux_switch based on board
requirements. Currently provision to support both fsa4480
and wcd939x as aux switches are provided.
Change-Id: Iafbee4d91d14aafb1e7a37ddfa2b1ea0d0e5e784
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Set topology override to cmdline topology before parsing timings so that
correct topology is set in mode.
Change-Id: I7ba371370c71516b436dbe5ec07064f7b54975bb
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Demura init property gets reapplied during first commit after resume.
However, first commit after resume is null commit and HFC correction
file will not be available during first commit.
This change marks error to warning for first commit after resume.
Change-Id: I01ec4bd977d60925d9b7a54076329c3becaa0b20
Signed-off-by: Sanskar Omar <quic_sansomar@quicinc.com>
In legacy POMS feature, there were separate timing nodes for
video and command mode. So, while calculating the total number
of modes, 1 extra mode is added for command mode if POMS feature
is enabled in video mode panel.
But as per the new design, this is clubbed into one timing node.
So, there is no separate mode for command mode. This change removes
the check to add 1 extra mode count otherwise it leads to null
pointer dereference while getting lm for this extra mode. Also
avoid overriding mode capability when POMS is enabled.
Change-Id: I73f3b89b22f566e40c88178f2af392214b1ada8d
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In POMS use case while disabling the virtual encoder, the virt
reset function sets the current master to null. concurrently, if
there is a query from the DRM client for the current vsync count,
it returns a zero value. This results in the blocking of the
drm_crtc_funcs.disable_vblank function. since the vsync count
has been relocated to the virtual encoder, remove the physical
encoder structure.
Change-Id: Ie692df657b5a86b6b8915a15e9a070642243fcfb
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In POMS use case, the handling of the wait for vsync event
completion coincides with the concurrent
drm_crtc_funcs.enable_vblank. This concurrency causes a vsync
event complete timeout while disabling the encoder. to fix this
concurrency problem, increment the vblank refcount in encoder
disable and release the vblank refcount in encoder enable.
Change-Id: I79671e4a2bafdd01a6b2523a80fe511bff23d6b6
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In CWB use case along with suspend commit, the function
drm_crtc_funcs.get_vblank_counter returns a zero vsync count
value. This causes blocking of drm_crtc_funcs.disable_vblank,
leading to a wait for vsync timeout while disabling the encoder.
hence clear a cwb encoder mask in encoder disable and set it
while performing mode set.
Change-Id: Ic994aa0a86faf48e2b25955cf6fe12166fe9d328
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Introduce vsync count variable in virtual encoder structure
to keep the vsync count variable value in sync while performing
the poms. Consequently, this prevents the blocking of
drm_vblank_put and the invocation of
drm_crtc_funcs.disable_vblank.
Change-Id: I74903a89b17a8f46fb1b21338500553f36771dd0
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Attach lt9611uxc bridge to DSI connector once drm connector and
encoder is initialized and attached.
Change-Id: I144938bc06b28a0b440b86318f45f18476182b3a
Signed-off-by: Shubham Talekar <quic_stalekar@quicinc.com>
Currently revalidation of features happening for mode change(like
fps change, resolution change). This change limits revalidation
of feature only to resolution switch.
Change-Id: I3678e0e94eaad51e7b7a342eb451aa6329e8279d
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
In lower fps the scheduled off_work for idle pc race with
crtc_commit thread causing janks in display. This change
updates the time required to enter idle_pc based on frame
rate instead of default time. It also sets max and min bound
for optimized performance.
Change-Id: I514015361d6773156971dcc5801ed4b75d78db86
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
During PM suspend in dual display usecase, the power off commit to
turn off primary and secondary crtcs is done with only one
drm_atomic_state scheduled on primary crtc_commit thread. At the
same, touch events can happen on secondary panel, which will
run input_event_work and schedule the sde_enc->delayed_off_work
to turn off its enabled resources. There can be race between primary
crtc_commit thread which unregisters input_event, cancels
all the pending works before setting sde_enc->cur_master to NULL
and input_event_work_handler which schedules the delayed_off_work
without checking the input_event_handler state.
This change adds input handler unregister check before triggering
_sde_encoder_rc_early_wakeup.
Change-Id: If6de3d45ccda5d0b84065a1a76964c1ab00eeaa1
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Testing of the SPR feature shows IPC restore frames where partial update
programming is not applied. This is a result of the pre-IPC cached ROI
region being used for filtering of CRTC ROI changes.
Update the CRTC cached ROI logic to clear the cached ROI on IPC events.
This ensures color processing partial update logic handles the post IPC
frame with a clean state.
Change-Id: I4e337bd150d02e4c8934ca04c0d632d5ad71dd5d
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
When there is CPU processing delay between first INTR clear and
second INTR clear there is a chance that the second register
write might clear the next frames interrupts which will avoid
triggering the irq callbacks causing software hung. This
patch avoids such a scenario by removing such double clearing
of INTR registers.
Change-Id: I8407991769c69d2d2c691763240671d5f3c0416d
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
DPU driver registers core clock with MMRM driver for clock
mitigation policy. In the event that MMRM driver is not enabled
then mark dpu driver clock as non MMRM type.
Change-Id: Id4dd4a512c81ba54514171867852531f00604a66
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
