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@@ -10,45 +10,45 @@
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#include "sde_kms.h"
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#include "sde_reg_dma.h"
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-#define CTL_LAYER(lm) \
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+#define CTL_LAYER(lm) \
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(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
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-#define CTL_LAYER_EXT(lm) \
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+#define CTL_LAYER_EXT(lm) \
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(0x40 + (((lm) - LM_0) * 0x004))
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-#define CTL_LAYER_EXT2(lm) \
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+#define CTL_LAYER_EXT2(lm) \
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(0x70 + (((lm) - LM_0) * 0x004))
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-#define CTL_LAYER_EXT3(lm) \
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+#define CTL_LAYER_EXT3(lm) \
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(0xA0 + (((lm) - LM_0) * 0x004))
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-#define CTL_TOP 0x014
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-#define CTL_FLUSH 0x018
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-#define CTL_START 0x01C
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-#define CTL_PREPARE 0x0d0
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-#define CTL_SW_RESET 0x030
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-#define CTL_SW_RESET_OVERRIDE 0x060
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-#define CTL_STATUS 0x064
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-#define CTL_LAYER_EXTN_OFFSET 0x40
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-#define CTL_ROT_TOP 0x0C0
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-#define CTL_ROT_FLUSH 0x0C4
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-#define CTL_ROT_START 0x0CC
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-
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-#define CTL_MERGE_3D_ACTIVE 0x0E4
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-#define CTL_DSC_ACTIVE 0x0E8
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-#define CTL_WB_ACTIVE 0x0EC
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-#define CTL_CWB_ACTIVE 0x0F0
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-#define CTL_INTF_ACTIVE 0x0F4
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-#define CTL_CDM_ACTIVE 0x0F8
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-#define CTL_FETCH_PIPE_ACTIVE 0x0FC
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-
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-#define CTL_MERGE_3D_FLUSH 0x100
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-#define CTL_DSC_FLUSH 0x104
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-#define CTL_WB_FLUSH 0x108
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-#define CTL_CWB_FLUSH 0x10C
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-#define CTL_INTF_FLUSH 0x110
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-#define CTL_CDM_FLUSH 0x114
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-#define CTL_PERIPH_FLUSH 0x128
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-#define CTL_DSPP_0_FLUSH 0x13c
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-
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-#define CTL_INTF_MASTER 0x134
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-#define CTL_UIDLE_ACTIVE 0x138
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+#define CTL_TOP 0x014
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+#define CTL_FLUSH 0x018
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+#define CTL_START 0x01C
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+#define CTL_PREPARE 0x0d0
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+#define CTL_SW_RESET 0x030
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+#define CTL_SW_RESET_OVERRIDE 0x060
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+#define CTL_STATUS 0x064
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+#define CTL_LAYER_EXTN_OFFSET 0x40
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+#define CTL_ROT_TOP 0x0C0
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+#define CTL_ROT_FLUSH 0x0C4
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+#define CTL_ROT_START 0x0CC
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+
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+#define CTL_MERGE_3D_ACTIVE 0x0E4
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+#define CTL_DSC_ACTIVE 0x0E8
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+#define CTL_WB_ACTIVE 0x0EC
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+#define CTL_CWB_ACTIVE 0x0F0
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+#define CTL_INTF_ACTIVE 0x0F4
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+#define CTL_CDM_ACTIVE 0x0F8
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+#define CTL_FETCH_PIPE_ACTIVE 0x0FC
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+
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+#define CTL_MERGE_3D_FLUSH 0x100
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+#define CTL_DSC_FLUSH 0x104
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+#define CTL_WB_FLUSH 0x108
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+#define CTL_CWB_FLUSH 0x10C
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+#define CTL_INTF_FLUSH 0x110
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+#define CTL_CDM_FLUSH 0x114
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+#define CTL_PERIPH_FLUSH 0x128
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+#define CTL_DSPP_0_FLUSH 0x13c
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+
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+#define CTL_INTF_MASTER 0x134
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+#define CTL_UIDLE_ACTIVE 0x138
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#define CTL_MIXER_BORDER_OUT BIT(24)
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#define CTL_FLUSH_MASK_ROT BIT(27)
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@@ -213,14 +213,14 @@ sspp_reg_cfg_tbl[SSPP_MAX][CTL_SSPP_MAX_RECTS] = {
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/**
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* Individual flush bit in CTL_FLUSH
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*/
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-#define WB_IDX 16
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-#define DSC_IDX 22
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-#define MERGE_3D_IDX 23
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-#define CDM_IDX 26
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-#define CWB_IDX 28
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-#define DSPP_IDX 29
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-#define PERIPH_IDX 30
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-#define INTF_IDX 31
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+#define WB_IDX 16
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+#define DSC_IDX 22
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+#define MERGE_3D_IDX 23
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+#define CDM_IDX 26
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+#define CWB_IDX 28
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+#define DSPP_IDX 29
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+#define PERIPH_IDX 30
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+#define INTF_IDX 31
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static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl,
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struct sde_mdss_cfg *m,
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