Update sample interval for class-H port to 64 so that the
class-H code is sent to WCD correctly over soundwire bus.
Change-Id: I60f134a962b1204f380ea6017468ff00521f708b
SWRM_DIN_DP_* registers are based on incorrect register values.
Update to match correct hardware addresses.
Also fix tabs/spaces mismatch in same file.
Fix CPS offset1 port parameter to be 0 instead of 0xff.
Change-Id: I641a925f1f3b454a6af0d2491d86459131bba2cf
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Update settings to match how swr_mstr_ctrl driver is using the
SWR settings to set the registers. Previously, an offset1 of
0xFF would write 0xFF to the register instead of skipping it, unlike
other swr settings. This is similarly true for SWR Slave setting
for bp_mode.
Change-Id: I3c5b2635c5a88a52639cbac9455a544d5cfee154
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Update HSTOP from 0 to 8 to match configuration.
Also fix slave ch en from 2 ch to 1 ch.
This fix resolves port collision/bus clash issues.
Change-Id: I91c6fe80a9db88d029e4ef81c7a06480a767b170
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Change wsa Word length param to be - 1.
Also, any value that is 0 should be set to 0xFF.
This causes the swr mstr driver to ignore the write
(default value).
Change-Id: I9bacb6657284c02cc023be655011b321a08ef3a9
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
Add PBR, CPS port types and port parameters for WSA
Update RX and TX port types to include full list of ports
Change-Id: I5b69ee777addebcf4167dccd4ce4ab0af31b754d
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
