asoc: codecs: Fix WSA Offset1, BP Mode SWR config

Update settings to match how swr_mstr_ctrl driver is using the
SWR settings to set the registers. Previously, an offset1 of
0xFF would write 0xFF to the register instead of skipping it, unlike
other swr settings. This is similarly true for SWR Slave setting
for bp_mode.

Change-Id: I3c5b2635c5a88a52639cbac9455a544d5cfee154
Signed-off-by: Matthew Rice <[email protected]>

asoc/kalama-port-config.h

@@ -17,36 +17,35 @@
  */
 
 static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
-	{7,    1,    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
-	{31,   3,    7,    0xFF, 0xFF, 0xFF, 1,    0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
-	{63,   5,    31,   0xFF, 0xFF, 0xFF, 1,    0xFF, 0xFF, 0x00, 0x00}, /* SB1 */
-	{7,    2,    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR2 */
-	{31,   4,    7,    0xFF, 0xFF, 0xFF, 1,    0xFF, 0xFF, 0x00, 0x00}, /* CMP2 */
-	{63,   21,   31,   0xFF, 0xFF, 0xFF, 1,    0xFF, 0xFF, 0x00, 0x00}, /* SB2 */
-	{399,  0xFF, 0xFF, 8,    8,    8,    0xFF, 0xFF, 0xFF, 0x00, 0x01}, /* PBR */
-	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
-	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
-	{15,   6,    0xFF, 0xFF, 15,   0xFF, 1,    0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
-	{15,   13,   0xFF, 0xFF, 15,   0xFF, 1,    0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
-	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
-	{799,  0xFF, 0xFF, 15,   15,   24,   0xFF, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
-
+	{7,    1,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
+	{31,   3,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
+	{63,   5,    31,   0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB1 */
+	{7,    2,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR2 */
+	{31,   4,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP2 */
+	{63,   21,   31,   0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB2 */
+	{399,  0,    0xFF, 8,    8,    8,    0, 0xFF, 0xFF, 0x00, 0x01}, /* PBR */
+	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
+	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
+	{15,   6,    0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
+	{15,   13,   0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
+	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
+	{799,  0xFF, 0xFF, 15,   15,   24,   0, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
 };
 
 static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
-	{3,    1,    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
-	{31,   3,    7,    0xFF, 0xFF, 0xFF, 1,    0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
-	{63,   5,    31,   0xFF, 0xFF, 0xFF, 1,    0xFF, 0xFF, 0x00, 0x00}, /* SB1 */
-	{3,    2,    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR2 */
-	{31,   4,    7,    0xFF, 0xFF, 0xFF, 1,    0xFF, 0xFF, 0x00, 0x00}, /* CMP2 */
-	{63,   21,   31,   0xFF, 0xFF, 0xFF, 1,    0xFF, 0xFF, 0x00, 0x00}, /* SB2 */
-	{399,  0xFF, 0xFF, 8,    0xFF, 8,    0xFF, 0xFF, 0xFF, 0x00, 0x01}, /* PBR */
-	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
-	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
-	{15,   6,    0xFF, 0xFF, 15,   0xFF, 1,    0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
-	{15,   13,   0xFF, 0xFF, 15,   0xFF, 1,    0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
-	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
-	{799,  0xFF, 0xFF, 15,   15,   24,   0xFF, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
+	{3,    1,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
+	{31,   3,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
+	{63,   5,    31,   0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB1 */
+	{3,    2,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR2 */
+	{31,   4,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP2 */
+	{63,   21,   31,   0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB2 */
+	{399,  0xFF, 0xFF, 8,    8,    8,    0, 0xFF, 0xFF, 0x00, 0x01}, /* PBR */
+	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
+	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
+	{15,   6,    0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
+	{15,   13,   0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
+	{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
+	{799,  0xFF, 0xFF, 15,   15,   24,   0, 0xFF, 0xFF, 0x01, 0x01}, /* CPS */
 };
 
 static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {

soc/swr-mstr-ctrl.c

@@ -1519,11 +1519,13 @@ static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
 						SWRS_DP_SAMPLE_CONTROL_2_BANK(slv_id,
 									bank));
 			}
-			reg[len] = SWRM_CMD_FIFO_WR_CMD(swrm->ee_val);
-			val[len++] = SWR_REG_VAL_PACK(port_req->offset1,
-					port_req->dev_num, get_cmd_id(swrm),
-					SWRS_DP_OFFSET_CONTROL_1_BANK(slv_id,
-								bank));
+			if (port_req->offset1 != SWR_INVALID_PARAM) {
+				reg[len] = SWRM_CMD_FIFO_WR_CMD(swrm->ee_val);
+				val[len++] = SWR_REG_VAL_PACK(port_req->offset1,
+						port_req->dev_num, get_cmd_id(swrm),
+						SWRS_DP_OFFSET_CONTROL_1_BANK(slv_id,
+									bank));
+			}
 
 			if (port_req->offset2 != SWR_INVALID_PARAM) {
 				reg[len] = SWRM_CMD_FIFO_WR_CMD(swrm->ee_val);