The kernel-doc script identified some documentation issues in the
hal/wifi3.0/qca6490 folder, so fix them.
Change-Id: If86930db21f7961acc067da4751641c749cadc48
CRs-Fixed: 3410723
For 802.11 Fragmented frames, currently there is a
generic GetFrameControl API from RX TLV for all Li
Chipsets. As the offset for frame control in RX TLV
is different for QCN9000 and QCA8074V2, reading the
frame control with generic API gives wrong frame
control value. The Offset is different as the size
of RX_MSDU_START struct is 8DWORDS in QCA8074v2 while
it is 9DWORDS in QCA9000. In the reo reinject path
the destination queue descriptor address read from ring
descriptor address is Invalid
Fix is Separating out the GetFrameControl API from
generic API to Chip specific API. Also fix the reading
of queue descriptor address.
CRs-Fixed: 3280809
change-Id: Ifc5eca31b9b7e70c84ca455d56a58c27601cd51d
In QCN9224 fetch the peer meta data from the msdu end tlv
instead of MPDU start
Change-Id: Icd9420cd83e06abe5e54e9e05cc8cbf8d8312ae1
CRs-Fixed: 3245626
Skb under panic issue is seen when a packet comes via RX err path,
MSDU length read by SW is coming as 0 and leaving no space for skb_push
in buffer, data is moving beyond the head and causing the issue.
MSDU length is read by generic API which is architecture-independent,
hence the struct size for one architecture is different from another
architecture.
FIX is to get the MSDU length by architecture-specific API.
Change-Id: I5a6259034e5e06ae9ce7ba6b135b44f2849f2fd9
CRs-Fixed: 3235636
In some cases we need to classify frames accordinging
to l3 type. This change mainly focus on this issue.
Change-Id: I4bc49a808a02b4bc8c65f920690922045d65e739
CRs-Fixed: 3198481
Currently in some case we are receiving non error packets on REO2TCL
ring, which is causing issue.
Fix is to set DEST_RING_MAPPING_0 to SW1 for REO dest ctrl
register, So that non error packets with reo_destination_indication
with 0x0 in the reo entrance ring will be routed to SW1 ring.
Change-Id: I67f78f35e7dba899943307902d99d0325a60498f
CRs-Fixed: 3150186
Add feature support to tag first packet that wakes up HOST from WoW.
rx_pkt_tlv.rx_msdu_end.reserved_1a field is used by TARGET to meet
such request.
Change-Id: I3d37e13e8cff49bc4f622d3070a19e4c4be56417
CRs-Fixed: 3137621
PHY related info. has been updated when processing PPDU status
in Monitor mode, but it's got overwritten uncorrectly when
processing RX_MSDU_START TLV in VHT mode. Change aims bypassing
the wrong update, when it's working in VHT mode.
Change-Id: I2c78db66bc7222e3eebf052fb6e57d6f9d859286
CRs-Fixed: 3108059
In WBM error processing read peer_id from peer_meta_data
instead of sw_peer_id.
This changes is needed because we need to process Rx packet
on ML peer. But in MLO case sw_peer_id field contains
link_peer_id where as peer_meta_data has ml_peer_id.
Change-Id: I3f469adfdf7efa88cb081e94fa9fe0c54c1fb078
The maximum WBM2SW rings in whunt for HSP is 5 and
the same could be 4 in wlan code which will result
in wcov failure for HSP. Use a maximum of 5 WBM2SW
rings for HSP based on FW_SIM config flag to address
this failure.
Change-Id: I8340cd094eb1e0cf842894e5c89174d410729028
CRs-Fixed: 3071662
Repurpose the IPA tx and tx completions rings for
normal use when IPA is disabled either via config
flag or ini.
Change-Id: Ia4b6a89c73d888a217bdef40e3c05435c3bb1bb2
CRs-Fixed: 3059730
Add fisa deletion support by invalidating the fisa
DDR entry when adding a new entry.
Change-Id: I02189e22e09ca0ef5e1fdb5952c7e72cd87d3673
CRs-Fixed: 2954060
HAL generic APIs which use HW definitons that
do not have same value across all lithium chipset
are moved to header files. So that these will be
compiled with appropriate header files
Change-Id: I6c167afa4212c5e884f5e18ff1ccb3bbbba8f5f5
Currently the hardware srng register offset is statically
assigned to the handle. This can lead to incorrect index access
when targets (eg: wcn7850) is added which require additional
register offsets to be stored in the hw srng register offset table.
Move to the index based assignment of the srng register offset.
Change-Id: I8e38bdd0c28068029a0267fce706edf4378b9df8
CRs-Fixed: 2965081
Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.
This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).
Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
To support IPA TX two pipes, WBM2SW4 is added as second WBM2IPA TX
transfer ring.
Change-Id: Id0762003c1d91e3614b15df2bc51f90e27add43c
CRs-Fixed: 2750073
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.
Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.
Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
Change hal_hw_txrx_ops struct to designated initializer syntax for
structs for 6490.
Change-Id: Icd72cd5e20f1ba88920f4a2bc8e1bc714959e9b7
CRs-Fixed: 2837917
Due to recent FW changes not filtering out BAR frames, redirect these
frames to REO exception ring and handle as normal data packets.
Change-Id: I4540929fddab14de57a23f6364fc916a70057cbe
CRs-Fixed: 2795499
If frames from the same FISA flow goes into different REO2SW rings, it
will result in an unexpected FISA behavior. This can happen if the
frames have been reinjected from FW offload module since FW will select
REO2SW1 ring. If the same flow frames hash to other REO2SW rings, then
the same flow UDP frames will do to different rings.
Reo_destination_indication of 6 indicates if the frame has been
reinjected from FW. If so, then continue to deliver the packet without
FISA.
Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70
CRs-Fixed: 2790292
Make sure to drop the raw Rx frames as both driver and stack
are not expected to handle them.
Add counter for invalid fisa flow_idx packet received.
Change-Id: I5107c554b8ce6a9a7973f2aeca44bb0f360dc2df
CRs-Fixed: 2733981
Rxdma decrypt errors are observed when the association
is in progress as AP sends encrypted data packets to
DUT-STA. As part of the rxdma error handling, excessive
prints are logged to console resulting in an assert.
Fix is to rate limit rxdma decrypt error related log
Change-Id: I2ef28c635d77e3acafd067b921cdb13c277756c7
CRs-Fixed: 2725335
Due to changes in datapath init/deinit path, mon_lock spinlock was not
getting created. Create mon_lock spinlock during
dp_rx_pdev_mon_cmn_desc_pool_init.
Add null check to validate rx_tlv_header before calling
hal_rx_mpdu_start_tlv_tag_valid.
Change-Id: I41c781de29f2c8c05ec1bfa90f9c8f742f2539bf
CRs-Fixed: 2693687
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers. Add
this change for HSP.
Change-Id: If3060271cf2923171487d30f99f2ab5c55370601
CRs-Fixed: 2634766
In HSP platform, ring index 0 is for spectral scan, and ring idex 1 is
for CFR capture. Extend max rings to 2 and support CFR capture.
Change-Id: I02b39dd626b67172123bc5e77173d50a132fc735
CRs-Fixed: 2634636
Add HAL layer changes for full monitor mode.
Define HAL API and Data structures to read sw_monitor_ring
descriptor.
CRs-Fixed: 2630982
Change-Id: I015fa106d9da74222bef092d50e96fc70a117a4a
For qcn9000, As part HW enhancements, PPDU_ID is sent
in reo_entrance_ring descriptor instead of RX_MPDU_START
tlv. Add support to read ppdu id from descriptor.
Modify existing hal API hal_rx_hw_desc_get_ppduid_get ()
arguments to pass RxDMA ring HW descriptor.
Usage:
a. Use hal_rx_hw_desc_get_ppduid_get () -
to get ppdu id from rx_tlv_hdr or hw descriptor based on target.
for qcn9000, this API gets ppdu_id from HW descriptor,
for other platforms, gets ppdu_id from rx_tv_hdr
b. Use hal_rx_get_ppdu_id () - to get ppdu_id from rx_tlv_hdr
Change-Id: I5838227c12cde50cbb2a9da7a0d8056b8b9b7ef5
Move HAL_RX_MSDU_END_DA_IDX_GET macros to chip specific header file.
Fixing compilation failure for 6490 and 6750.
hal_rx_msdu_packet_metadata_get_generic need not be chip specific,
macros defining the function are already chip specific.
Change-Id: I940a289662bdeddfbf99fae2a80d7796334832e7
CRs-Fixed: 2595314
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
the current HAL API is to read the WBM internal error
bit from the wbm release ring descriptor is always taking
HKv1 HW structure. But the wbm_internal_error bit
placement has changed from HKv2, for this reason we have
to use target specific HAL API.
Change-Id: I44789180754ca21ae59650b6d8620321a1f12569
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers.
Change-Id: I3662b60375cb8886447a2fba3efead6a1ef3a98d
CRs-Fixed: 2593408
Write into hal register using three floating windows instead of one.
This change is done to avoid frequent window changes for writing into
DP and CE registers. Instead 3 windows are used. One window is statically
mapped to CE block and another window is mapped statically to DP block.
Due to this design there is no need to change the window register to
write into these blocks and write can be done on corresponding window
with single iowrite32. Similar loginc is used for ioread32.
Also modified the hp_addr and tp_addr in initialisation stage so that
hal_write will not have multiple if checks.
Change-Id: Ibb99ec4da7f63323082e46a28afbe90e1f555545
CRs-fixed: 2507441
Add hal_rx_get_rx_sequence API to retrieve
rx sequence value based on the chipset.
Change-Id: I8377b96dfe04e9695a183482d9fcc4a804f845e0
CRs-Fixed: 2522133
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Implement hal_rx_tlv_get_tcp_chksum API
to retrieve tcp_udp_checksum value
based on the chipset.
Change-Id: Ifab970f10af06f8c0cdbd14d57cb66b49bae1648
CRs-Fixed: 2522133
Implement hal_rx_msdu_get_flow_params API
per chipset as the macro
to retrieve the flow parameters is
chipset dependent.
Change-Id: I6ef83232ebdf7497871a7fc588e082d14cdc9e75
CRs-Fixed: 2522133
Implement hal_rx_msdu_cce_metadata API per
chipset as the macro to retrieve the cce_metadata
value is chipset dependent.
Change-Id: Icd87d4ac32be78d69b24da106381a7669c86ada6
CRs-Fixed: 2522133
Implement hal_rx_msdu_fse_metadata API per
chipset as the macro to retrieve the fse_metadata
value is chipset dependent.
Change-Id: Iae7f532460b5203af2f95c504a6941c0b18b665e
CRs-Fixed: 2522133
