Граф коммитов

93 Коммитов

Автор SHA1 Сообщение Дата
Pavan Kumar M
0736e5599e msm: ipa3: End point configuration changes for IPA-V5.2
Added end point, resource config, GSI configuration and
SRAM entries for IPAv-5.2

Enabling IPA, GSI driver compilation as vendor DLKM
modules for pitti target.

Change-Id: Ib0ae6d6605f11a2b08c63782f8a11d8011d46bbe
Signed-off-by: Pavan Kumar M <quic_rpavan@quicinc.com>
2024-01-18 13:47:03 +05:30
Chaitanya Pratapa
e294f01cfe msm: ipa: make changes to avoid allocating userdata for WDI channels
WDI channels do not require userdata. Avoid allocating userdata for new
WDI protocols as otherwise allocations might fail due to large allocation
size resulting in pipe setup failure.

Change-Id: I7630a9c5b450937b264cdeb4b45ace70fd160be3
Signed-off-by: Chaitanya Pratapa <quic_cpratapa@quicinc.com>
2023-04-19 12:43:46 -07:00
Abhishek Raghuvanshi
46bc1041ae msm: ipa: fix to tx stop channel
When opt dpath is enabled, make changes to stop and start the
channel only when it is required.

Change-Id: I849ccbe969a6c965b18022f3c23e545902d551e2
Signed-off-by: Chaitanya Pratapa <quic_cpratapa@quicinc.com>
2023-04-13 22:12:01 +05:30
Michael Adisumarta
79759098f5 dataipa: avoid accessing NULL pointer
Fix accessing NULL pointer.

Change-Id: Ifef1b81a948e7d28336392ae286802da06574b15
Signed-off-by: Michael Adisumarta <quic_madisuma@quicinc.com>
2023-01-31 14:35:04 -08:00
Michael Adisumarta
2391721863 msm: ipa: enable ipa driver for pineapple
Make changes to enable IPA driver for pineapple. Fixed
compilation errors related to kernel upgrade.

Change-Id: Iecbe152fe0b6860616a9a63504d57b92a70ef72e
Signed-off-by: Michael Adisumarta <quic_madisuma@quicinc.com>
2022-11-14 16:49:29 -08:00
Raghavendar rao l
8a624916bf msm: ipa3: Add support for hamilton chip for pinnacles
Addded change to enable support for hamilton chipset as part of
pinnacles.

Change-Id: Ie8f58c1b385780e778b80f7581c81e2f1a7b6b44
Signed-off-by: Raghavendar rao l <quic_rlomte@quicinc.com>
2022-10-27 12:03:42 +05:30
Michael Adisumarta
dec6be012b dataipa: Rate limiting some IPA errors.
Rate limiting GSI and IPA errors.

Change-Id: I0b1dc675685e9f1ddefd3bdf928b22e4c130c2ca
Signed-off-by: Michael Adisumarta <quic_madisuma@quicinc.com
2022-10-13 11:56:17 -07:00
Dor Deri
9a8ec9379d ipa: updates for ipa_reg_save()
* update number of channels to collect in reg_save
* enable collection for uC channels
* parse gsi fw version

Change-Id: Iae5bd9e56b076717e7a157b0883b1efb7681c061
Signed-off-by: Dor Deri <quic_dderi@quicinc.com>
2022-08-18 14:43:23 +03:00
qctecmdr
6ac7530788 Merge "msm: ipa3: Adding support to save ipc logs in minidump" 2022-05-05 12:43:58 -07:00
Ashok Vuyyuru
33ed3c00f9 msm: ipa3: Adding support to save ipc logs in minidump
Adding support to save ipa/gsi ipc logs in minidump.

Change-Id: Ic83b173140aae5c985a497f7333596c540b094ff
Signed-off-by: Ashok Vuyyuru <quic_avuyyuru@quicinc.com>
2022-05-05 00:25:18 -07:00
Ashok Vuyyuru
7318b0ef5a msm: ipa3: Initial version of minidump support in IPA
Initial version of minidump support in IPA driver.

Change-Id: I73e98fd647dd487dda90049f5b0c5609f558aa92
Signed-off-by: Ashok Vuyyuru <quic_avuyyuru@quicinc.com>
2022-05-02 14:23:49 +05:30
qctecmdr
0c91e443eb Merge "msm: gsi: Fix the incorrect evt ring pointer" 2022-04-22 19:44:33 -07:00
qctecmdr
94587d3399 Merge "msm: gsi: Read 64-bit ring RP value from registers" 2022-04-22 19:09:02 -07:00
Chaitanya Pratapa
ee9eb5478a msm: ipa Add traces for latency measurement
Add traces for latency measurements
Add traces in ipa3_replenish_rx_page_recycle,
handle_page_completion, new qtimer trace to GSI IRQ.

Change-Id: Ie2f9bf5d61a23abded2bced86fd5e172e60cac8d
Acked-by: Abhishek Raghuvanshi <araghuva@qti.qualcomm.com>
Signed-off-by: Chaitanya Pratapa <quic_cpratapa@quicinc.com>
Signed-off-by: Jennifer Zenner <quic_jzenner@quicinc.com>
2022-04-12 22:30:57 -07:00
Ashok Vuyyuru
49899d14a2 msm: ipa3: Deepsleep enable changes
Adding support to deepsleep scenario.

Change-Id: I2b388396cf9a7f26f77bbcd49c1014e16475a980
2022-04-05 00:29:54 -07:00
Cheng Zeng
4c160e8d20 msm: gsi: Read 64-bit ring RP value from registers
The DMA address allocated may be in 64-bit address
range if dma mask is set to 64-bit, the MSB register
value is required.

Signed-off-by: Cheng Zeng <quic_chenzeng@quicinc.com>

Change-Id: Ie091b01ac44e70d450a8d050855b5f3f0f510695
2022-03-31 14:09:51 +08:00
Cheng Zeng
d382527383 msm: gsi: Fix the incorrect evt ring pointer
The pointer should be event ring pointer, not transfer
ring pointer, it has chance to get wrong upper 32 bits
when smmu is disabled.

Signed-off-by: Cheng Zeng <quic_chenzeng@quicinc.com>

Change-Id: I8aa0d102d81fb2632ce988fcc8d816e7fed7b5b1
2022-03-31 12:45:18 +08:00
Dor Deri
602f431d59 ipa: upgrade reg save to IPAv5.5
Add support for IPAv5.5 reg collection.

Change-Id: Id4c92d7120fff6e96e635c92369af7a3de0f2fc0
Signed-off-by: Dor Deri <quic_dderi@quicinc.com>
2022-01-31 00:44:21 -08:00
Chaitanya Pratapa
ba2f797e99 msm: gsi: GSI 5.5 updates
GSI version 5.5 updates.

Change-Id: Ib0949a64a5867c01ea5993c71c98392e9f6e3434
Signed-off-by: Chaitanya Pratapa <quic_cpratapa@quicinc.com>
(cherry picked from commit c117332d9db5f2c82158921f9380e314555cb247)
2021-12-01 22:45:34 -08:00
Ilia Lin
6cf42d86a8 msm: ipa: Add debugfs support for Dual NIC
Retrieves debugfs data for both ethernet clients in case of Dual NIC mode.

Change-Id: I62eb6af1dedaa738674979520d393c753c0f0190
Acked-by: Eliad Ben Yishay <ebenyish@qti.qualcomm.com>
Signed-off-by: Ilia Lin <quic_ilial@quicinc.com>
2021-10-31 00:31:01 -07:00
Pooja Kumari
ec747710eb msm: ipa: Add sa410m to dataipa MAKEFILE
Compile IPA driver in sa410m.

Change-Id: I18efc61e54632590a31dfb4f7e9e11e286cf7529
Signed-off-by: Pooja Kumari <quic_kumarip@quicinc.com>
2021-10-28 03:32:28 -07:00
Michael Adisumarta
db86553f4e msm: gsi: add support for 2 new MSI interrupts
Add support for 2 new seperate MSI interrupts
to pin rmnet_ll and rmnet_ctl processing to seperate
CPUs.

Change-Id: I83977081a72d734622525732a97f8563fb530ade
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-10-13 18:57:56 -07:00
Michael Adisumarta
7f721b5ebb msm: ipa: adding debug prints for flow control enable/disable
Adding debug and register prints for flow control enable or disable.

Change-Id: Id6a79880340cc3e7503da6add3ce9aaf9d0a991d
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-09-27 12:03:59 -07:00
Ashok Vuyyuru
0c2788282c msm: ipa3: Adding changes to read the return code if IRQ not received
In some cases GP_INT1 interrupt not receiving even GSI FW send the
interrupt. In those cases cases reading the flow control command return
code to check completion.

Change-Id: I329550ab94af9caac870c6050761d3701f0517cd
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-09-23 22:37:05 +05:30
qctecmdr
d1f804e2ac Merge "msm: ipa3: Changes to remove the CNTXT_SCRATCH_1 config" 2021-08-03 17:33:42 -07:00
Ashok Vuyyuru
3d2bf967c0 msm: ipa3: Changes to remove the CNTXT_SCRATCH_1 config
Context scratch 1 register configuration not required, So removing
these changes.

Change-Id: Ic72fc128fc6468e5844d10d9321a85a85c4ed60c
2021-08-03 00:01:19 +05:30
Michael Adisumarta
8e3953ea4e msm: ipa5: ipa_stats support for ipa_lnx_agent
Includes support for IPA stats to be able to send log packet
to ipa_lnx_agent and then to SPEARHEAD framework.

Change-Id: I3112fc6b2e66e15140f638bfff9905bba6997e46
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-07-20 13:44:23 -07:00
qctecmdr
76f2b86821 Merge "msm: gsi: Add debug code for Flow Control" 2021-05-20 18:08:58 -07:00
Sivan Reinstein
5b713d37b0 msm: gsi: Add debug code for Flow Control
Increase timeout while waiting for FC command to complete.
For enable FC command wait longer in case PENDING bit is set.

Change-Id: I6d4443b1688d2ae426079638216829a4ddb30d94
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-05-20 09:14:08 +03:00
qctecmdr
089976fc29 Merge "msm: ipa3: Changes to read the halt command return code after some delay" 2021-05-14 00:52:38 -07:00
Ashok Vuyyuru
797b181281 msm: ipa3: Changes to read the halt command return code after some delay
In some cases for updating the return code in SCRATCH register taking
time after raising the global interrupt. Adding changes to wait for
some time read the SCRATCH register again and also printing the
test bus registers and Q6 channel state in failed scenario.

Change-Id: I4112a2290739daa79629f718d9725258518aba4c
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-05-13 11:59:29 +05:30
Sivan Reinstein
2a9bd8f3af msm: ipa: Clear IEOB for stopped channels with MSI IRQ
Clear IEOBs as part of CH stop for channels with MSI IRQ type

Change-Id: I7b9af7f385b0876fc2f43314bd3588110911a021
Acked-by: Nadav Levintov <nadav@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-05-11 22:51:29 -07:00
Michael Adisumarta
91efd29ef8 msm: ipa3: new low latency data pipes support
Includes low latency data pipe definition and
support for waipio.

Change-Id: I0158eb15b38de0dfd2b0052b699c69a7c7f58fa1
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-05-10 17:21:49 -07:00
qctecmdr
aeea2f09f3 Merge "msm: ipa3: Adding chnages to update event RP from DDR" 2021-05-10 08:58:37 -07:00
Ashok Vuyyuru
9ea98412c7 msm: ipa3: Adding chnages to update event RP from DDR
In suspend scenario while checking channel empty scenario
updating the event ring RP pointer from direct register, it
may cause mismatch in reading in polling context. To avoid
discrepancy  reading RP pointer DDR location.

Change-Id: Ie198ea9ace033e31463acd974f10dccdcac45c55
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-05-06 22:50:16 +05:30
qctecmdr
5e63fdb447 Merge "msm: ipa: Enable GSI Channel almost empty Feature" 2021-05-05 15:11:15 -07:00
qctecmdr
e7414c97c6 Merge "msm: ipa: add unit tests for NTN3 offload" 2021-05-04 19:03:59 -07:00
Bojun Pan
5ad90dcb6e msm: ipa: Enable GSI Channel almost empty Feature
Enable GSI Channel almost empty Feature for MHI DL channel.

Change-Id: I9e27044f30bf61b91c0dcd7b7f109404b303bb62
2021-04-29 18:33:35 -07:00
Sivan Reinstein
d1dfec34da msm: gsi: add gsi profiling stats and fw version to debugfs
Add GSI profiling stats data and the GSI FW version to debug fs.

Change-Id: I5749339f5ec9656e636a512668025bb09a97a3ec
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-04-29 09:39:20 +03:00
Amir Levy
4d4a72f1da msm: ipa: Add NTN3 debug stats support
Add debugfs support for NTN3 stats.
Collect stats from uC add print from debugfs.

Change-Id: Iaf31beedb7403ee924a170f3b6c45ce0b78b7680
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-04-11 10:44:56 +03:00
Amir Levy
9115a93389 msm: ipa: add NTN3 offload support
Add NTN3 gsi scratch and protocol.
Add NTN3 support in ipa_eth.

Change-Id: I7dde0f21711617770ea31e325db803108d929565
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-04-11 10:44:56 +03:00
Chaitanya Pratapa
407bf99e8f msm: ipa: Fix TX NAPI handling
Make changes to ensure NAPI is scheduled only once.
Make changes to use right register
GSI_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_k for clearing interrupt.

Change-Id: I8de97f584ac4915d59b6716e7dff0c181a48cd1e
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-04-09 15:40:50 -07:00
Ashok Vuyyuru
9aeec4c5b7 msm: ipa3: Check channel in right state before access base address
Observing use after free issue during teardown WAN pipe if we
receive the incoming packet. Adding check channel in right state
before access base address.

Change-Id: I29a611693b78637811fe45abea93d9ed3e6f54e5
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-03-15 09:32:02 -07:00
Bojun Pan
05f6b458cf msm: ipa: fix the polling state on GSI
Adding the missing change to update the polling state.

Change-Id: Icfd26c17b91cfe62b67a44c27727fff1f14b6943
2021-03-11 09:41:28 -08:00
qctecmdr
7038889f3f Merge "msm: ipa3: Changes to decrease the num_of_chan_allocated count" 2021-03-10 08:44:43 -08:00
Praveen Kurapati
4ab3b7d997 msm: ipa3: Changes to decrease the num_of_chan_allocated count
Observing gsi assert in SSR scenario due to not decreasing the
num_of_chan_allocated count. Adding changes to decrease the count
in dealloc event ring.

Change-Id: Icc0713c25bc5566c377e46fef2a4feb3feed176a
Signed-off-by: Praveen Kurapati <pkurapat@codeaurora.org>
2021-03-10 11:43:41 +05:30
Sivan Reinstein
468a3b7e65 msm: ipa: napi on tx completion changed to polling
Masked interrupts, moved the producer apps
event ring and channel ring polling from
GSI IRQ to napi context, and disabled NOP
descriptors, since interrupt mitigation
is now coming from napi usage.

Change-Id: Id69ba519103255567654d5a11fcd3387900cb27d
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Acked-by: Tal Gelbard <tgelbard@qti.qualcomm.com>
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-03-05 10:26:35 +02:00
Bojun Pan
ac12b70a3c msm: ipa: update gsi config for RTK
1. Change the RTK doorbell to MSI doorbell.
2. Update RTK element size to 32B.

Change-Id: Iec9301e30b51841c139b97abeaa6354a88fdef59
2021-02-11 15:08:17 -08:00
Ashok Vuyyuru
7aa1dc1510 msm: ipa4: Enhanced flow control changes
Adding changes to support enhanced flow control.

Change-Id: Id656319703a27f5073c6fd129fb4202a37b49aad
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
2021-02-09 17:13:28 +05:30
qctecmdr
5015c14a5a Merge "msm: gsi: Fix gsi stop channel fail for old target." 2021-01-27 18:29:11 -08:00