Currently the EAPOL/ARP/DHCP frames arriving as 2K-jump
or out-of-order frmaes are being delivered to the network
stack, without checking for the packet-number sequence.
WCN7850 has hardware support to provide the packet number
of the previous successful re-ordered packet from hardware.
Use this feature to check if the packet-number are in proper
sequence for these EAPOL/ARP/DHCP packets arriving as 2k-jump
or out-of-order packets before submitting it to the network
stack.
Change-Id: I1078452afce4bc00b2509436295e5bd80000feb4
CRs-Fixed: 2965086
Currently the hardware srng register offset is statically
assigned to the handle. This can lead to incorrect index access
when targets (eg: wcn7850) is added which require additional
register offsets to be stored in the hw srng register offset table.
Move to the index based assignment of the srng register offset.
Change-Id: I8e38bdd0c28068029a0267fce706edf4378b9df8
CRs-Fixed: 2965081
WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
Add delayed SRNG register writes support for Tx Ring, also add
dedicated workqueue to do the delayed Tx SRNG register writes.
Change-Id: I8dd157d341f3035e988804eab50d1ca681ab789b
CRs-Fixed: 2868989
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.
Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.
Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
Change the alternate indication_0 to WBM instead of
REO2TCL. This is done such that, WBM takes care of
the of the de-linking of the link descriptors and
release the buffers to the respective WBM rings.
WBM should take care of the NULL entries if present
in link descriptor as WBM internal errors.
Change-Id: Ie084e54861bb4611a45cd724bb32d211c62f4f21
Add apis to map generic registers to shadow region. Existing
logic includes mapping only srng based regs to the shadow
region.
Add support to map REO control regs and WBM2SW2 rel
ring HP reg address to the shadow region in case the direct
reg writes in IPA enable/disable autonomy fail due to UMAC
block being in a power collapsed state.
Shadow reg mapping for these regs is provided to FW during
init. Add stat shadow_reg_write_fail to track shadow reg
write failure and shadow_reg_write_succ to track successful
shadow writes.
Change-Id: I04790765a3de80047689657e2cad0b73123440b9
CRs-Fixed: 2790321
If frames from the same FISA flow goes into different REO2SW rings, it
will result in an unexpected FISA behavior. This can happen if the
frames have been reinjected from FW offload module since FW will select
REO2SW1 ring. If the same flow frames hash to other REO2SW rings, then
the same flow UDP frames will do to different rings.
Reo_destination_indication of 6 indicates if the frame has been
reinjected from FW. If so, then continue to deliver the packet without
FISA.
Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70
CRs-Fixed: 2790292
In ipq5018 CE registers(0x08400000) kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.
Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
Currently as part of runtime PM, only the active
tasklets are being drained. For chips eg. QCA6390,
QCA6490 etc, there are grp_tasklets and delayed reg
write work which has to be drained before entering
runtime PM.
Add the logic to drain all the possible tasks
before entering runtime PM.
Change-Id: Ieb486f00fffd7346dcdc1faea6fed5850ef6daf7
CRs-Fixed: 2676000
Add prefetch_timer configuration for CE rings.
Set prefetch_timer=1 configuration for qca6490 destination CEs,
prefetch_timer=0 configuration for other targets CEs.
Basically setting to 1us asking CE hw to update ring tail pointer to
update within 1us. FW side CE SW sets all rings to 1us already.
Idea behind this change is, we have seen pre-silicon issue where SRC
ring TP read by SW was not seen updated value when prefetch was set
to 8us. Changing prefetch timer value to 1us helps to resolve
pre-silicon issue.
So host side rings need to update the prefetch timer to 1us.
Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741
CRs-Fixed: 2669762
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
The delayed register write for srngs will have
the value of the HP/TP at the time of enqueue,
but the final value which is written to the
hp_addr/tp_addr will be determined based on
HP/TP value at the time of dequeue of the
entry for a particular srng.
Hence to know what was the exact value which
was written to the HP/TP address, add one more
element in the delayed register write entry.
This element will contain the value of the
HP/TP which was actually written to the address.
Change-Id: I73e592611fa50b106da1deda06b839cf4fbe2126
CRs-Fixed: 2658331
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
In QCN9000, wbm release ring has msdu continuation bit
support for invld peer MPDUs. Host needs to form SG
buffer for packets with msdu continuation bit set
Change-Id: Ica03c78068d32d2c8dc609b9a50298b91dd48c0a
Currently hal_info, hal_err etc are using QDF_MODULE_ID_TXRX to print.
Since HAL is a separte module, use QDF_MODULE_ID_HAL.
Change-Id: I2345e1b333ef1f7a4808f5417657ac58da071475
CRs-Fixed: 2636911
Add HAL layer changes for full monitor mode.
Define HAL API and Data structures to read sw_monitor_ring
descriptor.
CRs-Fixed: 2630982
Change-Id: I015fa106d9da74222bef092d50e96fc70a117a4a
In case the bus is in low power mode, the register writes (followed by a
memory barrier) may take a long time (~4ms). This can cause the caller
to block till the PCIe write is completed. Thus, even though PCI
writes are posted, it can still block the caller.
Hence, in case the bus is in low power mode (not in M0), or not in high
throughput scenarios, queue the register write in a workqueue. The
register write will happen in the delayed work context. In other cases,
i.e ,when the bus is not in low power mode or in high thoughput
scenarios, do the register writes in caller context.
Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e
CRs-Fixed: 2602029
Maintain a history of the register writes which
have failed. The failure of register write is
determined by reading back the register after
writing a value to that register. If the read
value does not match the value which was written
then it is termed as a failed register write.
Change-Id: Ic3423c2cbd74bf498c0d3dd8ee7ce4231054541a
CRs-Fixed: 2624475
Sometimes the register write in windowed region
are not going through, thereby retaining the
previous value, which can be incorrect for a
certain mode of operation for the driver.
This kind of incorrect register values, due to
a register write not succeeding, can lead to
unwanted issues. Also the simple logging of
any such occcurence can be over-written in the
logs, thereby going unnoticed.
Add a HAL level statistics to maintain the
count of such failed register writes.
Change-Id: Ib5e98705c23f0c916cb85f518576663710eb30e0
CRs-Fixed: 2611839
For qcn9000, As part HW enhancements, PPDU_ID is sent
in reo_entrance_ring descriptor instead of RX_MPDU_START
tlv. Add support to read ppdu id from descriptor.
Modify existing hal API hal_rx_hw_desc_get_ppduid_get ()
arguments to pass RxDMA ring HW descriptor.
Usage:
a. Use hal_rx_hw_desc_get_ppduid_get () -
to get ppdu id from rx_tlv_hdr or hw descriptor based on target.
for qcn9000, this API gets ppdu_id from HW descriptor,
for other platforms, gets ppdu_id from rx_tv_hdr
b. Use hal_rx_get_ppdu_id () - to get ppdu_id from rx_tlv_hdr
Change-Id: I5838227c12cde50cbb2a9da7a0d8056b8b9b7ef5
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
the current HAL API is to read the WBM internal error
bit from the wbm release ring descriptor is always taking
HKv1 HW structure. But the wbm_internal_error bit
placement has changed from HKv2, for this reason we have
to use target specific HAL API.
Change-Id: I44789180754ca21ae59650b6d8620321a1f12569
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers.
Change-Id: I3662b60375cb8886447a2fba3efead6a1ef3a98d
CRs-Fixed: 2593408
Write into hal register using three floating windows instead of one.
This change is done to avoid frequent window changes for writing into
DP and CE registers. Instead 3 windows are used. One window is statically
mapped to CE block and another window is mapped statically to DP block.
Due to this design there is no need to change the window register to
write into these blocks and write can be done on corresponding window
with single iowrite32. Similar loginc is used for ioread32.
Also modified the hp_addr and tp_addr in initialisation stage so that
hal_write will not have multiple if checks.
Change-Id: Ibb99ec4da7f63323082e46a28afbe90e1f555545
CRs-fixed: 2507441
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
Add debugging infrastructure to record every event posted to reo
command ring. The infrastructure maintains the record of the last
64 events posted to the ring.
Change-Id: Id56fc352050eb664a64b0abb767f3b4a6b4c3aa3
CRs-Fixed: 2552822
Add hal_rx_get_rx_sequence API to retrieve
rx sequence value based on the chipset.
Change-Id: I8377b96dfe04e9695a183482d9fcc4a804f845e0
CRs-Fixed: 2522133
Add the following support for QCA6490:
1. Initialize the qca6490_hal_hw_txrx_ops
2. Initialize the hw_srng_table
3. Attach hal_qca6490_attach
Change-Id: Ic53c520ef804eb4fbe1434c704e9040c83011d3d
CRs-Fixed: 2522133
Implement hal_rx_tlv_get_tcp_chksum API
to retrieve tcp_udp_checksum value
based on the chipset.
Change-Id: Ifab970f10af06f8c0cdbd14d57cb66b49bae1648
CRs-Fixed: 2522133
Implement hal_rx_msdu_get_flow_params API
per chipset as the macro
to retrieve the flow parameters is
chipset dependent.
Change-Id: I6ef83232ebdf7497871a7fc588e082d14cdc9e75
CRs-Fixed: 2522133
Implement hal_rx_msdu_cce_metadata API per
chipset as the macro to retrieve the cce_metadata
value is chipset dependent.
Change-Id: Icd87d4ac32be78d69b24da106381a7669c86ada6
CRs-Fixed: 2522133
Implement hal_rx_msdu_fse_metadata API per
chipset as the macro to retrieve the fse_metadata
value is chipset dependent.
Change-Id: Iae7f532460b5203af2f95c504a6941c0b18b665e
CRs-Fixed: 2522133
Implement hal_rx_msdu_flow_idx_timeout API
per chipset as the macro
to retrieve the flow_idx_timeout value is
chipset dependent.
Change-Id: I03030e3763b3c4a9099699a2d24b8110961610cf
CRs-Fixed: 2522133
