8e01014b7d
Maintain a history of the register writes which have failed. The failure of register write is determined by reading back the register after writing a value to that register. If the read value does not match the value which was written then it is termed as a failed register write. Change-Id: Ic3423c2cbd74bf498c0d3dd8ee7ce4231054541a CRs-Fixed: 2624475
622 lines
19 KiB
C
622 lines
19 KiB
C
/*
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* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_INTERNAL_H_
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#define _HAL_INTERNAL_H_
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#include "qdf_types.h"
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#include "qdf_atomic.h"
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#include "qdf_lock.h"
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#include "qdf_mem.h"
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#include "qdf_nbuf.h"
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#include "pld_common.h"
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#define hal_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_TXRX, params)
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#define hal_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_TXRX, params)
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#define hal_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_TXRX, params)
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#define hal_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_TXRX, params)
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#define hal_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params)
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#define hal_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HAL, params)
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#define hal_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HAL, params)
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#define hal_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HAL, params)
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#define hal_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_HAL, params)
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#define hal_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_HAL, params)
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#ifdef ENABLE_VERBOSE_DEBUG
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extern bool is_hal_verbose_debug_enabled;
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#define hal_verbose_debug(params...) \
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if (unlikely(is_hal_verbose_debug_enabled)) \
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do {\
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QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params); \
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} while (0)
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#define hal_verbose_hex_dump(params...) \
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if (unlikely(is_hal_verbose_debug_enabled)) \
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do {\
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QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_TXRX, \
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QDF_TRACE_LEVEL_DEBUG, \
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params); \
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} while (0)
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#else
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#define hal_verbose_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_TXRX, params)
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#define hal_verbose_hex_dump(params...) \
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QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, \
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params)
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#endif
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/*
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* dp_hal_soc - opaque handle for DP HAL soc
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*/
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struct hal_soc_handle;
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typedef struct hal_soc_handle *hal_soc_handle_t;
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/* TBD: This should be movded to shared HW header file */
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enum hal_srng_ring_id {
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/* UMAC rings */
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HAL_SRNG_REO2SW1 = 0,
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HAL_SRNG_REO2SW2 = 1,
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HAL_SRNG_REO2SW3 = 2,
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HAL_SRNG_REO2SW4 = 3,
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HAL_SRNG_REO2TCL = 4,
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HAL_SRNG_SW2REO = 5,
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/* 6-7 unused */
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HAL_SRNG_REO_CMD = 8,
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HAL_SRNG_REO_STATUS = 9,
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/* 10-15 unused */
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HAL_SRNG_SW2TCL1 = 16,
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HAL_SRNG_SW2TCL2 = 17,
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HAL_SRNG_SW2TCL3 = 18,
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HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */
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/* 20-23 unused */
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HAL_SRNG_SW2TCL_CMD = 24,
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HAL_SRNG_TCL_STATUS = 25,
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/* 26-31 unused */
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HAL_SRNG_CE_0_SRC = 32,
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HAL_SRNG_CE_1_SRC = 33,
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HAL_SRNG_CE_2_SRC = 34,
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HAL_SRNG_CE_3_SRC = 35,
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HAL_SRNG_CE_4_SRC = 36,
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HAL_SRNG_CE_5_SRC = 37,
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HAL_SRNG_CE_6_SRC = 38,
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HAL_SRNG_CE_7_SRC = 39,
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HAL_SRNG_CE_8_SRC = 40,
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HAL_SRNG_CE_9_SRC = 41,
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HAL_SRNG_CE_10_SRC = 42,
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HAL_SRNG_CE_11_SRC = 43,
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/* 44-55 unused */
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HAL_SRNG_CE_0_DST = 56,
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HAL_SRNG_CE_1_DST = 57,
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HAL_SRNG_CE_2_DST = 58,
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HAL_SRNG_CE_3_DST = 59,
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HAL_SRNG_CE_4_DST = 60,
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HAL_SRNG_CE_5_DST = 61,
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HAL_SRNG_CE_6_DST = 62,
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HAL_SRNG_CE_7_DST = 63,
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HAL_SRNG_CE_8_DST = 64,
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HAL_SRNG_CE_9_DST = 65,
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HAL_SRNG_CE_10_DST = 66,
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HAL_SRNG_CE_11_DST = 67,
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/* 68-79 unused */
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HAL_SRNG_CE_0_DST_STATUS = 80,
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HAL_SRNG_CE_1_DST_STATUS = 81,
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HAL_SRNG_CE_2_DST_STATUS = 82,
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HAL_SRNG_CE_3_DST_STATUS = 83,
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HAL_SRNG_CE_4_DST_STATUS = 84,
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HAL_SRNG_CE_5_DST_STATUS = 85,
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HAL_SRNG_CE_6_DST_STATUS = 86,
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HAL_SRNG_CE_7_DST_STATUS = 87,
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HAL_SRNG_CE_8_DST_STATUS = 88,
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HAL_SRNG_CE_9_DST_STATUS = 89,
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HAL_SRNG_CE_10_DST_STATUS = 90,
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HAL_SRNG_CE_11_DST_STATUS = 91,
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/* 92-103 unused */
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HAL_SRNG_WBM_IDLE_LINK = 104,
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HAL_SRNG_WBM_SW_RELEASE = 105,
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HAL_SRNG_WBM2SW0_RELEASE = 106,
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HAL_SRNG_WBM2SW1_RELEASE = 107,
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HAL_SRNG_WBM2SW2_RELEASE = 108,
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HAL_SRNG_WBM2SW3_RELEASE = 109,
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/* 110-127 unused */
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HAL_SRNG_UMAC_ID_END = 127,
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/* LMAC rings - The following set will be replicated for each LMAC */
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HAL_SRNG_LMAC1_ID_START = 128,
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HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
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#ifdef IPA_OFFLOAD
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HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1),
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HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2),
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HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1),
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#else
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HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1),
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#endif
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HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1),
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HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1),
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HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF =
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(HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1),
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HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1),
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HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1),
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HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1),
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#ifdef WLAN_FEATURE_CIF_CFR
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HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
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HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1),
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#else
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HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
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#endif
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/* -142 unused */
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HAL_SRNG_LMAC1_ID_END = 143
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};
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#define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
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#define HAL_MAX_LMACS 3
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#define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
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#define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
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#define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS)
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enum hal_srng_dir {
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HAL_SRNG_SRC_RING,
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HAL_SRNG_DST_RING
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};
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/* Lock wrappers for SRNG */
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#define hal_srng_lock_t qdf_spinlock_t
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#define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock)
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#define SRNG_LOCK(_lock) qdf_spin_lock_bh(_lock)
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#define SRNG_UNLOCK(_lock) qdf_spin_unlock_bh(_lock)
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#define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock)
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struct hal_soc;
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/**
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* dp_hal_ring - opaque handle for DP HAL SRNG
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*/
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struct hal_ring_handle;
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typedef struct hal_ring_handle *hal_ring_handle_t;
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#define MAX_SRNG_REG_GROUPS 2
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/* Hal Srng bit mask
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* HAL_SRNG_FLUSH_EVENT: SRNG HP TP flush in case of link down
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*/
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#define HAL_SRNG_FLUSH_EVENT BIT(0)
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/* Common SRNG ring structure for source and destination rings */
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struct hal_srng {
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/* Unique SRNG ring ID */
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uint8_t ring_id;
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/* Ring initialization done */
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uint8_t initialized;
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/* Interrupt/MSI value assigned to this ring */
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int irq;
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/* Physical base address of the ring */
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qdf_dma_addr_t ring_base_paddr;
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/* Virtual base address of the ring */
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uint32_t *ring_base_vaddr;
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/* Number of entries in ring */
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uint32_t num_entries;
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/* Ring size */
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uint32_t ring_size;
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/* Ring size mask */
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uint32_t ring_size_mask;
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/* Size of ring entry */
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uint32_t entry_size;
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/* Interrupt timer threshold – in micro seconds */
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uint32_t intr_timer_thres_us;
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/* Interrupt batch counter threshold – in number of ring entries */
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uint32_t intr_batch_cntr_thres_entries;
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/* MSI Address */
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qdf_dma_addr_t msi_addr;
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/* MSI data */
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uint32_t msi_data;
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/* Misc flags */
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uint32_t flags;
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/* Lock for serializing ring index updates */
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hal_srng_lock_t lock;
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/* Start offset of SRNG register groups for this ring
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* TBD: See if this is required - register address can be derived
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* from ring ID
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*/
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void *hwreg_base[MAX_SRNG_REG_GROUPS];
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/* Source or Destination ring */
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enum hal_srng_dir ring_dir;
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union {
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struct {
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/* SW tail pointer */
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uint32_t tp;
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/* Shadow head pointer location to be updated by HW */
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uint32_t *hp_addr;
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/* Cached head pointer */
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uint32_t cached_hp;
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/* Tail pointer location to be updated by SW – This
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* will be a register address and need not be
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* accessed through SW structure */
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uint32_t *tp_addr;
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/* Current SW loop cnt */
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uint32_t loop_cnt;
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/* max transfer size */
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uint16_t max_buffer_length;
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} dst_ring;
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struct {
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/* SW head pointer */
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uint32_t hp;
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/* SW reap head pointer */
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uint32_t reap_hp;
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/* Shadow tail pointer location to be updated by HW */
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uint32_t *tp_addr;
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/* Cached tail pointer */
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uint32_t cached_tp;
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/* Head pointer location to be updated by SW – This
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* will be a register address and need not be accessed
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* through SW structure */
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uint32_t *hp_addr;
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/* Low threshold – in number of ring entries */
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uint32_t low_threshold;
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} src_ring;
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} u;
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struct hal_soc *hal_soc;
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/* Number of times hp/tp updated in runtime resume */
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uint32_t flush_count;
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/* hal srng event flag*/
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unsigned long srng_event;
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/* last flushed time stamp */
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uint64_t last_flush_ts;
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};
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/* HW SRNG configuration table */
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struct hal_hw_srng_config {
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int start_ring_id;
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uint16_t max_rings;
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uint16_t entry_size;
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uint32_t reg_start[MAX_SRNG_REG_GROUPS];
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uint16_t reg_size[MAX_SRNG_REG_GROUPS];
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uint8_t lmac_ring;
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enum hal_srng_dir ring_dir;
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uint32_t max_size;
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};
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#define MAX_SHADOW_REGISTERS 36
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/* REO parameters to be passed to hal_reo_setup */
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struct hal_reo_params {
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/** rx hash steering enabled or disabled */
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bool rx_hash_enabled;
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/** reo remap 1 register */
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uint32_t remap1;
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/** reo remap 2 register */
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uint32_t remap2;
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/** fragment destination ring */
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uint8_t frag_dst_ring;
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/** padding */
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uint8_t padding[3];
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};
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struct hal_hw_txrx_ops {
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/* init and setup */
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void (*hal_srng_dst_hw_init)(struct hal_soc *hal,
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struct hal_srng *srng);
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void (*hal_srng_src_hw_init)(struct hal_soc *hal,
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struct hal_srng *srng);
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void (*hal_get_hw_hptp)(struct hal_soc *hal,
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hal_ring_handle_t hal_ring_hdl,
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uint32_t *headp, uint32_t *tailp,
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uint8_t ring_type);
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void (*hal_reo_setup)(struct hal_soc *hal_soc, void *reoparams);
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void (*hal_setup_link_idle_list)(
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struct hal_soc *hal_soc,
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qdf_dma_addr_t scatter_bufs_base_paddr[],
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void *scatter_bufs_base_vaddr[],
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uint32_t num_scatter_bufs,
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uint32_t scatter_buf_size,
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uint32_t last_buf_end_offset,
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uint32_t num_entries);
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qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc,
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qdf_iomem_t addr);
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/* tx */
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void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
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void (*hal_tx_set_dscp_tid_map)(struct hal_soc *hal_soc, uint8_t *map,
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uint8_t id);
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void (*hal_tx_update_dscp_tid)(struct hal_soc *hal_soc, uint8_t tid,
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uint8_t id,
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uint8_t dscp);
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void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
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void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
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uint8_t pool_id, uint32_t desc_id, uint8_t type);
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void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type);
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void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index);
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void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index);
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void (*hal_tx_comp_get_status)(void *desc, void *ts,
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struct hal_soc *hal);
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uint8_t (*hal_tx_comp_get_release_reason)(void *hal_desc);
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uint8_t (*hal_get_wbm_internal_error)(void *hal_desc);
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void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en);
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/* rx */
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uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
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void (*hal_rx_mon_hw_desc_get_mpdu_status)(void *hw_desc_addr,
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struct mon_rx_status *rs);
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uint8_t (*hal_rx_get_tlv)(void *rx_tlv);
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void (*hal_rx_proc_phyrx_other_receive_info_tlv)(void *rx_tlv_hdr,
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void *ppdu_info_handle);
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void (*hal_rx_dump_msdu_start_tlv)(void *msdu_start, uint8_t dbg_level);
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void (*hal_rx_dump_msdu_end_tlv)(void *msdu_end,
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uint8_t dbg_level);
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uint32_t (*hal_get_link_desc_size)(void);
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uint32_t (*hal_rx_mpdu_start_tid_get)(uint8_t *buf);
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uint32_t (*hal_rx_msdu_start_reception_type_get)(uint8_t *buf);
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uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
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void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr);
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void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr);
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void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h);
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uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr,
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void *ppdu_info,
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hal_soc_handle_t hal_soc_hdl,
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qdf_nbuf_t nbuf);
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void (*hal_rx_wbm_err_info_get)(void *wbm_desc,
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void *wbm_er_info);
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void (*hal_rx_dump_mpdu_start_tlv)(void *mpdustart,
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uint8_t dbg_level);
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void (*hal_tx_set_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t *map);
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void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp,
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uint8_t id);
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void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
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uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
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uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
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uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
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uint16_t (*hal_rx_msdu_end_sa_idx_get)(uint8_t *buf);
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uint32_t (*hal_rx_desc_is_first_msdu)(void *hw_desc_addr);
|
||
uint32_t (*hal_rx_msdu_end_l3_hdr_padding_get)(uint8_t *buf);
|
||
uint32_t (*hal_rx_encryption_info_valid)(uint8_t *buf);
|
||
void (*hal_rx_print_pn)(uint8_t *buf);
|
||
uint8_t (*hal_rx_msdu_end_first_msdu_get)(uint8_t *buf);
|
||
uint8_t (*hal_rx_msdu_end_da_is_valid_get)(uint8_t *buf);
|
||
uint8_t (*hal_rx_msdu_end_last_msdu_get)(uint8_t *buf);
|
||
bool (*hal_rx_get_mpdu_mac_ad4_valid)(uint8_t *buf);
|
||
uint32_t (*hal_rx_mpdu_start_sw_peer_id_get)(uint8_t *buf);
|
||
uint32_t (*hal_rx_mpdu_get_to_ds)(uint8_t *buf);
|
||
uint32_t (*hal_rx_mpdu_get_fr_ds)(uint8_t *buf);
|
||
uint8_t (*hal_rx_get_mpdu_frame_control_valid)(uint8_t *buf);
|
||
QDF_STATUS
|
||
(*hal_rx_mpdu_get_addr1)(uint8_t *buf, uint8_t *mac_addr);
|
||
QDF_STATUS
|
||
(*hal_rx_mpdu_get_addr2)(uint8_t *buf, uint8_t *mac_addr);
|
||
QDF_STATUS
|
||
(*hal_rx_mpdu_get_addr3)(uint8_t *buf, uint8_t *mac_addr);
|
||
QDF_STATUS
|
||
(*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr);
|
||
uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf);
|
||
bool (*hal_rx_is_unicast)(uint8_t *buf);
|
||
uint32_t (*hal_rx_tid_get)(hal_soc_handle_t hal_soc_hdl, uint8_t *buf);
|
||
uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *rx_tlv_hdr,
|
||
void *rxdma_dst_ring_desc);
|
||
uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
|
||
uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf);
|
||
void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr);
|
||
void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0);
|
||
void * (*hal_ent_mpdu_desc_info)(void *hw_addr);
|
||
void * (*hal_dst_mpdu_desc_info)(void *hw_addr);
|
||
uint8_t (*hal_rx_get_fc_valid)(uint8_t *buf);
|
||
uint8_t (*hal_rx_get_to_ds_flag)(uint8_t *buf);
|
||
uint8_t (*hal_rx_get_mac_addr2_valid)(uint8_t *buf);
|
||
uint8_t (*hal_rx_get_filter_category)(uint8_t *buf);
|
||
uint32_t (*hal_rx_get_ppdu_id)(uint8_t *buf);
|
||
void (*hal_reo_config)(struct hal_soc *soc,
|
||
uint32_t reg_val,
|
||
struct hal_reo_params *reo_params);
|
||
uint32_t (*hal_rx_msdu_flow_idx_get)(uint8_t *buf);
|
||
bool (*hal_rx_msdu_flow_idx_invalid)(uint8_t *buf);
|
||
bool (*hal_rx_msdu_flow_idx_timeout)(uint8_t *buf);
|
||
uint32_t (*hal_rx_msdu_fse_metadata_get)(uint8_t *buf);
|
||
uint16_t (*hal_rx_msdu_cce_metadata_get)(uint8_t *buf);
|
||
void
|
||
(*hal_rx_msdu_get_flow_params)(
|
||
uint8_t *buf,
|
||
bool *flow_invalid,
|
||
bool *flow_timeout,
|
||
uint32_t *flow_index);
|
||
uint16_t (*hal_rx_tlv_get_tcp_chksum)(uint8_t *buf);
|
||
uint16_t (*hal_rx_get_rx_sequence)(uint8_t *buf);
|
||
void (*hal_rx_get_bb_info)(void *rx_tlv, void *ppdu_info_handle);
|
||
void (*hal_rx_get_rtt_info)(void *rx_tlv, void *ppdu_info_handle);
|
||
void (*hal_rx_msdu_packet_metadata_get)(uint8_t *buf,
|
||
void *msdu_pkt_metadata);
|
||
uint16_t (*hal_rx_get_fisa_cumulative_l4_checksum)(uint8_t *buf);
|
||
uint16_t (*hal_rx_get_fisa_cumulative_ip_length)(uint8_t *buf);
|
||
bool (*hal_rx_get_udp_proto)(uint8_t *buf);
|
||
bool (*hal_rx_get_fisa_flow_agg_continuation)(uint8_t *buf);
|
||
uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
|
||
bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
|
||
uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
|
||
};
|
||
|
||
/**
|
||
* struct hal_soc_stats - Hal layer stats
|
||
* @reg_write_fail: number of failed register writes
|
||
*
|
||
* This structure holds all the statistics at HAL layer.
|
||
*/
|
||
struct hal_soc_stats {
|
||
uint32_t reg_write_fail;
|
||
};
|
||
|
||
#ifdef ENABLE_HAL_REG_WR_HISTORY
|
||
/* The history size should always be a power of 2 */
|
||
#define HAL_REG_WRITE_HIST_SIZE 8
|
||
|
||
/**
|
||
* struct hal_reg_write_fail_entry - Record of
|
||
* register write which failed.
|
||
* @timestamp: timestamp of reg write failure
|
||
* @reg_offset: offset of register where the write failed
|
||
* @write_val: the value which was to be written
|
||
* @read_val: the value read back from the register after write
|
||
*/
|
||
struct hal_reg_write_fail_entry {
|
||
uint64_t timestamp;
|
||
uint32_t reg_offset;
|
||
uint32_t write_val;
|
||
uint32_t read_val;
|
||
};
|
||
|
||
/**
|
||
* struct hal_reg_write_fail_history - Hal layer history
|
||
* of all the register write failures.
|
||
* @index: index to add the new record
|
||
* @record: array of all the records in history
|
||
*
|
||
* This structure holds the history of register write
|
||
* failures at HAL layer.
|
||
*/
|
||
struct hal_reg_write_fail_history {
|
||
qdf_atomic_t index;
|
||
struct hal_reg_write_fail_entry record[HAL_REG_WRITE_HIST_SIZE];
|
||
};
|
||
#endif
|
||
|
||
/**
|
||
* HAL context to be used to access SRNG APIs (currently used by data path
|
||
* and transport (CE) modules)
|
||
*/
|
||
struct hal_soc {
|
||
/* HIF handle to access HW registers */
|
||
struct hif_opaque_softc *hif_handle;
|
||
|
||
/* QDF device handle */
|
||
qdf_device_t qdf_dev;
|
||
|
||
/* Device base address */
|
||
void *dev_base_addr;
|
||
|
||
/* HAL internal state for all SRNG rings.
|
||
* TODO: See if this is required
|
||
*/
|
||
struct hal_srng srng_list[HAL_SRNG_ID_MAX];
|
||
|
||
/* Remote pointer memory for HW/FW updates */
|
||
uint32_t *shadow_rdptr_mem_vaddr;
|
||
qdf_dma_addr_t shadow_rdptr_mem_paddr;
|
||
|
||
/* Shared memory for ring pointer updates from host to FW */
|
||
uint32_t *shadow_wrptr_mem_vaddr;
|
||
qdf_dma_addr_t shadow_wrptr_mem_paddr;
|
||
|
||
/* REO blocking resource index */
|
||
uint8_t reo_res_bitmap;
|
||
uint8_t index;
|
||
uint32_t target_type;
|
||
|
||
/* shadow register configuration */
|
||
struct pld_shadow_reg_v2_cfg shadow_config[MAX_SHADOW_REGISTERS];
|
||
int num_shadow_registers_configured;
|
||
bool use_register_windowing;
|
||
uint32_t register_window;
|
||
qdf_spinlock_t register_access_lock;
|
||
|
||
/* Static window map configuration for multiple window write*/
|
||
bool static_window_map;
|
||
|
||
/* srng table */
|
||
struct hal_hw_srng_config *hw_srng_table;
|
||
int32_t *hal_hw_reg_offset;
|
||
struct hal_hw_txrx_ops *ops;
|
||
|
||
/* Indicate srngs initialization */
|
||
bool init_phase;
|
||
/* Hal level stats */
|
||
struct hal_soc_stats stats;
|
||
#ifdef ENABLE_HAL_REG_WR_HISTORY
|
||
struct hal_reg_write_fail_history *reg_wr_fail_hist;
|
||
#endif
|
||
};
|
||
|
||
void hal_qca6750_attach(struct hal_soc *hal_soc);
|
||
void hal_qca6490_attach(struct hal_soc *hal_soc);
|
||
void hal_qca6390_attach(struct hal_soc *hal_soc);
|
||
void hal_qca6290_attach(struct hal_soc *hal_soc);
|
||
void hal_qca8074_attach(struct hal_soc *hal_soc);
|
||
|
||
/*
|
||
* hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque
|
||
* dp_hal_soc handle type
|
||
* @hal_soc - hal_soc type
|
||
*
|
||
* Return: hal_soc_handle_t type
|
||
*/
|
||
static inline
|
||
hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc)
|
||
{
|
||
return (hal_soc_handle_t)hal_soc;
|
||
}
|
||
|
||
/*
|
||
* hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque
|
||
* dp_hal_ring handle type
|
||
* @hal_srng - hal_srng type
|
||
*
|
||
* Return: hal_ring_handle_t type
|
||
*/
|
||
static inline
|
||
hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng)
|
||
{
|
||
return (hal_ring_handle_t)hal_srng;
|
||
}
|
||
|
||
/*
|
||
* hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle
|
||
* @hal_ring - hal_ring_handle_t type
|
||
*
|
||
* Return: hal_srng pointer type
|
||
*/
|
||
static inline
|
||
struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)
|
||
{
|
||
return (struct hal_srng *)hal_ring;
|
||
}
|
||
#endif /* _HAL_INTERNAL_H_ */
|