コミットグラフ

88 コミット

作成者 SHA1 メッセージ 日付
yuayang
568d8d0822 asoc: audio-kernel: Remove trace_printk
Remove trace_printk point.

Change-Id: I76b53eda77bc41c75e06a885084022d74c248188
Signed-off-by: yuayang <quic_yuayang@quicinc.com>
2023-12-21 16:26:31 +08:00
Laxminath Kasam
001ba433b2 wsa: soundwire: Add support for 4p8MHz DAC rate
Add support to use 4p8MHz DAC rate for receiver over WSA.

Change-Id: Ia0811670326be8131687fbdff70464da063902b2
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2021-09-15 22:22:09 -07:00
Laxminath Kasam
ae258cb2f8 asoc: wsa883x: Update low_noise gain for receiver
Add changes to use wsa883x for receiver with
low_noise mode settings.

Change-Id: Icfa43ebbdb1e366f365053535f541bee03751ca3
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2021-09-15 22:19:46 -07:00
Laxminath Kasam
01756036b5 asoc: lpass-cdc: Update swr pdev initialize order
During sound card register init call, if swr pdev
is not initialized yet respective soundwire port
config is not updated to soundwire controller device.
In macro drivers, update swr pdev into macro private
data prior to platform device add.

Change-Id: Ifa67471cfc7a10b102b573df6285e598bb0b5e5e
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2021-04-26 07:50:25 -07:00
Vatsal Bucha
7dcefcdc50 asoc: bolero: Add core_vote before gfmux access
GFMUX access happen during WSA macro usecase.
Update wsa macro to do core_vote before clock
request.

Change-Id: I0b96e725e5150fff4d8bef0d6a50837fc9a3f873
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
2021-03-18 04:13:06 -07:00
Vatsal Bucha
b6430e162b asoc: codecs: add child devices after completing initialization
In bolero-cdc and tx, va, wsa and rx macros, move schedule_work call to
add the child devices to the point later to where the parent
initialization gets completed.

Change-Id: Iaa07329a25020dde21d9249c3848bb7fcf7d816a
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
2021-03-15 21:53:10 -07:00
Vatsal Bucha
79d3ed87ca asoc: codecs: fix race condition of core vote and reg access
Auto suspend timer for core vote is triggering before read write complete.
Move the auto suspend of core vote to post read write operation.

Change-Id: I758cf57bde4e0b56320ef18f6f17adc655fc8fcb
Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
2021-03-08 06:24:35 -08:00
Jyotirmoi Sarma
a3d8911945 audio-kernel: asoc : Upgrade asoc to support 5.10 kernel
Change-Id: Ia54112cfbde418d66b9314d4ba731928aa057558
Signed-off-by: Jyotirmoi Sarma <jyosarma@codeaurora.org>
2020-12-08 08:49:44 -08:00
Vidyakumar Athota
584244b6ac Merge commit '5efb3a4ee3959f20ed2b697663205ec9a6bd1e5c' into audio-kernel-5-4.lnx.1.0
Change-Id: I58fbdf6b91c33ab5d147efbe5f5706616052c7fe
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
2020-09-06 18:25:28 -07:00
Linux Build Service Account
b9c15b6953 Merge "Merge commit '33ea77356f47c6c596c8505ca90307fc1245ef3f' into audio-kernel-5-4.lnx.1.0" into audio-kernel-5-4.lnx.1.0 2020-09-06 06:58:55 -07:00
Rohit kumar
e25a1fdc64 asoc: codecs: Update logic for active ch cnt calculation
Use number of bits set in active_ch_mask to calculate
active channel count. This fixes improper update of
channel count if same kcontrol is issued more than
once.

Change-Id: I84dc33ad5b6dbfc3babf5bbfeab1e2e71af5983b
Signed-off-by: Rohit kumar <rohitkr@codeaurora.org>
2020-08-31 22:42:09 -07:00
qctecmdr
1d2d2a7f9b Merge "soc: wsa883x: Update the PDM_WD at startup/teardown" 2020-07-24 00:05:32 -07:00
qctecmdr
ce0d91646a Merge "ASoC: wsa-macro: Add core vote before accessing registers" 2020-07-16 23:56:45 -07:00
Sudheer Papothi
de83e87f07 ASoC: wsa-macro: Add core vote before accessing registers
Add core vote before accessing registers to avoid unclocked
access.

Change-Id: I02ce78d71787f5a12c44cd3194dde62682f20037
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
2020-07-11 04:27:42 +05:30
Laxminath Kasam
d8d90b4afa soc: wsa: Fix adie loopback test
In ADIE loopback, need PA enable to
avoid mute. Ensure PA enable post slave
path setup and FS clock.

Change-Id: I4df9d7b919325b50f237f31338859e1b5b34b2eb
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-07-10 18:02:56 +05:30
Laxminath Kasam
b9ff5ac5b0 asoc: bolero: Ensure va-macro is registered before other macros
As va-macro has fs_clk gen, ensure va-macro
is registered before other macros.

Change-Id: I8283dc11817caf0c208fe231132951a7a79b7d51
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-07-08 19:51:47 +05:30
Laxminath Kasam
034cd15ba8 Revert "soc: mstr-ctrl: Retain Audio_HM voting until suspend"
This reverts commit d02c7efb35.
and commit 61f235e5bd to avoid AOP
related issues.

Change-Id: I0b8b44bc5cca6bef6bc18c228f08a9c585c79c1c
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-06-22 09:40:14 +05:30
qctecmdr
f1b31e25a5 Merge "ASoC: bolero: Disable wsa swr gpio as wakeup capable" 2020-06-11 04:15:16 -07:00
Laxminath Kasam
d02c7efb35 soc: mstr-ctrl: Retain Audio_HM voting until suspend
Restore change to retain audio_hm voting and
ensure AOP hang issue not seen by masking interrupt
wakeup of swr pinctrl pins.

Change-Id: I51bf36d6d6b0999abf10a4bc94cce900d1adf1d5
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-06-08 16:24:54 +05:30
qctecmdr
d187ddf230 Merge "asoc: wsa-macro: Fix mixing path on WSA" 2020-06-05 01:54:03 -07:00
Sudheer Papothi
b0e4323d6a ASoC: bolero: Disable wsa swr gpio as wakeup capable
Disable wsa swr gpio as wakeup capable to avoid waking up system
during power collapse.

Change-Id: I54d769d63c9e7c13d2920f038c64353a92556cfe
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
2020-06-05 09:58:38 +05:30
qctecmdr
3938234bc8 Merge "asoc: codec: Add pre ssr up event for all macros" 2020-06-01 10:27:01 -07:00
Laxminath Kasam
346cb8b0e9 asoc: wsa-macro: Fix mixing path on WSA
Standalone mixing path on WSA is mute.
Enable soundwire path is not happening,
add respective call in mixing path widget
callback to setup soundwire and WSA.

Change-Id: Ia8df0fdcc4a022e4b86c11283dd3606412a2fb69
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-05-29 01:34:57 -07:00
Prasad Kumpatla
515fc228ee asoc: codec: Add pre ssr up event for all macros
Add a pre ssr up event in all macros ,where GFMUX reset
to done before set the dev_up flag to true.

Change-Id: I77229ccd0ed68aac841146a89fe7f76961260aea
Signed-off-by: Prasad Kumpatla <nkumpat@codeaurora.org>
2020-05-26 15:15:51 +05:30
Meng Wang
30fad2dc20 asoc: codec: update SOC_SINGLE_SX_TLV to SOC_SINGLE_S8_TLV
Update SOC_SINGLE_SX_TLV to SOC_SINGLE_S8_TLV to make codec
driver compatiable with upstream driver.

Change-Id: I4061b015d715978f3b294ad630f53b64bf66c2b7
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2020-05-19 08:34:39 +08:00
qctecmdr
3dc027a3da Merge "asoc: Fix port collision interrupt in WSA" 2020-05-10 05:35:13 -07:00
Prasad Kumpatla
a804ab121b asoc: Fix port collision interrupt in WSA
During multiple PDR usecases, due to sync issues
port collision interrupt is observed.
set wsa state to device down  before cancelling the ocp
workqueue and bail out from the workqueue when wsa state
is set to device down.

Change-Id: Ibefb338c1d6d2901b8773928fa2c0c48b51ac6f7
Signed-off-by: Prasad Kumpatla <nkumpat@codeaurora.org>
2020-04-29 23:25:56 -07:00
Laxminath Kasam
cb88df80a7 asoc: wsa-macro: Update VI sense setting based on pcm rate
Retrieve sample rate for VI sense and update codec settings
based on it.

Change-Id: If4341bac77ecae290c44c4412a39b9e5cbf46ac0
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-04-27 13:21:11 -07:00
Aditya Bavanari
236ff485d2 codecs: Enable clock voting logs to debug AHB/NOC issues
Enable clock voting logs to debug stability issues.

Change-Id: Ie1f995ab004778a81ea42baad15ea36858407e9a
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
2020-04-20 10:17:02 -07:00
Laxminath Kasam
b4d55c7149 asoc: bolero: Update mask of wsa macro
Update mask of wsa macro to apply sample rate
as per config send during hw_params at powerup.

Change-Id: Icf9b40fecf655c06cc60d56ac31808e886f8a49d
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2020-04-10 10:50:00 -07:00
Sudheer Papothi
fd6155a232 ASoC: wsa-macro: Update smart boost sequence for wsa883x
Update smart boost sequence for wsa883x speaker amplifier
to reach max voltage at full scale signal.

Change-Id: Ic1a9ce13753d6e573c7916ae99643c85d6892aa0
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
2020-03-28 10:07:33 +05:30
Aditya Bavanari
e2f52ea5c0 asoc: codecs: Add system sleep ops for macro drivers
Add system sleep ops and invoke force runtime suspend for all
the macro drivers in bolero in order to synchronize
system suspend and runtime suspend callbacks.
Use freezable delayed work queues instead of normal
delayed workqueues in order to avoid contention with
pm suspend callflow.

Change-Id: Ibb0d35ad80c09e7f2a7032b4daef53c359056dfd
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
2020-03-23 20:44:38 -07:00
qctecmdr
0f6392dc14 Merge "asoc: codecs: Check for core votes count before accessing registers" 2019-10-15 00:22:20 -07:00
qctecmdr
6a164b940d Merge "asoc: codecs: bolero: ignore children for pm suspend" 2019-10-15 00:15:16 -07:00
qctecmdr
75b962681c Merge "asoc: codecs: bolero: Do not return error for unused gpio" 2019-10-12 08:58:56 -07:00
Aditya Bavanari
d577af909c asoc: codecs: Check for core votes count before accessing registers
Check for core votes count before accessing swrm registers
to avoid NOC errors.

Change-Id: I5689d6a6db0886ed4cc791738a28290f3d953412
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
2019-10-10 20:29:49 +05:30
Karthikeyan Mani
3d209514a9 asoc: codecs: bolero: ignore children for pm suspend
Allow bolero macro's child  devices to pm enable
irrespective of state of their parents.

Change-Id: Ie615ea2db097760de75682b5881f71a37a735fa2
Signed-off-by: Karthikeyan Mani <kmani@codeaurora.org>
2019-10-06 23:06:32 -07:00
qctecmdr
3c19b49560 Merge "asoc: codecs: bolero: Update mixing path and channel mask for RX path" 2019-09-30 23:31:40 -07:00
Laxminath Kasam
069df14aa0 asoc: codecs: Fix pop issue on WSA cold start
Observe pop if FS clock is turned on at end of
powerup sequence. Ensure WSA PA is turned on
after FS clock to avoid pop.

Change-Id: Ic1214d361e77db252b7a90a89fc99c69f51e270b
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2019-09-19 11:37:00 +05:30
Karthikeyan Mani
8d40a06347 asoc: codecs: Add core vote functionality for soundwire
Add callback to vote for core votes that the
soundwire master can use while doing a clock request.
Check for pinctrl function errors and in case of any
failures return from clock enable with an error.

Change-Id: Ic5c200d7179a1e3a9695955d8711358cd7618bd1
Signed-off-by: Karthikeyan Mani <kmani@codeaurora.org>
2019-09-11 11:20:27 -07:00
Karthikeyan Mani
b44e4551b1 asoc: codecs: bolero: Do not return error for unused gpio
If soundwire gpio is not used, then no need to return
error if not able to get gpio data.

Change-Id: I97705b49d3b01f99b7a4e91190a15ffb211d32f2
Signed-off-by: Karthikeyan Mani <kmani@codeaurora.org>
2019-09-09 23:08:07 -07:00
Laxminath Kasam
f8adb5f3c3 asoc: codecs: bolero: Update mixing path and channel mask for RX path
RX_CDC_DMA_RX0/1/2/3 ports  drives RX0/RX1, RX2/RX3, RX4 and RX5
channels on bolero rx-macro. Update channel mask
as per these mapping and return to channel map
accordingly.

Change-Id: I2e66e601b5137ebc513527827332bbb7cde0acb3
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2019-09-09 10:47:49 +05:30
Laxminath Kasam
52ae6581d7 asoc: codecs: bolero: Fix L/R swap issue on bolero RX
Left and right channel content can get swapped
in new cdc_dma interface.

DMA interfaces underrun results in Channels being swapped.

This issue is a side effect current SW setup for RX path:
  1.  HLOS Setup WCD Analog Path, Bolero CODEC.
      CODEC would drive Fs to LPASS DMAs requesting for PCM samples.
  2.  DSP setup RX Buffers in Memory :
  3.  DSP Configures RD DMAs and DMA RXTX CODEC interface
      (Enable CODEC DMA interface buffer and
       Enable DMA LPASS_RXTX_LPAIF_RDDMA_CTL0.ENABLE
       and LPASS_RXTX_LPAIF_RDDMA_CODEC_INTF0.ENABLE
    If CODEC Fs, aligns with DMA interface being enabled
    there is an underrun as DMA interface pingpong buffer is empty.
    This results in channels being swapped.

Proposed work around while keeping current SW setup order.
Provide a workaround to Keep Fs disabled  until DMAs and
CODEC DMA interface are enabled and HW could  prefetch all buffers.
SW would keep existing setup order:
  1.  HLOS Setup WCD Analog Path, Bolero CODEC.
      CODEC would drive Fs to LPASS DMAs requesting for PCM samples.
  2.  DSP setup RX Buffers in Memory :
  3.  DSP Configures DMAs and DMA CODEC interface
      (Enable CODEC DMA interface buffer and
       Enable DMA LPASS_RXTX_LPAIF_RDDMA_CTL0.ENABLE
       and LPASS_RXTX_LPAIF_RDDMA_CODEC_INTF0.ENABLE)
  4.  Enable Fs Set #LPASS_RX_CDC_RX0_RX_PATH_CTL. CLK_EN to ONE

Change-Id: I7916667f5d857464cc7d77b51da307ab234cc7bb
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
2019-08-28 19:08:02 +05:30
Sudheer Papothi
c0f75b7727 ASoC: bolero: check for port validation before configuration
Check for valid port before mux configuration.

Change-Id: Iaa32925f0c23305a2a3cedd0e476372aac380e0c
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
2019-08-19 22:52:56 +05:30
Aditya Bavanari
50ef13eca6 asoc: codecs: Fix LPI TLMM GPIO invalid access issue
Runtime suspend gets called multiple times during SSR
scenarios leading to clock count mismatch. Add logic
to prevent this in all macros and pinctrl lpi driver.

Change-Id: I380631c1db8cd7d94a8909affd8c96c87f24817c
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
2019-08-09 15:14:43 +05:30
qctecmdr
42ebbffad4 Merge "asoc: bolero: check if clock is enabled before accessing register" 2019-07-06 08:49:47 -07:00
Meng Wang
bf1fe8fbad asoc: bolero: force bolero runtime suspend during adsp ssr
During adsp SSR, bolero runtime suspend is not called and
hw vote clks are not reset. Force bolero runtime suspend
during adsp SSR to avoid kernel panic.

Change-Id: Iff5983ef07f77ecc7f3f344948c013906b4bad60
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2019-07-02 08:26:55 +08:00
Meng Wang
bd93024823 asoc: bolero: check if clock is enabled before accessing register
Reset GFMUX reg for va-macro and wsa-macro when adsp is up
after SSR. And check if clock is enabled before accessing
register to avoid kernel panic.

Change-Id: Idce9695be552cab0e8e389cf72eeb7a67a754bf9
Signed-off-by: Meng Wang <mengw@codeaurora.org>
2019-06-28 08:38:15 +08:00
qctecmdr
1dffa77438 Merge "asoc: bolero: reset all clks after SSR/PDR" 2019-06-17 21:04:15 -07:00
qctecmdr
45b4733d63 Merge "asoc: codecs: defer probe if soundwire pin is not ready" 2019-06-17 20:25:32 -07:00