samsung-sm8650/android_kernel_samsung_sm8650-modules
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Merge "msm: ipa3: upgrade reg save to IPAv5"

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Цей коміт міститься в:
qctecmdr
2021-08-26 01:30:37 -07:00
зафіксовано Gerrit - the friendly Code Review server
джерело c6e2859a34 e927e01f4f
коміт d2a3698807
17 змінених файлів з 122802 додано та 117 видалено
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2
config/dataipa.h
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@@ -8,3 +8,5 @@
#define CONFIG_RNDIS_IPA 1
#define CONFIG_IPA_WDI_UNIFIED_API 1
#define CONFIG_ECM_IPA 1
#define CONFIG_IPA3_REGDUMP 1
#define CONFIG_IPA3_REGDUMP_IPA_5_0 1

2
config/dataipa_GKI.conf
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@@ -4,3 +4,5 @@ export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y
export CONFIG_IPA3_MHI_PRIME_MANAGER=y
export CONFIG_RNDIS_IPA=m
export CONFIG_IPA3_REGDUMP=y
export CONFIG_IPA3_REGDUMP_IPA_5_0=y

2
config/dataipa_QGKI.conf
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@@ -4,3 +4,5 @@ export CONFIG_IPA_WDI_UNIFIED_API=y
export CONFIG_RMNET_IPA3=y
export CONFIG_RNDIS_IPA=y
export CONFIG_ECM_IPA=y
export CONFIG_IPA3_REGDUMP=y
export CONFIG_IPA3_REGDUMP_IPA_5_0=y

2
config/dataipa_vendor.h
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@@ -9,3 +9,5 @@
#define CONFIG_IPA_WDI_UNIFIED_API 1
#define CONFIG_IPA_VENDOR_DLKM 1
#define CONFIG_IPA3_MHI_PRIME_MANAGER 1
#define CONFIG_IPA3_REGDUMP 1
#define CONFIG_IPA3_REGDUMP_IPA_5_0 1

4
drivers/platform/msm/Kbuild
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@@ -65,6 +65,10 @@ ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_5),y m))
LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa4.5
endif
ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_5_0),y m))
LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa5.0
endif
obj-$(CONFIG_GSI) += gsi/
obj-$(CONFIG_IPA3) += ipa/

4602
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio.h Звичайний файл
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4991
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/gsi_hwio_def.h Звичайний файл
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49
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_access_control.h Звичайний файл
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@@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#if !defined(_IPA_ACCESS_CONTROL_H_)
#define _IPA_ACCESS_CONTROL_H_
#include "ipa_reg_dump.h"
/*
* AA_COMBO - actual read, actual write
* AN_COMBO - actual read, no-op write
* NA_COMBO - no-op read, actual write
* NN_COMBO - no-op read, no-op write
*/
/*
* The following is target specific.
*/
static struct reg_mem_access_map_t mem_access_map[] = {
/*------------------------------------------------------------*/
/* Range Use when Use when */
/* Begin End SD_ENABLED SD_DISABLED */
/*------------------------------------------------------------*/
{ 0x04000, 0x04FFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0xA8000, 0xB7FFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x05000, 0x0EFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x0F000, 0x0FFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x18000, 0x29FFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x2A000, 0x3BFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x3C000, 0x4DFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x10000, 0x10FFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x11000, 0x11FFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x12000, 0x12FFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x14C000, 0x14CFFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x14D000, 0x14DFFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x14E000, 0x14FFFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x140000, 0x147FFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x148000, 0x14BFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x150000, 0x15FFFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
{ 0x160000, 0x17FFFF, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x180000, 0x180FFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x181000, 0x19FFFF, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } },
{ 0x1A0000, 0x1BFFFF, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x1C0000, 0x1C1FFF, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } },
{ 0x1C2000, 0x1C3FFF, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } },
};
#endif /* #if !defined(_IPA_ACCESS_CONTROL_H_) */

47043
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_gcc_hwio.h Звичайний файл
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28406
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_gcc_hwio_def.h Звичайний файл
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649
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h Звичайний файл
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@@ -0,0 +1,649 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#if !defined(_IPA_HW_COMMON_EX_H_)
#define _IPA_HW_COMMON_EX_H_
/* VLVL defs are available for 854 */
#define FEATURE_VLVL_DEFS true
#define FEATURE_IPA_HW_VERSION_4_5 true
/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */
#define IPA_HW_BAM_IRQ_NUM 639
/* Q6 IRQ number for IPA. */
#define IPA_HW_IRQ_NUM 640
/* Total number of different interrupts that can be enabled */
#define IPA_HW_IRQ_CNT_TOTAL 23
/* IPAv4 spare reg value */
#define IPA_HW_SPARE_1_REG_VAL 0xC0000005
/* Whether to allow setting step mode on IPA when we crash or not */
#define IPA_CFG_HW_IS_STEP_MODE_ALLOWED (false)
/* GSI MHI related definitions */
#define IPA_HW_GSI_MHI_CONSUMER_CHANNEL_NUM 0x0
#define IPA_HW_GSI_MHI_PRODUCER_CHANNEL_NUM 0x1
#define IPA_HW_GSI_MHI_CONSUMER_EP_NUM 0x1
#define IPA_HW_GSI_MHI_PRODUCER_EP_NUM 0x11
/* IPA ZIP WA related Macros */
#define IPA_HW_DCMP_SRC_PIPE 0x8
#define IPA_HW_DCMP_DEST_PIPE 0x4
#define IPA_HW_ACK_MNGR_MASK 0x1D
#define IPA_HW_DCMP_SRC_GRP 0x5
/* IPA Clock resource name */
#define IPA_CLK_RESOURCE_NAME "/clk/pcnoc"
/* IPA Clock Bus Client name */
#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT"
/* HPS Sequences */
#define IPA_HW_PKT_PROCESS_HPS_DMA 0x0
#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_CIPHE 0x1
#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_UCP 0x2
#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP 0x3
#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH 0x4
#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH 0x5
#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_NO_UCP 0x6
#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP 0x7
#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER 0x8
#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER 0x9
#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_NO_DECIPH 0xA
#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_UCP_TWICE_DECIPH 0xB
#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_NO_DECIPH 0xC
#define IPA_HW_PKT_PROCESS_HPS_3_PKT_PRS_UCP_TWICE_DECIPH 0xD
/* DPS Sequences */
#define IPA_HW_PKT_PROCESS_DPS_DMA 0x0
#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH 0x1
#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP 0x2
#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_CIPH 0x3
/* Src RSRC GRP config */
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0 0x0B040803
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1 0x0C0C0909
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2 0x0E0E0909
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3 0x3F003F00
#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4 0x10101616
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0 0x01010101
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1 0x02020202
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2 0x04040404
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3 0x3F003F00
#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4 0x02020606
#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_0 0x00000000
#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_1 0x00000000
#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_2 0x00000000
#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_3 0x00003F00
#define IPA_HW_SRC_RSRC_GRP_45_RSRC_TYPE_4 0x00000000
/* Dest RSRC GRP config */
#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0 0x05051010
#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1 0x3F013F02
#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0 0x02020202
#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1 0x02010201
#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_0 0x00000000
#define IPA_HW_DST_RSRC_GRP_45_RSRC_TYPE_1 0x00000200
#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0 0x03030303
#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0 0x03030303
#define IPA_HW_RSRP_GRP_0 0x0
#define IPA_HW_RSRP_GRP_1 0x1
#define IPA_HW_RSRP_GRP_2 0x2
#define IPA_HW_RSRP_GRP_3 0x3
#define IPA_HW_PCIE_SRC_RSRP_GRP IPA_HW_RSRP_GRP_0
#define IPA_HW_PCIE_DEST_RSRP_GRP IPA_HW_RSRP_GRP_0
#define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1
#define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1
#define IPA_HW_DMA_SRC_RSRP_GRP IPA_HW_RSRP_GRP_2
#define IPA_HW_DMA_DEST_RSRP_GRP IPA_HW_RSRP_GRP_2
#define IPA_HW_SRC_RSRP_TYPE_MAX 0x05
#define IPA_HW_DST_RSRP_TYPE_MAX 0x03
#define GSI_HW_QSB_LOG_MISC_MAX 0x4
/* IPA Clock Bus Client name */
#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT"
/* Is IPA decompression feature enabled */
#define IPA_HW_IS_DECOMPRESSION_ENABLED (1)
/* Whether to allow setting step mode on IPA when we crash or not */
#define IPA_HW_IS_STEP_MODE_ALLOWED (true)
/* Max number of virtual pipes for UL QBAP provided by HW */
#define IPA_HW_MAX_VP_NUM (32)
/*
* HW specific clock vote freq values in KHz
* (BIMC/SNOC/PCNOC/IPA/Q6 CPU)
*/
enum ipa_hw_clk_freq_e {
/* BIMC */
IPA_HW_CLK_FREQ_BIMC_PEAK = 518400,
IPA_HW_CLK_FREQ_BIMC_NOM_PLUS = 404200,
IPA_HW_CLK_FREQ_BIMC_NOM = 404200,
IPA_HW_CLK_FREQ_BIMC_SVS = 100000,
/* PCNOC */
IPA_HW_CLK_FREQ_PCNOC_PEAK = 133330,
IPA_HW_CLK_FREQ_PCNOC_NOM_PLUS = 100000,
IPA_HW_CLK_FREQ_PCNOC_NOM = 100000,
IPA_HW_CLK_FREQ_PCNOC_SVS = 50000,
/*IPA_HW_CLK_SNOC*/
IPA_HW_CLK_FREQ_SNOC_PEAK = 200000,
IPA_HW_CLK_FREQ_SNOC_NOM_PLUS = 150000,
IPA_HW_CLK_FREQ_SNOC_NOM = 150000,
IPA_HW_CLK_FREQ_SNOC_SVS = 85000,
IPA_HW_CLK_FREQ_SNOC_SVS_2 = 50000,
/* IPA */
IPA_HW_CLK_FREQ_IPA_PEAK = 600000,
IPA_HW_CLK_FREQ_IPA_NOM_PLUS = 500000,
IPA_HW_CLK_FREQ_IPA_NOM = 500000,
IPA_HW_CLK_FREQ_IPA_SVS = 250000,
IPA_HW_CLK_FREQ_IPA_SVS_2 = 150000,
/* Q6 CPU */
IPA_HW_CLK_FREQ_Q6_PEAK = 729600,
IPA_HW_CLK_FREQ_Q6_NOM_PLUS = 729600,
IPA_HW_CLK_FREQ_Q6_NOM = 729600,
IPA_HW_CLK_FREQ_Q6_SVS = 729600,
};
enum ipa_hw_qtimer_gran_e {
IPA_HW_QTIMER_GRAN_0 = 0, /* granularity 0 is 10us */
IPA_HW_QTIMER_GRAN_1 = 1, /* granularity 1 is 100us */
IPA_HW_QTIMER_GRAN_MAX,
};
/* Pipe ID of all the IPA pipes */
enum ipa_hw_pipe_id_e {
IPA_HW_PIPE_ID_0,
IPA_HW_PIPE_ID_1,
IPA_HW_PIPE_ID_2,
IPA_HW_PIPE_ID_3,
IPA_HW_PIPE_ID_4,
IPA_HW_PIPE_ID_5,
IPA_HW_PIPE_ID_6,
IPA_HW_PIPE_ID_7,
IPA_HW_PIPE_ID_8,
IPA_HW_PIPE_ID_9,
IPA_HW_PIPE_ID_10,
IPA_HW_PIPE_ID_11,
IPA_HW_PIPE_ID_12,
IPA_HW_PIPE_ID_13,
IPA_HW_PIPE_ID_14,
IPA_HW_PIPE_ID_15,
IPA_HW_PIPE_ID_16,
IPA_HW_PIPE_ID_17,
IPA_HW_PIPE_ID_18,
IPA_HW_PIPE_ID_19,
IPA_HW_PIPE_ID_20,
IPA_HW_PIPE_ID_21,
IPA_HW_PIPE_ID_22,
IPA_HW_PIPE_ID_23,
IPA_HW_PIPE_ID_24,
IPA_HW_PIPE_ID_25,
IPA_HW_PIPE_ID_26,
IPA_HW_PIPE_ID_27,
IPA_HW_PIPE_ID_28,
IPA_HW_PIPE_ID_29,
IPA_HW_PIPE_ID_30,
IPA_HW_PIPE_ID_31,
IPA_HW_PIPE_ID_32,
IPA_HW_PIPE_ID_33,
IPA_HW_PIPE_ID_34,
IPA_HW_PIPE_ID_35,
IPA_HW_PIPE_ID_MAX
};
/* Pipe ID's of System Bam Endpoints between Q6 & IPA */
enum ipa_hw_q6_pipe_id_e {
/* Pipes used by IPA Q6 driver */
IPA_HW_Q6_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_5,
IPA_HW_Q6_CTL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_6,
IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_8,
IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_20,
IPA_HW_Q6_UL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_21,
IPA_HW_Q6_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_17,
IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_18,
IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_19,
IPA_HW_Q6_UL_ACK_PRODUCER_PIPE_ID =
IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE_ID,
IPA_HW_Q6_UL_DATA_PRODUCER_PIPE_ID =
IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE_ID,
IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_4,
IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_29,
/* Test Simulator Pipes */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID = IPA_HW_PIPE_ID_0,
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_1,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_3,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_10,
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_7,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_9,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID = IPA_HW_PIPE_ID_23,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_24,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_25,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_26,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_27,
IPA_HW_Q6_PIPE_ID_MAX = IPA_HW_PIPE_ID_MAX,
};
enum ipa_hw_q6_pipe_ch_id_e {
/* Channels used by IPA Q6 driver */
IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID = 0,
IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID = 1,
IPA_HW_Q6_DL_NLO_CONSUMER_PIPE_CH_ID = 2,
IPA_HW_Q6_UL_ACC_PATH_ACK_PRODUCER_PIPE_CH_ID = 6,
IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID = 7,
IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID = 3,
IPA_HW_Q6_UL_ACC_PATH_DATA_PRODUCER_PIPE_CH_ID = 5,
IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE_CH_ID = 4,
IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE_CH_ID = 8,
IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE_CH_ID = 9,
/* CH_ID 8 and 9 are Q6 SPARE CONSUMERs */
/* Test Simulator Channels */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID = 10,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID = 11,
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID = 12,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID = 13,
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID = 14,
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID = 15,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID = 16,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID = 17,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID = 18,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID = 19,
};
/* System Bam Endpoints between Q6 & IPA */
enum ipa_hw_q6_pipe_e {
/* DL Pipe IPA->Q6 */
IPA_HW_Q6_DL_PRODUCER_PIPE = 0,
/* UL Pipe IPA->Q6 */
IPA_HW_Q6_UL_PRODUCER_PIPE = 1,
/* DL Pipe Q6->IPA */
IPA_HW_Q6_DL_CONSUMER_PIPE = 2,
/* CTL Pipe Q6->IPA */
IPA_HW_Q6_CTL_CONSUMER_PIPE = 3,
/* Q6 -> IPA, DL NLO */
IPA_HW_Q6_DL_NLO_CONSUMER_PIPE = 4,
/* DMA ASYNC CONSUMER */
IPA_HW_Q6_DMA_ASYNC_CONSUMER_PIPE = 5,
/* DMA ASYNC PRODUCER */
IPA_HW_Q6_DMA_ASYNC_PRODUCER_PIPE = 6,
/* UL Acc Path Data Pipe IPA->Q6 */
IPA_HW_Q6_UL_ACC_DATA_PRODUCER_PIPE = 7,
/* UL Acc Path ACK Pipe IPA->Q6 */
IPA_HW_Q6_UL_ACC_ACK_PRODUCER_PIPE = 8,
/* UL Acc Path QBAP status Pipe IPA->Q6 */
IPA_HW_Q6_QBAP_STATUS_PRODUCER_PIPE = 9,
/* Diag status pipe IPA->Q6 */
/* Used only when FEATURE_IPA_TEST_PER_SIM is ON */
/* SIM Pipe IPA->Sim */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 10,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 11,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 12,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 13,
/* SIM B2B PROD Pipe */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 14,
/* SIM Pipe IPA->Sim */
IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 15,
/* End FEATURE_IPA_TEST_PER_SIM */
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 16,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 17,
/* GSI UT channel SW->IPA */
IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 18,
/* GSI UT channel IPA->SW */
IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 19,
IPA_HW_Q6_PIPE_TOTAL
};
/* System Bam Endpoints between Q6 & IPA */
enum ipa_hw_q6_gsi_ev_e { /* In Sdx24 0..11 */
/* DL Pipe IPA->Q6 */
IPA_HW_Q6_DL_PRODUCER_PIPE_GSI_EV = 0,
/* UL Pipe IPA->Q6 */
IPA_HW_Q6_UL_PRODUCER_PIPE_GSI_EV = 1,
/* DL Pipe Q6->IPA */
//IPA_HW_Q6_DL_CONSUMER_PIPE_GSI_EV = 2,
/* CTL Pipe Q6->IPA */
//IPA_HW_Q6_CTL_CONSUMER_PIPE_GSI_EV = 3,
/* Q6 -> IPA, LTE DL Optimized path */
//IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_GSI_EV = 4,
/* LWA DL(Wifi to Q6) */
//IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_GSI_EV = 5,
/* Diag status pipe IPA->Q6 */
//IPA_HW_Q6_DIAG_STATUS_PRODUCER_PIPE_GSI_EV = 6,
/* Used only when FEATURE_IPA_TEST_PER_SIM is ON */
/* SIM Pipe IPA->Sim */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_GSI_EV = 2,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_GSI_EV = 3,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_GSI_EV = 4,
/* SIM Pipe Sim->IPA */
IPA_HW_Q6_SIM_1_GSI_EV = 5,
IPA_HW_Q6_SIM_2_GSI_EV = 6,
IPA_HW_Q6_SIM_3_GSI_EV = 7,
IPA_HW_Q6_SIM_4_GSI_EV = 8,
IPA_HW_Q6_PIPE_GSI_EV_TOTAL
};
/*
* All the IRQ's supported by the IPA HW. Use this enum to set IRQ_EN
* register and read IRQ_STTS register
*/
enum ipa_hw_irq_e {
IPA_HW_IRQ_GSI_HWP = (1 << 25),
IPA_HW_IRQ_GSI_IPA_IF_TLV_RCVD = (1 << 24),
IPA_HW_IRQ_GSI_EE_IRQ = (1 << 23),
IPA_HW_IRQ_DCMP_ERR = (1 << 22),
IPA_HW_IRQ_HWP_ERR = (1 << 21),
IPA_HW_IRQ_RED_MARKER_ABOVE = (1 << 20),
IPA_HW_IRQ_YELLOW_MARKER_ABOVE = (1 << 19),
IPA_HW_IRQ_RED_MARKER_BELOW = (1 << 18),
IPA_HW_IRQ_YELLOW_MARKER_BELOW = (1 << 17),
IPA_HW_IRQ_BAM_IDLE_IRQ = (1 << 16),
IPA_HW_IRQ_TX_HOLB_DROP = (1 << 15),
IPA_HW_IRQ_TX_SUSPEND = (1 << 14),
IPA_HW_IRQ_PROC_ERR = (1 << 13),
IPA_HW_IRQ_STEP_MODE = (1 << 12),
IPA_HW_IRQ_TX_ERR = (1 << 11),
IPA_HW_IRQ_DEAGGR_ERR = (1 << 10),
IPA_HW_IRQ_RX_ERR = (1 << 9),
IPA_HW_IRQ_PROC_TO_HW_ACK_Q_NOT_EMPTY = (1 << 8),
IPA_HW_IRQ_HWP_RX_CMD_Q_NOT_FULL = (1 << 7),
IPA_HW_IRQ_HWP_IN_Q_NOT_EMPTY = (1 << 6),
IPA_HW_IRQ_HWP_IRQ_3 = (1 << 5),
IPA_HW_IRQ_HWP_IRQ_2 = (1 << 4),
IPA_HW_IRQ_HWP_IRQ_1 = (1 << 3),
IPA_HW_IRQ_HWP_IRQ_0 = (1 << 2),
IPA_HW_IRQ_EOT_COAL = (1 << 1),
IPA_HW_IRQ_BAD_SNOC_ACCESS = (1 << 0),
IPA_HW_IRQ_NONE = 0,
IPA_HW_IRQ_ALL = 0xFFFFFFFF
};
/*
* All the IRQ sources supported by the IPA HW. Use this enum to set
* IRQ_SRCS register
*/
enum ipa_hw_irq_srcs_e {
IPA_HW_IRQ_SRCS_PIPE_0 = (1 << IPA_HW_PIPE_ID_0),
IPA_HW_IRQ_SRCS_PIPE_1 = (1 << IPA_HW_PIPE_ID_1),
IPA_HW_IRQ_SRCS_PIPE_2 = (1 << IPA_HW_PIPE_ID_2),
IPA_HW_IRQ_SRCS_PIPE_3 = (1 << IPA_HW_PIPE_ID_3),
IPA_HW_IRQ_SRCS_PIPE_4 = (1 << IPA_HW_PIPE_ID_4),
IPA_HW_IRQ_SRCS_PIPE_5 = (1 << IPA_HW_PIPE_ID_5),
IPA_HW_IRQ_SRCS_PIPE_6 = (1 << IPA_HW_PIPE_ID_6),
IPA_HW_IRQ_SRCS_PIPE_7 = (1 << IPA_HW_PIPE_ID_7),
IPA_HW_IRQ_SRCS_PIPE_8 = (1 << IPA_HW_PIPE_ID_8),
IPA_HW_IRQ_SRCS_PIPE_9 = (1 << IPA_HW_PIPE_ID_9),
IPA_HW_IRQ_SRCS_PIPE_10 = (1 << IPA_HW_PIPE_ID_10),
IPA_HW_IRQ_SRCS_PIPE_11 = (1 << IPA_HW_PIPE_ID_11),
IPA_HW_IRQ_SRCS_PIPE_12 = (1 << IPA_HW_PIPE_ID_12),
IPA_HW_IRQ_SRCS_PIPE_13 = (1 << IPA_HW_PIPE_ID_13),
IPA_HW_IRQ_SRCS_PIPE_14 = (1 << IPA_HW_PIPE_ID_14),
IPA_HW_IRQ_SRCS_PIPE_15 = (1 << IPA_HW_PIPE_ID_15),
IPA_HW_IRQ_SRCS_PIPE_16 = (1 << IPA_HW_PIPE_ID_16),
IPA_HW_IRQ_SRCS_PIPE_17 = (1 << IPA_HW_PIPE_ID_17),
IPA_HW_IRQ_SRCS_PIPE_18 = (1 << IPA_HW_PIPE_ID_18),
IPA_HW_IRQ_SRCS_PIPE_19 = (1 << IPA_HW_PIPE_ID_19),
IPA_HW_IRQ_SRCS_PIPE_20 = (1 << IPA_HW_PIPE_ID_20),
IPA_HW_IRQ_SRCS_PIPE_21 = (1 << IPA_HW_PIPE_ID_21),
IPA_HW_IRQ_SRCS_PIPE_22 = (1 << IPA_HW_PIPE_ID_22),
IPA_HW_IRQ_SRCS_NONE = 0,
IPA_HW_IRQ_SRCS_ALL = 0xFFFFFFFF,
};
/*
* Total number of channel contexts that need to be saved for APPS
*/
#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 20
/*
* Total number of channel contexts that need to be saved for UC
*/
#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC 2
/*
* Total number of channel contexts that need to be saved for Q6
*/
#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6 11
/*
* Total number of event ring contexts that need to be saved for APPS
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 27
/*
* Total number of event ring contexts that need to be saved for UC
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 2
/*
* Total number of endpoints for which ipa_reg_save.pipes[endp_number]
* are not saved by default (only if ipa_cfg.gen.full_reg_trace =
* true) There is no extra endpoints in Stingray
*/
#define IPA_HW_REG_SAVE_NUM_ENDP_EXTRA 0
/*
* Total number of endpoints for which ipa_reg_save.pipes[endp_number]
* are always saved
*/
#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES IPA_HW_PIPE_ID_MAX
/*
* SHRAM Bytes per ch
*/
#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM 12
/*
* Total number of rx splt cmdq's see:
* ipa_rx_splt_cmdq_n_cmd[IPA_RX_SPLT_CMDQ_MAX]
*/
#define IPA_RX_SPLT_CMDQ_MAX 4
/*
* Although not necessary for the numbers below, the use of round_up
* is so that future developers know that these particular constants
* have to be a multiple of four bytes, because the IPA memory reads
* that they drive are always 32 bits...
*/
#define IPA_IU_ADDR 0x000A0000
#define IPA_IU_SIZE round_up(40704, sizeof(u32))
#define IPA_SRAM_ADDR 0x00050000
#define IPA_SRAM_SIZE round_up(19232, sizeof(u32))
#define IPA_MBOX_ADDR 0x000C2000
#define IPA_MBOX_SIZE round_up(256, sizeof(u32))
#define IPA_HRAM_ADDR 0x00060000
#define IPA_HRAM_SIZE round_up(47536, sizeof(u32))
#define IPA_SEQ_ADDR 0x00081000
#define IPA_SEQ_SIZE round_up(768, sizeof(u32))
#define IPA_GSI_ADDR 0x00006000
#define IPA_GSI_SIZE round_up(5376, sizeof(u32))
/*
* Macro to define a particular register cfg entry for all pipe
* indexed register
*/
#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \
{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \
(u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \
(u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 2), \
(u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 3), \
(u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 4), \
(u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 5), \
(u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 6), \
(u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 7), \
(u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 8), \
(u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 9), \
(u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 10), \
(u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 11), \
(u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 12), \
(u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 13), \
(u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 14), \
(u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 15), \
(u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 16), \
(u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 17), \
(u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 18), \
(u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 19), \
(u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 20), \
(u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 21), \
(u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 22), \
(u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 23), \
(u32 *)&ipa_reg_save.ipa.pipes[23].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 24), \
(u32 *)&ipa_reg_save.ipa.pipes[24].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 25), \
(u32 *)&ipa_reg_save.ipa.pipes[25].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 26), \
(u32 *)&ipa_reg_save.ipa.pipes[26].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 27), \
(u32 *)&ipa_reg_save.ipa.pipes[27].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 28), \
(u32 *)&ipa_reg_save.ipa.pipes[28].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 29), \
(u32 *)&ipa_reg_save.ipa.pipes[29].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 30), \
(u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 31), \
(u32 *)&ipa_reg_save.ipa.pipes[31].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 32), \
(u32 *)&ipa_reg_save.ipa.pipes[32].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 33), \
(u32 *)&ipa_reg_save.ipa.pipes[33].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 34), \
(u32 *)&ipa_reg_save.ipa.pipes[34].endp.var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_1xVECTOR_REG_OFST(reg_name, 35), \
(u32 *)&ipa_reg_save.ipa.pipes[35].endp.var_name, \
GEN_REG_ATTR(reg_name) }
/*
* Macro to define a particular register cfg entry for the remaining
* pipe indexed register. In Stingray case we don't have extra
* endpoints so it is intentially empty
*/
#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(REG_NAME, VAR_NAME) \
{ 0, 0 }
/*
* Macro to set the active flag for all active pipe indexed register
* In Stingray case we don't have extra endpoints so it is intentially
* empty
*/
#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE() \
do { \
} while (0)
#endif /* #if !defined(_IPA_HW_COMMON_EX_H_) */

16822
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio.h Звичайний файл
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19048
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hwio_def.h Звичайний файл
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183
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_pkt_cntxt.h Звичайний файл
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@@ -0,0 +1,183 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#if !defined(_IPA_PKT_CNTXT_H_)
#define _IPA_PKT_CNTXT_H_
#define IPA_HW_PKT_CTNTX_MAX 0x10
#define IPA_HW_NUM_SAVE_PKT_CTNTX 0x8
#define IPA_HW_PKT_CTNTX_START_ADDR 0xE434CA00
#define IPA_HW_PKT_CTNTX_SIZE (sizeof(ipa_pkt_ctntx_opcode_state_s) + \
sizeof(ipa_pkt_ctntx_u))
/*
* Packet Context States
*/
enum ipa_hw_pkt_cntxt_state_e {
IPA_HW_PKT_CNTXT_STATE_HFETCHER_INIT = 1,
IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR,
IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR_REP,
IPA_HW_PKT_CNTXT_STATE_H_DCPH,
IPA_HW_PKT_CNTXT_STATE_PKT_PARSER,
IPA_HW_PKT_CNTXT_STATE_FILTER_NAT,
IPA_HW_PKT_CNTXT_STATE_ROUTER,
IPA_HW_PKT_CNTXT_STATE_HDRI,
IPA_HW_PKT_CNTXT_STATE_UCP,
IPA_HW_PKT_CNTXT_STATE_ENQUEUER,
IPA_HW_PKT_CNTXT_STATE_DFETCHER,
IPA_HW_PKT_CNTXT_STATE_D_DCPH,
IPA_HW_PKT_CNTXT_STATE_DISPATCHER,
IPA_HW_PKT_CNTXT_STATE_TX,
IPA_HW_PKT_CNTXT_STATE_TX_ZLT,
IPA_HW_PKT_CNTXT_STATE_DFETCHER_DMAR,
IPA_HW_PKT_CNTXT_STATE_DCMP,
};
/*
* Packet Context fields as received from VI/Design
*/
struct ipa_pkt_ctntx_s {
u64 opcode : 8;
u64 state : 5;
u64 not_used_1 : 2;
u64 tx_pkt_dma_done : 1;
u64 exc_deagg : 1;
u64 exc_pkt_version : 1;
u64 exc_pkt_len : 1;
u64 exc_threshold : 1;
u64 exc_sw : 1;
u64 exc_nat : 1;
u64 exc_frag_miss : 1;
u64 filter_bypass : 1;
u64 router_bypass : 1;
u64 nat_bypass : 1;
u64 hdri_bypass : 1;
u64 dcph_bypass : 1;
u64 security_credentials_select : 1;
u64 pkt_2nd_pass : 1;
u64 xlat_bypass : 1;
u64 dcph_valid : 1;
u64 ucp_on : 1;
u64 replication : 1;
u64 src_status_en : 1;
u64 dest_status_en : 1;
u64 frag_status_en : 1;
u64 eot_dest : 1;
u64 eot_notif : 1;
u64 prev_eot_dest : 1;
u64 src_hdr_len : 8;
u64 tx_valid_sectors : 8;
u64 rx_flags : 8;
u64 rx_packet_length : 16;
u64 revised_packet_length : 16;
u64 frag_en : 1;
u64 frag_bypass : 1;
u64 frag_process : 1;
u64 notif_pipe : 5;
u64 src_id : 8;
u64 tx_pkt_transferred : 1;
u64 src_pipe : 5;
u64 dest_pipe : 5;
u64 frag_pipe : 5;
u64 ihl_offset : 8;
u64 protocol : 8;
u64 tos : 8;
u64 id : 16;
u64 v6_reserved : 4;
u64 ff : 1;
u64 mf : 1;
u64 pkt_israg : 1;
u64 tx_holb_timer_overflow : 1;
u64 tx_holb_timer_running : 1;
u64 trnseq_0 : 3;
u64 trnseq_1 : 3;
u64 trnseq_2 : 3;
u64 trnseq_3 : 3;
u64 trnseq_4 : 3;
u64 trnseq_ex_length : 8;
u64 trnseq_4_length : 8;
u64 trnseq_4_offset : 8;
u64 dps_tx_pop_cnt : 2;
u64 dps_tx_push_cnt : 2;
u64 vol_ic_dcph_cfg : 1;
u64 vol_ic_tag_stts : 1;
u64 vol_ic_pxkt_init_e : 1;
u64 vol_ic_pkt_init : 1;
u64 tx_holb_counter : 32;
u64 trnseq_0_length : 8;
u64 trnseq_0_offset : 8;
u64 trnseq_1_length : 8;
u64 trnseq_1_offset : 8;
u64 trnseq_2_length : 8;
u64 trnseq_2_offset : 8;
u64 trnseq_3_length : 8;
u64 trnseq_3_offset : 8;
u64 dmar_valid_length : 16;
u64 dcph_valid_length : 16;
u64 frag_hdr_offset : 9;
u64 ip_payload_offset : 9;
u64 frag_rule : 4;
u64 frag_table : 1;
u64 frag_hit : 1;
u64 data_cmdq_ptr : 8;
u64 filter_result : 6;
u64 router_result : 6;
u64 nat_result : 6;
u64 hdri_result : 6;
u64 dcph_result : 6;
u64 dcph_result_valid : 1;
u32 not_used_2 : 4;
u64 tx_pkt_suspended : 1;
u64 tx_pkt_dropped : 1;
u32 not_used_3 : 3;
u64 metadata_valid : 1;
u64 metadata_type : 4;
u64 ul_cs_start_diff : 9;
u64 cs_disable_trlr_vld_bit : 1;
u64 cs_required : 1;
u64 dest_hdr_len : 8;
u64 fr_l : 1;
u64 fl_h : 1;
u64 fr_g : 1;
u64 fr_ret : 1;
u64 fr_rule_id : 10;
u64 rt_l : 1;
u64 rt_h : 1;
u64 rtng_tbl_index : 5;
u64 rt_match : 1;
u64 rt_rule_id : 10;
u64 nat_tbl_index : 13;
u64 nat_type : 2;
u64 hdr_l : 1;
u64 header_offset : 10;
u64 not_used_4 : 1;
u64 filter_result_valid : 1;
u64 router_result_valid : 1;
u64 nat_result_valid : 1;
u64 hdri_result_valid : 1;
u64 not_used_5 : 1;
u64 stream_id : 8;
u64 not_used_6 : 6;
u64 dcph_context_index : 2;
u64 dcph_cfg_size : 16;
u64 dcph_cfg_count : 32;
u64 tag_info : 48;
u64 ucp_cmd_id : 16;
u64 metadata : 32;
u64 ucp_cmd_params : 32;
u64 nat_ip_address : 32;
u64 nat_ip_cs_diff : 16;
u64 frag_dest_pipe : 5;
u64 frag_nat_type : 2;
u64 fragr_ret : 1;
u64 frag_protocol : 8;
u64 src_ip_address : 32;
u64 dest_ip_address : 32;
u64 not_used_7 : 37;
u64 frag_hdr_l : 1;
u64 frag_header_offset : 10;
u64 frag_id : 16;
} __packed;
#endif /* #if !defined(_IPA_PKT_CNTXT_H_) */

352
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c
Переглянути файл

@@ -4,10 +4,13 @@
*/
#include "ipa_reg_dump.h"
#include "ipa_access_control.h"
#include <linux/io.h>
/* Total size required for test bus */
#define IPA_MEM_OVERLAY_SIZE 0x66000
#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0
/*
* The following structure contains a hierarchy of structures that
* ultimately leads to a series of leafs. The leafs are structures
@@ -34,21 +37,41 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_STATE,
ipa.gen,
ipa_state),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_STATE_RX_ACTIVE,
ipa.gen,
ipa_state_rx_active),
#else
GEN_SRC_DST_ADDR_MAP_ARR(IPA_STATE_RX_ACTIVE_n,
ipa.gen,
ipa_state_rx_active_n),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX_WRAPPER,
ipa.gen,
ipa_state_tx_wrapper),
GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX0,
ipa.gen,
ipa_state_tx0),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX0_MISC,
ipa.gen,
ipa_state_tx0_misc),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX1,
ipa.gen,
ipa_state_tx1),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_STATE_AGGR_ACTIVE,
ipa.gen,
ipa_state_aggr_active),
#else
GEN_SRC_DST_ADDR_MAP(IPA_STATE_TX1_MISC,
ipa.gen,
ipa_state_tx1_misc),
GEN_SRC_DST_ADDR_MAP_ARR(IPA_STATE_AGGR_ACTIVE_n,
ipa.gen,
ipa_state_aggr_active_n),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_STATE_DFETCHER,
ipa.gen,
ipa_state_dfetcher),
@@ -58,18 +81,25 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_1,
ipa.gen,
ipa_state_fetcher_mask_1),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_2,
ipa.gen,
ipa_state_fetcher_mask_2),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_AOS,
ipa.gen,
ipa_state_gsi_aos),
GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_IF,
ipa.gen,
ipa_state_gsi_if),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_SKIP,
ipa.gen,
ipa_state_gsi_skip),
GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_TLV,
ipa.gen,
ipa_state_gsi_tlv),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_DPL_TIMER_LSB,
ipa.gen,
ipa_dpl_timer_lsb),
@@ -85,12 +115,15 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_1,
ipa.gen,
ipa_spare_reg_1),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_SPARE_REG_2,
ipa.gen,
ipa_spare_reg_2),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_LOG,
ipa.gen,
ipa_log),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_CFG,
ipa.gen,
ipa_log_buf_status_cfg),
@@ -103,6 +136,7 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_STATUS_RAM_PTR,
ipa.gen,
ipa_log_buf_status_ram_ptr),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_CFG,
ipa.gen,
ipa_log_buf_hw_cmd_cfg),
@@ -121,12 +155,21 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_COMP_HW_VERSION,
ipa.gen,
ipa_comp_hw_version),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_HASH_EN,
ipa.gen,
ipa_filt_rout_hash_en),
GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_HASH_FLUSH,
ipa.gen,
ipa_filt_rout_hash_flush),
#else
GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CACHE_CFG,
ipa.gen,
ipa_filt_rout_cache_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CACHE_FLUSH,
ipa.gen,
ipa_filt_rout_cache_flush),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER,
ipa.gen,
ipa_state_fetcher),
@@ -142,9 +185,15 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_IPV6_ROUTE_INIT_VALUES,
ipa.gen,
ipa_ipv6_route_init_values),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_BAM_ACTIVATED_PORTS,
ipa.gen,
ipa_bam_activated_ports),
#else
GEN_SRC_DST_ADDR_MAP_ARR(IPA_BAM_ACTIVATED_PORTS_n,
ipa.gen,
ipa_bam_activated_ports_n),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_TX_COMMANDER_CMDQ_STATUS,
ipa.gen,
ipa_tx_commander_cmdq_status),
@@ -157,6 +206,11 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX,
ipa.gen,
ipa_log_buf_hw_snif_el_cli_mux),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_NOC_MASTER_SEL,
ipa.gen,
ipa_log_buf_hw_cmd_noc_master_sel),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_STATE_ACL,
ipa.gen,
ipa_state_acl),
@@ -172,30 +226,59 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG,
ipa.gen,
ipa_rsrc_grp_cfg),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE,
ipa.gen,
ipa_pipeline_disable),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_COMP_CFG,
ipa.gen,
ipa_comp_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_STATE_NLO_AGGR,
ipa.gen,
ipa_state_nlo_aggr),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER,
ipa.gen,
ipa_state_coal_master),
GEN_SRC_DST_ADDR_MAP(IPA_STATE_COAL_MASTER_1,
ipa.gen,
ipa_state_coal_master_1),
GEN_SRC_DST_ADDR_MAP(IPA_COAL_EVICT_LRU,
ipa.gen,
ipa_coal_evict_lru),
GEN_SRC_DST_ADDR_MAP(IPA_COAL_QMAP_CFG,
ipa.gen,
ipa_coal_qmap_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_TAG_TIMER,
ipa.gen,
ipa_tag_timer),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_CFG1,
ipa.gen,
ipa_nlo_pp_cfg1),
GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_CFG2,
ipa.gen,
ipa_nlo_pp_cfg2),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_ACK_LIMIT_CFG,
ipa.gen,
ipa_nlo_pp_ack_limit_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_NLO_PP_DATA_LIMIT_CFG,
ipa.gen,
ipa_nlo_pp_data_limit_cfg),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_NLO_MIN_DSM_CFG,
ipa.gen,
ipa_nlo_min_dsm_cfg),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP_ARR(IPA_NLO_VP_AGGR_CFG_LSB_n,
ipa.gen,
ipa_nlo_vp_aggr_cfg_lsb_n),
GEN_SRC_DST_ADDR_MAP_ARR(IPA_NLO_VP_LIMIT_CFG_n,
ipa.gen,
ipa_nlo_vp_limit_cfg_n),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_FLUSH_REQ,
ipa.gen,
ipa_nlo_vp_flush_req),
@@ -211,6 +294,38 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_NLO_VP_QBAP_OPEN,
ipa.gen,
ipa_nlo_vp_qbap_open),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_QSB_MAX_READS,
ipa.gen,
ipa_qsb_max_reads),
GEN_SRC_DST_ADDR_MAP(IPA_QSB_MAX_WRITES,
ipa.gen,
ipa_qsb_max_writes),
GEN_SRC_DST_ADDR_MAP(IPA_IDLE_INDICATION_CFG,
ipa.gen,
ipa_idle_indication_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_CLKON_CFG,
ipa.gen,
ipa_clkon_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_TIMERS_XO_CLK_DIV_CFG,
ipa.gen,
ipa_timers_xo_clk_div_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_TIMERS_PULSE_GRAN_CFG,
ipa.gen,
ipa_timers_pulse_gran_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_QTIME_TIMESTAMP_CFG,
ipa.gen,
ipa_qtime_timestamp_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_0,
ipa.gen,
ipa_flavor_0),
GEN_SRC_DST_ADDR_MAP(IPA_FLAVOR_1,
ipa.gen,
ipa_flavor_1),
GEN_SRC_DST_ADDR_MAP(IPA_FILT_ROUT_CFG,
ipa.gen,
ipa_filt_rout_cfg),
#endif
/* Debug Registers */
GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA,
@@ -255,6 +370,55 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_CMD,
ipa.dbg,
ipa_rx_hps_cmdq_cmd),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_STAT_FILTER_IPV4_BASE,
ipa.dbg,
ipa_stat_filter_ipv4_base),
GEN_SRC_DST_ADDR_MAP(IPA_STAT_FILTER_IPV6_BASE,
ipa.dbg,
ipa_stat_filter_ipv6_base),
GEN_SRC_DST_ADDR_MAP(IPA_STAT_ROUTER_IPV4_BASE,
ipa.dbg,
ipa_stat_router_ipv4_base),
GEN_SRC_DST_ADDR_MAP(IPA_STAT_ROUTER_IPV6_BASE,
ipa.dbg,
ipa_stat_router_ipv6_base),
GEN_SRC_DST_ADDR_MAP(IPA_RSRC_MNGR_CONTEXTS,
ipa.dbg,
ipa_rsrc_mngr_contexts),
GEN_SRC_DST_ADDR_MAP(IPA_SNOC_MONITORING_CFG,
ipa.dbg,
ipa_snoc_monitoring_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_PCIE_SNOC_MONITOR_CNT,
ipa.dbg,
ipa_pcie_snoc_monitor_cnt),
GEN_SRC_DST_ADDR_MAP(IPA_DDR_SNOC_MONITOR_CNT,
ipa.dbg,
ipa_ddr_snoc_monitor_cnt),
GEN_SRC_DST_ADDR_MAP(IPA_GSI_SNOC_MONITOR_CNT,
ipa.dbg,
ipa_gsi_snoc_monitor_cnt),
GEN_SRC_DST_ADDR_MAP(IPA_RAM_SNIFFER_HW_BASE_ADDR,
ipa.dbg,
ipa_ram_sniffer_hw_base_addr),
GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_CFG,
ipa.dbg,
ipa_bresp_db_cfg),
GEN_SRC_DST_ADDR_MAP(IPA_BRESP_DB_DATA,
ipa.dbg,
ipa_bresp_db_data),
GEN_SRC_DST_ADDR_MAP(IPA_ENDP_GSI_CONS_BYTES_TLV,
ipa.dbg,
ipa_endp_gsi_cons_bytes_tlv),
GEN_SRC_DST_ADDR_MAP(IPA_RAM_GSI_TLV_BASE_ADDR,
ipa.dbg,
ipa_ram_gsi_tlv_base_addr),
GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD,
ipa.dbg,
ipa_ackmngr_cmdq_cmd),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_RX_HPS_CMDQ_STATUS_EMPTY,
ipa.dbg,
ipa_rx_hps_cmdq_status_empty),
@@ -267,9 +431,15 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_CMD,
ipa.dbg,
ipa_hps_dps_cmdq_cmd),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_HPS_DPS_CMDQ_STATUS_EMPTY,
ipa.dbg,
ipa_hps_dps_cmdq_status_empty),
#else
GEN_SRC_DST_ADDR_MAP_ARR(IPA_HPS_DPS_CMDQ_STATUS_EMPTY_n,
ipa.dbg,
ipa_hps_dps_cmdq_status_empty_n),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_DPS_TX_CMDQ_CMD,
ipa.dbg,
ipa_dps_tx_cmdq_cmd),
@@ -279,10 +449,18 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_CMD,
ipa.dbg,
ipa_ackmngr_cmdq_cmd),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_ACKMNGR_CMDQ_STATUS_EMPTY,
ipa.dbg,
ipa_ackmngr_cmdq_status_empty),
#else
GEN_SRC_DST_ADDR_MAP_ARR(IPA_ACKMNGR_CMDQ_STATUS_EMPTY_n,
ipa.dbg,
ipa_ackmngr_cmdq_status_empty_n),
GEN_SRC_DST_ADDR_MAP_ARR(IPA_NTF_TX_CMDQ_STATUS_EMPTY_n,
ipa.dbg,
ipa_ntf_tx_cmdq_status_empty_n),
#endif
/*
* NOTE: That GEN_SRC_DST_ADDR_MAP() not used below. This is
* because the following registers are not scaler, rather
@@ -298,12 +476,36 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_fec_attr_ee_n),
IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SNOC_FEC_EE_n,
ipa_snoc_fec_ee_n),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_HOLB_DROP_IRQ_INFO_EE_n,
ipa_holb_drop_irq_info_ee_n),
IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_INFO_EE_n,
ipa_suspend_irq_info_ee_n),
IPA_REG_SAVE_CFG_ENTRY_GEN_EE(IPA_SUSPEND_IRQ_EN_EE_n,
ipa_suspend_irq_en_ee_n),
ipa_suspend_irq_en_ee_n),
#else
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_HOLB_DROP_IRQ_INFO_EE_n_REG_k,
ipa.gen_ee, ipa_holb_drop_irq_info_ee_n_reg_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_SUSPEND_IRQ_INFO_EE_n_REG_k,
ipa.gen_ee, ipa_suspend_irq_info_ee_n_reg_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_SUSPEND_IRQ_EN_EE_n_REG_k,
ipa.gen_ee, ipa_suspend_irq_en_ee_n_reg_k),
#endif
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_QUOTA_BASE_n,
ipa.stat_ee, ipa_stat_quota_base_n),
GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_TETHERING_BASE_n,
ipa.stat_ee, ipa_stat_tethering_base_n),
GEN_SRC_DST_ADDR_MAP_EE_n_ARR(IPA_STAT_DROP_CNT_BASE_n,
ipa.stat_ee, ipa_stat_drop_cnt_base_n),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_QUOTA_MASK_EE_n_REG_k,
ipa.stat_ee, ipa_stat_quota_mask_ee_n_reg_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_TETHERING_MASK_EE_n_REG_k,
ipa.stat_ee, ipa_stat_tethering_mask_ee_n_reg_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(IPA_STAT_DROP_CNT_MASK_EE_n_REG_k,
ipa.stat_ee, ipa_stat_drop_cnt_mask_ee_n_reg_k),
#endif
/* Pipe Endp Registers */
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_INIT_CTRL_n,
@@ -344,8 +546,15 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_endp_gsi_cfg_aos_n),
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_GSI_CFG1_n,
ipa_endp_gsi_cfg1_n),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ENDP_FILTER_ROUTER_HSH_CFG_n,
ipa_endp_filter_router_hsh_cfg_n),
#else
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_FILTER_CACHE_CFG_n,
ipa_filter_cache_cfg_n),
IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(IPA_ROUTER_CACHE_CFG_n,
ipa_router_cache_cfg_n),
#endif
/* Source Resource Group Config Registers */
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n,
@@ -354,6 +563,12 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_src_rsrc_grp_23_rsrc_type_n),
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n,
ipa_src_rsrc_grp_45_rsrc_type_n),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_67_RSRC_TYPE_n,
ipa_src_rsrc_grp_67_rsrc_type_n),
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_TYPE_AMOUNT_n,
ipa_src_rsrc_type_amount),
#endif
/* Destination Resource Group Config Registers */
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n,
@@ -362,6 +577,12 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ipa_dst_rsrc_grp_23_rsrc_type_n),
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n,
ipa_dst_rsrc_grp_45_rsrc_type_n),
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_67_RSRC_TYPE_n,
ipa_dst_rsrc_grp_67_rsrc_type_n),
IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_TYPE_AMOUNT_n,
ipa_dst_rsrc_type_amount),
#endif
/* Source Resource Group Count Registers */
IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(
@@ -400,6 +621,7 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_BUSY_REG,
gsi.debug,
ipa_gsi_top_gsi_debug_busy_reg),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING,
gsi.debug,
ipa_gsi_top_gsi_debug_event_pending),
@@ -409,6 +631,7 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING,
gsi.debug,
ipa_gsi_top_gsi_debug_rd_wr_pending),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW,
gsi.debug,
ipa_gsi_top_gsi_debug_pc_from_sw),
@@ -462,9 +685,15 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT,
gsi.debug.gsi_iram_ptrs,
ipa_gsi_top_gsi_iram_ptr_uc_gp_int),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED,
gsi.debug.gsi_iram_ptrs,
ipa_gsi_top_gsi_iram_ptr_int_mod_stopped),
#else
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPED,
gsi.debug.gsi_iram_ptrs,
ipa_gsi_top_gsi_iram_ptr_int_mod_stoped),
#endif
/* GSI SHRAM pointers Registers */
GEN_SRC_DST_ADDR_MAP(IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR,
@@ -501,6 +730,7 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ee_n_cntxt_type_irq),
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_TYPE_IRQ_MSK,
ee_n_cntxt_type_irq_msk),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_GSI_CH_IRQ,
ee_n_cntxt_src_gsi_ch_irq),
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_EV_CH_IRQ,
@@ -513,6 +743,26 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = {
ee_n_cntxt_src_ieob_irq),
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_SRC_IEOB_IRQ_MSK,
ee_n_cntxt_src_ieob_irq_msk),
#else
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_GSI_CH_IRQ_k,
gsi.gen_ee,
ee_n_cntxt_src_gsi_ch_irq_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_EV_CH_IRQ_k,
gsi.gen_ee,
ee_n_cntxt_src_ev_ch_irq_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_k,
gsi.gen_ee,
ee_n_cntxt_src_gsi_ch_irq_msk_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_k,
gsi.gen_ee,
ee_n_cntxt_src_ev_ch_irq_msk_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_IEOB_IRQ_k,
gsi.gen_ee,
ee_n_cntxt_src_ieob_irq_k),
GEN_SRC_DST_ADDR_MAP_EE_n_REG_k_ARR(EE_n_CNTXT_SRC_IEOB_IRQ_MSK_k,
gsi.gen_ee,
ee_n_cntxt_src_ieob_irq_msk_k),
#endif
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GSI_IRQ_STTS,
ee_n_cntxt_gsi_irq_stts),
IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(EE_n_CNTXT_GLOB_IRQ_STTS,
@@ -663,6 +913,7 @@ static struct map_src_dst_addr_s ipa_uc_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_TRIGGER,
ipa.hwp,
ipa_uc_qmb_trigger),
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_PENDING_TID,
ipa.hwp,
ipa_uc_qmb_pending_tid),
@@ -678,6 +929,7 @@ static struct map_src_dst_addr_s ipa_uc_regs_to_save_array[] = {
GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_STATUS,
ipa.hwp,
ipa_uc_qmb_status),
#endif
GEN_SRC_DST_ADDR_MAP(IPA_UC_QMB_BUS_ATTRIB,
ipa.hwp,
ipa_uc_qmb_bus_attrib),
@@ -708,35 +960,59 @@ static struct reg_access_funcs_s *get_access_funcs(u32 addr)
}
static u32 in_dword(
u32 addr)
u32 addr,
u8 perm)
{
struct reg_access_funcs_s *io = get_access_funcs(addr);
return io->read(ipa3_ctx->reg_collection_base + addr);
if (perm & REG_READ_PERM) {
if (io->read == nop_read)
IPADBG_LOW("nop read action for address 0x%X\n", addr);
return io->read(ipa3_ctx->reg_collection_base + addr);
} else {
IPADBG_LOW("not permitted to read addr 0x%X\n", addr);
return nop_read(ipa3_ctx->reg_collection_base + addr);
}
}
static u32 in_dword_masked(
u32 addr,
u32 mask)
u32 mask,
u8 perm)
{
struct reg_access_funcs_s *io = get_access_funcs(addr);
u32 val;
val = io->read(ipa3_ctx->reg_collection_base + addr);
if (perm & REG_READ_PERM) {
if (io->read == nop_read)
IPADBG_LOW("nop read action for address 0x%X\n", addr);
if (io->read == act_read)
return val & mask;
val = io->read(ipa3_ctx->reg_collection_base + addr);
if (io->read == act_read)
return val & mask;
} else {
IPADBG_LOW("not permitted to read addr 0x%X\n", addr);
val = nop_read(ipa3_ctx->reg_collection_base + addr);
}
return val;
}
static void out_dword(
u32 addr,
u32 val)
u32 val,
u8 perm)
{
struct reg_access_funcs_s *io = get_access_funcs(addr);
io->write(ipa3_ctx->reg_collection_base + addr, val);
if (perm & REG_WRITE_PERM) {
io->write(ipa3_ctx->reg_collection_base + addr, val);
if (io->write == nop_write)
IPADBG_LOW("nop write action for address 0x%X\n", addr);
} else {
IPADBG_LOW("not permitted to write addr 0x%X\n", addr);
return;
}
}
/*
@@ -752,8 +1028,12 @@ void ipa_save_gsi_ver(void)
if (!ipa3_ctx->do_register_collection_on_crash)
return;
ipa_reg_save.gsi.fw_ver =
if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
ipa_reg_save.gsi.fw_ver =
IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 0);
if (ipa3_ctx->ipa_hw_type == IPA_HW_v5_0)
ipa_reg_save.gsi.fw_ver =
IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 64);
}
/*
@@ -788,11 +1068,13 @@ void ipa_save_registers(void)
memset(&for_cfg, 0, sizeof(for_cfg));
memset(&for_read, 0, sizeof(for_read));
IPAERR("reading %d registers\n", num_regs);
/* Now save all the configured registers */
for (i = 0; i < num_regs; i++) {
/* Copy reg value to our data struct */
*(ipa_regs_to_save_array[i].dst_addr) =
in_dword(ipa_regs_to_save_array[i].src_addr);
in_dword(ipa_regs_to_save_array[i].src_addr,
ipa_regs_to_save_array[i].perm);
}
/*
@@ -806,7 +1088,8 @@ void ipa_save_registers(void)
IPA_REG_SAVE_NUM_EXTRA_ENDP_REGS); i++) {
/* Copy reg value to our data struct */
*(ipa_regs_to_save_array[num_regs + i].dst_addr) =
in_dword(ipa_regs_to_save_array[num_regs + i].src_addr);
in_dword(ipa_regs_to_save_array[num_regs + i].src_addr,
ipa_regs_to_save_array[num_regs + i].perm);
}
IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE();
@@ -830,7 +1113,8 @@ void ipa_save_registers(void)
for (i = 0; i < num_uc_per_regs; i++) {
/* Copy reg value to our data struct */
*(ipa_uc_regs_to_save_array[i].dst_addr) =
in_dword(ipa_uc_regs_to_save_array[i].src_addr);
in_dword(ipa_uc_regs_to_save_array[i].src_addr,
ipa_uc_regs_to_save_array[i].perm);
}
/* Saving CMD Queue registers */
@@ -971,27 +1255,33 @@ void ipa_save_registers(void)
if (ipa3_ctx->do_ram_collection_on_crash) {
for (i = 0; i < IPA_IU_SIZE / sizeof(u32); i++) {
ipa_reg_save.ipa.ipa_iu_ptr[i] =
in_dword(IPA_IU_ADDR + (i * sizeof(u32)));
in_dword(IPA_IU_ADDR + (i * sizeof(u32)),
REG_READ_PERM);
}
for (i = 0; i < IPA_SRAM_SIZE / sizeof(u32); i++) {
ipa_reg_save.ipa.ipa_sram_ptr[i] =
in_dword(IPA_SRAM_ADDR + (i * sizeof(u32)));
in_dword(IPA_SRAM_ADDR + (i * sizeof(u32)),
REG_READ_PERM);
}
for (i = 0; i < IPA_MBOX_SIZE / sizeof(u32); i++) {
ipa_reg_save.ipa.ipa_mbox_ptr[i] =
in_dword(IPA_MBOX_ADDR + (i * sizeof(u32)));
in_dword(IPA_MBOX_ADDR + (i * sizeof(u32)),
REG_READ_PERM);
}
for (i = 0; i < IPA_HRAM_SIZE / sizeof(u32); i++) {
ipa_reg_save.ipa.ipa_hram_ptr[i] =
in_dword(IPA_HRAM_ADDR + (i * sizeof(u32)));
in_dword(IPA_HRAM_ADDR + (i * sizeof(u32)),
REG_READ_PERM);
}
for (i = 0; i < IPA_SEQ_SIZE / sizeof(u32); i++) {
ipa_reg_save.ipa.ipa_seq_ptr[i] =
in_dword(IPA_SEQ_ADDR + (i * sizeof(u32)));
in_dword(IPA_SEQ_ADDR + (i * sizeof(u32)),
REG_READ_PERM);
}
for (i = 0; i < IPA_GSI_SIZE / sizeof(u32); i++) {
ipa_reg_save.ipa.ipa_gsi_ptr[i] =
in_dword(IPA_GSI_ADDR + (i * sizeof(u32)));
in_dword(IPA_GSI_ADDR + (i * sizeof(u32)),
REG_READ_PERM);
}
IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_iu_ptr);
IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_sram_ptr);
@@ -1373,8 +1663,9 @@ static void ipa_hal_save_regs_save_ipa_testbus(void)
sel_internal++) {
testbus_sel.value = 0;
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
testbus_sel.def.pipe_select = 0;
#endif
testbus_sel.def.external_block_select =
sel_external;
testbus_sel.def.internal_block_select =
@@ -1410,8 +1701,9 @@ static void ipa_hal_save_regs_save_ipa_testbus(void)
sel_internal++) {
testbus_sel.value = 0;
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
testbus_sel.def.pipe_select = sel_ep;
#endif
testbus_sel.def.external_block_select =
sel_external;
testbus_sel.def.internal_block_select =
@@ -1610,11 +1902,24 @@ static void ipa_reg_save_anomaly_check(void)
{
if ((ipa_reg_save.ipa.gen.ipa_state.rx_wait != 0)
|| (ipa_reg_save.ipa.gen.ipa_state.rx_idle != 1)) {
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
IPADBG(
"RX ACTIVITY, ipa_state.rx_wait = %d, ipa_state.rx_idle = %d, ipa_state_rx_active.endpoints = %d (bitmask)\n",
ipa_reg_save.ipa.gen.ipa_state.rx_wait,
ipa_reg_save.ipa.gen.ipa_state.rx_idle,
ipa_reg_save.ipa.gen.ipa_state_rx_active.endpoints);
#else
int i = 0;
for (i = 0; i < GEN_MAX_n(IPA_STATE_RX_ACTIVE_n) + 1; i++) {
IPADBG(
"RX ACTIVITY_%d, ipa_state.rx_wait = %d, ipa_state.rx_idle = %d, ipa_state_rx_active.endpoints = %d (bitmask)\n",
i,
ipa_reg_save.ipa.gen.ipa_state.rx_wait,
ipa_reg_save.ipa.gen.ipa_state.rx_idle,
ipa_reg_save.ipa.gen.ipa_state_rx_active_n[i].endpoints);
}
#endif
if (ipa_reg_save.ipa.gen.ipa_state.tx_idle != 1) {
IPADBG(
@@ -1622,11 +1927,12 @@ static void ipa_reg_save_anomaly_check(void)
ipa_reg_save.ipa.gen.ipa_state.tx_idle,
ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx0_idle,
ipa_reg_save.ipa.gen.ipa_state_tx_wrapper.tx1_idle);
#ifndef CONFIG_IPA3_REGDUMP_IPA_5_0
IPADBG(
"ipa_state_tx0.last_cmd_pipe = %d, ipa_state_tx1.last_cmd_pipe = %d\n",
ipa_reg_save.ipa.gen.ipa_state_tx0.last_cmd_pipe,
ipa_reg_save.ipa.gen.ipa_state_tx1.last_cmd_pipe);
#endif
}
}
}

760
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h
Переглянути файл

Різницю між файлами не показано, бо вона завелика Завантажити різницю

2
drivers/platform/msm/ipa/ipa_v3/ipa.c
Переглянути файл

@@ -6994,8 +6994,8 @@ static int ipa3_panic_notifier(struct notifier_block *this,
if (res) {
IPAERR("IPA clk off not saving the IPA registers\n");
} else {
ipahal_print_all_regs(false);
ipa_save_registers();
ipahal_print_all_regs(false);
ipa_wigig_save_regs();
}