Revert "video: driver: 5 percent increase for vsp and vpp cycles"
This reverts commit 4fa2fc8142ee7aa9da4bf2da7bb6ab52d634ab17. Change-Id: Iaa0156c0442fdbf928ba03aa2b833340601ff395 Signed-off-by: Akshata Sahukar <quic_asahukar@quicinc.com>
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@@ -83,16 +83,6 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
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if (inst->capabilities->cap[REQUEST_PREPROCESS].value)
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vpp_cycles = vpp_cycles + vpp_cycles / 2;
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if (res_is_greater_than(inst->crop.width, inst->crop.height,
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4096 + (4096 >> 1), 2176 + (2176 >> 1))) {
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/*
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* 8k@30 fps encode has a very low margin for sw/fw at 338MHz.
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* Hence, increase core clock little bit(5%) to move to the next
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* corner i.e., 366MHz.
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*/
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vpp_cycles = div_u64(vpp_cycles * 21, 20);
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}
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/* VSP */
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/* bitrate is based on fps, scale it using operating rate */
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operating_rate = inst->capabilities->cap[OPERATING_RATE].value >> 16;
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@@ -123,15 +113,6 @@ u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size)
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vsp_cycles += mbs_per_second * base_cycles;
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if (res_is_greater_than(inst->crop.width, inst->crop.height,
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4096 + (4096 >> 1), 2176 + (2176 >> 1))) {
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/*
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* 8k@30 fps encode has a very low margin for sw/fw at 338MHz.
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* Hence, increase core clock little bit(5%) to move to the next
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* corner i.e., 366MHz.
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*/
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vsp_cycles = div_u64(vsp_cycles * 21, 20);
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}
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} else if (inst->domain == MSM_VIDC_DECODER) {
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/* VPP */
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vpp_cycles = mbs_per_second * inst->capabilities->cap[MB_CYCLES_VPP].value /
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