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@@ -21,6 +21,7 @@
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#include "target_type.h"
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#include "wcss_version.h"
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#include "qdf_module.h"
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+
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#ifdef QCA_WIFI_QCA8074
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void hal_qca6290_attach(struct hal_soc *hal);
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#endif
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@@ -340,6 +341,338 @@ uint32_t hal_get_target_type(hal_soc_handle_t hal_soc_hdl)
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qdf_export_symbol(hal_get_target_type);
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+#ifdef FEATURE_HAL_DELAYED_REG_WRITE
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+#ifdef MEMORY_DEBUG
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+/*
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+ * Length of the queue(array) used to hold delayed register writes.
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+ * Must be a multiple of 2.
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+ */
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+#define HAL_REG_WRITE_QUEUE_LEN 128
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+#else
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+#define HAL_REG_WRITE_QUEUE_LEN 32
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+#endif
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+
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+/**
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+ * hal_is_reg_write_tput_level_high() - throughput level for delayed reg writes
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+ * @hal: hal_soc pointer
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+ *
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+ * Return: true if throughput is high, else false.
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+ */
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+static inline bool hal_is_reg_write_tput_level_high(struct hal_soc *hal)
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+{
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+ int bw_level = hif_get_bandwidth_level(hal->hif_handle);
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+
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+ return (bw_level >= PLD_BUS_WIDTH_MEDIUM) ? true : false;
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+}
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+
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+/**
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+ * hal_process_reg_write_q_elem() - process a regiter write queue element
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+ * @hal: hal_soc pointer
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+ * @q_elem: pointer to hal regiter write queue element
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+ *
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+ * Return: None
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+ */
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+static void hal_process_reg_write_q_elem(struct hal_soc *hal,
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+ struct hal_reg_write_q_elem *q_elem)
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+{
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+ struct hal_srng *srng = q_elem->srng;
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+
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+ SRNG_LOCK(&srng->lock);
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+
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+ srng->reg_write_in_progress = false;
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+ srng->wstats.dequeues++;
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+
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+ if (srng->ring_dir == HAL_SRNG_SRC_RING)
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+ hal_write_address_32_mb(hal,
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+ srng->u.src_ring.hp_addr,
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+ srng->u.src_ring.hp);
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+ else
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+ hal_write_address_32_mb(hal,
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+ srng->u.dst_ring.tp_addr,
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+ srng->u.dst_ring.tp);
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+
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+ SRNG_UNLOCK(&srng->lock);
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+}
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+
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+/**
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+ * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal
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+ * @hal: hal_soc pointer
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+ * @delay: delay in us
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+ *
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+ * Return: None
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+ */
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+static inline void hal_reg_write_fill_sched_delay_hist(struct hal_soc *hal,
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+ uint64_t delay_us)
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+{
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+ uint32_t *hist;
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+
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+ hist = hal->stats.wstats.sched_delay;
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+
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+ if (delay_us < 100)
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+ hist[REG_WRITE_SCHED_DELAY_SUB_100us]++;
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+ else if (delay_us < 1000)
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+ hist[REG_WRITE_SCHED_DELAY_SUB_1000us]++;
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+ else if (delay_us < 5000)
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+ hist[REG_WRITE_SCHED_DELAY_SUB_5000us]++;
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+ else
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+ hist[REG_WRITE_SCHED_DELAY_GT_5000us]++;
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+}
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+
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+/**
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+ * hal_reg_write_work() - Worker to process delayed writes
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+ * @arg: hal_soc pointer
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+ *
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+ * Return: None
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+ */
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+static void hal_reg_write_work(void *arg)
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+{
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+ int32_t q_depth;
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+ struct hal_soc *hal = arg;
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+ struct hal_reg_write_q_elem *q_elem;
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+ qdf_time_t delta_us;
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+
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+ q_elem = &hal->reg_write_queue[(hal->read_idx)];
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+
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+ if (!q_elem->valid)
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+ return;
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+
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+ q_depth = qdf_atomic_read(&hal->stats.wstats.q_depth);
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+ if (q_depth > hal->stats.wstats.max_q_depth)
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+ hal->stats.wstats.max_q_depth = q_depth;
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+
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+ if (hif_prevent_link_low_power_states(hal->hif_handle)) {
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+ hal->stats.wstats.prevent_l1_fails++;
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+ return;
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+ }
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+
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+ while (q_elem->valid) {
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+ q_elem->dequeue_time = qdf_get_log_timestamp();
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+ delta_us = qdf_log_timestamp_to_usecs(q_elem->dequeue_time -
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+ q_elem->enqueue_time);
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+ hal_reg_write_fill_sched_delay_hist(hal, delta_us);
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+ hal_verbose_debug("read_idx %u srng 0x%x, addr 0x%x val %u sched delay %u us",
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+ hal->read_idx,
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+ q_elem->srng->ring_id,
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+ q_elem->addr,
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+ q_elem->val,
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+ delta_us);
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+
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+ hal->stats.wstats.dequeues++;
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+ qdf_atomic_dec(&hal->stats.wstats.q_depth);
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+
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+ hal_process_reg_write_q_elem(hal, q_elem);
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+
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+ q_elem->valid = 0;
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+ hal->read_idx = (hal->read_idx + 1) &
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+ (HAL_REG_WRITE_QUEUE_LEN - 1);
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+ q_elem = &hal->reg_write_queue[(hal->read_idx)];
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+ }
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+
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+ hif_allow_link_low_power_states(hal->hif_handle);
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+}
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+
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+/**
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+ * hal_flush_reg_write_work() - flush all writes from regiter write queue
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+ * @arg: hal_soc pointer
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+ *
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+ * Return: None
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+ */
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+static inline void hal_flush_reg_write_work(struct hal_soc *hal)
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+{
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+ qdf_cancel_work(&hal->reg_write_work);
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+ qdf_flush_work(&hal->reg_write_work);
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+ qdf_flush_workqueue(0, hal->reg_write_wq);
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+}
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+
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+/**
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+ * hal_reg_write_enqueue() - enqueue register writes into kworker
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+ * @hal_soc: hal_soc pointer
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+ * @srng: srng pointer
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+ * @addr: iomem address of regiter
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+ * @value: value to be written to iomem address
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+ *
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+ * This function executes from within the SRNG LOCK
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+ *
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+ * Return: None
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+ */
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+static void hal_reg_write_enqueue(struct hal_soc *hal_soc,
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+ struct hal_srng *srng,
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+ void __iomem *addr,
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+ uint32_t value)
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+{
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+ struct hal_reg_write_q_elem *q_elem;
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+ uint32_t write_idx;
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+
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+ if (srng->reg_write_in_progress) {
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+ hal_verbose_debug("Already in progress srng ring id 0x%x addr 0x%x val %u",
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+ srng->ring_id, addr, value);
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+ qdf_atomic_inc(&hal_soc->stats.wstats.coalesces);
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+ srng->wstats.coalesces++;
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+ return;
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+ }
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+
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+ write_idx = qdf_atomic_inc_return(&hal_soc->write_idx);
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+
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+ write_idx = write_idx & (HAL_REG_WRITE_QUEUE_LEN - 1);
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+
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+ q_elem = &hal_soc->reg_write_queue[write_idx];
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+
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+ if (q_elem->valid) {
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+ hal_err("queue full");
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+ QDF_BUG(0);
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+ return;
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+ }
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+
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+ qdf_atomic_inc(&hal_soc->stats.wstats.enqueues);
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+ srng->wstats.enqueues++;
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+
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+ qdf_atomic_inc(&hal_soc->stats.wstats.q_depth);
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+
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+ q_elem->srng = srng;
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+ q_elem->addr = addr;
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+ q_elem->val = value;
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+ q_elem->enqueue_time = qdf_get_log_timestamp();
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+
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+ q_elem->valid = true;
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+
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+ srng->reg_write_in_progress = true;
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+
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+ hal_verbose_debug("write_idx %u srng ring id 0x%x addr 0x%x val %u",
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+ write_idx, srng->ring_id, addr, value);
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+
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+ qdf_queue_work(hal_soc->qdf_dev, hal_soc->reg_write_wq,
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+ &hal_soc->reg_write_work);
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+}
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+
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+void hal_delayed_reg_write(struct hal_soc *hal_soc,
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+ struct hal_srng *srng,
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+ void __iomem *addr,
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+ uint32_t value)
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+{
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+ if (pld_is_device_awake(hal_soc->qdf_dev->dev) ||
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+ hal_is_reg_write_tput_level_high(hal_soc)) {
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+ qdf_atomic_inc(&hal_soc->stats.wstats.direct);
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+ srng->wstats.direct++;
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+ hal_write_address_32_mb(hal_soc, addr, value);
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+ } else {
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+ hal_reg_write_enqueue(hal_soc, srng, addr, value);
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+ }
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+}
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+
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+/**
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+ * hal_delayed_reg_write_init() - Initialization function for delayed reg writes
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+ * @hal_soc: hal_soc pointer
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+ *
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+ * Initialize main data structures to process register writes in a delayed
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+ * workqueue.
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+ *
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+ * Return: QDF_STATUS_SUCCESS on success else a QDF error.
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+ */
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+static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
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+{
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+ hal->reg_write_wq =
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+ qdf_alloc_high_prior_ordered_workqueue("hal_register_write_wq");
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+ qdf_create_work(0, &hal->reg_write_work, hal_reg_write_work, hal);
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+ hal->reg_write_queue = qdf_mem_malloc(HAL_REG_WRITE_QUEUE_LEN *
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+ sizeof(*hal->reg_write_queue));
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+ if (!hal->reg_write_queue) {
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+ hal_err("unable to allocate memory");
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+ QDF_BUG(0);
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+ return QDF_STATUS_E_NOMEM;
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+ }
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+
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+ /* Initial value of indices */
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+ hal->read_idx = 0;
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+ qdf_atomic_set(&hal->write_idx, -1);
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+ return QDF_STATUS_SUCCESS;
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+}
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+
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+/**
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+ * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing
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+ * @hal_soc: hal_soc pointer
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+ *
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+ * De-initialize main data structures to process register writes in a delayed
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+ * workqueue.
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+ *
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+ * Return: None
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+ */
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+static void hal_delayed_reg_write_deinit(struct hal_soc *hal)
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+{
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+ hal_flush_reg_write_work(hal);
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+ qdf_destroy_workqueue(0, hal->reg_write_wq);
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+ qdf_mem_free(hal->reg_write_queue);
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+}
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+
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+static inline
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+char *hal_fill_reg_write_srng_stats(struct hal_srng *srng,
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+ char *buf, qdf_size_t size)
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+{
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+ qdf_scnprintf(buf, size, "enq %u deq %u coal %u direct %u",
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+ srng->wstats.enqueues, srng->wstats.dequeues,
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+ srng->wstats.coalesces, srng->wstats.direct);
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+ return buf;
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+}
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+
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+/* bytes for local buffer */
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+#define HAL_REG_WRITE_SRNG_STATS_LEN 100
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+
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+void hal_dump_reg_write_srng_stats(hal_soc_handle_t hal_soc_hdl)
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+{
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+ struct hal_srng *srng;
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+ char buf[HAL_REG_WRITE_SRNG_STATS_LEN];
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+ struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
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+
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+ srng = hal_get_srng(hal, HAL_SRNG_SW2TCL1);
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+ hal_debug("SW2TCL1: %s",
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+ hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
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+
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+ srng = hal_get_srng(hal, HAL_SRNG_WBM2SW0_RELEASE);
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+ hal_debug("WBM2SW0: %s",
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+ hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
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+
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+ srng = hal_get_srng(hal, HAL_SRNG_REO2SW1);
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+ hal_debug("REO2SW1: %s",
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+ hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
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+
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+ srng = hal_get_srng(hal, HAL_SRNG_REO2SW2);
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+ hal_debug("REO2SW2: %s",
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+ hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
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+
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+ srng = hal_get_srng(hal, HAL_SRNG_REO2SW3);
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+ hal_debug("REO2SW3: %s",
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+ hal_fill_reg_write_srng_stats(srng, buf, sizeof(buf)));
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+}
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+
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+void hal_dump_reg_write_stats(hal_soc_handle_t hal_soc_hdl)
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+{
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+ uint32_t *hist;
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+ struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
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+
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+ hist = hal->stats.wstats.sched_delay;
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+
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+ hal_debug("enq %u deq %u coal %u direct %u q_depth %u max_q %u sched-delay hist %u %u %u %u",
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+ qdf_atomic_read(&hal->stats.wstats.enqueues),
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+ hal->stats.wstats.dequeues,
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+ qdf_atomic_read(&hal->stats.wstats.coalesces),
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+ qdf_atomic_read(&hal->stats.wstats.direct),
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+ qdf_atomic_read(&hal->stats.wstats.q_depth),
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+ hal->stats.wstats.max_q_depth,
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+ hist[REG_WRITE_SCHED_DELAY_SUB_100us],
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+ hist[REG_WRITE_SCHED_DELAY_SUB_1000us],
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+ hist[REG_WRITE_SCHED_DELAY_SUB_5000us],
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+ hist[REG_WRITE_SCHED_DELAY_GT_5000us]);
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+}
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+#else
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+static inline QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
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+{
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+ return QDF_STATUS_SUCCESS;
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+}
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+
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+static inline void hal_delayed_reg_write_deinit(struct hal_soc *hal)
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+{
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+}
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+#endif
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+
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/**
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* hal_attach - Initialize HAL layer
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* @hif_handle: Opaque HIF handle
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@@ -402,7 +735,9 @@ void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
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hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal));
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hal_target_based_configure(hal);
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+
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hal_reg_write_fail_history_init(hal);
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+
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/**
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* Indicate Initialization of srngs to avoid force wake
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* as umac power collapse is not enabled yet
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@@ -411,6 +746,8 @@ void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
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qdf_minidump_log(hal, sizeof(*hal), "hal_soc");
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+ hal_delayed_reg_write_init(hal);
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+
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return (void *)hal;
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fail2:
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@@ -459,6 +796,8 @@ extern void hal_detach(void *hal_soc)
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{
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struct hal_soc *hal = (struct hal_soc *)hal_soc;
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+ hal_delayed_reg_write_deinit(hal);
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+
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qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
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sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,
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hal->shadow_rdptr_mem_vaddr, hal->shadow_rdptr_mem_paddr, 0);
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Mohit Khanna