qcacmn: add new files for HAL v2

add hal v2 new files

Change-Id: I7728be33db7d28e44d04f19c99e8b9f47145f2e3
CRs-Fixed: 3249002

hal/wifi3.0/be/hal_be_generic_api.h

@@ -3137,4 +3137,141 @@ void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
 	}
 }
 
+/**
+ * hal_tx_populate_bank_register() - populate the bank register with
+ *		the software configs.
+ * @soc: HAL soc handle
+ * @config: bank config
+ * @bank_id: bank id to be configured
+ *
+ * Returns: None
+ */
+#ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
+static inline void
+hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
+				 union hal_tx_bank_config *config,
+				 uint8_t bank_id)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+	uint32_t reg_addr, reg_val = 0;
+
+	reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
+						     bank_id);
+
+	reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
+	reg_val |= (config->encap_type <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
+	reg_val |= (config->encrypt_type <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
+	reg_val |= (config->src_buffer_swap <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
+	reg_val |= (config->link_meta_swap <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
+	reg_val |= (config->index_lookup_enable <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
+	reg_val |= (config->addrx_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
+	reg_val |= (config->addry_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
+	reg_val |= (config->mesh_enable <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
+	reg_val |= (config->vdev_id_check_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
+	reg_val |= (config->pmac_id <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
+	reg_val |= (config->mcast_pkt_ctrl <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
+
+	HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
+}
+#else
+static inline void
+hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
+				 union hal_tx_bank_config *config,
+				 uint8_t bank_id)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+	uint32_t reg_addr, reg_val = 0;
+
+	reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
+						     bank_id);
+
+	reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
+	reg_val |= (config->encap_type <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
+	reg_val |= (config->encrypt_type <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
+	reg_val |= (config->src_buffer_swap <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
+	reg_val |= (config->link_meta_swap <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
+	reg_val |= (config->index_lookup_enable <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
+	reg_val |= (config->addrx_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
+	reg_val |= (config->addry_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
+	reg_val |= (config->mesh_enable <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
+	reg_val |= (config->vdev_id_check_en <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
+	reg_val |= (config->pmac_id <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
+	reg_val |= (config->dscp_tid_map_id <<
+			HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
+
+	HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
+}
+#endif
+
+
+#ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
+
+#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
+#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
+#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
+#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
+
+/**
+ * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value
+ * @hal_soc: HAL SoC context
+ * @mcast_ctrl_val: mcast ctrl value for this VAP
+ *
+ * Return: void
+ */
+static inline void
+hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
+			      uint8_t vdev_id, uint8_t mcast_ctrl_val)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+	uint32_t reg_addr, reg_val = 0;
+	uint32_t val;
+	uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
+	uint8_t index_in_reg =
+		HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
+
+	reg_addr =
+	HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
+						      reg_idx);
+
+	val = HAL_REG_READ(hal_soc, reg_addr);
+
+	/* mask out other stored value */
+	val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
+		  (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
+
+	reg_val = val |
+		((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
+		 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
+
+	HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
+}
+#else
+static inline void
+hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
+			      uint8_t vdev_id, uint8_t mcast_ctrl_val)
+{
+}
+#endif
+
 #endif /* _HAL_BE_GENERIC_API_H_ */

hal/wifi3.0/be/hal_be_tx.h

@@ -627,83 +627,16 @@ hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl)
  *
  * Returns: None
  */
-#ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
 static inline void
 hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
 			      union hal_tx_bank_config *config,
 			      uint8_t bank_id)
 {
 	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
-	uint32_t reg_addr, reg_val = 0;
-
-	reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
-						     bank_id);
-
-	reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
-	reg_val |= (config->encap_type <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
-	reg_val |= (config->encrypt_type <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
-	reg_val |= (config->src_buffer_swap <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
-	reg_val |= (config->link_meta_swap <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
-	reg_val |= (config->index_lookup_enable <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
-	reg_val |= (config->addrx_en <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
-	reg_val |= (config->addry_en <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
-	reg_val |= (config->mesh_enable <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
-	reg_val |= (config->vdev_id_check_en <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
-	reg_val |= (config->pmac_id <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
-	reg_val |= (config->mcast_pkt_ctrl <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
-
-	HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
-}
-#else
-static inline void
-hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
-			      union hal_tx_bank_config *config,
-			      uint8_t bank_id)
-{
-	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
-	uint32_t reg_addr, reg_val = 0;
-
-	reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
-						     bank_id);
-
-	reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
-	reg_val |= (config->encap_type <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
-	reg_val |= (config->encrypt_type <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
-	reg_val |= (config->src_buffer_swap <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
-	reg_val |= (config->link_meta_swap <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
-	reg_val |= (config->index_lookup_enable <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
-	reg_val |= (config->addrx_en <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
-	reg_val |= (config->addry_en <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
-	reg_val |= (config->mesh_enable <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
-	reg_val |= (config->vdev_id_check_en <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
-	reg_val |= (config->pmac_id <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
-	reg_val |= (config->dscp_tid_map_id <<
-			HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
-
-	HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
+
+	hal_soc->ops->hal_tx_populate_bank_register(hal_soc_hdl, config,
+						    bank_id);
 }
-#endif
 
 #ifdef DP_TX_IMPLICIT_RBM_MAPPING
 
@@ -817,57 +750,6 @@ hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
 }
 #endif
 
-#ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
-
-#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
-#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
-#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
-#define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
-
-/**
- * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value
- * @hal_soc: HAL SoC context
- * @mcast_ctrl_val: mcast ctrl value for this VAP
- *
- * Return: void
- */
-static inline void
-hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
-			   uint8_t vdev_id,
-			   uint8_t mcast_ctrl_val)
-{
-	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
-	uint32_t reg_addr, reg_val = 0;
-	uint32_t val;
-	uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
-	uint8_t index_in_reg =
-		HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
-
-	reg_addr =
-	HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
-						      reg_idx);
-
-	val = HAL_REG_READ(hal_soc, reg_addr);
-
-	/* mask out other stored value */
-	val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
-		  (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
-
-	reg_val = val |
-		((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
-		 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
-
-	HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
-}
-#else
-static inline void
-hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
-			   uint8_t vdev_id,
-			   uint8_t mcast_ctrl_val)
-{
-}
-#endif
-
 /**
  * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing
  * @hal_soc: HAL SoC context
@@ -1032,4 +914,22 @@ hal_tx_enable_pri2tid_map(hal_soc_handle_t hal_soc_hdl, bool val,
 	hal_soc->ops->hal_tx_enable_pri2tid_map(hal_soc_hdl, val,
 						ppe_vp_idx);
 }
+
+#ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
+static inline void
+hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
+		uint8_t vdev_id, uint8_t mcast_ctrl_val)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	hal_soc->ops->hal_tx_vdev_mcast_ctrl_set(hal_soc_hdl, vdev_id,
+						 mcast_ctrl_val);
+}
+#else
+static inline void
+hal_tx_vdev_mcast_ctrl_set(hal_soc_handle_t hal_soc_hdl,
+		uint8_t vdev_id, uint8_t mcast_ctrl_val)
+{
+}
+#endif
 #endif /* _HAL_BE_TX_H_ */

hal/wifi3.0/hal_internal.h

@@ -164,6 +164,7 @@ typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t;
  */
 union hal_tx_ppe_vp_config;
 union hal_tx_cmn_config_ppe;
+union hal_tx_bank_config;
 
 /* TBD: This should be movded to shared HW header file */
 enum hal_srng_ring_id {
@@ -1173,6 +1174,12 @@ struct hal_hw_txrx_ops {
 	void (*hal_cookie_conversion_reg_cfg_be)(hal_soc_handle_t hal_soc_hdl,
 						 struct hal_hw_cc_config
 						 *cc_cfg);
+	void (*hal_tx_populate_bank_register)(hal_soc_handle_t hal_soc_hdl,
+					      union hal_tx_bank_config *config,
+					      uint8_t bank_id);
+	void (*hal_tx_vdev_mcast_ctrl_set)(hal_soc_handle_t hal_soc_hdl,
+					   uint8_t vdev_id,
+					   uint8_t mcast_ctrl_val);
 };
 
 /**
@@ -1297,6 +1304,7 @@ struct hal_soc {
 	uint8_t reo_res_bitmap;
 	uint8_t index;
 	uint32_t target_type;
+	uint32_t version;
 
 	/* shadow register configuration */
 	union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS];
@@ -1366,7 +1374,8 @@ void hal_qca6390_attach(struct hal_soc *hal_soc);
 void hal_qca6290_attach(struct hal_soc *hal_soc);
 void hal_qca8074_attach(struct hal_soc *hal_soc);
 void hal_kiwi_attach(struct hal_soc *hal_soc);
-void hal_qcn9224_attach(struct hal_soc *hal_soc);
+void hal_qcn9224v1_attach(struct hal_soc *hal_soc);
+void hal_qcn9224v2_attach(struct hal_soc *hal_soc);
 /*
  * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque
  * dp_hal_soc handle type

hal/wifi3.0/hal_srng.c

@@ -47,7 +47,8 @@ void hal_qca6490_attach(struct hal_soc *hal);
 void hal_qcn9000_attach(struct hal_soc *hal);
 #endif
 #ifdef QCA_WIFI_QCN9224
-void hal_qcn9224_attach(struct hal_soc *hal);
+void hal_qcn9224v1_attach(struct hal_soc *hal);
+void hal_qcn9224v2_attach(struct hal_soc *hal);
 #endif
 #ifdef QCA_WIFI_QCN6122
 void hal_qcn6122_attach(struct hal_soc *hal);
@@ -506,7 +507,10 @@ static void hal_target_based_configure(struct hal_soc *hal)
 	case TARGET_TYPE_QCN9224:
 		hal->use_register_windowing = true;
 		hal->static_window_map = true;
-		hal_qcn9224_attach(hal);
+		if (hal->version == 1)
+			hal_qcn9224v1_attach(hal);
+		else
+			hal_qcn9224v2_attach(hal);
 	break;
 #endif
 #ifdef QCA_WIFI_QCA5332
@@ -1097,6 +1101,7 @@ void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
 	qdf_spinlock_create(&hal->register_access_lock);
 	hal->register_window = 0;
 	hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal));
+	hal->version = hif_get_soc_version(hif_handle);
 	hal->ops = qdf_mem_malloc(sizeof(*hal->ops));
 
 	if (!hal->ops) {

hal/wifi3.0/hal_tx.h

@@ -316,6 +316,8 @@ enum hal_tx_encap_type {
  * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available
  * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow
  * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV
+ * @HAL_TX_TQM_RR_VDEV_MISMATCH_DROP: Dropped due to being set with
+ *				'TCL_drop_reason'
  *
  */
 enum hal_tx_tqm_release_reason {
@@ -333,6 +335,7 @@ enum hal_tx_tqm_release_reason {
 	HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE,
 	HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU,
 	HAL_TX_TQM_RR_MULTICAST_DROP,
+	HAL_TX_TQM_RR_VDEV_MISMATCH_DROP,
 };
 
 /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports

hal/wifi3.0/kiwi/hal_kiwi.c

@@ -2073,6 +2073,10 @@ static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc)
 		hal_cookie_conversion_reg_cfg_generic_be;
 	hal_soc->ops->hal_set_ba_aging_timeout =
 		hal_set_ba_aging_timeout_be_generic;
+	hal_soc->ops->hal_tx_populate_bank_register =
+		hal_tx_populate_bank_register_be;
+	hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
+		hal_tx_vdev_mcast_ctrl_set_be;
 };
 
 struct hal_hw_srng_config hw_srng_table_kiwi[] = {

hal/wifi3.0/qca5332/hal_5332.c

@@ -1925,6 +1925,10 @@ static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc)
 		hal_cookie_conversion_reg_cfg_generic_be;
 	hal_soc->ops->hal_set_ba_aging_timeout =
 		hal_set_ba_aging_timeout_be_generic;
+	hal_soc->ops->hal_tx_populate_bank_register =
+		hal_tx_populate_bank_register_be;
+	hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
+		hal_tx_vdev_mcast_ctrl_set_be;
 };
 
 struct hal_hw_srng_config hw_srng_table_5332[] = {

hal/wifi3.0/qcn9224/hal_9224.c → hal/wifi3.0/qcn9224/hal_9224.h

@@ -694,6 +694,7 @@ static uint8_t hal_rx_get_tlv_9224(void *rx_tlv)
  *
  * Return: true if msdu continuation bit is set.
  */
+static inline
 uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc)
 {
 	uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
@@ -1981,536 +1982,10 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
 		hal_cookie_conversion_reg_cfg_generic_be;
 	hal_soc->ops->hal_set_ba_aging_timeout =
 		hal_set_ba_aging_timeout_be_generic;
-};
-
-struct hal_hw_srng_config hw_srng_table_9224[] = {
-	/* TODO: max_rings can populated by querying HW capabilities */
-	{ /* REO_DST */
-		.start_ring_id = HAL_SRNG_REO2SW1,
-		.max_rings = 8,
-		.entry_size = sizeof(struct reo_destination_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
-				REO_REG_REG_BASE)
-		},
-		.reg_size = {
-			HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
-				HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
-			HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
-				HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
-		},
-		.max_size =
-			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* REO_EXCEPTION */
-		/* Designating REO2SW0 ring as exception ring. This ring is
-		 * similar to other REO2SW rings though it is named as REO2SW0.
-		 * Any of theREO2SW rings can be used as exception ring.
-		 */
-		.start_ring_id = HAL_SRNG_REO2SW0,
-		.max_rings = 1,
-		.entry_size = sizeof(struct reo_destination_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
-				REO_REG_REG_BASE)
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* REO_REINJECT */
-		.start_ring_id = HAL_SRNG_SW2REO,
-		.max_rings = 4,
-		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_SW2REO_RING_HP_ADDR(
-				REO_REG_REG_BASE)
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {
-			HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
-				HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
-			HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
-				HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
-		},
-		.max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
-				HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* REO_CMD */
-		.start_ring_id = HAL_SRNG_REO_CMD,
-		.max_rings = 1,
-		.entry_size = (sizeof(struct tlv_32_hdr) +
-			sizeof(struct reo_get_queue_stats)) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
-				REO_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* REO_STATUS */
-		.start_ring_id = HAL_SRNG_REO_STATUS,
-		.max_rings = 1,
-		.entry_size = (sizeof(struct tlv_32_hdr) +
-			sizeof(struct reo_get_queue_stats_status)) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
-				REO_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-		HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* TCL_DATA */
-		.start_ring_id = HAL_SRNG_SW2TCL1,
-		.max_rings = 6,
-		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
-				MAC_TCL_REG_REG_BASE),
-			HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
-				MAC_TCL_REG_REG_BASE),
-		},
-		.reg_size = {
-			HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
-				HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
-			HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
-				HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
-		},
-		.max_size =
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* TCL_CMD/CREDIT */
-	  /* qca8074v2 and qcn9224 uses this ring for data commands */
-		.start_ring_id = HAL_SRNG_SW2TCL_CMD,
-		.max_rings = 1,
-		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
-		.lmac_ring =  FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
-				MAC_TCL_REG_REG_BASE),
-			HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
-				MAC_TCL_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* TCL_STATUS */
-		.start_ring_id = HAL_SRNG_TCL_STATUS,
-		.max_rings = 1,
-		.entry_size = (sizeof(struct tlv_32_hdr) +
-			sizeof(struct tcl_status_ring)) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
-				MAC_TCL_REG_REG_BASE),
-			HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
-				MAC_TCL_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* CE_SRC */
-		.start_ring_id = HAL_SRNG_CE_0_SRC,
-		.max_rings = 16,
-		.entry_size = sizeof(struct ce_src_desc) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
-				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
-		HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
-				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
-		},
-		.reg_size = {
-		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
-		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
-		},
-		.max_size =
-		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* CE_DST */
-		.start_ring_id = HAL_SRNG_CE_0_DST,
-		.max_rings = 16,
-		.entry_size = 8 >> 2,
-		/*TODO: entry_size above should actually be
-		 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
-		 * of struct ce_dst_desc in HW header files
-		 */
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
-		HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
-		},
-		.reg_size = {
-		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
-		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
-		},
-		.max_size =
-		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* CE_DST_STATUS */
-		.start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
-		.max_rings = 16,
-		.entry_size = sizeof(struct ce_stat_desc) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
-				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
-		HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
-				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
-		},
-		/* TODO: check destination status ring registers */
-		.reg_size = {
-		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
-		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
-		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
-		},
-		.max_size =
-	HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* WBM_IDLE_LINK */
-		.start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
-		.max_rings = 1,
-		.entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
-		HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* SW2WBM_RELEASE */
-		.start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
-		.max_rings = 2,
-		.entry_size = sizeof(struct wbm_release_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
-		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
-		},
-		.reg_size = {
-		HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) -
-		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
-		HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) -
-		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE)
-		},
-		.max_size =
-		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* WBM2SW_RELEASE */
-		.start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
-		.max_rings = 8,
-		.entry_size = sizeof(struct wbm_release_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
-				WBM_REG_REG_BASE),
-		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
-				WBM_REG_REG_BASE),
-		},
-		.reg_size = {
-		HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
-				WBM_REG_REG_BASE) -
-		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
-				WBM_REG_REG_BASE),
-		HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
-				WBM_REG_REG_BASE) -
-		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
-				WBM_REG_REG_BASE),
-		},
-		.max_size =
-		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* RXDMA_BUF */
-		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
-#ifdef IPA_OFFLOAD
-		.max_rings = 3,
-#else
-		.max_rings = 3,
-#endif
-		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE,
-	},
-	{ /* RXDMA_DST */
-		.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
-		.max_rings = 0,
-		.entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
-		.lmac_ring =  TRUE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE,
-	},
-#ifdef QCA_MONITOR_2_0_SUPPORT
-	{ /* RXDMA_MONITOR_BUF */
-		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
-		.max_rings = 1,
-		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-#else
-	{},
-#endif
-	{ /* RXDMA_MONITOR_STATUS */
-		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
-		.max_rings = 0,
-		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE,
-	},
-#ifdef QCA_MONITOR_2_0_SUPPORT
-	{ /* RXDMA_MONITOR_DST */
-		.start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
-		.max_rings = 2,
-		.entry_size = sizeof(struct mon_destination_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-#else
-	{},
-#endif
-	{ /* RXDMA_MONITOR_DESC */
-		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
-		.max_rings = 0,
-		.entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-
-	{ /* DIR_BUF_RX_DMA_SRC */
-		.start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
-		/* one ring for spectral and one ring for cfr */
-		.max_rings = 2,
-		.entry_size = 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE,
-	},
-#ifdef WLAN_FEATURE_CIF_CFR
-	{ /* WIFI_POS_SRC */
-		.start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
-		.max_rings = 1,
-		.entry_size = sizeof(wmi_oem_dma_buf_release_entry)  >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-#endif
-	{ /* REO2PPE */
-		.start_ring_id = HAL_SRNG_REO2PPE,
-		.max_rings = 1,
-		.entry_size = sizeof(struct reo_destination_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		.reg_start = {
-			HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(
-				REO_REG_REG_BASE),
-			HWIO_REO_R2_REO2PPE_RING_HP_ADDR(
-				REO_REG_REG_BASE),
-		},
-		/* Single ring - provide ring size if multiple rings of this
-		 * type are supported
-		 */
-		.reg_size = {},
-		.max_size =
-		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >>
-		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT,
-	},
-	{ /* PPE2TCL */
-		.start_ring_id = HAL_SRNG_PPE2TCL1,
-		.max_rings = 1,
-		.entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-			HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(
-				MAC_TCL_REG_REG_BASE),
-			HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(
-				MAC_TCL_REG_REG_BASE),
-		},
-		.reg_size = {},
-		.max_size =
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
-			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-	{ /* PPE_RELEASE */
-		.start_ring_id = HAL_SRNG_WBM_PPE_RELEASE,
-		.max_rings = 1,
-		.entry_size = sizeof(struct wbm_release_ring) >> 2,
-		.lmac_ring = FALSE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		.reg_start = {
-		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
-		HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
-		},
-		.reg_size = {},
-		.max_size =
-		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
-		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
-	},
-#ifdef QCA_MONITOR_2_0_SUPPORT
-	{ /* TX_MONITOR_BUF */
-		.start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
-		.max_rings = 1,
-		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-	{ /* TX_MONITOR_DST */
-		.start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
-		.max_rings = 2,
-		.entry_size = sizeof(struct mon_destination_ring) >> 2,
-		.lmac_ring = TRUE,
-		.ring_dir = HAL_SRNG_DST_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
-#else
-	{},
-	{},
-#endif
-	{ /* SW2RXDMA */
-		.start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
-		.max_rings = 3,
-		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
-		.lmac_ring =  TRUE,
-		.ring_dir = HAL_SRNG_SRC_RING,
-		/* reg_start is not set because LMAC rings are not accessed
-		 * from host
-		 */
-		.reg_start = {},
-		.reg_size = {},
-		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
-	},
+	hal_soc->ops->hal_tx_populate_bank_register =
+		hal_tx_populate_bank_register_be;
+	hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
+		hal_tx_vdev_mcast_ctrl_set_be;
 };
 
 /**
@@ -2530,22 +2005,3 @@ static inline void hal_srng_hw_reg_offset_init_qcn9224(struct hal_soc *hal_soc)
 	hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
 					REG_OFFSET(DST, PRODUCER_INT2_SETUP);
 }
-
-/**
- * hal_qcn9224_attach()- Attach 9224 target specific hal_soc ops,
- *			  offset and srng table
- * Return: void
- */
-void hal_qcn9224_attach(struct hal_soc *hal_soc)
-{
-	hal_soc->hw_srng_table = hw_srng_table_9224;
-
-	hal_srng_hw_reg_offset_init_generic(hal_soc);
-	hal_srng_hw_reg_offset_init_qcn9224(hal_soc);
-
-	hal_hw_txrx_default_ops_attach_be(hal_soc);
-	hal_hw_txrx_ops_attach_qcn9224(hal_soc);
-	if (hal_soc->static_window_map)
-		hal_write_window_register(hal_soc);
-	hal_soc->dmac_cmn_src_rxbuf_ring = true;
-}

hal/wifi3.0/qcn9224/v1/hal_9224v1.c

@@ -0,0 +1,566 @@
+/*
+ * Copyright (c) 2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "hal_9224.h"
+
+struct hal_hw_srng_config hw_srng_table_9224v1[] = {
+	/* TODO: max_rings can populated by querying HW capabilities */
+	{ /* REO_DST */
+		.start_ring_id = HAL_SRNG_REO2SW1,
+		.max_rings = 8,
+		.entry_size = sizeof(struct reo_destination_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
+				REO_REG_REG_BASE)
+		},
+		.reg_size = {
+			HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
+				HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
+			HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
+				HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
+		},
+		.max_size =
+			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_EXCEPTION */
+		/* Designating REO2SW0 ring as exception ring. This ring is
+		 * similar to other REO2SW rings though it is named as REO2SW0.
+		 * Any of theREO2SW rings can be used as exception ring.
+		 */
+		.start_ring_id = HAL_SRNG_REO2SW0,
+		.max_rings = 1,
+		.entry_size = sizeof(struct reo_destination_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
+				REO_REG_REG_BASE)
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_REINJECT */
+		.start_ring_id = HAL_SRNG_SW2REO,
+		.max_rings = 4,
+		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_SW2REO_RING_HP_ADDR(
+				REO_REG_REG_BASE)
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {
+			HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
+				HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
+			HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
+				HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
+		},
+		.max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
+				HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_CMD */
+		.start_ring_id = HAL_SRNG_REO_CMD,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct reo_get_queue_stats)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
+				REO_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_STATUS */
+		.start_ring_id = HAL_SRNG_REO_STATUS,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct reo_get_queue_stats_status)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
+				REO_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_DATA */
+		.start_ring_id = HAL_SRNG_SW2TCL1,
+		.max_rings = 6,
+		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
+				MAC_TCL_REG_REG_BASE),
+			HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
+				MAC_TCL_REG_REG_BASE),
+		},
+		.reg_size = {
+			HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
+				HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
+			HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
+				HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
+		},
+		.max_size =
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_CMD/CREDIT */
+	  /* qca8074v2 and qcn9224 uses this ring for data commands */
+		.start_ring_id = HAL_SRNG_SW2TCL_CMD,
+		.max_rings = 1,
+		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
+		.lmac_ring =  FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
+				MAC_TCL_REG_REG_BASE),
+			HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
+				MAC_TCL_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_STATUS */
+		.start_ring_id = HAL_SRNG_TCL_STATUS,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct tcl_status_ring)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
+				MAC_TCL_REG_REG_BASE),
+			HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
+				MAC_TCL_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_SRC */
+		.start_ring_id = HAL_SRNG_CE_0_SRC,
+		.max_rings = 16,
+		.entry_size = sizeof(struct ce_src_desc) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
+				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
+		HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
+				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
+		},
+		.reg_size = {
+		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
+		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
+		},
+		.max_size =
+		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_DST */
+		.start_ring_id = HAL_SRNG_CE_0_DST,
+		.max_rings = 16,
+		.entry_size = 8 >> 2,
+		/*TODO: entry_size above should actually be
+		 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
+		 * of struct ce_dst_desc in HW header files
+		 */
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
+		HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
+		},
+		.reg_size = {
+		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
+		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
+		},
+		.max_size =
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_DST_STATUS */
+		.start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
+		.max_rings = 16,
+		.entry_size = sizeof(struct ce_stat_desc) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
+				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
+		HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
+				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
+		},
+		/* TODO: check destination status ring registers */
+		.reg_size = {
+		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
+		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
+		},
+		.max_size =
+	HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* WBM_IDLE_LINK */
+		.start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
+		HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* SW2WBM_RELEASE */
+		.start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
+		.max_rings = 2,
+		.entry_size = sizeof(struct wbm_release_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
+		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
+		},
+		.reg_size = {
+		HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) -
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
+		HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) -
+		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE)
+		},
+		.max_size =
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* WBM2SW_RELEASE */
+		.start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
+		.max_rings = 8,
+		.entry_size = sizeof(struct wbm_release_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
+				WBM_REG_REG_BASE),
+		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
+				WBM_REG_REG_BASE),
+		},
+		.reg_size = {
+		HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
+				WBM_REG_REG_BASE) -
+		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
+				WBM_REG_REG_BASE),
+		HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
+				WBM_REG_REG_BASE) -
+		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
+				WBM_REG_REG_BASE),
+		},
+		.max_size =
+		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* RXDMA_BUF */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
+#ifdef IPA_OFFLOAD
+		.max_rings = 3,
+#else
+		.max_rings = 3,
+#endif
+		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+	{ /* RXDMA_DST */
+		.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
+		.max_rings = 0,
+		.entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
+		.lmac_ring =  TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+#ifdef QCA_MONITOR_2_0_SUPPORT
+	{ /* RXDMA_MONITOR_BUF */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
+		.max_rings = 1,
+		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+#else
+	{},
+#endif
+	{ /* RXDMA_MONITOR_STATUS */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
+		.max_rings = 0,
+		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+#ifdef QCA_MONITOR_2_0_SUPPORT
+	{ /* RXDMA_MONITOR_DST */
+		.start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
+		.max_rings = 2,
+		.entry_size = sizeof(struct mon_destination_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+#else
+	{},
+#endif
+	{ /* RXDMA_MONITOR_DESC */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
+		.max_rings = 0,
+		.entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+
+	{ /* DIR_BUF_RX_DMA_SRC */
+		.start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
+		/* one ring for spectral and one ring for cfr */
+		.max_rings = 2,
+		.entry_size = 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+#ifdef WLAN_FEATURE_CIF_CFR
+	{ /* WIFI_POS_SRC */
+		.start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
+		.max_rings = 1,
+		.entry_size = sizeof(wmi_oem_dma_buf_release_entry)  >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+#endif
+	{ /* REO2PPE */
+		.start_ring_id = HAL_SRNG_REO2PPE,
+		.max_rings = 1,
+		.entry_size = sizeof(struct reo_destination_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO2PPE_RING_HP_ADDR(
+				REO_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >>
+		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT,
+	},
+	{ /* PPE2TCL */
+		.start_ring_id = HAL_SRNG_PPE2TCL1,
+		.max_rings = 1,
+		.entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(
+				MAC_TCL_REG_REG_BASE),
+			HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(
+				MAC_TCL_REG_REG_BASE),
+		},
+		.reg_size = {},
+		.max_size =
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* PPE_RELEASE */
+		.start_ring_id = HAL_SRNG_WBM_PPE_RELEASE,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_release_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
+		HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
+		},
+		.reg_size = {},
+		.max_size =
+		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+#ifdef QCA_MONITOR_2_0_SUPPORT
+	{ /* TX_MONITOR_BUF */
+		.start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
+		.max_rings = 1,
+		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+	{ /* TX_MONITOR_DST */
+		.start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
+		.max_rings = 2,
+		.entry_size = sizeof(struct mon_destination_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+#else
+	{},
+	{},
+#endif
+	{ /* SW2RXDMA */
+		.start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
+		.max_rings = 3,
+		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
+		.lmac_ring =  TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+};
+
+/**
+ * hal_qcn9224_attach()- Attach 9224 target specific hal_soc ops,
+ *			  offset and srng table
+ * Return: void
+ */
+void hal_qcn9224v1_attach(struct hal_soc *hal_soc)
+{
+	hal_soc->hw_srng_table = hw_srng_table_9224v1;
+
+	hal_srng_hw_reg_offset_init_generic(hal_soc);
+	hal_srng_hw_reg_offset_init_qcn9224(hal_soc);
+
+	hal_hw_txrx_default_ops_attach_be(hal_soc);
+	hal_hw_txrx_ops_attach_qcn9224(hal_soc);
+	if (hal_soc->static_window_map)
+		hal_write_window_register(hal_soc);
+	hal_soc->dmac_cmn_src_rxbuf_ring = true;
+}

hal/wifi3.0/qcn9224/v2/hal_9224v2.c

@@ -0,0 +1,566 @@
+/*
+ * Copyright (c) 2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "hal_9224.h"
+
+struct hal_hw_srng_config hw_srng_table_9224v2[] = {
+	/* TODO: max_rings can populated by querying HW capabilities */
+	{ /* REO_DST */
+		.start_ring_id = HAL_SRNG_REO2SW1,
+		.max_rings = 8,
+		.entry_size = sizeof(struct reo_destination_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
+				REO_REG_REG_BASE)
+		},
+		.reg_size = {
+			HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
+				HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
+			HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
+				HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
+		},
+		.max_size =
+			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_EXCEPTION */
+		/* Designating REO2SW0 ring as exception ring. This ring is
+		 * similar to other REO2SW rings though it is named as REO2SW0.
+		 * Any of theREO2SW rings can be used as exception ring.
+		 */
+		.start_ring_id = HAL_SRNG_REO2SW0,
+		.max_rings = 1,
+		.entry_size = sizeof(struct reo_destination_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
+				REO_REG_REG_BASE)
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_REINJECT */
+		.start_ring_id = HAL_SRNG_SW2REO,
+		.max_rings = 4,
+		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_SW2REO_RING_HP_ADDR(
+				REO_REG_REG_BASE)
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {
+			HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
+				HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
+			HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
+				HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
+		},
+		.max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
+				HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_CMD */
+		.start_ring_id = HAL_SRNG_REO_CMD,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct reo_get_queue_stats)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
+				REO_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* REO_STATUS */
+		.start_ring_id = HAL_SRNG_REO_STATUS,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct reo_get_queue_stats_status)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
+				REO_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_DATA */
+		.start_ring_id = HAL_SRNG_SW2TCL1,
+		.max_rings = 6,
+		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
+				MAC_TCL_REG_REG_BASE),
+			HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
+				MAC_TCL_REG_REG_BASE),
+		},
+		.reg_size = {
+			HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
+				HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
+			HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
+				HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
+		},
+		.max_size =
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_CMD/CREDIT */
+	  /* qca8074v2 and qcn9224 uses this ring for data commands */
+		.start_ring_id = HAL_SRNG_SW2TCL_CMD,
+		.max_rings = 1,
+		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
+		.lmac_ring =  FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
+				MAC_TCL_REG_REG_BASE),
+			HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
+				MAC_TCL_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* TCL_STATUS */
+		.start_ring_id = HAL_SRNG_TCL_STATUS,
+		.max_rings = 1,
+		.entry_size = (sizeof(struct tlv_32_hdr) +
+			sizeof(struct tcl_status_ring)) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
+				MAC_TCL_REG_REG_BASE),
+			HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
+				MAC_TCL_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_SRC */
+		.start_ring_id = HAL_SRNG_CE_0_SRC,
+		.max_rings = 16,
+		.entry_size = sizeof(struct ce_src_desc) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
+				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
+		HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
+				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
+		},
+		.reg_size = {
+		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
+		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
+		},
+		.max_size =
+		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_DST */
+		.start_ring_id = HAL_SRNG_CE_0_DST,
+		.max_rings = 16,
+		.entry_size = 8 >> 2,
+		/*TODO: entry_size above should actually be
+		 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
+		 * of struct ce_dst_desc in HW header files
+		 */
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
+		HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
+		},
+		.reg_size = {
+		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
+		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
+		},
+		.max_size =
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* CE_DST_STATUS */
+		.start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
+		.max_rings = 16,
+		.entry_size = sizeof(struct ce_stat_desc) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
+				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
+		HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
+				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
+		},
+		/* TODO: check destination status ring registers */
+		.reg_size = {
+		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
+		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
+		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
+		},
+		.max_size =
+	HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* WBM_IDLE_LINK */
+		.start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
+		HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* SW2WBM_RELEASE */
+		.start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
+		.max_rings = 2,
+		.entry_size = sizeof(struct wbm_release_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
+		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
+		},
+		.reg_size = {
+		HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) -
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
+		HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) -
+		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE)
+		},
+		.max_size =
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* WBM2SW_RELEASE */
+		.start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
+		.max_rings = 8,
+		.entry_size = sizeof(struct wbm_release_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
+				WBM_REG_REG_BASE),
+		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
+				WBM_REG_REG_BASE),
+		},
+		.reg_size = {
+		HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
+				WBM_REG_REG_BASE) -
+		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
+				WBM_REG_REG_BASE),
+		HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
+				WBM_REG_REG_BASE) -
+		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
+				WBM_REG_REG_BASE),
+		},
+		.max_size =
+		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* RXDMA_BUF */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
+#ifdef IPA_OFFLOAD
+		.max_rings = 3,
+#else
+		.max_rings = 3,
+#endif
+		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+	{ /* RXDMA_DST */
+		.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
+		.max_rings = 0,
+		.entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
+		.lmac_ring =  TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+#ifdef QCA_MONITOR_2_0_SUPPORT
+	{ /* RXDMA_MONITOR_BUF */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
+		.max_rings = 1,
+		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+#else
+	{},
+#endif
+	{ /* RXDMA_MONITOR_STATUS */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
+		.max_rings = 0,
+		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+#ifdef QCA_MONITOR_2_0_SUPPORT
+	{ /* RXDMA_MONITOR_DST */
+		.start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
+		.max_rings = 2,
+		.entry_size = sizeof(struct mon_destination_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+#else
+	{},
+#endif
+	{ /* RXDMA_MONITOR_DESC */
+		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
+		.max_rings = 0,
+		.entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+
+	{ /* DIR_BUF_RX_DMA_SRC */
+		.start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
+		/* one ring for spectral and one ring for cfr */
+		.max_rings = 2,
+		.entry_size = 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE,
+	},
+#ifdef WLAN_FEATURE_CIF_CFR
+	{ /* WIFI_POS_SRC */
+		.start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
+		.max_rings = 1,
+		.entry_size = sizeof(wmi_oem_dma_buf_release_entry)  >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+#endif
+	{ /* REO2PPE */
+		.start_ring_id = HAL_SRNG_REO2PPE,
+		.max_rings = 1,
+		.entry_size = sizeof(struct reo_destination_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		.reg_start = {
+			HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(
+				REO_REG_REG_BASE),
+			HWIO_REO_R2_REO2PPE_RING_HP_ADDR(
+				REO_REG_REG_BASE),
+		},
+		/* Single ring - provide ring size if multiple rings of this
+		 * type are supported
+		 */
+		.reg_size = {},
+		.max_size =
+		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >>
+		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT,
+	},
+	{ /* PPE2TCL */
+		.start_ring_id = HAL_SRNG_PPE2TCL1,
+		.max_rings = 1,
+		.entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+			HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(
+				MAC_TCL_REG_REG_BASE),
+			HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(
+				MAC_TCL_REG_REG_BASE),
+		},
+		.reg_size = {},
+		.max_size =
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
+			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+	{ /* PPE_RELEASE */
+		.start_ring_id = HAL_SRNG_WBM_PPE_RELEASE,
+		.max_rings = 1,
+		.entry_size = sizeof(struct wbm_release_ring) >> 2,
+		.lmac_ring = FALSE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		.reg_start = {
+		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
+		HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
+		},
+		.reg_size = {},
+		.max_size =
+		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
+		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
+	},
+#ifdef QCA_MONITOR_2_0_SUPPORT
+	{ /* TX_MONITOR_BUF */
+		.start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
+		.max_rings = 1,
+		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+	{ /* TX_MONITOR_DST */
+		.start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
+		.max_rings = 2,
+		.entry_size = sizeof(struct mon_destination_ring) >> 2,
+		.lmac_ring = TRUE,
+		.ring_dir = HAL_SRNG_DST_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+#else
+	{},
+	{},
+#endif
+	{ /* SW2RXDMA */
+		.start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
+		.max_rings = 3,
+		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
+		.lmac_ring =  TRUE,
+		.ring_dir = HAL_SRNG_SRC_RING,
+		/* reg_start is not set because LMAC rings are not accessed
+		 * from host
+		 */
+		.reg_start = {},
+		.reg_size = {},
+		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
+	},
+};
+
+/**
+ * hal_qcn9224_attach()- Attach 9224 target specific hal_soc ops,
+ *			  offset and srng table
+ * Return: void
+ */
+void hal_qcn9224v2_attach(struct hal_soc *hal_soc)
+{
+	hal_soc->hw_srng_table = hw_srng_table_9224v2;
+
+	hal_srng_hw_reg_offset_init_generic(hal_soc);
+	hal_srng_hw_reg_offset_init_qcn9224(hal_soc);
+
+	hal_hw_txrx_default_ops_attach_be(hal_soc);
+	hal_hw_txrx_ops_attach_qcn9224(hal_soc);
+	if (hal_soc->static_window_map)
+		hal_write_window_register(hal_soc);
+	hal_soc->dmac_cmn_src_rxbuf_ring = true;
+}

hif/inc/target_type.h

@@ -90,6 +90,10 @@ extern "C" {
 #define TARGET_TYPE_MANGO 34
 #endif
 
+#ifndef TARGET_TYPE_QCN9224V2
+#define TARGET_TYPE_QCN9224V2      35
+#endif
+
 #ifdef __cplusplus
 }
 #endif