hal_be_generic_api.h 92 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_GENERIC_API_H_
  20. #define _HAL_BE_GENERIC_API_H_
  21. #include <hal_be_hw_headers.h>
  22. #include "hal_be_tx.h"
  23. #include "hal_be_reo.h"
  24. #include <hal_api_mon.h>
  25. #include <hal_generic_api.h>
  26. #include <hal_be_api_mon.h>
  27. /**
  28. * Debug macro to print the TLV header tag
  29. */
  30. #define SHOW_DEFINED(x) do {} while (0)
  31. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(CONFIG_SAWF)
  32. static inline void
  33. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  34. struct hal_tx_completion_status *ts)
  35. {
  36. ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  37. BUFFER_TIMESTAMP);
  38. }
  39. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */
  40. static inline void
  41. hal_tx_comp_get_buffer_timestamp_be(void *desc,
  42. struct hal_tx_completion_status *ts)
  43. {
  44. }
  45. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || CONFIG_SAWF */
  46. /**
  47. * hal_tx_comp_get_status() - TQM Release reason
  48. * @hal_desc: completion ring Tx status
  49. *
  50. * This function will parse the WBM completion descriptor and populate in
  51. * HAL structure
  52. *
  53. * Return: none
  54. */
  55. static inline void
  56. hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
  57. struct hal_soc *hal)
  58. {
  59. uint8_t rate_stats_valid = 0;
  60. uint32_t rate_stats = 0;
  61. struct hal_tx_completion_status *ts =
  62. (struct hal_tx_completion_status *)ts1;
  63. ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  64. TQM_STATUS_NUMBER);
  65. ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  66. ACK_FRAME_RSSI);
  67. ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  68. FIRST_MSDU);
  69. ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  70. LAST_MSDU);
  71. #if 0
  72. // TODO - This has to be calculated form first and last msdu
  73. ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc,
  74. WBM2SW_COMPLETION_RING_TX,
  75. MSDU_PART_OF_AMSDU);
  76. #endif
  77. ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  78. SW_PEER_ID);
  79. ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID);
  80. ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX,
  81. TRANSMIT_COUNT);
  82. rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
  83. rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO,
  84. TX_RATE_STATS_INFO_VALID, rate_stats);
  85. ts->valid = rate_stats_valid;
  86. if (rate_stats_valid) {
  87. ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW,
  88. rate_stats);
  89. ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO,
  90. TRANSMIT_PKT_TYPE, rate_stats);
  91. ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO,
  92. TRANSMIT_STBC, rate_stats);
  93. ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC,
  94. rate_stats);
  95. ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI,
  96. rate_stats);
  97. ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS,
  98. rate_stats);
  99. ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION,
  100. rate_stats);
  101. ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU,
  102. rate_stats);
  103. }
  104. ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc);
  105. ts->status = hal_tx_comp_get_release_reason(
  106. desc,
  107. hal_soc_to_hal_soc_handle(hal));
  108. ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
  109. TX_RATE_STATS_INFO_TX_RATE_STATS);
  110. hal_tx_comp_get_buffer_timestamp_be(desc, ts);
  111. }
  112. /**
  113. * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
  114. * @soc: HAL SoC context
  115. * @map: PCP-TID mapping table
  116. *
  117. * PCP are mapped to 8 TID values using TID values programmed
  118. * in one set of mapping registers PCP_TID_MAP_<0 to 6>
  119. * The mapping register has TID mapping for 8 PCP values
  120. *
  121. * Return: none
  122. */
  123. static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map)
  124. {
  125. uint32_t addr, value;
  126. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  127. MAC_TCL_REG_REG_BASE);
  128. value = (map[0] |
  129. (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
  130. (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
  131. (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
  132. (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
  133. (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
  134. (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
  135. (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
  136. HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  137. }
  138. /**
  139. * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with
  140. * value received from user-space
  141. * @soc: HAL SoC context
  142. * @pcp: pcp value
  143. * @tid : tid value
  144. *
  145. * Return: void
  146. */
  147. static void
  148. hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc,
  149. uint8_t pcp, uint8_t tid)
  150. {
  151. uint32_t addr, value, regval;
  152. addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
  153. MAC_TCL_REG_REG_BASE);
  154. value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
  155. /* Read back previous PCP TID config and update
  156. * with new config.
  157. */
  158. regval = HAL_REG_READ(soc, addr);
  159. regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
  160. regval |= value;
  161. HAL_REG_WRITE(soc, addr,
  162. (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
  163. }
  164. /**
  165. * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority
  166. * @soc: HAL SoC context
  167. * @val: priority value
  168. *
  169. * Return: void
  170. */
  171. static
  172. void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value)
  173. {
  174. uint32_t addr;
  175. addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
  176. MAC_TCL_REG_REG_BASE);
  177. HAL_REG_WRITE(soc, addr,
  178. (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
  179. }
  180. /**
  181. * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size
  182. * @rx_pkt_tlv_size: TLV size for regular RX packets
  183. * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
  184. *
  185. * Return: size of rx pkt tlv before the actual data
  186. */
  187. static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size,
  188. uint16_t *rx_mon_pkt_tlv_size)
  189. {
  190. *rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
  191. /* For now mon pkt tlv is same as rx pkt tlv */
  192. *rx_mon_pkt_tlv_size = RX_PKT_TLVS_LEN;
  193. }
  194. /**
  195. * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST
  196. * @fst: Pointer to the Rx Flow Search Table
  197. * @hal_hash: HAL 5 tuple hash
  198. * @tuple_info: 5-tuple info of the flow returned to the caller
  199. *
  200. * Return: Success/Failure
  201. */
  202. static void *
  203. hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash,
  204. uint8_t *flow_tuple_info)
  205. {
  206. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  207. void *hal_fse = NULL;
  208. struct hal_flow_tuple_info *tuple_info
  209. = (struct hal_flow_tuple_info *)flow_tuple_info;
  210. hal_fse = (uint8_t *)fst->base_vaddr +
  211. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  212. if (!hal_fse || !tuple_info)
  213. return NULL;
  214. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID))
  215. return NULL;
  216. tuple_info->src_ip_127_96 =
  217. qdf_ntohl(HAL_GET_FLD(hal_fse,
  218. RX_FLOW_SEARCH_ENTRY,
  219. SRC_IP_127_96));
  220. tuple_info->src_ip_95_64 =
  221. qdf_ntohl(HAL_GET_FLD(hal_fse,
  222. RX_FLOW_SEARCH_ENTRY,
  223. SRC_IP_95_64));
  224. tuple_info->src_ip_63_32 =
  225. qdf_ntohl(HAL_GET_FLD(hal_fse,
  226. RX_FLOW_SEARCH_ENTRY,
  227. SRC_IP_63_32));
  228. tuple_info->src_ip_31_0 =
  229. qdf_ntohl(HAL_GET_FLD(hal_fse,
  230. RX_FLOW_SEARCH_ENTRY,
  231. SRC_IP_31_0));
  232. tuple_info->dest_ip_127_96 =
  233. qdf_ntohl(HAL_GET_FLD(hal_fse,
  234. RX_FLOW_SEARCH_ENTRY,
  235. DEST_IP_127_96));
  236. tuple_info->dest_ip_95_64 =
  237. qdf_ntohl(HAL_GET_FLD(hal_fse,
  238. RX_FLOW_SEARCH_ENTRY,
  239. DEST_IP_95_64));
  240. tuple_info->dest_ip_63_32 =
  241. qdf_ntohl(HAL_GET_FLD(hal_fse,
  242. RX_FLOW_SEARCH_ENTRY,
  243. DEST_IP_63_32));
  244. tuple_info->dest_ip_31_0 =
  245. qdf_ntohl(HAL_GET_FLD(hal_fse,
  246. RX_FLOW_SEARCH_ENTRY,
  247. DEST_IP_31_0));
  248. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  249. RX_FLOW_SEARCH_ENTRY,
  250. DEST_PORT);
  251. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  252. RX_FLOW_SEARCH_ENTRY,
  253. SRC_PORT);
  254. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  255. RX_FLOW_SEARCH_ENTRY,
  256. L4_PROTOCOL);
  257. return hal_fse;
  258. }
  259. /**
  260. * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST
  261. * @fst: Pointer to the Rx Flow Search Table
  262. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  263. *
  264. * Return: Success/Failure
  265. */
  266. static QDF_STATUS
  267. hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse)
  268. {
  269. uint8_t *fse = (uint8_t *)hal_rx_fse;
  270. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID))
  271. return QDF_STATUS_E_NOENT;
  272. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
  273. return QDF_STATUS_SUCCESS;
  274. }
  275. /**
  276. * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST
  277. *
  278. * Return: size of each entry/flow in Rx FST
  279. */
  280. static inline uint32_t
  281. hal_rx_fst_get_fse_size_be(void)
  282. {
  283. return HAL_RX_FST_ENTRY_SIZE;
  284. }
  285. /*
  286. * TX MONITOR
  287. */
  288. #ifdef QCA_MONITOR_2_0_SUPPORT
  289. /**
  290. * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv
  291. * @tx_tlv: pointer to TLV header
  292. *
  293. * Return: bool based on tlv tag matches monitor buffer address tlv
  294. */
  295. static inline bool
  296. hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr)
  297. {
  298. uint32_t tlv_tag;
  299. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  300. if (WIFIMON_BUFFER_ADDR_E == tlv_tag)
  301. return true;
  302. return false;
  303. }
  304. /**
  305. * hal_txmon_populate_packet_info_generic_be() - api to populate packet info
  306. * @tx_tlv: pointer to TLV header
  307. * @packet_info: place holder for packet info
  308. *
  309. * Return: Address to void
  310. */
  311. static inline void
  312. hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info)
  313. {
  314. struct hal_mon_packet_info *pkt_info;
  315. struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv;
  316. pkt_info = (struct hal_mon_packet_info *)packet_info;
  317. pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) |
  318. (addr->buffer_virt_addr_31_0));
  319. pkt_info->dma_length = addr->dma_length + 1;
  320. pkt_info->msdu_continuation = addr->msdu_continuation;
  321. pkt_info->truncated = addr->truncated;
  322. }
  323. #if defined(TX_MONITOR_WORD_MASK)
  324. /**
  325. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  326. *
  327. * @tx_tlv: pointer to tx_fes_setup tlv header
  328. *
  329. * Return: number of users
  330. */
  331. static inline uint8_t
  332. hal_txmon_get_num_users(void *tx_tlv)
  333. {
  334. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  335. return tx_fes_setup->number_of_users;
  336. }
  337. /**
  338. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  339. *
  340. * @tx_tlv: pointer to tx_fes_setup tlv header
  341. * @ppdu_info: pointer to hal_tx_ppdu_info
  342. *
  343. * Return: void
  344. */
  345. static inline void
  346. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  347. struct hal_tx_ppdu_info *tx_ppdu_info)
  348. {
  349. hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv;
  350. tx_ppdu_info->num_users = tx_fes_setup->number_of_users;
  351. if (tx_ppdu_info->num_users == 0)
  352. tx_ppdu_info->num_users = 1;
  353. tx_ppdu_info->ppdu_id = tx_fes_setup->schedule_id;
  354. }
  355. /**
  356. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  357. *
  358. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  359. * @data_status_info: pointer to data hal_tx_status_info
  360. * @prot_status_info: pointer to protection hal_tx_status_info
  361. *
  362. * Return: void
  363. */
  364. static inline void
  365. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  366. struct hal_tx_status_info *data_status_info,
  367. struct hal_tx_status_info *prot_status_info)
  368. {
  369. }
  370. /**
  371. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  372. *
  373. * @tx_tlv: pointer to peer_entry tlv header
  374. * @user_id: user_id
  375. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  376. * @tx_status_info: pointer to hal_tx_status_info
  377. *
  378. * Return: void
  379. */
  380. static inline void
  381. hal_txmon_parse_peer_entry(void *tx_tlv,
  382. uint8_t user_id,
  383. struct hal_tx_ppdu_info *tx_ppdu_info,
  384. struct hal_tx_status_info *tx_status_info)
  385. {
  386. }
  387. /**
  388. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  389. *
  390. * @tx_tlv: pointer to queue exten tlv header
  391. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  392. *
  393. * Return: void
  394. */
  395. static inline void
  396. hal_txmon_parse_queue_exten(void *tx_tlv,
  397. struct hal_tx_ppdu_info *tx_ppdu_info)
  398. {
  399. }
  400. /**
  401. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  402. *
  403. * @tx_tlv: pointer to mpdu start tlv header
  404. * @user_id: user id
  405. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  406. *
  407. * Return: void
  408. */
  409. static inline void
  410. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  411. struct hal_tx_ppdu_info *tx_ppdu_info)
  412. {
  413. }
  414. #else
  415. /**
  416. * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv
  417. *
  418. * @tx_tlv: pointer to tx_fes_setup tlv header
  419. *
  420. * Return: number of users
  421. */
  422. static inline uint8_t
  423. hal_txmon_get_num_users(void *tx_tlv)
  424. {
  425. uint8_t num_users = HAL_TX_DESC_GET_64(tx_tlv,
  426. TX_FES_SETUP, NUMBER_OF_USERS);
  427. return num_users;
  428. }
  429. /**
  430. * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv
  431. *
  432. * @tx_tlv: pointer to tx_fes_setup tlv header
  433. * @ppdu_info: pointer to hal_tx_ppdu_info
  434. *
  435. * Return: void
  436. */
  437. static inline void
  438. hal_txmon_parse_tx_fes_setup(void *tx_tlv,
  439. struct hal_tx_ppdu_info *tx_ppdu_info)
  440. {
  441. uint32_t num_users = 0;
  442. uint32_t ppdu_id = 0;
  443. num_users = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, NUMBER_OF_USERS);
  444. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_SETUP, SCHEDULE_ID);
  445. if (num_users == 0)
  446. num_users = 1;
  447. tx_ppdu_info->num_users = num_users;
  448. tx_ppdu_info->ppdu_id = ppdu_id;
  449. }
  450. /**
  451. * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv
  452. *
  453. * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header
  454. * @data_status_info: pointer to data hal_tx_status_info
  455. * @prot_status_info: pointer to protection hal_tx_status_info
  456. *
  457. * Return: void
  458. */
  459. static inline void
  460. hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv,
  461. struct hal_tx_status_info *data_status_info,
  462. struct hal_tx_status_info *prot_status_info)
  463. {
  464. prot_status_info->protection_addr =
  465. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  466. USE_ADDRESS_FIELDS_FOR_PROTECTION);
  467. /* protection frame address 1 */
  468. *(uint32_t *)&prot_status_info->addr1[0] =
  469. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  470. PROTECTION_FRAME_AD1_31_0);
  471. *(uint32_t *)&prot_status_info->addr1[4] =
  472. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  473. PROTECTION_FRAME_AD1_47_32);
  474. /* protection frame address 2 */
  475. *(uint32_t *)&prot_status_info->addr2[0] =
  476. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  477. PROTECTION_FRAME_AD2_15_0);
  478. *(uint32_t *)&prot_status_info->addr2[2] =
  479. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  480. PROTECTION_FRAME_AD2_47_16);
  481. /* protection frame address 3 */
  482. *(uint32_t *)&prot_status_info->addr3[0] =
  483. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  484. PROTECTION_FRAME_AD3_31_0);
  485. *(uint32_t *)&prot_status_info->addr3[4] =
  486. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  487. PROTECTION_FRAME_AD3_47_32);
  488. /* protection frame address 4 */
  489. *(uint32_t *)&prot_status_info->addr4[0] =
  490. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  491. PROTECTION_FRAME_AD4_15_0);
  492. *(uint32_t *)&prot_status_info->addr4[2] =
  493. HAL_TX_DESC_GET_64(tx_tlv, PCU_PPDU_SETUP_INIT,
  494. PROTECTION_FRAME_AD4_47_16);
  495. }
  496. /**
  497. * hal_txmon_parse_peer_entry() - parse peer entry tlv
  498. *
  499. * @tx_tlv: pointer to peer_entry tlv header
  500. * @user_id: user_id
  501. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  502. * @tx_status_info: pointer to hal_tx_status_info
  503. *
  504. * Return: void
  505. */
  506. static inline void
  507. hal_txmon_parse_peer_entry(void *tx_tlv,
  508. uint8_t user_id,
  509. struct hal_tx_ppdu_info *tx_ppdu_info,
  510. struct hal_tx_status_info *tx_status_info)
  511. {
  512. *(uint32_t *)&tx_status_info->addr1[0] =
  513. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_31_0);
  514. *(uint32_t *)&tx_status_info->addr1[4] =
  515. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_A_47_32);
  516. *(uint32_t *)&tx_status_info->addr2[0] =
  517. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_15_0);
  518. *(uint32_t *)&tx_status_info->addr2[2] =
  519. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, MAC_ADDR_B_47_16);
  520. TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) =
  521. HAL_TX_DESC_GET_64(tx_tlv, TX_PEER_ENTRY, SW_PEER_ID);
  522. }
  523. /**
  524. * hal_txmon_parse_queue_exten() - parse queue exten tlv
  525. *
  526. * @tx_tlv: pointer to queue exten tlv header
  527. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  528. *
  529. * Return: void
  530. */
  531. static inline void
  532. hal_txmon_parse_queue_exten(void *tx_tlv,
  533. struct hal_tx_ppdu_info *tx_ppdu_info)
  534. {
  535. TXMON_HAL_STATUS(tx_ppdu_info, frame_control) =
  536. HAL_TX_DESC_GET_64(tx_tlv, TX_QUEUE_EXTENSION,
  537. FRAME_CTL);
  538. TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true;
  539. }
  540. /**
  541. * hal_txmon_parse_mpdu_start() - parse mpdu start tlv
  542. *
  543. * @tx_tlv: pointer to mpdu start tlv header
  544. * @user_id: user id
  545. * @tx_ppdu_info: pointer to hal_tx_ppdu_info
  546. *
  547. * Return: void
  548. */
  549. static inline void
  550. hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id,
  551. struct hal_tx_ppdu_info *tx_ppdu_info)
  552. {
  553. TXMON_HAL_USER(tx_ppdu_info, user_id,
  554. start_seq) = HAL_TX_DESC_GET_64(tx_tlv, TX_MPDU_START,
  555. MPDU_SEQUENCE_NUMBER);
  556. TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id;
  557. }
  558. #endif
  559. /**
  560. * hal_txmon_status_get_num_users_generic_be() - api to get num users
  561. * from start of fes window
  562. *
  563. * @tx_tlv_hdr: pointer to TLV header
  564. * @num_users: reference to number of user
  565. *
  566. * Return: status
  567. */
  568. static inline uint32_t
  569. hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users)
  570. {
  571. uint32_t tlv_tag, user_id, tlv_len;
  572. uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  573. void *tx_tlv;
  574. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr);
  575. user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr);
  576. tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr);
  577. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  578. /* window starts with either initiator or response */
  579. switch (tlv_tag) {
  580. case WIFITX_FES_SETUP_E:
  581. {
  582. *num_users = hal_txmon_get_num_users(tx_tlv);
  583. if (*num_users == 0)
  584. *num_users = 1;
  585. tlv_status = HAL_MON_TX_FES_SETUP;
  586. break;
  587. }
  588. case WIFIRX_RESPONSE_REQUIRED_INFO_E:
  589. {
  590. *num_users = HAL_TX_DESC_GET_64(tx_tlv,
  591. RX_RESPONSE_REQUIRED_INFO,
  592. RESPONSE_STA_COUNT);
  593. if (*num_users == 0)
  594. *num_users = 1;
  595. tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  596. break;
  597. }
  598. };
  599. return tlv_status;
  600. }
  601. /**
  602. * hal_tx_get_ppdu_info() - api to get tx ppdu info
  603. * @pdev_handle: DP_PDEV handle
  604. * @prot_ppdu_info: populate dp_ppdu_info protection
  605. * @tx_data_ppdu_info: populate dp_ppdu_info data
  606. * @tlv_tag: Tag
  607. *
  608. * Return: dp_tx_ppdu_info pointer
  609. */
  610. static inline void *
  611. hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag)
  612. {
  613. struct hal_tx_ppdu_info *prot_ppdu_info = prot_info;
  614. switch (tlv_tag) {
  615. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  616. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  617. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  618. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  619. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  620. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  621. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  622. case WIFITX_DATA_E:/* DOWNSTREAM */
  623. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  624. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  625. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  626. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  627. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  628. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  629. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  630. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  631. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  632. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  633. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  634. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  635. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  636. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  637. case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */
  638. {
  639. return data_info;
  640. }
  641. }
  642. /*
  643. * check current prot_tlv_status is start protection
  644. * check current tlv_tag is either start protection or end protection
  645. */
  646. if (TXMON_HAL(prot_ppdu_info,
  647. prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) {
  648. return prot_info;
  649. } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E ||
  650. tlv_tag == WIFITX_FES_STATUS_START_PROT_E) {
  651. TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag;
  652. return prot_info;
  653. } else {
  654. TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag;
  655. return data_info;
  656. }
  657. return data_info;
  658. }
  659. /**
  660. * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv.
  661. * @data_ppdu_info: hal_txmon data ppdu info
  662. * @prot_ppdu_info: hal_txmon prot ppdu info
  663. * @data_status_info: pointer to data status info
  664. * @prot_status_info: pointer to prot status info
  665. * @tx_tlv_hdr: fragment of tx_tlv_hdr
  666. * @status_frag: qdf_frag_t buffer
  667. *
  668. * Return: status
  669. */
  670. static inline uint32_t
  671. hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info,
  672. void *prot_ppdu_info,
  673. void *data_status_info,
  674. void *prot_status_info,
  675. void *tx_tlv_hdr,
  676. qdf_frag_t status_frag)
  677. {
  678. struct hal_tx_ppdu_info *ppdu_info;
  679. struct hal_tx_status_info *tx_status_info;
  680. struct hal_mon_packet_info *packet_info = NULL;
  681. uint32_t tlv_tag, user_id, tlv_len;
  682. uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE;
  683. void *tx_tlv;
  684. tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(tx_tlv_hdr);
  685. /* user_id start with 1, decrement by 1 to start from 0 */
  686. user_id = HAL_RX_GET_USER_TLV64_USERID(tx_tlv_hdr) - 1;
  687. tlv_len = HAL_RX_GET_USER_TLV64_LEN(tx_tlv_hdr);
  688. tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
  689. /* parse tlv and populate tx_ppdu_info */
  690. ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info,
  691. prot_ppdu_info, tlv_tag);
  692. tx_status_info = (ppdu_info->is_data ? data_status_info :
  693. prot_status_info);
  694. user_id = user_id > ppdu_info->num_users ? 0 : ppdu_info->num_users;
  695. switch (tlv_tag) {
  696. /* start of initiator FES window */
  697. case WIFITX_FES_SETUP_E:/* DOWNSTREAM */
  698. {
  699. /* initiator PPDU window start */
  700. hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info);
  701. status = HAL_MON_TX_FES_SETUP;
  702. SHOW_DEFINED(WIFITX_FES_SETUP_E);
  703. break;
  704. }
  705. /* end of initiator FES window */
  706. case WIFITX_FES_STATUS_END_E:/* UPSTREAM */
  707. {
  708. /* initiator PPDU window end */
  709. uint32_t ppdu_timestamp_start = 0;
  710. uint32_t ppdu_timestamp_end = 0;
  711. uint8_t response_type = 0;
  712. uint8_t r2r_end_status_follow = 0;
  713. status = HAL_MON_TX_FES_STATUS_END;
  714. ppdu_timestamp_start =
  715. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  716. START_OF_FRAME_TIMESTAMP_15_0) |
  717. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  718. START_OF_FRAME_TIMESTAMP_31_16) <<
  719. HAL_TX_LSB(TX_FES_STATUS_END,
  720. START_OF_FRAME_TIMESTAMP_31_16));
  721. ppdu_timestamp_end =
  722. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  723. END_OF_FRAME_TIMESTAMP_15_0) |
  724. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  725. END_OF_FRAME_TIMESTAMP_31_16) <<
  726. HAL_TX_LSB(TX_FES_STATUS_END,
  727. END_OF_FRAME_TIMESTAMP_31_16));
  728. response_type = HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  729. RESPONSE_TYPE);
  730. /*
  731. * r2r end status follow to inform whether to look for
  732. * rx_response_required_info
  733. */
  734. r2r_end_status_follow =
  735. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_END,
  736. R2R_END_STATUS_TO_FOLLOW);
  737. TXMON_STATUS_INFO(tx_status_info,
  738. response_type) = response_type;
  739. TXMON_STATUS_INFO(tx_status_info,
  740. r2r_to_follow) = r2r_end_status_follow;
  741. /* update phy timestamp to ppdu timestamp */
  742. TXMON_HAL_STATUS(ppdu_info,
  743. ppdu_timestamp) = ppdu_timestamp_start;
  744. SHOW_DEFINED(WIFITX_FES_STATUS_END_E);
  745. break;
  746. }
  747. /* response window open */
  748. case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */
  749. {
  750. /* response PPDU window start */
  751. uint32_t ppdu_id = 0;
  752. uint8_t reception_type = 0;
  753. uint8_t response_sta_count = 0;
  754. status = HAL_MON_RX_RESPONSE_REQUIRED_INFO;
  755. ppdu_id = HAL_TX_DESC_GET_64(tx_tlv,
  756. RX_RESPONSE_REQUIRED_INFO,
  757. PHY_PPDU_ID);
  758. reception_type =
  759. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  760. SU_OR_UPLINK_MU_RECEPTION);
  761. response_sta_count =
  762. HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO,
  763. RESPONSE_STA_COUNT);
  764. /* get mac address */
  765. *(uint32_t *)&tx_status_info->addr1[0] =
  766. HAL_TX_DESC_GET_64(tx_tlv,
  767. RX_RESPONSE_REQUIRED_INFO,
  768. ADDR1_31_0);
  769. *(uint32_t *)&tx_status_info->addr1[4] =
  770. HAL_TX_DESC_GET_64(tx_tlv,
  771. RX_RESPONSE_REQUIRED_INFO,
  772. ADDR1_47_32);
  773. *(uint32_t *)&tx_status_info->addr2[0] =
  774. HAL_TX_DESC_GET_64(tx_tlv,
  775. RX_RESPONSE_REQUIRED_INFO,
  776. ADDR2_15_0);
  777. *(uint32_t *)&tx_status_info->addr2[2] =
  778. HAL_TX_DESC_GET_64(tx_tlv,
  779. RX_RESPONSE_REQUIRED_INFO,
  780. ADDR2_47_16);
  781. TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id;
  782. TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id;
  783. if (response_sta_count == 0)
  784. response_sta_count = 1;
  785. TXMON_HAL(ppdu_info, num_users) = response_sta_count;
  786. if (reception_type)
  787. TXMON_STATUS_INFO(tx_status_info,
  788. transmission_type) =
  789. TXMON_SU_TRANSMISSION;
  790. else
  791. TXMON_STATUS_INFO(tx_status_info,
  792. transmission_type) =
  793. TXMON_MU_TRANSMISSION;
  794. SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E);
  795. break;
  796. }
  797. /* Response window close */
  798. case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM */
  799. {
  800. /* response PPDU window end */
  801. uint8_t generated_response = 0;
  802. uint32_t bandwidth = 0;
  803. uint32_t ppdu_timestamp_start = 0;
  804. uint32_t ppdu_timestamp_end = 0;
  805. status = HAL_MON_RESPONSE_END_STATUS_INFO;
  806. generated_response = HAL_TX_DESC_GET_64(tx_tlv,
  807. RESPONSE_END_STATUS,
  808. GENERATED_RESPONSE);
  809. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  810. COEX_BASED_TX_BW);
  811. /* 32 bits TSF */
  812. ppdu_timestamp_start =
  813. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  814. START_OF_FRAME_TIMESTAMP_15_0) |
  815. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  816. START_OF_FRAME_TIMESTAMP_31_16) <<
  817. 16));
  818. ppdu_timestamp_end =
  819. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  820. END_OF_FRAME_TIMESTAMP_15_0) |
  821. (HAL_TX_DESC_GET_64(tx_tlv, RESPONSE_END_STATUS,
  822. END_OF_FRAME_TIMESTAMP_31_16) <<
  823. 16));
  824. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  825. /* update phy timestamp to ppdu timestamp */
  826. TXMON_HAL_STATUS(ppdu_info,
  827. ppdu_timestamp) = ppdu_timestamp_start;
  828. TXMON_STATUS_INFO(tx_status_info,
  829. generated_response) = generated_response;
  830. SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E);
  831. break;
  832. }
  833. case WIFITX_FLUSH_E:/* DOWNSTREAM */
  834. {
  835. SHOW_DEFINED(WIFITX_FLUSH_E);
  836. break;
  837. }
  838. /* Downstream tlv */
  839. case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */
  840. {
  841. hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info,
  842. prot_status_info);
  843. status = HAL_MON_TX_PCU_PPDU_SETUP_INIT;
  844. SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E);
  845. break;
  846. }
  847. case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */
  848. {
  849. hal_txmon_parse_peer_entry(tx_tlv, user_id,
  850. ppdu_info, tx_status_info);
  851. SHOW_DEFINED(WIFITX_PEER_ENTRY_E);
  852. break;
  853. }
  854. case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */
  855. {
  856. status = HAL_MON_TX_QUEUE_EXTENSION;
  857. hal_txmon_parse_queue_exten(tx_tlv, ppdu_info);
  858. SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E);
  859. break;
  860. }
  861. /* payload and data frame handling */
  862. case WIFITX_MPDU_START_E:/* DOWNSTREAM */
  863. {
  864. hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info);
  865. status = HAL_MON_TX_MPDU_START;
  866. SHOW_DEFINED(WIFITX_MPDU_START_E);
  867. break;
  868. }
  869. case WIFITX_MSDU_START_E:/* DOWNSTREAM */
  870. {
  871. /* compacted */
  872. /* we expect frame to be 802.11 frame type */
  873. status = HAL_MON_TX_MSDU_START;
  874. SHOW_DEFINED(WIFITX_MSDU_START_E);
  875. break;
  876. }
  877. case WIFITX_DATA_E:/* DOWNSTREAM */
  878. {
  879. status = HAL_MON_TX_DATA;
  880. /*
  881. * TODO: do we need a conversion api to convert
  882. * user_id from hw to get host user_index
  883. */
  884. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  885. TXMON_STATUS_INFO(tx_status_info,
  886. buffer) = (void *)status_frag;
  887. TXMON_STATUS_INFO(tx_status_info,
  888. offset) = ((void *)tx_tlv -
  889. (void *)status_frag);
  890. TXMON_STATUS_INFO(tx_status_info,
  891. length) = tlv_len;
  892. /*
  893. * reference of the status buffer will be held in
  894. * dp_tx_update_ppdu_info_status()
  895. */
  896. status = HAL_MON_TX_DATA;
  897. SHOW_DEFINED(WIFITX_DATA_E);
  898. break;
  899. }
  900. case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */
  901. {
  902. packet_info = &ppdu_info->packet_info;
  903. status = HAL_MON_TX_BUFFER_ADDR;
  904. /*
  905. * TODO: do we need a conversion api to convert
  906. * user_id from hw to get host user_index
  907. */
  908. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  909. hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info);
  910. SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E);
  911. break;
  912. }
  913. case WIFITX_MPDU_END_E:/* DOWNSTREAM */
  914. {
  915. /* no tlv content */
  916. SHOW_DEFINED(WIFITX_MPDU_END_E);
  917. break;
  918. }
  919. case WIFITX_MSDU_END_E:/* DOWNSTREAM */
  920. {
  921. /* no tlv content */
  922. SHOW_DEFINED(WIFITX_MSDU_END_E);
  923. break;
  924. }
  925. case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */
  926. {
  927. /* no tlv content */
  928. SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E);
  929. break;
  930. }
  931. case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */
  932. {
  933. /* no tlv content */
  934. SHOW_DEFINED(WIFITX_LAST_MPDU_END_E);
  935. break;
  936. }
  937. case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */
  938. {
  939. /*
  940. * transmitting power
  941. * minimum transmitting power
  942. * desired nss
  943. * tx chain mask
  944. * desired bw
  945. * duration of transmit and response
  946. *
  947. * since most of the field we are deriving from other tlv
  948. * we don't need to enable this in our tlv.
  949. */
  950. SHOW_DEFINED(WIFICOEX_TX_REQ_E);
  951. break;
  952. }
  953. case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */
  954. {
  955. /* user tlv */
  956. /*
  957. * All Tx monitor will have 802.11 hdr
  958. * we don't need to enable this TLV
  959. */
  960. SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E);
  961. break;
  962. }
  963. case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */
  964. {
  965. /*
  966. * no tlv content
  967. *
  968. * TLV that indicates to TXPCU that preamble phase for the NDP
  969. * frame transmission is now over
  970. */
  971. SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E);
  972. break;
  973. }
  974. case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */
  975. {
  976. /*
  977. * no tlv content
  978. *
  979. * TLV indicates to the SCH that all timing critical TLV
  980. * has been passed on to the transmit path
  981. */
  982. SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E);
  983. break;
  984. }
  985. case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */
  986. {
  987. /*
  988. * Loopback specific setup info - not needed for Tx monitor
  989. */
  990. SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E);
  991. break;
  992. }
  993. case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */
  994. {
  995. /*
  996. * no tlv content
  997. *
  998. * TLV indicates that other modules besides the scheduler can
  999. * now also start generating TLV's
  1000. * prevent colliding or generating TLV's out of order
  1001. */
  1002. SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E);
  1003. break;
  1004. }
  1005. case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */
  1006. {
  1007. /*
  1008. * no tlv content
  1009. *
  1010. * TLV indicates to SCH that a burst of MPDU info will
  1011. * start to come in over the TLV
  1012. */
  1013. SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E);
  1014. break;
  1015. }
  1016. case WIFITX_WUR_DATA_E:/* DOWNSTREAM */
  1017. {
  1018. SHOW_DEFINED(WIFITX_WUR_DATA_E);
  1019. break;
  1020. }
  1021. case WIFISCHEDULER_END_E:/* DOWNSTREAM */
  1022. {
  1023. /*
  1024. * no tlv content
  1025. *
  1026. * TLV indicates END of all TLV's within the scheduler TLV
  1027. */
  1028. SHOW_DEFINED(WIFISCHEDULER_END_E);
  1029. break;
  1030. }
  1031. /* Upstream tlv */
  1032. case WIFIPDG_TX_REQ_E:
  1033. {
  1034. SHOW_DEFINED(WIFIPDG_TX_REQ_E);
  1035. break;
  1036. }
  1037. case WIFITX_FES_STATUS_START_E:
  1038. {
  1039. /*
  1040. * TLV indicating that first transmission on the medium
  1041. */
  1042. uint8_t medium_prot_type = 0;
  1043. status = HAL_MON_TX_FES_STATUS_START;
  1044. medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv,
  1045. TX_FES_STATUS_START,
  1046. MEDIUM_PROT_TYPE);
  1047. ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info;
  1048. /* update what type of medium protection frame */
  1049. TXMON_STATUS_INFO(tx_status_info,
  1050. medium_prot_type) = medium_prot_type;
  1051. SHOW_DEFINED(WIFITX_FES_STATUS_START_E);
  1052. break;
  1053. }
  1054. case WIFITX_FES_STATUS_PROT_E:
  1055. {
  1056. uint32_t start_timestamp = 0;
  1057. uint32_t end_timestamp = 0;
  1058. /*
  1059. * generated by TXPCU to indicate the result of having
  1060. * received of the expected protection frame
  1061. */
  1062. status = HAL_MON_TX_FES_STATUS_PROT;
  1063. start_timestamp =
  1064. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1065. START_OF_FRAME_TIMESTAMP_15_0);
  1066. start_timestamp |=
  1067. (HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1068. START_OF_FRAME_TIMESTAMP_31_16) <<
  1069. 15);
  1070. end_timestamp = HAL_TX_DESC_GET_64(tx_tlv,
  1071. TX_FES_STATUS_PROT,
  1072. END_OF_FRAME_TIMESTAMP_15_0);
  1073. end_timestamp |=
  1074. HAL_TX_DESC_GET_64(tx_tlv, TX_FES_STATUS_PROT,
  1075. END_OF_FRAME_TIMESTAMP_31_16) << 15;
  1076. /* ppdu timestamp as phy timestamp */
  1077. TXMON_HAL_STATUS(ppdu_info,
  1078. ppdu_timestamp) = start_timestamp;
  1079. SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E);
  1080. break;
  1081. }
  1082. case WIFITX_FES_STATUS_START_PROT_E:
  1083. {
  1084. uint64_t tsft_64;
  1085. uint32_t response_type;
  1086. status = HAL_MON_TX_FES_STATUS_START_PROT;
  1087. TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag;
  1088. /* timestamp */
  1089. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1090. TX_FES_STATUS_START_PROT,
  1091. PROT_TIMESTAMP_LOWER_32);
  1092. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1093. TX_FES_STATUS_START_PROT,
  1094. PROT_TIMESTAMP_UPPER_32) << 32);
  1095. response_type = HAL_TX_DESC_GET_64(tx_tlv,
  1096. TX_FES_STATUS_START_PROT,
  1097. RESPONSE_TYPE);
  1098. TXMON_STATUS_INFO(tx_status_info,
  1099. response_type) = response_type;
  1100. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1101. SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E);
  1102. break;
  1103. }
  1104. case WIFIPROT_TX_END_E:
  1105. {
  1106. /*
  1107. * no tlv content
  1108. *
  1109. * generated by TXPCU the moment that protection frame
  1110. * transmission has finished on the medium
  1111. */
  1112. SHOW_DEFINED(WIFIPROT_TX_END_E);
  1113. break;
  1114. }
  1115. case WIFITX_FES_STATUS_START_PPDU_E:
  1116. {
  1117. uint64_t tsft_64;
  1118. uint8_t ndp_frame;
  1119. status = HAL_MON_TX_FES_STATUS_START_PPDU;
  1120. tsft_64 = HAL_TX_DESC_GET_64(tx_tlv,
  1121. TX_FES_STATUS_START_PPDU,
  1122. PPDU_TIMESTAMP_LOWER_32);
  1123. tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv,
  1124. TX_FES_STATUS_START_PPDU,
  1125. PPDU_TIMESTAMP_UPPER_32) << 32);
  1126. ndp_frame = HAL_TX_DESC_GET_64(tx_tlv,
  1127. TX_FES_STATUS_START_PPDU,
  1128. NDP_FRAME);
  1129. TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame;
  1130. TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64;
  1131. SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E);
  1132. break;
  1133. }
  1134. case WIFITX_FES_STATUS_USER_PPDU_E:
  1135. {
  1136. /* user tlv */
  1137. uint16_t duration;
  1138. uint8_t transmitted_tid;
  1139. duration = HAL_TX_DESC_GET_64(tx_tlv,
  1140. TX_FES_STATUS_USER_PPDU,
  1141. DURATION);
  1142. transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv,
  1143. TX_FES_STATUS_USER_PPDU,
  1144. TRANSMITTED_TID);
  1145. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1146. TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid;
  1147. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  1148. status = HAL_MON_TX_FES_STATUS_USER_PPDU;
  1149. SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E);
  1150. break;
  1151. }
  1152. case WIFIPPDU_TX_END_E:
  1153. {
  1154. /*
  1155. * no tlv content
  1156. *
  1157. * generated by TXPCU the moment that PPDU transmission has
  1158. * finished on the medium
  1159. */
  1160. SHOW_DEFINED(WIFIPPDU_TX_END_E);
  1161. break;
  1162. }
  1163. case WIFITX_FES_STATUS_USER_RESPONSE_E:
  1164. {
  1165. /*
  1166. * TLV contains the FES transmit result of the each
  1167. * of the MAC users. TLV are forwarded to HWSCH
  1168. */
  1169. SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E);
  1170. break;
  1171. }
  1172. case WIFITX_FES_STATUS_ACK_OR_BA_E:
  1173. {
  1174. /* user tlv */
  1175. /*
  1176. * TLV generated by RXPCU and provide information related to
  1177. * the received BA or ACK frame
  1178. */
  1179. SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E);
  1180. break;
  1181. }
  1182. case WIFITX_FES_STATUS_1K_BA_E:
  1183. {
  1184. /* user tlv */
  1185. /*
  1186. * TLV generated by RXPCU and providing information related
  1187. * to the received BA frame in case of 512/1024 bitmaps
  1188. */
  1189. SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E);
  1190. break;
  1191. }
  1192. case WIFIRECEIVED_RESPONSE_USER_7_0_E:
  1193. {
  1194. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E);
  1195. break;
  1196. }
  1197. case WIFIRECEIVED_RESPONSE_USER_15_8_E:
  1198. {
  1199. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E);
  1200. break;
  1201. }
  1202. case WIFIRECEIVED_RESPONSE_USER_23_16_E:
  1203. {
  1204. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E);
  1205. break;
  1206. }
  1207. case WIFIRECEIVED_RESPONSE_USER_31_24_E:
  1208. {
  1209. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E);
  1210. break;
  1211. }
  1212. case WIFIRECEIVED_RESPONSE_USER_36_32_E:
  1213. {
  1214. /*
  1215. * RXPCU generates this TLV when it receives a response frame
  1216. * that TXPCU pre-announced it was waiting for and in
  1217. * RXPCU_SETUP TLV, TLV generated before the
  1218. * RECEIVED_RESPONSE_INFO TLV.
  1219. *
  1220. * received info user fields are there which is not needed
  1221. * for TX monitor
  1222. */
  1223. SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E);
  1224. break;
  1225. }
  1226. case WIFITXPCU_BUFFER_STATUS_E:
  1227. {
  1228. SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E);
  1229. break;
  1230. }
  1231. case WIFITXPCU_USER_BUFFER_STATUS_E:
  1232. {
  1233. /*
  1234. * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv
  1235. * for TX monitor we aren't interested in this tlv
  1236. */
  1237. SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E);
  1238. break;
  1239. }
  1240. case WIFITXDMA_STOP_REQUEST_E:
  1241. {
  1242. /*
  1243. * no tlv content
  1244. *
  1245. * TLV is destined to TXDMA and informs TXDMA to stop
  1246. * pushing data into the transmit path.
  1247. */
  1248. SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E);
  1249. break;
  1250. }
  1251. case WIFITX_CBF_INFO_E:
  1252. {
  1253. /*
  1254. * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to
  1255. * TXPCU to respond the CBF frame
  1256. *
  1257. * compressed beamforming pkt doesn't has mac header
  1258. * Tx monitor not interested in this pkt.
  1259. */
  1260. SHOW_DEFINED(WIFITX_CBF_INFO_E);
  1261. break;
  1262. }
  1263. case WIFITX_MPDU_COUNT_TRANSFER_END_E:
  1264. {
  1265. /*
  1266. * no tlv content
  1267. *
  1268. * TLV indicates that TXPCU has finished generating the
  1269. * TQM_UPDATE_TX_MPDU_COUNT TLV for all users
  1270. */
  1271. SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E);
  1272. break;
  1273. }
  1274. case WIFIPDG_RESPONSE_E:
  1275. {
  1276. /*
  1277. * most of the feilds are already covered in
  1278. * other TLV
  1279. * This is generated by TX_PCU to PDG to calculate
  1280. * all the PHY header info.
  1281. *
  1282. * some useful fields like min transmit power,
  1283. * rate used for transmitting packet is present.
  1284. */
  1285. SHOW_DEFINED(WIFIPDG_RESPONSE_E);
  1286. break;
  1287. }
  1288. case WIFIPDG_TRIG_RESPONSE_E:
  1289. {
  1290. /* no tlv content */
  1291. SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E);
  1292. break;
  1293. }
  1294. case WIFIRECEIVED_TRIGGER_INFO_E:
  1295. {
  1296. /*
  1297. * TLV generated by RXPCU to inform the scheduler that
  1298. * a trigger frame has been received
  1299. */
  1300. SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E);
  1301. break;
  1302. }
  1303. case WIFIOFDMA_TRIGGER_DETAILS_E:
  1304. {
  1305. SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E);
  1306. break;
  1307. }
  1308. case WIFIRX_FRAME_BITMAP_ACK_E:
  1309. {
  1310. /* user tlv */
  1311. status = HAL_MON_RX_FRAME_BITMAP_ACK;
  1312. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E);
  1313. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1314. TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) =
  1315. HAL_TX_DESC_GET_64(tx_tlv,
  1316. RX_FRAME_BITMAP_ACK,
  1317. NO_BITMAP_AVAILABLE);
  1318. TXMON_STATUS_INFO(tx_status_info, explicit_ack) =
  1319. HAL_TX_DESC_GET_64(tx_tlv,
  1320. RX_FRAME_BITMAP_ACK,
  1321. EXPLICIT_ACK);
  1322. /*
  1323. * get mac address, since address is received frame
  1324. * change the order and store it
  1325. */
  1326. *(uint32_t *)&tx_status_info->addr2[0] =
  1327. HAL_TX_DESC_GET_64(tx_tlv,
  1328. RX_FRAME_BITMAP_ACK,
  1329. ADDR1_31_0);
  1330. *(uint32_t *)&tx_status_info->addr2[4] =
  1331. HAL_TX_DESC_GET_64(tx_tlv,
  1332. RX_FRAME_BITMAP_ACK,
  1333. ADDR1_47_32);
  1334. *(uint32_t *)&tx_status_info->addr1[0] =
  1335. HAL_TX_DESC_GET_64(tx_tlv,
  1336. RX_FRAME_BITMAP_ACK,
  1337. ADDR2_15_0);
  1338. *(uint32_t *)&tx_status_info->addr1[2] =
  1339. HAL_TX_DESC_GET_64(tx_tlv,
  1340. RX_FRAME_BITMAP_ACK,
  1341. ADDR2_47_16);
  1342. TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) =
  1343. HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK,
  1344. EXPLICT_ACK_TYPE);
  1345. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1346. HAL_TX_DESC_GET_64(tx_tlv,
  1347. RX_FRAME_BITMAP_ACK,
  1348. BA_TID);
  1349. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1350. HAL_TX_DESC_GET_64(tx_tlv,
  1351. RX_FRAME_BITMAP_ACK,
  1352. STA_FULL_AID);
  1353. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1354. HAL_TX_DESC_GET_64(tx_tlv,
  1355. RX_FRAME_BITMAP_ACK,
  1356. BA_TS_SEQ);
  1357. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1358. HAL_TX_DESC_GET_64(tx_tlv,
  1359. RX_FRAME_BITMAP_ACK,
  1360. BA_TS_CTRL);
  1361. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  1362. HAL_TX_DESC_GET_64(tx_tlv,
  1363. RX_FRAME_BITMAP_ACK,
  1364. BA_BITMAP_SIZE);
  1365. /* ba bitmap */
  1366. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  1367. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  1368. RX_FRAME_BITMAP_ACK,
  1369. BA_TS_BITMAP_31_0, 0), 32);
  1370. break;
  1371. }
  1372. case WIFIRX_FRAME_1K_BITMAP_ACK_E:
  1373. {
  1374. /* user tlv */
  1375. status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K;
  1376. SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E);
  1377. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1378. TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) =
  1379. (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK,
  1380. BA_BITMAP_SIZE));
  1381. TXMON_HAL_USER(ppdu_info, user_id, tid) =
  1382. HAL_TX_DESC_GET_64(tx_tlv,
  1383. RX_FRAME_1K_BITMAP_ACK,
  1384. BA_TID);
  1385. TXMON_HAL_USER(ppdu_info, user_id, aid) =
  1386. HAL_TX_DESC_GET_64(tx_tlv,
  1387. RX_FRAME_1K_BITMAP_ACK,
  1388. STA_FULL_AID);
  1389. /* get mac address */
  1390. *(uint32_t *)&tx_status_info->addr1[0] =
  1391. HAL_TX_DESC_GET_64(tx_tlv,
  1392. RX_FRAME_1K_BITMAP_ACK,
  1393. ADDR1_31_0);
  1394. *(uint32_t *)&tx_status_info->addr1[4] =
  1395. HAL_TX_DESC_GET_64(tx_tlv,
  1396. RX_FRAME_1K_BITMAP_ACK,
  1397. ADDR1_47_32);
  1398. *(uint32_t *)&tx_status_info->addr2[0] =
  1399. HAL_TX_DESC_GET_64(tx_tlv,
  1400. RX_FRAME_1K_BITMAP_ACK,
  1401. ADDR2_15_0);
  1402. *(uint32_t *)&tx_status_info->addr2[2] =
  1403. HAL_TX_DESC_GET_64(tx_tlv,
  1404. RX_FRAME_1K_BITMAP_ACK,
  1405. ADDR2_47_16);
  1406. TXMON_HAL_USER(ppdu_info, user_id, start_seq) =
  1407. HAL_TX_DESC_GET_64(tx_tlv,
  1408. RX_FRAME_1K_BITMAP_ACK,
  1409. BA_TS_SEQ);
  1410. TXMON_HAL_USER(ppdu_info, user_id, ba_control) =
  1411. HAL_TX_DESC_GET_64(tx_tlv,
  1412. RX_FRAME_1K_BITMAP_ACK,
  1413. BA_TS_CTRL);
  1414. /* memcpy ba bitmap */
  1415. qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap),
  1416. &HAL_SET_FLD_OFFSET_64(tx_tlv,
  1417. RX_FRAME_1K_BITMAP_ACK,
  1418. BA_TS_BITMAP_31_0, 0),
  1419. 4 << TXMON_HAL_USER(ppdu_info,
  1420. user_id, ba_bitmap_sz));
  1421. break;
  1422. }
  1423. case WIFIRESPONSE_START_STATUS_E:
  1424. {
  1425. /*
  1426. * TLV indicates which HW response the TXPCU
  1427. * started generating
  1428. *
  1429. * HW generated frames like
  1430. * ACK frame - handled
  1431. * CTS frame - handled
  1432. * BA frame - handled
  1433. * MBA frame - handled
  1434. * CBF frame - no frame header
  1435. * Trigger response - TODO
  1436. * NDP LMR - no frame header
  1437. */
  1438. SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E);
  1439. break;
  1440. }
  1441. case WIFIRX_START_PARAM_E:
  1442. {
  1443. /*
  1444. * RXPCU send this TLV after PHY RX detected a frame
  1445. * in the medium
  1446. *
  1447. * TX monitor not interested in this TLV
  1448. */
  1449. SHOW_DEFINED(WIFIRX_START_PARAM_E);
  1450. break;
  1451. }
  1452. case WIFIRXPCU_EARLY_RX_INDICATION_E:
  1453. {
  1454. /*
  1455. * early indication of pkt type and mcs rate
  1456. * already captured in other tlv
  1457. */
  1458. SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E);
  1459. break;
  1460. }
  1461. case WIFIRX_PM_INFO_E:
  1462. {
  1463. SHOW_DEFINED(WIFIRX_PM_INFO_E);
  1464. break;
  1465. }
  1466. /* Active window */
  1467. case WIFITX_FLUSH_REQ_E:
  1468. {
  1469. SHOW_DEFINED(WIFITX_FLUSH_REQ_E);
  1470. break;
  1471. }
  1472. case WIFICOEX_TX_STATUS_E:
  1473. {
  1474. /* duration are retrieved from coex tx status */
  1475. uint16_t duration;
  1476. uint8_t status_reason;
  1477. status = HAL_MON_COEX_TX_STATUS;
  1478. duration = HAL_TX_DESC_GET_64(tx_tlv,
  1479. COEX_TX_STATUS,
  1480. CURRENT_TX_DURATION);
  1481. status_reason = HAL_TX_DESC_GET_64(tx_tlv,
  1482. COEX_TX_STATUS,
  1483. TX_STATUS_REASON);
  1484. /* update duration */
  1485. if (status_reason == COEX_FES_TX_START ||
  1486. status_reason == COEX_RESPONSE_TX_START)
  1487. TXMON_HAL_USER(ppdu_info, user_id, duration) = duration;
  1488. SHOW_DEFINED(WIFICOEX_TX_STATUS_E);
  1489. break;
  1490. }
  1491. case WIFIR2R_STATUS_END_E:
  1492. {
  1493. SHOW_DEFINED(WIFIR2R_STATUS_END_E);
  1494. break;
  1495. }
  1496. case WIFIRX_PREAMBLE_E:
  1497. {
  1498. SHOW_DEFINED(WIFIRX_PREAMBLE_E);
  1499. break;
  1500. }
  1501. case WIFIMACTX_SERVICE_E:
  1502. {
  1503. SHOW_DEFINED(WIFIMACTX_SERVICE_E);
  1504. break;
  1505. }
  1506. case WIFIMACTX_U_SIG_EHT_SU_MU_E:
  1507. {
  1508. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E);
  1509. break;
  1510. }
  1511. case WIFIMACTX_U_SIG_EHT_TB_E:
  1512. {
  1513. /* TODO: no radiotap info available */
  1514. SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E);
  1515. break;
  1516. }
  1517. case WIFIMACTX_EHT_SIG_USR_OFDMA_E:
  1518. {
  1519. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E);
  1520. break;
  1521. }
  1522. case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E:
  1523. {
  1524. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E);
  1525. break;
  1526. }
  1527. case WIFIMACTX_EHT_SIG_USR_SU_E:
  1528. {
  1529. SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E);
  1530. /* TODO: no radiotap info available */
  1531. break;
  1532. }
  1533. case WIFIMACTX_HE_SIG_A_SU_E:
  1534. {
  1535. uint8_t mcs_of_sig_b = 0;
  1536. uint8_t dcm_of_sig_b = 0;
  1537. uint8_t sig_a_bw = 0;
  1538. uint16_t he_mu_flag_1 = 0;
  1539. uint16_t he_mu_flag_2 = 0;
  1540. status = HAL_MON_MACTX_HE_SIG_A_SU;
  1541. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1542. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1543. TRANSMIT_MCS);
  1544. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1545. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1546. DCM);
  1547. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  1548. MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS,
  1549. TRANSMIT_BW);
  1550. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1551. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1552. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  1553. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  1554. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  1555. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN;
  1556. /* MCS */
  1557. he_mu_flag_1 |= mcs_of_sig_b <<
  1558. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  1559. /* DCM */
  1560. he_mu_flag_1 |= dcm_of_sig_b <<
  1561. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  1562. /* bandwidth */
  1563. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  1564. he_mu_flag_2 |= sig_a_bw <<
  1565. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  1566. TXMON_HAL_STATUS(ppdu_info, he_flags1) = he_mu_flag_1;
  1567. TXMON_HAL_STATUS(ppdu_info, he_flags2) = he_mu_flag_2;
  1568. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E);
  1569. break;
  1570. }
  1571. case WIFIMACTX_HE_SIG_A_MU_DL_E:
  1572. {
  1573. uint8_t mcs_of_sig_b = 0;
  1574. uint8_t dcm_of_sig_b = 0;
  1575. uint8_t sig_a_bw = 0;
  1576. uint8_t num_sig_b_symb = 0;
  1577. uint8_t comp_mode_sig_b = 0;
  1578. uint8_t punc_bw = 0;
  1579. uint16_t he_mu_flag_1 = 0;
  1580. uint16_t he_mu_flag_2 = 0;
  1581. status = HAL_MON_MACTX_HE_SIG_A_MU_DL;
  1582. mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1583. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1584. MCS_OF_SIG_B);
  1585. dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1586. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1587. DCM_OF_SIG_B);
  1588. sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv,
  1589. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1590. TRANSMIT_BW);
  1591. num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv,
  1592. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1593. NUM_SIG_B_SYMBOLS);
  1594. comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv,
  1595. MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS,
  1596. COMP_MODE_SIG_B);
  1597. he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1598. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1599. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1600. QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN |
  1601. QDF_MON_STATUS_CHANNEL_1_RU_KNOWN |
  1602. QDF_MON_STATUS_CHANNEL_2_RU_KNOWN |
  1603. QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN |
  1604. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1605. QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN;
  1606. /* MCS */
  1607. he_mu_flag_1 |= mcs_of_sig_b <<
  1608. QDF_MON_STATUS_SIG_B_MCS_SHIFT;
  1609. /* DCM */
  1610. he_mu_flag_1 |= dcm_of_sig_b <<
  1611. QDF_MON_STATUS_SIG_B_DCM_SHIFT;
  1612. /* Compression */
  1613. he_mu_flag_2 |= comp_mode_sig_b <<
  1614. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1615. /* bandwidth */
  1616. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN;
  1617. he_mu_flag_2 |= sig_a_bw <<
  1618. QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT;
  1619. he_mu_flag_2 |= comp_mode_sig_b <<
  1620. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1621. /* number of symbol */
  1622. he_mu_flag_2 |= num_sig_b_symb <<
  1623. QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1624. /* puncture bw */
  1625. he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN;
  1626. punc_bw = sig_a_bw;
  1627. he_mu_flag_2 |=
  1628. punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT;
  1629. /* copy per user info to all user */
  1630. TXMON_HAL_STATUS(ppdu_info, he_mu_flags) = 1;
  1631. TXMON_HAL_STATUS(ppdu_info, he_flags1) = he_mu_flag_1;
  1632. TXMON_HAL_STATUS(ppdu_info, he_flags2) = he_mu_flag_2;
  1633. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E);
  1634. break;
  1635. }
  1636. case WIFIMACTX_HE_SIG_A_MU_UL_E:
  1637. {
  1638. SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E);
  1639. break;
  1640. }
  1641. case WIFIMACTX_HE_SIG_B1_MU_E:
  1642. {
  1643. status = HAL_MON_MACTX_HE_SIG_B1_MU;
  1644. SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E);
  1645. break;
  1646. }
  1647. case WIFIMACTX_HE_SIG_B2_MU_E:
  1648. {
  1649. /* user tlv */
  1650. uint16_t sta_id = 0;
  1651. uint16_t sta_spatial_config = 0;
  1652. uint8_t sta_mcs = 0;
  1653. uint8_t coding = 0;
  1654. uint8_t nss = 0;
  1655. uint8_t user_order = 0;
  1656. status = HAL_MON_MACTX_HE_SIG_B2_MU;
  1657. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1658. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  1659. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1660. STA_ID);
  1661. sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv,
  1662. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1663. STA_SPATIAL_CONFIG);
  1664. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  1665. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1666. STA_MCS);
  1667. coding = HAL_TX_DESC_GET_64(tx_tlv,
  1668. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1669. STA_CODING);
  1670. nss = HAL_TX_DESC_GET_64(tx_tlv,
  1671. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1672. NSTS);
  1673. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  1674. MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS,
  1675. USER_ORDER);
  1676. /* HE data 1 */
  1677. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  1678. QDF_MON_STATUS_HE_MCS_KNOWN |
  1679. QDF_MON_STATUS_HE_CODING_KNOWN;
  1680. /* HE data 2 */
  1681. /* HE data 3 */
  1682. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  1683. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1684. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1685. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1686. coding << QDF_MON_STATUS_CODING_SHIFT;
  1687. /* HE data 4 */
  1688. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  1689. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  1690. /* HE data 5 */
  1691. /* HE data 6 */
  1692. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  1693. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  1694. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E);
  1695. break;
  1696. }
  1697. case WIFIMACTX_HE_SIG_B2_OFDMA_E:
  1698. {
  1699. /* user tlv */
  1700. uint8_t *he_sig_b2_ofdma_info = NULL;
  1701. uint16_t sta_id = 0;
  1702. uint8_t nss = 0;
  1703. uint8_t txbf = 0;
  1704. uint8_t sta_mcs = 0;
  1705. uint8_t sta_dcm = 0;
  1706. uint8_t coding = 0;
  1707. uint8_t user_order = 0;
  1708. status = HAL_MON_MACTX_HE_SIG_B2_OFDMA;
  1709. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  1710. he_sig_b2_ofdma_info = (uint8_t *)tx_tlv +
  1711. HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1712. STA_ID);
  1713. sta_id = HAL_TX_DESC_GET_64(tx_tlv,
  1714. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1715. STA_ID);
  1716. nss = HAL_TX_DESC_GET_64(tx_tlv,
  1717. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1718. NSTS);
  1719. txbf = HAL_TX_DESC_GET_64(tx_tlv,
  1720. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1721. TXBF);
  1722. sta_mcs = HAL_TX_DESC_GET_64(tx_tlv,
  1723. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1724. STA_MCS);
  1725. sta_dcm = HAL_TX_DESC_GET_64(tx_tlv,
  1726. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1727. STA_DCM);
  1728. coding = HAL_TX_DESC_GET_64(tx_tlv,
  1729. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1730. STA_CODING);
  1731. user_order = HAL_TX_DESC_GET_64(tx_tlv,
  1732. MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS,
  1733. USER_ORDER);
  1734. /* HE data 1 */
  1735. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |=
  1736. QDF_MON_STATUS_HE_MCS_KNOWN |
  1737. QDF_MON_STATUS_HE_CODING_KNOWN |
  1738. QDF_MON_STATUS_HE_DCM_KNOWN;
  1739. /* HE data 2 */
  1740. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |=
  1741. QDF_MON_STATUS_TXBF_KNOWN;
  1742. /* HE data 3 */
  1743. TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs;
  1744. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1745. sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1746. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1747. sta_dcm << QDF_MON_STATUS_DCM_SHIFT;
  1748. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |=
  1749. coding << QDF_MON_STATUS_CODING_SHIFT;
  1750. /* HE data 4 */
  1751. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |=
  1752. sta_id << QDF_MON_STATUS_STA_ID_SHIFT;
  1753. /* HE data 5 */
  1754. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |=
  1755. txbf << QDF_MON_STATUS_TXBF_SHIFT;
  1756. /* HE data 6 */
  1757. TXMON_HAL_USER(ppdu_info, user_id, nss) = nss;
  1758. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss;
  1759. SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E);
  1760. break;
  1761. }
  1762. case WIFIMACTX_L_SIG_A_E:
  1763. {
  1764. uint8_t *l_sig_a_info = NULL;
  1765. uint8_t rate = 0;
  1766. status = HAL_MON_MACTX_L_SIG_A;
  1767. l_sig_a_info = (uint8_t *)tx_tlv +
  1768. HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  1769. RATE);
  1770. rate = HAL_TX_DESC_GET_64(tx_tlv,
  1771. MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS,
  1772. RATE);
  1773. switch (rate) {
  1774. case 8:
  1775. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS;
  1776. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  1777. break;
  1778. case 9:
  1779. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS;
  1780. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  1781. break;
  1782. case 10:
  1783. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS;
  1784. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  1785. break;
  1786. case 11:
  1787. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS;
  1788. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  1789. break;
  1790. case 12:
  1791. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS;
  1792. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  1793. break;
  1794. case 13:
  1795. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS;
  1796. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  1797. break;
  1798. case 14:
  1799. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS;
  1800. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  1801. break;
  1802. case 15:
  1803. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS;
  1804. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7;
  1805. break;
  1806. default:
  1807. break;
  1808. }
  1809. TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1;
  1810. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  1811. TXMON_HAL_STATUS(ppdu_info, l_sig_a_info) = *l_sig_a_info;
  1812. SHOW_DEFINED(WIFIMACTX_L_SIG_A_E);
  1813. break;
  1814. }
  1815. case WIFIMACTX_L_SIG_B_E:
  1816. {
  1817. uint8_t *l_sig_b_info = NULL;
  1818. uint8_t rate = 0;
  1819. status = HAL_MON_MACTX_L_SIG_B;
  1820. l_sig_b_info = (uint8_t *)tx_tlv +
  1821. HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  1822. RATE);
  1823. rate = HAL_TX_DESC_GET_64(tx_tlv,
  1824. MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS,
  1825. RATE);
  1826. switch (rate) {
  1827. case 1:
  1828. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS;
  1829. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3;
  1830. break;
  1831. case 2:
  1832. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS;
  1833. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2;
  1834. break;
  1835. case 3:
  1836. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS;
  1837. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1;
  1838. break;
  1839. case 4:
  1840. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS;
  1841. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0;
  1842. break;
  1843. case 5:
  1844. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS;
  1845. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6;
  1846. break;
  1847. case 6:
  1848. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS;
  1849. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5;
  1850. break;
  1851. case 7:
  1852. TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS;
  1853. TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4;
  1854. break;
  1855. default:
  1856. break;
  1857. }
  1858. TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1;
  1859. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  1860. TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info;
  1861. SHOW_DEFINED(WIFIMACTX_L_SIG_B_E);
  1862. break;
  1863. }
  1864. case WIFIMACTX_HT_SIG_E:
  1865. {
  1866. uint8_t mcs = 0;
  1867. uint8_t bw = 0;
  1868. uint8_t is_stbc = 0;
  1869. uint8_t coding = 0;
  1870. uint8_t gi = 0;
  1871. status = HAL_MON_MACTX_HT_SIG;
  1872. mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS);
  1873. bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW);
  1874. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC);
  1875. coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING);
  1876. gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI);
  1877. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  1878. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  1879. TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs;
  1880. TXMON_HAL_STATUS(ppdu_info, bw) = bw;
  1881. TXMON_HAL_STATUS(ppdu_info, sgi) = gi;
  1882. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  1883. TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU;
  1884. SHOW_DEFINED(WIFIMACTX_HT_SIG_E);
  1885. break;
  1886. }
  1887. case WIFIMACTX_VHT_SIG_A_E:
  1888. {
  1889. uint8_t bandwidth = 0;
  1890. uint8_t is_stbc = 0;
  1891. uint8_t group_id = 0;
  1892. uint32_t nss_comb = 0;
  1893. uint8_t nss_su = 0;
  1894. uint8_t nss_mu[4] = {0};
  1895. uint8_t sgi = 0;
  1896. uint8_t coding = 0;
  1897. uint8_t mcs = 0;
  1898. uint8_t beamformed = 0;
  1899. uint8_t partial_aid = 0;
  1900. status = HAL_MON_MACTX_VHT_SIG_A;
  1901. bandwidth = HAL_TX_DESC_GET_64(tx_tlv,
  1902. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  1903. BANDWIDTH);
  1904. is_stbc = HAL_TX_DESC_GET_64(tx_tlv,
  1905. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  1906. STBC);
  1907. group_id = HAL_TX_DESC_GET_64(tx_tlv,
  1908. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  1909. GROUP_ID);
  1910. /* nss_comb is su nss, MU nss and partial AID */
  1911. nss_comb = HAL_TX_DESC_GET_64(tx_tlv,
  1912. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  1913. N_STS);
  1914. /* if it is SU */
  1915. nss_su = nss_comb & 0x7;
  1916. /* partial aid - applicable only for SU */
  1917. partial_aid = (nss_comb >> 3) & 0x1F;
  1918. /* if it is MU */
  1919. nss_mu[0] = nss_comb & 0x7;
  1920. nss_mu[1] = (nss_comb >> 3) & 0x7;
  1921. nss_mu[2] = (nss_comb >> 6) & 0x7;
  1922. nss_mu[3] = (nss_comb >> 9) & 0x7;
  1923. sgi = HAL_TX_DESC_GET_64(tx_tlv,
  1924. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  1925. GI_SETTING);
  1926. coding = HAL_TX_DESC_GET_64(tx_tlv,
  1927. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  1928. SU_MU_CODING);
  1929. mcs = HAL_TX_DESC_GET_64(tx_tlv,
  1930. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  1931. MCS);
  1932. beamformed = HAL_TX_DESC_GET_64(tx_tlv,
  1933. MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS,
  1934. BEAMFORMED);
  1935. TXMON_HAL_STATUS(ppdu_info, ldpc) =
  1936. (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0;
  1937. TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id;
  1938. TXMON_HAL_STATUS(ppdu_info, sgi) = sgi;
  1939. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  1940. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  1941. TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed;
  1942. if (group_id == 0 || group_id == 63) {
  1943. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  1944. HAL_RX_TYPE_SU;
  1945. TXMON_HAL_STATUS(ppdu_info, mcs) = mcs;
  1946. TXMON_HAL_STATUS(ppdu_info, nss) =
  1947. nss_su & VHT_SIG_SU_NSS_MASK;
  1948. } else {
  1949. TXMON_HAL_STATUS(ppdu_info, reception_type) =
  1950. HAL_RX_TYPE_MU_MIMO;
  1951. TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs;
  1952. TXMON_HAL_USER(ppdu_info, user_id, nss) =
  1953. nss_su & VHT_SIG_SU_NSS_MASK;
  1954. }
  1955. /* TODO: loop over multiple user */
  1956. TXMON_HAL_USER(ppdu_info, user_id,
  1957. vht_flag_values2) = bandwidth;
  1958. TXMON_HAL_USER(ppdu_info, user_id,
  1959. vht_flag_values3[0]) = (mcs << 4) | nss_su;
  1960. TXMON_HAL_USER(ppdu_info, user_id,
  1961. vht_flag_values3[1]) = (mcs << 4) | nss_mu[1];
  1962. TXMON_HAL_USER(ppdu_info, user_id,
  1963. vht_flag_values3[2]) = (mcs << 4) | nss_mu[2];
  1964. TXMON_HAL_USER(ppdu_info, user_id,
  1965. vht_flag_values3[3]) = (mcs << 4) | nss_mu[3];
  1966. TXMON_HAL_USER(ppdu_info, user_id,
  1967. vht_flag_values4) = coding;
  1968. TXMON_HAL_USER(ppdu_info, user_id,
  1969. vht_flag_values5) = group_id;
  1970. TXMON_HAL_USER(ppdu_info, user_id,
  1971. vht_flag_values6) = partial_aid;
  1972. SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E);
  1973. break;
  1974. }
  1975. case WIFIMACTX_VHT_SIG_B_MU160_E:
  1976. {
  1977. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E);
  1978. break;
  1979. }
  1980. case WIFIMACTX_VHT_SIG_B_MU80_E:
  1981. {
  1982. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E);
  1983. break;
  1984. }
  1985. case WIFIMACTX_VHT_SIG_B_MU40_E:
  1986. {
  1987. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E);
  1988. break;
  1989. }
  1990. case WIFIMACTX_VHT_SIG_B_MU20_E:
  1991. {
  1992. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E);
  1993. break;
  1994. }
  1995. case WIFIMACTX_VHT_SIG_B_SU160_E:
  1996. {
  1997. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E);
  1998. break;
  1999. }
  2000. case WIFIMACTX_VHT_SIG_B_SU80_E:
  2001. {
  2002. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E);
  2003. break;
  2004. }
  2005. case WIFIMACTX_VHT_SIG_B_SU40_E:
  2006. {
  2007. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E);
  2008. break;
  2009. }
  2010. case WIFIMACTX_VHT_SIG_B_SU20_E:
  2011. {
  2012. SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E);
  2013. break;
  2014. }
  2015. case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E:
  2016. {
  2017. SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E);
  2018. break;
  2019. }
  2020. case WIFIMACTX_USER_DESC_PER_USER_E:
  2021. {
  2022. uint32_t psdu_length = 0;
  2023. uint8_t ru_start_index = 0;
  2024. uint8_t ru_size = 0;
  2025. uint8_t nss = 0;
  2026. uint8_t mcs = 0;
  2027. uint8_t dcm = 0;
  2028. uint8_t fec_type = 0;
  2029. uint8_t is_ldpc_extra_symb = 0;
  2030. uint32_t he_data1 = 0;
  2031. uint32_t he_data2 = 0;
  2032. uint32_t he_data3 = 0;
  2033. uint32_t he_data4 = 0;
  2034. uint32_t he_data5 = 0;
  2035. uint32_t he_data6 = 0;
  2036. status = HAL_MON_MACTX_USER_DESC_PER_USER;
  2037. TXMON_HAL(ppdu_info, cur_usr_idx) = user_id;
  2038. psdu_length = HAL_TX_DESC_GET_64(tx_tlv,
  2039. MACTX_USER_DESC_PER_USER,
  2040. PSDU_LENGTH);
  2041. ru_start_index = HAL_TX_DESC_GET_64(tx_tlv,
  2042. MACTX_USER_DESC_PER_USER,
  2043. RU_START_INDEX);
  2044. ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  2045. RU_SIZE);
  2046. nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, NSS);
  2047. mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS);
  2048. dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM);
  2049. fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  2050. FEC_TYPE);
  2051. is_ldpc_extra_symb =
  2052. HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER,
  2053. LDPC_EXTRA_SYMBOL);
  2054. if (!TXMON_HAL_STATUS(ppdu_info, he_flags))
  2055. break;
  2056. /* update */
  2057. /* MCS */
  2058. he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN;
  2059. he_data3 |= (mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT);
  2060. /* DCM */
  2061. he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN;
  2062. he_data3 |= (dcm << QDF_MON_STATUS_DCM_SHIFT);
  2063. /* LDPC EXTRA SYMB */
  2064. he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN;
  2065. he_data3 |= (is_ldpc_extra_symb <<
  2066. QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT);
  2067. /* RU offset and RU */
  2068. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2069. he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN;
  2070. he_data2 |= (ru_start_index <<
  2071. QDF_MON_STATUS_RU_ALLOCATION_SHIFT);
  2072. /* Data BW and RU allocation */
  2073. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2074. he_data5 |= ru_size << 2;
  2075. TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs;
  2076. /* update stack variable to ppdu_info */
  2077. TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= he_data1;
  2078. TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= he_data2;
  2079. TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= he_data3;
  2080. TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= he_data4;
  2081. TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= he_data5;
  2082. TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= he_data6;
  2083. SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E);
  2084. break;
  2085. }
  2086. case WIFIMACTX_USER_DESC_COMMON_E:
  2087. {
  2088. SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E);
  2089. break;
  2090. }
  2091. case WIFIMACTX_PHY_DESC_E:
  2092. {
  2093. uint32_t bf_type = 0;
  2094. /* pkt_type - preamble type */
  2095. uint32_t pkt_type = 0;
  2096. uint8_t bandwidth = 0;
  2097. uint8_t mcs = 0;
  2098. uint8_t is_stbc = 0;
  2099. uint8_t nss = 0;
  2100. uint8_t is_triggered = 0;
  2101. uint8_t gi = 0;
  2102. uint8_t he_ppdu_subtype = 0;
  2103. uint32_t ltf_size = 0;
  2104. uint32_t ru_start = 0;
  2105. uint32_t he_data1 = 0;
  2106. uint32_t he_data2 = 0;
  2107. uint32_t he_data3 = 0;
  2108. uint32_t he_data4 = 0;
  2109. uint32_t he_data5 = 0;
  2110. uint32_t he_data6 = 0;
  2111. uint16_t he_mu_flag_1 = 0;
  2112. uint16_t he_mu_flag_2 = 0;
  2113. uint8_t i = 0;
  2114. status = HAL_MON_MACTX_PHY_DESC;
  2115. bf_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, BF_TYPE);
  2116. pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE);
  2117. mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, MCS);
  2118. is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC);
  2119. is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2120. TRIGGERED);
  2121. if (!is_triggered) {
  2122. nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2123. HEAVY_CLIP_NSS);
  2124. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2125. BANDWIDTH);
  2126. } else {
  2127. nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, NSS);
  2128. /*
  2129. * is_triggered, bw is minimum of AP pkt bw
  2130. * or STA bw
  2131. */
  2132. bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2133. AP_PKT_BW);
  2134. if (pkt_type == TXMON_PKT_TYPE_11AX ||
  2135. pkt_type == TXMON_PKT_TYPE_11BE)
  2136. ru_start =
  2137. HAL_TX_DESC_GET_64(tx_tlv,
  2138. MACTX_PHY_DESC,
  2139. RU_SIZE_UPDATED_V2);
  2140. }
  2141. gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2142. CP_SETTING);
  2143. ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE);
  2144. he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC,
  2145. HE_PPDU_SUBTYPE);
  2146. TXMON_HAL_STATUS(ppdu_info, beamformed) = bf_type;
  2147. TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type;
  2148. TXMON_HAL_STATUS(ppdu_info, mcs) = mcs;
  2149. TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size;
  2150. TXMON_HAL_STATUS(ppdu_info, nss) = nss;
  2151. TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc;
  2152. TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth;
  2153. switch (ppdu_info->rx_status.preamble_type) {
  2154. case TXMON_PKT_TYPE_11N_MM:
  2155. TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1;
  2156. TXMON_HAL_STATUS(ppdu_info,
  2157. rtap_flags) |= HT_SGI_PRESENT;
  2158. break;
  2159. case TXMON_PKT_TYPE_11AC:
  2160. TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1;
  2161. break;
  2162. case TXMON_PKT_TYPE_11AX:
  2163. TXMON_HAL_STATUS(ppdu_info, he_flags) = 1;
  2164. break;
  2165. default:
  2166. break;
  2167. }
  2168. if (!TXMON_HAL_STATUS(ppdu_info, he_flags))
  2169. break;
  2170. /* update he flags */
  2171. /* PPDU FORMAT */
  2172. switch (he_ppdu_subtype) {
  2173. case TXMON_HE_SUBTYPE_SU:
  2174. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2175. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  2176. break;
  2177. case TXMON_HE_SUBTYPE_TRIG:
  2178. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2179. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  2180. break;
  2181. case TXMON_HE_SUBTYPE_MU:
  2182. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2183. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  2184. break;
  2185. case TXMON_HE_SUBTYPE_EXT_SU:
  2186. TXMON_HAL_STATUS(ppdu_info, he_data1) |=
  2187. QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE;
  2188. break;
  2189. };
  2190. /* BEAM CHANGE */
  2191. he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN;
  2192. if (ppdu_info->rx_status.beamformed) {
  2193. he_data1 |= QDF_MON_STATUS_TXBF_KNOWN;
  2194. he_data5 |= (1 << QDF_MON_STATUS_TXBF_SHIFT);
  2195. he_data3 |= (1 << QDF_MON_STATUS_BEAM_CHANGE_SHIFT);
  2196. }
  2197. /* UL/DL known */
  2198. he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN;
  2199. he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT);
  2200. /* MCS */
  2201. he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN;
  2202. he_data3 |= (mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT);
  2203. /* STBC */
  2204. he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN;
  2205. he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT);
  2206. /* GI */
  2207. he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN;
  2208. he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT);
  2209. /* NSS */
  2210. he_data6 |= (nss << QDF_MON_STATUS_HE_DATA_6_NSS_SHIFT);
  2211. /* Data BW and RU allocation */
  2212. he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  2213. he_data5 |= bandwidth;
  2214. /* update stack variable to ppdu_info */
  2215. TXMON_HAL_STATUS(ppdu_info, he_data1) |= he_data1;
  2216. TXMON_HAL_STATUS(ppdu_info, he_data2) |= he_data2;
  2217. TXMON_HAL_STATUS(ppdu_info, he_data3) |= he_data3;
  2218. TXMON_HAL_STATUS(ppdu_info, he_data4) |= he_data4;
  2219. TXMON_HAL_STATUS(ppdu_info, he_data5) |= he_data5;
  2220. TXMON_HAL_STATUS(ppdu_info, he_data6) |= he_data6;
  2221. for (i = 0; i < TXMON_HAL(ppdu_info, num_users); i++) {
  2222. TXMON_HAL_USER(ppdu_info, i, he_data1) |= he_data1;
  2223. TXMON_HAL_USER(ppdu_info, i, he_data2) |= he_data2;
  2224. TXMON_HAL_USER(ppdu_info, i, he_data3) |= he_data3;
  2225. TXMON_HAL_USER(ppdu_info, i, he_data4) |= he_data4;
  2226. TXMON_HAL_USER(ppdu_info, i, he_data5) |= he_data5;
  2227. TXMON_HAL_USER(ppdu_info, i, he_data6) |= he_data6;
  2228. TXMON_HAL_USER(ppdu_info, i, he_flags1) = he_mu_flag_1;
  2229. TXMON_HAL_USER(ppdu_info, i, he_flags2) = he_mu_flag_2;
  2230. }
  2231. SHOW_DEFINED(WIFIMACTX_PHY_DESC_E);
  2232. break;
  2233. }
  2234. case WIFICOEX_RX_STATUS_E:
  2235. {
  2236. SHOW_DEFINED(WIFICOEX_RX_STATUS_E);
  2237. break;
  2238. }
  2239. case WIFIRX_PPDU_ACK_REPORT_E:
  2240. {
  2241. SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E);
  2242. break;
  2243. }
  2244. case WIFIRX_PPDU_NO_ACK_REPORT_E:
  2245. {
  2246. SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E);
  2247. break;
  2248. }
  2249. case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E:
  2250. {
  2251. SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E);
  2252. break;
  2253. }
  2254. case WIFITXPCU_PHYTX_DEBUG32_E:
  2255. {
  2256. SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E);
  2257. break;
  2258. }
  2259. case WIFITXPCU_PREAMBLE_DONE_E:
  2260. {
  2261. SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E);
  2262. break;
  2263. }
  2264. case WIFIRX_PHY_SLEEP_E:
  2265. {
  2266. SHOW_DEFINED(WIFIRX_PHY_SLEEP_E);
  2267. break;
  2268. }
  2269. case WIFIRX_FRAME_BITMAP_REQ_E:
  2270. {
  2271. SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E);
  2272. break;
  2273. }
  2274. case WIFIRXPCU_TX_SETUP_CLEAR_E:
  2275. {
  2276. SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E);
  2277. break;
  2278. }
  2279. case WIFIRX_TRIG_INFO_E:
  2280. {
  2281. SHOW_DEFINED(WIFIRX_TRIG_INFO_E);
  2282. break;
  2283. }
  2284. case WIFIEXPECTED_RESPONSE_E:
  2285. {
  2286. SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E);
  2287. break;
  2288. }
  2289. case WIFITRIGGER_RESPONSE_TX_DONE_E:
  2290. {
  2291. SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E);
  2292. break;
  2293. }
  2294. }
  2295. return status;
  2296. }
  2297. #endif /* QCA_MONITOR_2_0_SUPPORT */
  2298. #ifdef REO_SHARED_QREF_TABLE_EN
  2299. static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
  2300. {
  2301. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2302. uint32_t reg_val = 0;
  2303. /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
  2304. * of 37 peer/tids
  2305. */
  2306. reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
  2307. reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
  2308. HAL_REG_WRITE(hal,
  2309. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2310. reg_val);
  2311. /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
  2312. * of 37 peer/tids
  2313. */
  2314. reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
  2315. HAL_REG_WRITE(hal,
  2316. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2317. reg_val);
  2318. hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
  2319. "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
  2320. "to erase stale entries in reo storage: regval:%x", hal, reg_val);
  2321. }
  2322. /* hal_reo_shared_qaddr_write(): Write REO tid queue addr
  2323. * LUT shared by SW and HW at the index given by peer id
  2324. * and tid.
  2325. *
  2326. * @hal_soc: hal soc pointer
  2327. * @reo_qref_addr: pointer to index pointed to be peer_id
  2328. * and tid
  2329. * @tid: tid queue number
  2330. * @hw_qdesc_paddr: reo queue addr
  2331. */
  2332. static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
  2333. uint16_t peer_id,
  2334. int tid,
  2335. qdf_dma_addr_t hw_qdesc_paddr)
  2336. {
  2337. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2338. struct rx_reo_queue_reference *reo_qref;
  2339. uint32_t peer_tid_idx;
  2340. /* Plug hw_desc_addr in Host reo queue reference table */
  2341. if (HAL_PEER_ID_IS_MLO(peer_id)) {
  2342. peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) *
  2343. DP_MAX_TIDS) + tid;
  2344. reo_qref = (struct rx_reo_queue_reference *)
  2345. &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx];
  2346. } else {
  2347. peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid;
  2348. reo_qref = (struct rx_reo_queue_reference *)
  2349. &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx];
  2350. }
  2351. reo_qref->rx_reo_queue_desc_addr_31_0 =
  2352. hw_qdesc_paddr & 0xffffffff;
  2353. reo_qref->rx_reo_queue_desc_addr_39_32 =
  2354. (hw_qdesc_paddr & 0xff00000000) >> 32;
  2355. if (hw_qdesc_paddr != 0)
  2356. reo_qref->receive_queue_number = tid;
  2357. else
  2358. reo_qref->receive_queue_number = 0;
  2359. hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl);
  2360. hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK,"
  2361. "rx_reo_queue_desc_addr_31_0: %x,"
  2362. "rx_reo_queue_desc_addr_39_32: %x",
  2363. (void *)hw_qdesc_paddr, tid, reo_qref,
  2364. reo_qref->rx_reo_queue_desc_addr_31_0,
  2365. reo_qref->rx_reo_queue_desc_addr_39_32);
  2366. }
  2367. /**
  2368. * hal_reo_shared_qaddr_setup() - Allocate MLO and Non MLO reo queue
  2369. * reference table shared between SW and HW and initialize in Qdesc Base0
  2370. * base1 registers provided by HW.
  2371. *
  2372. * @hal_soc: HAL Soc handle
  2373. *
  2374. * Return: None
  2375. */
  2376. static void hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl)
  2377. {
  2378. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2379. hal->reo_qref.reo_qref_table_en = 1;
  2380. hal->reo_qref.mlo_reo_qref_table_vaddr =
  2381. (uint64_t *)qdf_mem_alloc_consistent(
  2382. hal->qdf_dev, hal->qdf_dev->dev,
  2383. REO_QUEUE_REF_ML_TABLE_SIZE,
  2384. &hal->reo_qref.mlo_reo_qref_table_paddr);
  2385. hal->reo_qref.non_mlo_reo_qref_table_vaddr =
  2386. (uint64_t *)qdf_mem_alloc_consistent(
  2387. hal->qdf_dev, hal->qdf_dev->dev,
  2388. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  2389. &hal->reo_qref.non_mlo_reo_qref_table_paddr);
  2390. hal_verbose_debug("MLO table start paddr:%pK,"
  2391. "Non-MLO table start paddr:%pK,"
  2392. "MLO table start vaddr: %pK,"
  2393. "Non MLO table start vaddr: %pK",
  2394. (void *)hal->reo_qref.mlo_reo_qref_table_paddr,
  2395. (void *)hal->reo_qref.non_mlo_reo_qref_table_paddr,
  2396. hal->reo_qref.mlo_reo_qref_table_vaddr,
  2397. hal->reo_qref.non_mlo_reo_qref_table_vaddr);
  2398. }
  2399. /**
  2400. * hal_reo_shared_qaddr_init() - Zero out REO qref LUT and
  2401. * write start addr of MLO and Non MLO table in HW
  2402. *
  2403. * @hal_soc: HAL Soc handle
  2404. *
  2405. * Return: None
  2406. */
  2407. static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl)
  2408. {
  2409. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2410. qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr,
  2411. REO_QUEUE_REF_ML_TABLE_SIZE);
  2412. qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr,
  2413. REO_QUEUE_REF_NON_ML_TABLE_SIZE);
  2414. /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address
  2415. * and lower 8 bits to be 0. Shift the physical address by 8 to plug
  2416. * upper 32bits only
  2417. */
  2418. HAL_REG_WRITE(hal,
  2419. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  2420. hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8);
  2421. HAL_REG_WRITE(hal,
  2422. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  2423. hal->reo_qref.mlo_reo_qref_table_paddr >> 8);
  2424. HAL_REG_WRITE(hal,
  2425. HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
  2426. HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE,
  2427. 1));
  2428. HAL_REG_WRITE(hal,
  2429. HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE),
  2430. HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED,
  2431. 0x1fff));
  2432. }
  2433. /**
  2434. * hal_reo_shared_qaddr_detach() - Free MLO and Non MLO reo queue
  2435. * reference table shared between SW and HW
  2436. *
  2437. * @hal_soc: HAL Soc handle
  2438. *
  2439. * Return: None
  2440. */
  2441. static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl)
  2442. {
  2443. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  2444. HAL_REG_WRITE(hal,
  2445. HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE),
  2446. 0);
  2447. HAL_REG_WRITE(hal,
  2448. HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
  2449. 0);
  2450. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  2451. REO_QUEUE_REF_ML_TABLE_SIZE,
  2452. hal->reo_qref.mlo_reo_qref_table_vaddr,
  2453. hal->reo_qref.mlo_reo_qref_table_paddr, 0);
  2454. qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
  2455. REO_QUEUE_REF_NON_ML_TABLE_SIZE,
  2456. hal->reo_qref.non_mlo_reo_qref_table_vaddr,
  2457. hal->reo_qref.non_mlo_reo_qref_table_paddr, 0);
  2458. }
  2459. #endif
  2460. /**
  2461. * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing
  2462. * @hal_soc: HAL SoC context
  2463. * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
  2464. * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
  2465. *
  2466. * Return: void
  2467. */
  2468. #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
  2469. static inline void
  2470. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  2471. enum hal_tx_vdev_mismatch_notify
  2472. config)
  2473. {
  2474. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2475. uint32_t reg_addr, reg_val = 0;
  2476. uint32_t val = 0;
  2477. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  2478. val = HAL_REG_READ(hal_soc, reg_addr);
  2479. /* reset the corresponding bits in register */
  2480. val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK));
  2481. /* set config value */
  2482. reg_val = val | (config <<
  2483. HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT);
  2484. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  2485. }
  2486. #else
  2487. static inline void
  2488. hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
  2489. enum hal_tx_vdev_mismatch_notify
  2490. config)
  2491. {
  2492. }
  2493. #endif
  2494. /**
  2495. * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing
  2496. * @hal_soc: HAL SoC context
  2497. * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
  2498. * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
  2499. *
  2500. * Return: void
  2501. */
  2502. #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
  2503. defined(WLAN_MCAST_MLO)
  2504. static inline void
  2505. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  2506. hal_soc_handle_t hal_soc_hdl,
  2507. enum hal_tx_mcast_mlo_reinject_notify config)
  2508. {
  2509. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2510. uint32_t reg_addr, reg_val = 0;
  2511. uint32_t val = 0;
  2512. reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
  2513. val = HAL_REG_READ(hal_soc, reg_addr);
  2514. /* reset the corresponding bits in register */
  2515. val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK));
  2516. /* set config value */
  2517. reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT);
  2518. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  2519. }
  2520. #else
  2521. static inline void
  2522. hal_tx_mcast_mlo_reinject_routing_set_generic_be(
  2523. hal_soc_handle_t hal_soc_hdl,
  2524. enum hal_tx_mcast_mlo_reinject_notify config)
  2525. {
  2526. }
  2527. #endif
  2528. /**
  2529. * hal_get_ba_aging_timeout_be - Get BA Aging timeout
  2530. *
  2531. * @hal_soc: Opaque HAL SOC handle
  2532. * @ac: Access category
  2533. * @value: window size to get
  2534. */
  2535. static inline
  2536. void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  2537. uint8_t ac, uint32_t *value)
  2538. {
  2539. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  2540. switch (ac) {
  2541. case WME_AC_BE:
  2542. *value = HAL_REG_READ(soc,
  2543. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  2544. REO_REG_REG_BASE)) / 1000;
  2545. break;
  2546. case WME_AC_BK:
  2547. *value = HAL_REG_READ(soc,
  2548. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  2549. REO_REG_REG_BASE)) / 1000;
  2550. break;
  2551. case WME_AC_VI:
  2552. *value = HAL_REG_READ(soc,
  2553. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  2554. REO_REG_REG_BASE)) / 1000;
  2555. break;
  2556. case WME_AC_VO:
  2557. *value = HAL_REG_READ(soc,
  2558. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  2559. REO_REG_REG_BASE)) / 1000;
  2560. break;
  2561. default:
  2562. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2563. "Invalid AC: %d\n", ac);
  2564. }
  2565. }
  2566. /**
  2567. * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
  2568. * buffer list provided
  2569. *
  2570. * @hal_soc: Opaque HAL SOC handle
  2571. * @scatter_bufs_base_paddr: Array of physical base addresses
  2572. * @scatter_bufs_base_vaddr: Array of virtual base addresses
  2573. * @num_scatter_bufs: Number of scatter buffers in the above lists
  2574. * @scatter_buf_size: Size of each scatter buffer
  2575. * @last_buf_end_offset: Offset to the last entry
  2576. * @num_entries: Total entries of all scatter bufs
  2577. *
  2578. * Return: None
  2579. */
  2580. static inline void
  2581. hal_setup_link_idle_list_generic_be(struct hal_soc *soc,
  2582. qdf_dma_addr_t scatter_bufs_base_paddr[],
  2583. void *scatter_bufs_base_vaddr[],
  2584. uint32_t num_scatter_bufs,
  2585. uint32_t scatter_buf_size,
  2586. uint32_t last_buf_end_offset,
  2587. uint32_t num_entries)
  2588. {
  2589. int i;
  2590. uint32_t *prev_buf_link_ptr = NULL;
  2591. uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
  2592. uint32_t val;
  2593. /* Link the scatter buffers */
  2594. for (i = 0; i < num_scatter_bufs; i++) {
  2595. if (i > 0) {
  2596. prev_buf_link_ptr[0] =
  2597. scatter_bufs_base_paddr[i] & 0xffffffff;
  2598. prev_buf_link_ptr[1] = HAL_SM(
  2599. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2600. BASE_ADDRESS_39_32,
  2601. ((uint64_t)(scatter_bufs_base_paddr[i])
  2602. >> 32)) | HAL_SM(
  2603. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2604. ADDRESS_MATCH_TAG,
  2605. ADDRESS_MATCH_TAG_VAL);
  2606. }
  2607. prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
  2608. scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
  2609. }
  2610. /* TBD: Register programming partly based on MLD & the rest based on
  2611. * inputs from HW team. Not complete yet.
  2612. */
  2613. reg_scatter_buf_size = (scatter_buf_size -
  2614. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
  2615. reg_tot_scatter_buf_size = ((scatter_buf_size -
  2616. WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
  2617. HAL_REG_WRITE(soc,
  2618. HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
  2619. WBM_REG_REG_BASE),
  2620. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
  2621. reg_scatter_buf_size) |
  2622. HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
  2623. 0x1));
  2624. HAL_REG_WRITE(soc,
  2625. HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
  2626. WBM_REG_REG_BASE),
  2627. HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
  2628. SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
  2629. reg_tot_scatter_buf_size));
  2630. HAL_REG_WRITE(soc,
  2631. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
  2632. WBM_REG_REG_BASE),
  2633. scatter_bufs_base_paddr[0] & 0xffffffff);
  2634. HAL_REG_WRITE(soc,
  2635. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  2636. WBM_REG_REG_BASE),
  2637. ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
  2638. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
  2639. HAL_REG_WRITE(soc,
  2640. HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
  2641. WBM_REG_REG_BASE),
  2642. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2643. BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
  2644. >> 32)) |
  2645. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
  2646. ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
  2647. /* ADDRESS_MATCH_TAG field in the above register is expected to match
  2648. * with the upper bits of link pointer. The above write sets this field
  2649. * to zero and we are also setting the upper bits of link pointers to
  2650. * zero while setting up the link list of scatter buffers above
  2651. */
  2652. /* Setup head and tail pointers for the idle list */
  2653. HAL_REG_WRITE(soc,
  2654. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  2655. WBM_REG_REG_BASE),
  2656. scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
  2657. HAL_REG_WRITE(soc,
  2658. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
  2659. WBM_REG_REG_BASE),
  2660. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  2661. BUFFER_ADDRESS_39_32,
  2662. ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1])
  2663. >> 32)) |
  2664. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
  2665. HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
  2666. HAL_REG_WRITE(soc,
  2667. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
  2668. WBM_REG_REG_BASE),
  2669. scatter_bufs_base_paddr[0] & 0xffffffff);
  2670. HAL_REG_WRITE(soc,
  2671. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
  2672. WBM_REG_REG_BASE),
  2673. scatter_bufs_base_paddr[0] & 0xffffffff);
  2674. HAL_REG_WRITE(soc,
  2675. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
  2676. WBM_REG_REG_BASE),
  2677. HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  2678. BUFFER_ADDRESS_39_32,
  2679. ((uint64_t)(scatter_bufs_base_paddr[0]) >>
  2680. 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
  2681. TAIL_POINTER_OFFSET, 0));
  2682. HAL_REG_WRITE(soc,
  2683. HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
  2684. WBM_REG_REG_BASE),
  2685. 2 * num_entries);
  2686. /* Set RING_ID_DISABLE */
  2687. val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
  2688. /*
  2689. * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
  2690. * check the presence of the bit before toggling it.
  2691. */
  2692. #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
  2693. val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
  2694. #endif
  2695. HAL_REG_WRITE(soc,
  2696. HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE),
  2697. val);
  2698. }
  2699. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  2700. #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
  2701. #endif
  2702. /**
  2703. * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register
  2704. * for REO/WBM
  2705. * @soc: HAL soc handle
  2706. * @cc_cfg: structure pointer for HW cookie conversion configuration
  2707. *
  2708. * Return: None
  2709. */
  2710. static inline
  2711. void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl,
  2712. struct hal_hw_cc_config *cc_cfg)
  2713. {
  2714. uint32_t reg_addr, reg_val = 0;
  2715. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  2716. /* REO CFG */
  2717. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
  2718. reg_val = cc_cfg->lut_base_addr_31_0;
  2719. HAL_REG_WRITE(soc, reg_addr, reg_val);
  2720. reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
  2721. reg_val = 0;
  2722. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  2723. SW_COOKIE_CONVERT_GLOBAL_ENABLE,
  2724. cc_cfg->cc_global_en);
  2725. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  2726. SW_COOKIE_CONVERT_ENABLE,
  2727. cc_cfg->cc_global_en);
  2728. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  2729. PAGE_ALIGNMENT,
  2730. cc_cfg->page_4k_align);
  2731. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  2732. COOKIE_OFFSET_MSB,
  2733. cc_cfg->cookie_offset_msb);
  2734. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  2735. COOKIE_PAGE_MSB,
  2736. cc_cfg->cookie_page_msb);
  2737. reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
  2738. CMEM_LUT_BASE_ADDR_39_32,
  2739. cc_cfg->lut_base_addr_39_32);
  2740. HAL_REG_WRITE(soc, reg_addr, reg_val);
  2741. /* WBM CFG */
  2742. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
  2743. reg_val = cc_cfg->lut_base_addr_31_0;
  2744. HAL_REG_WRITE(soc, reg_addr, reg_val);
  2745. reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
  2746. reg_val = 0;
  2747. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  2748. PAGE_ALIGNMENT,
  2749. cc_cfg->page_4k_align);
  2750. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  2751. COOKIE_OFFSET_MSB,
  2752. cc_cfg->cookie_offset_msb);
  2753. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  2754. COOKIE_PAGE_MSB,
  2755. cc_cfg->cookie_page_msb);
  2756. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
  2757. CMEM_LUT_BASE_ADDR_39_32,
  2758. cc_cfg->lut_base_addr_39_32);
  2759. HAL_REG_WRITE(soc, reg_addr, reg_val);
  2760. /*
  2761. * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
  2762. */
  2763. reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
  2764. reg_val = 0;
  2765. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2766. WBM_COOKIE_CONV_GLOBAL_ENABLE,
  2767. cc_cfg->cc_global_en);
  2768. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2769. WBM2SW6_COOKIE_CONVERSION_EN,
  2770. cc_cfg->wbm2sw6_cc_en);
  2771. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2772. WBM2SW5_COOKIE_CONVERSION_EN,
  2773. cc_cfg->wbm2sw5_cc_en);
  2774. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2775. WBM2SW4_COOKIE_CONVERSION_EN,
  2776. cc_cfg->wbm2sw4_cc_en);
  2777. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2778. WBM2SW3_COOKIE_CONVERSION_EN,
  2779. cc_cfg->wbm2sw3_cc_en);
  2780. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2781. WBM2SW2_COOKIE_CONVERSION_EN,
  2782. cc_cfg->wbm2sw2_cc_en);
  2783. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2784. WBM2SW1_COOKIE_CONVERSION_EN,
  2785. cc_cfg->wbm2sw1_cc_en);
  2786. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2787. WBM2SW0_COOKIE_CONVERSION_EN,
  2788. cc_cfg->wbm2sw0_cc_en);
  2789. reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
  2790. WBM2FW_COOKIE_CONVERSION_EN,
  2791. cc_cfg->wbm2fw_cc_en);
  2792. HAL_REG_WRITE(soc, reg_addr, reg_val);
  2793. #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
  2794. reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
  2795. reg_val = 0;
  2796. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  2797. COOKIE_DEBUG_SEL,
  2798. cc_cfg->cc_global_en);
  2799. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  2800. COOKIE_CONV_INDICATION_EN,
  2801. cc_cfg->cc_global_en);
  2802. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  2803. ERROR_PATH_COOKIE_CONV_EN,
  2804. cc_cfg->error_path_cookie_conv_en);
  2805. reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
  2806. RELEASE_PATH_COOKIE_CONV_EN,
  2807. cc_cfg->release_path_cookie_conv_en);
  2808. HAL_REG_WRITE(soc, reg_addr, reg_val);
  2809. #endif
  2810. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  2811. /*
  2812. * To enable indication for HW cookie conversion done or not for
  2813. * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
  2814. * bit spare_control[15] should be set.
  2815. */
  2816. reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
  2817. reg_val = HAL_REG_READ(soc, reg_addr);
  2818. reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
  2819. SPARE_CONTROL,
  2820. HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
  2821. HAL_REG_WRITE(soc, reg_addr, reg_val);
  2822. #endif
  2823. }
  2824. /**
  2825. * hal_set_ba_aging_timeout_be - Set BA Aging timeout
  2826. *
  2827. * @hal_soc: Opaque HAL SOC handle
  2828. * @ac: Access category
  2829. * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
  2830. * @value: Input value to set
  2831. */
  2832. static inline
  2833. void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
  2834. uint8_t ac, uint32_t value)
  2835. {
  2836. struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
  2837. switch (ac) {
  2838. case WME_AC_BE:
  2839. HAL_REG_WRITE(soc,
  2840. HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
  2841. REO_REG_REG_BASE),
  2842. value * 1000);
  2843. break;
  2844. case WME_AC_BK:
  2845. HAL_REG_WRITE(soc,
  2846. HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
  2847. REO_REG_REG_BASE),
  2848. value * 1000);
  2849. break;
  2850. case WME_AC_VI:
  2851. HAL_REG_WRITE(soc,
  2852. HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
  2853. REO_REG_REG_BASE),
  2854. value * 1000);
  2855. break;
  2856. case WME_AC_VO:
  2857. HAL_REG_WRITE(soc,
  2858. HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
  2859. REO_REG_REG_BASE),
  2860. value * 1000);
  2861. break;
  2862. default:
  2863. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2864. "Invalid AC: %d\n", ac);
  2865. }
  2866. }
  2867. /**
  2868. * hal_tx_populate_bank_register() - populate the bank register with
  2869. * the software configs.
  2870. * @soc: HAL soc handle
  2871. * @config: bank config
  2872. * @bank_id: bank id to be configured
  2873. *
  2874. * Returns: None
  2875. */
  2876. #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT
  2877. static inline void
  2878. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  2879. union hal_tx_bank_config *config,
  2880. uint8_t bank_id)
  2881. {
  2882. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2883. uint32_t reg_addr, reg_val = 0;
  2884. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  2885. bank_id);
  2886. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  2887. reg_val |= (config->encap_type <<
  2888. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  2889. reg_val |= (config->encrypt_type <<
  2890. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  2891. reg_val |= (config->src_buffer_swap <<
  2892. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  2893. reg_val |= (config->link_meta_swap <<
  2894. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  2895. reg_val |= (config->index_lookup_enable <<
  2896. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  2897. reg_val |= (config->addrx_en <<
  2898. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  2899. reg_val |= (config->addry_en <<
  2900. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  2901. reg_val |= (config->mesh_enable <<
  2902. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  2903. reg_val |= (config->vdev_id_check_en <<
  2904. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  2905. reg_val |= (config->pmac_id <<
  2906. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  2907. reg_val |= (config->mcast_pkt_ctrl <<
  2908. HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
  2909. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  2910. }
  2911. #else
  2912. static inline void
  2913. hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl,
  2914. union hal_tx_bank_config *config,
  2915. uint8_t bank_id)
  2916. {
  2917. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2918. uint32_t reg_addr, reg_val = 0;
  2919. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  2920. bank_id);
  2921. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  2922. reg_val |= (config->encap_type <<
  2923. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  2924. reg_val |= (config->encrypt_type <<
  2925. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  2926. reg_val |= (config->src_buffer_swap <<
  2927. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  2928. reg_val |= (config->link_meta_swap <<
  2929. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  2930. reg_val |= (config->index_lookup_enable <<
  2931. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  2932. reg_val |= (config->addrx_en <<
  2933. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  2934. reg_val |= (config->addry_en <<
  2935. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  2936. reg_val |= (config->mesh_enable <<
  2937. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  2938. reg_val |= (config->vdev_id_check_en <<
  2939. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  2940. reg_val |= (config->pmac_id <<
  2941. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  2942. reg_val |= (config->dscp_tid_map_id <<
  2943. HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT);
  2944. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  2945. }
  2946. #endif
  2947. #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT
  2948. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4)
  2949. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF)
  2950. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3
  2951. #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2
  2952. /**
  2953. * hal_tx_vdev_mcast_ctrl_set - set mcast_ctrl value
  2954. * @hal_soc: HAL SoC context
  2955. * @mcast_ctrl_val: mcast ctrl value for this VAP
  2956. *
  2957. * Return: void
  2958. */
  2959. static inline void
  2960. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  2961. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  2962. {
  2963. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2964. uint32_t reg_addr, reg_val = 0;
  2965. uint32_t val;
  2966. uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id);
  2967. uint8_t index_in_reg =
  2968. HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id);
  2969. reg_addr =
  2970. HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE,
  2971. reg_idx);
  2972. val = HAL_REG_READ(hal_soc, reg_addr);
  2973. /* mask out other stored value */
  2974. val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK <<
  2975. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)));
  2976. reg_val = val |
  2977. ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) <<
  2978. (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg));
  2979. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  2980. }
  2981. #else
  2982. static inline void
  2983. hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl,
  2984. uint8_t vdev_id, uint8_t mcast_ctrl_val)
  2985. {
  2986. }
  2987. #endif
  2988. #endif /* _HAL_BE_GENERIC_API_H_ */