samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

qcedev: vote for clocks based on dts values

Browse Source 
Use DTSI values to vote for clocks instead of using
fixed values. This enables to vote for crypto clocks
on a per target basis.

Change-Id: I05c9e55f4aa0ec876903f1963f859ecf1fc929ab
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
This commit is contained in:
Gaurav Kashyap
2022-07-15 09:18:24 -07:00
committed by Gerrit - the friendly Code Review server
parent 1bdcb08f83
commit 79b3d0e377
3 changed files with 30 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
crypto-qti/qce.h
View File

@@ -55,9 +55,9 @@
#define QCE_CLK_DISABLE_FIRST 3 #define QCE_CLK_DISABLE_FIRST 3
#define QCE_BW_REQUEST_RESET_FIRST 4 #define QCE_BW_REQUEST_RESET_FIRST 4
/* interconnect average and peak bw for crypto device */ /* default average and peak bw for crypto device */
#define CRYPTO_AVG_BW 393600 #define CRYPTO_AVG_BW 100100
#define CRYPTO_PEAK_BW 393600 #define CRYPTO_PEAK_BW 100100
typedef void (*qce_comp_func_ptr_t)(void *areq, typedef void (*qce_comp_func_ptr_t)(void *areq,
unsigned char *icv, unsigned char *iv, int ret); unsigned char *icv, unsigned char *iv, int ret);

27
crypto-qti/qcedev.c
View File

@@ -113,7 +113,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
return ret; return ret;
} }
ret = icc_set_bw(podev->icc_path, ret = icc_set_bw(podev->icc_path,
CRYPTO_AVG_BW, CRYPTO_PEAK_BW); podev->icc_avg_bw, podev->icc_peak_bw);
if (ret) { if (ret) {
pr_err("%s Unable to set high bw\n", __func__); pr_err("%s Unable to set high bw\n", __func__);
ret = qce_disable_clk(podev->qce); ret = qce_disable_clk(podev->qce);
@@ -124,7 +124,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
break; break;
case QCE_BW_REQUEST_FIRST: case QCE_BW_REQUEST_FIRST:
ret = icc_set_bw(podev->icc_path, ret = icc_set_bw(podev->icc_path,
CRYPTO_AVG_BW, CRYPTO_PEAK_BW); podev->icc_avg_bw, podev->icc_peak_bw);
if (ret) { if (ret) {
pr_err("%s Unable to set high bw\n", __func__); pr_err("%s Unable to set high bw\n", __func__);
return ret; return ret;
@@ -163,7 +163,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
if (ret) { if (ret) {
pr_err("%s Unable to disable clk\n", __func__); pr_err("%s Unable to disable clk\n", __func__);
ret = icc_set_bw(podev->icc_path, ret = icc_set_bw(podev->icc_path,
CRYPTO_AVG_BW, CRYPTO_PEAK_BW); podev->icc_avg_bw, podev->icc_peak_bw);
if (ret) if (ret)
pr_err("%s Unable to set high bw\n", __func__); pr_err("%s Unable to set high bw\n", __func__);
return ret; return ret;
@@ -2495,7 +2495,26 @@ static int qcedev_probe_device(struct platform_device *pdev)
goto exit_del_cdev; goto exit_del_cdev;
} }
rc = icc_set_bw(podev->icc_path, CRYPTO_AVG_BW, CRYPTO_PEAK_BW); /*
* HLOS crypto vote values from DTSI. If no values specified, use
* nominal values.
*/
if (of_property_read_u32((&pdev->dev)->of_node,
"qcom,icc_avg_bw",
&podev->icc_avg_bw)) {
pr_warn("%s: No icc avg BW set, using default\n", __func__);
podev->icc_avg_bw = CRYPTO_AVG_BW;
}
if (of_property_read_u32((&pdev->dev)->of_node,
"qcom,icc_peak_bw",
&podev->icc_peak_bw)) {
pr_warn("%s: No icc peak BW set, using default\n", __func__);
podev->icc_peak_bw = CRYPTO_PEAK_BW;
}
rc = icc_set_bw(podev->icc_path, podev->icc_avg_bw,
podev->icc_peak_bw);
if (rc) { if (rc) {
pr_err("%s Unable to set high bandwidth\n", __func__); pr_err("%s Unable to set high bandwidth\n", __func__);
goto exit_unregister_bus_scale; goto exit_unregister_bus_scale;

4
crypto-qti/qcedevi.h
View File

@@ -89,6 +89,10 @@ struct qcedev_control {
/* replaced msm_bus with interconnect path */ /* replaced msm_bus with interconnect path */
struct icc_path *icc_path; struct icc_path *icc_path;
/* average and peak bw values for interconnect */
uint32_t icc_avg_bw;
uint32_t icc_peak_bw;
/* char device */ /* char device */
struct cdev cdev; struct cdev cdev;