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@@ -113,7 +113,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
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return ret;
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}
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ret = icc_set_bw(podev->icc_path,
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- CRYPTO_AVG_BW, CRYPTO_PEAK_BW);
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+ podev->icc_avg_bw, podev->icc_peak_bw);
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if (ret) {
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pr_err("%s Unable to set high bw\n", __func__);
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ret = qce_disable_clk(podev->qce);
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@@ -124,7 +124,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
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break;
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case QCE_BW_REQUEST_FIRST:
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ret = icc_set_bw(podev->icc_path,
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- CRYPTO_AVG_BW, CRYPTO_PEAK_BW);
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+ podev->icc_avg_bw, podev->icc_peak_bw);
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if (ret) {
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pr_err("%s Unable to set high bw\n", __func__);
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return ret;
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@@ -163,7 +163,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
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if (ret) {
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pr_err("%s Unable to disable clk\n", __func__);
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ret = icc_set_bw(podev->icc_path,
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- CRYPTO_AVG_BW, CRYPTO_PEAK_BW);
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+ podev->icc_avg_bw, podev->icc_peak_bw);
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if (ret)
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pr_err("%s Unable to set high bw\n", __func__);
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return ret;
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@@ -2495,7 +2495,26 @@ static int qcedev_probe_device(struct platform_device *pdev)
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goto exit_del_cdev;
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}
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- rc = icc_set_bw(podev->icc_path, CRYPTO_AVG_BW, CRYPTO_PEAK_BW);
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+ /*
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+ * HLOS crypto vote values from DTSI. If no values specified, use
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+ * nominal values.
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+ */
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+ if (of_property_read_u32((&pdev->dev)->of_node,
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+ "qcom,icc_avg_bw",
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+ &podev->icc_avg_bw)) {
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+ pr_warn("%s: No icc avg BW set, using default\n", __func__);
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+ podev->icc_avg_bw = CRYPTO_AVG_BW;
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+ }
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+
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+ if (of_property_read_u32((&pdev->dev)->of_node,
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+ "qcom,icc_peak_bw",
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+ &podev->icc_peak_bw)) {
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+ pr_warn("%s: No icc peak BW set, using default\n", __func__);
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+ podev->icc_peak_bw = CRYPTO_PEAK_BW;
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+ }
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+
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+ rc = icc_set_bw(podev->icc_path, podev->icc_avg_bw,
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+ podev->icc_peak_bw);
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if (rc) {
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pr_err("%s Unable to set high bandwidth\n", __func__);
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goto exit_unregister_bus_scale;
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