diff --git a/crypto-qti/qce.h b/crypto-qti/qce.h
index a0e1e36912..3c64e30b60 100644
--- a/crypto-qti/qce.h
+++ b/crypto-qti/qce.h
@@ -55,9 +55,9 @@
 #define QCE_CLK_DISABLE_FIRST		3
 #define QCE_BW_REQUEST_RESET_FIRST	4
 
-/* interconnect average and peak bw for crypto device */
-#define CRYPTO_AVG_BW			393600
-#define CRYPTO_PEAK_BW			393600
+/* default average and peak bw for crypto device */
+#define CRYPTO_AVG_BW			100100
+#define CRYPTO_PEAK_BW			100100
 
 typedef void (*qce_comp_func_ptr_t)(void *areq,
 		unsigned char *icv, unsigned char *iv, int ret);
diff --git a/crypto-qti/qcedev.c b/crypto-qti/qcedev.c
index db0cbf3a93..8b4b737ae2 100644
--- a/crypto-qti/qcedev.c
+++ b/crypto-qti/qcedev.c
@@ -113,7 +113,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
 			return ret;
 		}
 		ret = icc_set_bw(podev->icc_path,
-				CRYPTO_AVG_BW, CRYPTO_PEAK_BW);
+				podev->icc_avg_bw, podev->icc_peak_bw);
 		if (ret) {
 			pr_err("%s Unable to set high bw\n", __func__);
 			ret = qce_disable_clk(podev->qce);
@@ -124,7 +124,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
 		break;
 	case QCE_BW_REQUEST_FIRST:
 		ret = icc_set_bw(podev->icc_path,
-				CRYPTO_AVG_BW, CRYPTO_PEAK_BW);
+				podev->icc_avg_bw, podev->icc_peak_bw);
 		if (ret) {
 			pr_err("%s Unable to set high bw\n", __func__);
 			return ret;
@@ -163,7 +163,7 @@ static int qcedev_control_clocks(struct qcedev_control *podev, bool enable)
 		if (ret) {
 			pr_err("%s Unable to disable clk\n", __func__);
 			ret = icc_set_bw(podev->icc_path,
-					CRYPTO_AVG_BW, CRYPTO_PEAK_BW);
+					podev->icc_avg_bw, podev->icc_peak_bw);
 			if (ret)
 				pr_err("%s Unable to set high bw\n", __func__);
 			return ret;
@@ -2495,7 +2495,26 @@ static int qcedev_probe_device(struct platform_device *pdev)
 		goto exit_del_cdev;
 	}
 
-	rc = icc_set_bw(podev->icc_path, CRYPTO_AVG_BW, CRYPTO_PEAK_BW);
+	/*
+	 * HLOS crypto vote values from DTSI. If no values specified, use
+	 * nominal values.
+	 */
+	if (of_property_read_u32((&pdev->dev)->of_node,
+				"qcom,icc_avg_bw",
+				&podev->icc_avg_bw)) {
+		pr_warn("%s: No icc avg BW set, using default\n", __func__);
+		podev->icc_avg_bw = CRYPTO_AVG_BW;
+	}
+
+	if (of_property_read_u32((&pdev->dev)->of_node,
+				"qcom,icc_peak_bw",
+				&podev->icc_peak_bw)) {
+		pr_warn("%s: No icc peak BW set, using default\n", __func__);
+		podev->icc_peak_bw = CRYPTO_PEAK_BW;
+	}
+
+	rc = icc_set_bw(podev->icc_path, podev->icc_avg_bw,
+				podev->icc_peak_bw);
 	if (rc) {
 		pr_err("%s Unable to set high bandwidth\n", __func__);
 		goto exit_unregister_bus_scale;
diff --git a/crypto-qti/qcedevi.h b/crypto-qti/qcedevi.h
index ca0208a736..6a7ec0b57c 100644
--- a/crypto-qti/qcedevi.h
+++ b/crypto-qti/qcedevi.h
@@ -89,6 +89,10 @@ struct qcedev_control {
 	/* replaced msm_bus with interconnect path */
 	struct icc_path *icc_path;
 
+	/* average and peak bw values for interconnect */
+	uint32_t icc_avg_bw;
+	uint32_t icc_peak_bw;
+
 	/* char device */
 	struct cdev cdev;