asoc: add the initial tambora driver files

Add the initial tambora driver files.

Change-Id: Ic6bebd953f031549e7cf72874cebd4fae05deae3
Signed-off-by: Yuhui Zhao <[email protected]>

asoc/codecs/wcd9378/Kbuild

@@ -0,0 +1,125 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_KONA), y)
+		include $(AUDIO_ROOT)/config/konaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/konaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_LITO), y)
+		include $(AUDIO_ROOT)/config/litoauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/litoautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_WAIPIO), y)
+		include $(AUDIO_ROOT)/config/waipioauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/waipioautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KALAMA), y)
+		include $(AUDIO_ROOT)/config/kalamaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/kalamaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
+		include $(AUDIO_ROOT)/config/pineappleauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pineappleautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_PITTI), y)
+		include $(AUDIO_ROOT)/config/pittiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pittiautoconf.h
+	endif
+
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ WCD9378 ############
+
+# for WCD9378 Codec
+ifdef CONFIG_SND_SOC_WCD9378
+	WCD9378_OBJS += wcd9378.o
+	WCD9378_OBJS += wcd9378-regmap.o
+	WCD9378_OBJS += wcd9378-tables.o
+	WCD9378_OBJS += wcd9378-mbhc.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD9378_SLAVE
+	WCD9378_SLAVE_OBJS += wcd9378-slave.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+ccflags-y += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+ccflags-y += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+ccflags-y += -Wheader-guard
+endif
+
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_WCD9378) += wcd9378_dlkm.o
+wcd9378_dlkm-y := $(WCD9378_OBJS)
+
+obj-$(CONFIG_SND_SOC_WCD9378_SLAVE) += wcd9378_slave_dlkm.o
+wcd9378_slave_dlkm-y := $(WCD9378_SLAVE_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

asoc/codecs/wcd9378/Makefile

@@ -0,0 +1,6 @@
+modules:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
+modules_install:
+	$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

asoc/codecs/wcd9378/internal.h

@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _WCD9378_INTERNAL_H
+#define _WCD9378_INTERNAL_H
+
+#include <asoc/wcd-mbhc-v2.h>
+#include <asoc/wcd-irq.h>
+#include <asoc/wcd-clsh.h>
+#include <soc/soundwire.h>
+#include "wcd9378-mbhc.h"
+#include "wcd9378.h"
+
+#define SWR_SCP_CONTROL    0x44
+#define SWR_SCP_HOST_CLK_DIV2_CTL_BANK 0xE0
+#define WCD9378_MAX_MICBIAS 3
+#define SIM_MIC_NUM	3
+
+
+/* Convert from vout ctl to micbias voltage in mV */
+#define  WCD_VOUT_CTL_TO_MICB(v)  (1000 + v * 50)
+#define MAX_PORT 8
+#define MAX_CH_PER_PORT 8
+#define TX_ADC_MAX 3
+#define SWR_NUM_PORTS	4
+
+enum {
+	TX_HDR12 = 0,
+	TX_HDR34,
+	TX_HDR_MAX,
+};
+
+enum {
+	SIM_MIC0,
+	SIM_MIC1,
+	SIM_MIC2,
+	SIM_JACK,
+	MICB_VAL_NUM,
+};
+
+extern struct regmap_config wcd9378_regmap_config;
+
+struct codec_port_info {
+	u32 slave_port_type;
+	u32 master_port_type;
+	u32 ch_mask;
+	u32 num_ch;
+	u32 ch_rate;
+};
+
+enum {
+	RX_CLK_9P6MHZ,
+	RX_CLK_12P288MHZ,
+	RX_CLK_11P2896MHZ,
+};
+
+enum {
+	RX_PATH,
+	TX_PATH,
+};
+
+struct wcd9378_priv {
+	struct device *dev;
+	u32 sys_usage;
+	u32 wcd_mode;
+
+	int variant;
+	struct snd_soc_component *component;
+	struct device_node *rst_np;
+	struct regmap *regmap;
+
+	struct swr_device *rx_swr_dev;
+	struct swr_device *tx_swr_dev;
+
+	s32 micb_ref[WCD9378_MAX_MICBIAS];
+	s32 pullup_ref[WCD9378_MAX_MICBIAS];
+
+	u32 micb_sel[SIM_MIC_NUM];
+	u32 micb_val[MICB_VAL_NUM];
+
+	struct device_node *wcd_rst_np;
+
+	struct mutex micb_lock;
+	struct mutex wakeup_lock;
+	s32 dmic_0_1_clk_cnt;
+	s32 dmic_2_3_clk_cnt;
+	s32 dmic_4_5_clk_cnt;
+	int hdr_en[TX_HDR_MAX];
+	/* class h specific info */
+	struct wcd_clsh_cdc_info clsh_info;
+	/* mbhc module */
+	struct wcd9378_mbhc *mbhc;
+
+	u32 hph_mode;
+	u16 hph_gain;
+	u32 rx2_clk_mode;
+	u32 tx_mode[TX_ADC_MAX];
+	s32 adc_count;
+	bool comp1_enable;
+	bool comp2_enable;
+	bool va_amic_en;
+	bool ear_enable;
+	bool aux_enable;
+	bool ldoh;
+	bool bcs_dis;
+	bool dapm_bias_off;
+	struct irq_domain *virq;
+	struct wcd_irq_info irq_info;
+	u32 rx_clk_cnt;
+	int num_irq_regs;
+	/* to track the status */
+	unsigned long status_mask;
+
+	u8 num_tx_ports;
+	u8 num_rx_ports;
+	struct codec_port_info
+			tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
+	struct codec_port_info
+			rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
+	struct swr_port_params tx_port_params[SWR_UC_MAX][SWR_NUM_PORTS];
+	struct swr_dev_frame_config swr_tx_port_params[SWR_UC_MAX];
+	struct regulator_bulk_data *supplies;
+	struct notifier_block nblock;
+	/* wcd callback to bolero */
+	void *handle;
+	int (*update_wcd_event)(void *handle, u16 event, u32 data);
+	int (*register_notifier)(void *handle,
+				struct notifier_block *nblock,
+				bool enable);
+	int (*wakeup)(void *handle, bool enable);
+	u32 version;
+	/* Entry for version info */
+	struct snd_info_entry *entry;
+	struct snd_info_entry *version_entry;
+	struct snd_info_entry *variant_entry;
+	int flyback_cur_det_disable;
+	int ear_rx_path;
+	int aux_rx_path;
+	bool dev_up;
+	u8 tx_master_ch_map[WCD9378_MAX_SLAVE_CH_TYPES];
+	bool usbc_hs_status;
+	/* wcd to swr dmic notification */
+	bool notify_swr_dmic;
+	u8 swr_base_clk;
+	u8 swr_clk_scale;
+	struct blocking_notifier_head notifier;
+};
+
+struct wcd9378_micbias_setting {
+	u8 ldoh_v;
+	u32 cfilt1_mv;
+	u32 micb1_mv;
+	u32 micb2_mv;
+	u32 micb3_mv;
+	u32 micb1_usage_val;
+	u32 micb2_usage_val;
+	u32 micb3_usage_val;
+
+	u8 bias1_cfilt_sel;
+};
+
+struct wcd9378_pdata {
+	struct device_node *rst_np;
+	struct device_node *rx_slave;
+	struct device_node *tx_slave;
+	struct wcd9378_micbias_setting micbias;
+
+	struct cdc_regulator *regulator;
+	int num_supplies;
+};
+
+struct wcd_ctrl_platform_data {
+	void *handle;
+	int (*update_wcd_event)(void *handle, u16 event, u32 data);
+	int (*register_notifier)(void *handle,
+				 struct notifier_block *nblock,
+				 bool enable);
+};
+
+enum {
+	WCD_RX1,
+	WCD_RX2,
+	WCD_RX3
+};
+
+enum {
+	/* INTR_CTRL_INT_MASK_0 */
+	WCD9378_IRQ_MBHC_BUTTON_PRESS_DET = 0,
+	WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET,
+	WCD9378_IRQ_MBHC_ELECT_INS_REM_DET,
+	WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
+	WCD9378_IRQ_MBHC_SW_DET,
+	WCD9378_IRQ_HPHR_OCP_INT,
+	WCD9378_IRQ_HPHR_CNP_INT,
+	WCD9378_IRQ_HPHL_OCP_INT,
+
+	/* INTR_CTRL_INT_MASK_1 */
+	WCD9378_IRQ_HPHL_CNP_INT,
+	WCD9378_IRQ_EAR_CNP_INT,
+	WCD9378_IRQ_EAR_SCD_INT,
+	WCD9378_IRQ_AUX_CNP_INT,
+	WCD9378_IRQ_AUX_SCD_INT,
+	WCD9378_IRQ_HPHL_PDM_WD_INT,
+	WCD9378_IRQ_HPHR_PDM_WD_INT,
+	WCD9378_IRQ_AUX_PDM_WD_INT,
+
+	/* INTR_CTRL_INT_MASK_2 */
+	WCD9378_IRQ_LDORT_SCD_INT,
+	WCD9378_IRQ_MBHC_MOISTURE_INT,
+	WCD9378_IRQ_HPHL_SURGE_DET_INT,
+	WCD9378_IRQ_HPHR_SURGE_DET_INT,
+	WCD9378_IRQ_SAPU_PROT_MODE_CHG,
+	WCD9378_NUM_IRQS,
+};
+
+extern struct wcd9378_mbhc *wcd9378_soc_get_mbhc(
+				struct snd_soc_component *component);
+extern void wcd9378_disable_bcs_before_slow_insert(
+				struct snd_soc_component *component,
+				bool bcs_disable);
+extern int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
+					int volt, int micb_num);
+extern int wcd9378_get_micb_vout_ctl_val(u32 micb_mv);
+extern int wcd9378_micbias_control(struct snd_soc_component *component,
+			int micb_num, int req, bool is_dapm);
+#endif /* _WCD9378_INTERNAL_H */

asoc/codecs/wcd9378/wcd9378-mbhc.c

@@ -0,0 +1,1147 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/printk.h>
+#include <linux/ratelimit.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/regmap.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <asoc/wcdcal-hwdep.h>
+#include <asoc/wcd-mbhc-v2-api.h>
+#include "wcd9378-registers.h"
+#include "internal.h"
+
+#define WCD9378_ZDET_SUPPORTED          true
+/* Z value defined in milliohm */
+#define WCD9378_ZDET_VAL_32             32000
+#define WCD9378_ZDET_VAL_400            400000
+#define WCD9378_ZDET_VAL_1200           1200000
+#define WCD9378_ZDET_VAL_100K           100000000
+/* Z floating defined in ohms */
+#define WCD9378_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
+
+#define WCD9378_ZDET_NUM_MEASUREMENTS   900
+#define WCD9378_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
+#define WCD9378_MBHC_GET_X1(x)          (x & 0x3FFF)
+/* Z value compared in milliOhm */
+#define WCD9378_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
+#define WCD9378_MBHC_ZDET_CONST         (86 * 16384)
+#define WCD9378_MBHC_MOISTURE_RREF      R_24_KOHM
+
+static struct wcd_mbhc_register
+	wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = {
+	WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN",
+			  WCD9378_ANA_MBHC_MECH, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_GND_DET_EN",
+			  WCD9378_ANA_MBHC_MECH, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MECH_DETECTION_TYPE",
+			  WCD9378_ANA_MBHC_MECH, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MIC_CLAMP_CTL",
+			  WCD9378_MBHC_NEW_PLUG_DETECT_CTL, 0x30, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_DETECTION_TYPE",
+			  WCD9378_ANA_MBHC_ELECT, 0x08, 3, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_CTRL",
+			  WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL",
+			  WCD9378_ANA_MBHC_MECH, 0x04, 2, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PLUG_TYPE",
+			  WCD9378_ANA_MBHC_MECH, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_GND_PLUG_TYPE",
+			  WCD9378_ANA_MBHC_MECH, 0x08, 3, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_SW_HPH_LP_100K_TO_GND",
+			  WCD9378_ANA_MBHC_MECH, 0x01, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_SCHMT_ISRC",
+			  WCD9378_ANA_MBHC_ELECT, 0x06, 1, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_FSM_EN",
+			  WCD9378_ANA_MBHC_ELECT, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_INSREM_DBNC",
+			  WCD9378_MBHC_NEW_PLUG_DETECT_CTL, 0x0F, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_BTN_DBNC",
+			  WCD9378_MBHC_NEW_CTL_1, 0x0F, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HS_VREF",
+			  WCD9378_MBHC_NEW_CTL_2, 0x03, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HS_COMP_RESULT",
+			  WCD9378_ANA_MBHC_RESULT_3, 0x08, 3, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_IN2P_CLAMP_STATE",
+			  WCD9378_ANA_MBHC_RESULT_3, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MIC_SCHMT_RESULT",
+			  WCD9378_ANA_MBHC_RESULT_3, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_SCHMT_RESULT",
+			  WCD9378_ANA_MBHC_RESULT_3, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_SCHMT_RESULT",
+			  WCD9378_ANA_MBHC_RESULT_3, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_OCP_FSM_EN",
+			  WCD9378_HPH_OCP_CTL, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_BTN_RESULT",
+			  WCD9378_ANA_MBHC_RESULT_3, 0x07, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_BTN_ISRC_CTL",
+			  WCD9378_ANA_MBHC_ELECT, 0x70, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
+			  WCD9378_ANA_MBHC_RESULT_3, 0xFF, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
+			  WCD9378_ANA_MICB2, 0xC0, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
+			  WCD9378_HPH_CNP_WG_TIME, 0xFF, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",
+			  WCD9378_ANA_HPH, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PA_EN",
+			  WCD9378_ANA_HPH, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPH_PA_EN",
+			  WCD9378_ANA_HPH, 0xC0, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_SWCH_LEVEL_REMOVE",
+			  WCD9378_ANA_MBHC_RESULT_3, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_PULLDOWN_CTRL",
+			  0, 0, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ANC_DET_EN",
+			  WCD9378_MBHC_CTL_BCS, 0x02, 1, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_FSM_STATUS",
+			  WCD9378_MBHC_NEW_FSM_STATUS, 0x01, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MUX_CTL",
+			  WCD9378_MBHC_NEW_CTL_2, 0x70, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MOISTURE_STATUS",
+			  WCD9378_MBHC_NEW_FSM_STATUS, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_GND",
+			  WCD9378_HPH_PA_CTL2, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_GND",
+			  WCD9378_HPH_PA_CTL2, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_OCP_DET_EN",
+			  WCD9378_HPH_L_TEST, 0x01, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_OCP_DET_EN",
+			  WCD9378_HPH_R_TEST, 0x01, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_OCP_STATUS",
+			  SWRS_SCP_SDCA_INTSTAT_1, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_OCP_STATUS",
+			  SWRS_SCP_SDCA_INTSTAT_1, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_EN",
+			  WCD9378_MBHC_NEW_CTL_1, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_COMPLETE", WCD9378_MBHC_NEW_FSM_STATUS,
+			  0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_TIMEOUT", WCD9378_MBHC_NEW_FSM_STATUS,
+			  0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_RESULT", WCD9378_MBHC_NEW_ADC_RESULT,
+			  0xFF, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MICB2_VOUT", WCD9378_ANA_MICB2, 0x3F, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_MODE",
+			  WCD9378_MBHC_NEW_CTL_1, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_DETECTION_DONE",
+			  WCD9378_MBHC_NEW_CTL_1, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_ISRC_EN",
+			  WCD9378_ANA_MBHC_ZDET, 0x02, 1, 0),
+};
+
+static const struct wcd_mbhc_intr intr_ids = {
+	.mbhc_sw_intr =  WCD9378_IRQ_MBHC_SW_DET,
+	.mbhc_btn_press_intr = WCD9378_IRQ_MBHC_BUTTON_PRESS_DET,
+	.mbhc_btn_release_intr = WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET,
+	.mbhc_hs_ins_intr = WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
+	.mbhc_hs_rem_intr = WCD9378_IRQ_MBHC_ELECT_INS_REM_DET,
+	.hph_left_ocp = WCD9378_IRQ_HPHL_OCP_INT,
+	.hph_right_ocp = WCD9378_IRQ_HPHR_OCP_INT,
+};
+
+struct wcd9378_mbhc_zdet_param {
+	u16 ldo_ctl;
+	u16 noff;
+	u16 nshift;
+	u16 btn5;
+	u16 btn6;
+	u16 btn7;
+};
+
+static int wcd9378_mbhc_request_irq(struct snd_soc_component *component,
+				  int irq, irq_handler_t handler,
+				  const char *name, void *data)
+{
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(component->dev);
+
+	return wcd_request_irq(&wcd9378->irq_info, irq, name, handler, data);
+}
+
+static void wcd9378_mbhc_irq_control(struct snd_soc_component *component,
+				   int irq, bool enable)
+{
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(component->dev);
+
+	if (enable)
+		wcd_enable_irq(&wcd9378->irq_info, irq);
+	else
+		wcd_disable_irq(&wcd9378->irq_info, irq);
+}
+
+static int wcd9378_mbhc_free_irq(struct snd_soc_component *component,
+			       int irq, void *data)
+{
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(component->dev);
+
+	wcd_free_irq(&wcd9378->irq_info, irq, data);
+
+	return 0;
+}
+
+static void wcd9378_mbhc_clk_setup(struct snd_soc_component *component,
+				 bool enable)
+{
+	if (enable) {
+		snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_1,
+				    0x80, 0x80);
+		snd_soc_component_update_bits(component, WCD9378_CDC_ANA_TX_CLK_CTL,
+				    0x01, 0x01);
+	} else {
+		snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_1,
+				    0x80, 0x00);
+		snd_soc_component_update_bits(component, WCD9378_CDC_ANA_TX_CLK_CTL,
+				    0x01, 0x00);
+
+	}
+}
+
+static int wcd9378_mbhc_btn_to_num(struct snd_soc_component *component)
+{
+	return snd_soc_component_read(component, WCD9378_ANA_MBHC_RESULT_3) & 0x7;
+}
+
+static void wcd9378_mbhc_mbhc_bias_control(struct snd_soc_component *component,
+					 bool enable)
+{
+	if (enable)
+		snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_ELECT,
+				    0x01, 0x01);
+	else
+		snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_ELECT,
+				    0x01, 0x00);
+}
+
+static void wcd9378_mbhc_program_btn_thr(struct snd_soc_component *component,
+				       s16 *btn_low, s16 *btn_high,
+				       int num_btn, bool is_micbias)
+{
+	int i;
+	int vth;
+
+	if (num_btn > WCD_MBHC_DEF_BUTTONS) {
+		dev_err(component->dev, "%s: invalid number of buttons: %d\n",
+			__func__, num_btn);
+		return;
+	}
+
+	for (i = 0; i < num_btn; i++) {
+		vth = ((btn_high[i] * 2) / 25) & 0x3F;
+		snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_BTN0 + i,
+				    0xFC, vth << 2);
+		dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
+			__func__, i, btn_high[i], vth);
+	}
+}
+
+static bool wcd9378_mbhc_lock_sleep(struct wcd_mbhc *mbhc, bool lock)
+{
+	struct snd_soc_component *component = mbhc->component;
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(component->dev);
+
+	wcd9378->wakeup((void *)wcd9378, lock);
+
+	return true;
+}
+
+static int wcd9378_mbhc_register_notifier(struct wcd_mbhc *mbhc,
+					struct notifier_block *nblock,
+					bool enable)
+{
+	struct wcd9378_mbhc *wcd9378_mbhc;
+
+	wcd9378_mbhc = container_of(mbhc, struct wcd9378_mbhc, wcd_mbhc);
+
+	if (enable)
+		return blocking_notifier_chain_register(&wcd9378_mbhc->notifier,
+							nblock);
+	else
+		return blocking_notifier_chain_unregister(
+				&wcd9378_mbhc->notifier, nblock);
+}
+
+static bool wcd9378_mbhc_micb_en_status(struct wcd_mbhc *mbhc, int micb_num)
+{
+	u8 val = 0;
+
+	if (micb_num == MIC_BIAS_2) {
+		val = ((snd_soc_component_read(mbhc->component,
+								WCD9378_ANA_MICB2) & 0xC0)
+			>> 6);
+		if (val == 0x01)
+			return true;
+	}
+	return false;
+}
+
+static bool wcd9378_mbhc_hph_pa_on_status(struct snd_soc_component *component)
+{
+	return (snd_soc_component_read(component, WCD9378_ANA_HPH) & 0xC0) ?
+									true : false;
+}
+
+static void wcd9378_mbhc_hph_l_pull_up_control(
+							struct snd_soc_component *component,
+							int pull_up_cur)
+{
+	/* Default pull up current to 2uA */
+	if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA ||
+	    pull_up_cur == HS_PULLUP_I_DEFAULT)
+		pull_up_cur = HS_PULLUP_I_2P0_UA;
+
+	dev_dbg(component->dev, "%s: HS pull up current:%d\n",
+		__func__, pull_up_cur);
+
+	snd_soc_component_update_bits(component,
+				WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT,
+			    0x1F, pull_up_cur);
+}
+
+static int wcd9378_mbhc_request_micbias(struct snd_soc_component *component,
+					int micb_num, int req)
+{
+	int ret = 0;
+
+	ret = wcd9378_micbias_control(component, micb_num, req, false);
+
+	return ret;
+}
+
+static void wcd9378_mbhc_micb_ramp_control(struct snd_soc_component *component,
+					   bool enable)
+{
+	if (enable) {
+		snd_soc_component_update_bits(component, WCD9378_ANA_MICB2_RAMP,
+				    0x1C, 0x0C);
+		snd_soc_component_update_bits(component, WCD9378_ANA_MICB2_RAMP,
+				    0x80, 0x80);
+	} else {
+		snd_soc_component_update_bits(component, WCD9378_ANA_MICB2_RAMP,
+				    0x80, 0x00);
+		snd_soc_component_update_bits(component, WCD9378_ANA_MICB2_RAMP,
+				    0x1C, 0x00);
+	}
+}
+
+static struct firmware_cal *wcd9378_get_hwdep_fw_cal(struct wcd_mbhc *mbhc,
+						   enum wcd_cal_type type)
+{
+	struct wcd9378_mbhc *wcd9378_mbhc;
+	struct firmware_cal *hwdep_cal;
+	struct snd_soc_component *component = mbhc->component;
+
+	wcd9378_mbhc = container_of(mbhc, struct wcd9378_mbhc, wcd_mbhc);
+
+	if (!component) {
+		pr_err("%s: NULL component pointer\n", __func__);
+		return NULL;
+	}
+	hwdep_cal = wcdcal_get_fw_cal(wcd9378_mbhc->fw_data, type);
+	if (!hwdep_cal)
+		dev_err(component->dev, "%s: cal not sent by %d\n",
+			__func__, type);
+
+	return hwdep_cal;
+}
+
+static int wcd9378_mbhc_micb_ctrl_threshold_mic(
+							struct snd_soc_component *component,
+							int micb_num, bool req_en)
+{
+	struct wcd9378_pdata *pdata = dev_get_platdata(component->dev);
+	int rc, micb_mv;
+
+	if (micb_num != MIC_BIAS_2)
+		return -EINVAL;
+	/*
+	 * If device tree micbias level is already above the minimum
+	 * voltage needed to detect threshold microphone, then do
+	 * not change the micbias, just return.
+	 */
+	if (pdata->micbias.micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
+		return 0;
+
+	micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : pdata->micbias.micb2_mv;
+
+	rc = wcd9378_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
+
+	return rc;
+}
+
+static inline void wcd9378_mbhc_get_result_params(struct wcd9378_priv *wcd9378,
+						s16 *d1_a, u16 noff,
+						int32_t *zdet)
+{
+	int i;
+	int val, val1;
+	s16 c1;
+	s32 x1, d1;
+	int32_t denom;
+	int minCode_param[] = {
+			3277, 1639, 820, 410, 205, 103, 52, 26
+	};
+
+	regmap_update_bits(wcd9378->regmap, WCD9378_ANA_MBHC_ZDET, 0x20, 0x20);
+	for (i = 0; i < WCD9378_ZDET_NUM_MEASUREMENTS; i++) {
+		regmap_read(wcd9378->regmap, WCD9378_ANA_MBHC_RESULT_2, &val);
+		if (val & 0x80)
+			break;
+	}
+	val = val << 0x8;
+	regmap_read(wcd9378->regmap, WCD9378_ANA_MBHC_RESULT_1, &val1);
+	val |= val1;
+	regmap_update_bits(wcd9378->regmap, WCD9378_ANA_MBHC_ZDET, 0x20, 0x00);
+	x1 = WCD9378_MBHC_GET_X1(val);
+	c1 = WCD9378_MBHC_GET_C1(val);
+	/* If ramp is not complete, give additional 5ms */
+	if ((c1 < 2) && x1)
+		usleep_range(5000, 5050);
+
+	if (!c1 || !x1) {
+		dev_dbg(wcd9378->dev,
+			"%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
+			__func__, c1, x1);
+		goto ramp_down;
+	}
+	d1 = d1_a[c1];
+	denom = (x1 * d1) - (1 << (14 - noff));
+	if (denom > 0)
+		*zdet = (WCD9378_MBHC_ZDET_CONST * 1000) / denom;
+	else if (x1 < minCode_param[noff])
+		*zdet = WCD9378_ZDET_FLOATING_IMPEDANCE;
+
+	dev_dbg(wcd9378->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
+		__func__, d1, c1, x1, *zdet);
+ramp_down:
+	i = 0;
+	while (x1) {
+		regmap_read(wcd9378->regmap,
+				 WCD9378_ANA_MBHC_RESULT_1, &val);
+		regmap_read(wcd9378->regmap,
+				 WCD9378_ANA_MBHC_RESULT_2, &val1);
+		val = val << 0x08;
+		val |= val1;
+		x1 = WCD9378_MBHC_GET_X1(val);
+		i++;
+		if (i == WCD9378_ZDET_NUM_MEASUREMENTS)
+			break;
+	}
+}
+
+static void wcd9378_mbhc_zdet_ramp(struct snd_soc_component *component,
+				 struct wcd9378_mbhc_zdet_param *zdet_param,
+				 int32_t *zl, int32_t *zr, s16 *d1_a)
+{
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(component->dev);
+	int32_t zdet = 0;
+
+	snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_ZDET_ANA_CTL,
+				0x70, zdet_param->ldo_ctl << 4);
+	snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_BTN5, 0xFC,
+			    zdet_param->btn5);
+	snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_BTN6, 0xFC,
+			    zdet_param->btn6);
+	snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_BTN7, 0xFC,
+			    zdet_param->btn7);
+	snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_ZDET_ANA_CTL,
+				0x0F, zdet_param->noff);
+	snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_ZDET_RAMP_CTL,
+				0x0F, zdet_param->nshift);
+
+	if (!zl)
+		goto z_right;
+	/* Start impedance measurement for HPH_L */
+	regmap_update_bits(wcd9378->regmap,
+			   WCD9378_ANA_MBHC_ZDET, 0x80, 0x80);
+	dev_dbg(wcd9378->dev, "%s: ramp for HPH_L, noff = %d\n",
+		__func__, zdet_param->noff);
+	wcd9378_mbhc_get_result_params(wcd9378, d1_a, zdet_param->noff, &zdet);
+	regmap_update_bits(wcd9378->regmap,
+			   WCD9378_ANA_MBHC_ZDET, 0x80, 0x00);
+
+	*zl = zdet;
+
+z_right:
+	if (!zr)
+		return;
+	/* Start impedance measurement for HPH_R */
+	regmap_update_bits(wcd9378->regmap,
+			   WCD9378_ANA_MBHC_ZDET, 0x40, 0x40);
+	dev_dbg(wcd9378->dev, "%s: ramp for HPH_R, noff = %d\n",
+		__func__, zdet_param->noff);
+	wcd9378_mbhc_get_result_params(wcd9378, d1_a, zdet_param->noff, &zdet);
+	regmap_update_bits(wcd9378->regmap,
+			   WCD9378_ANA_MBHC_ZDET, 0x40, 0x00);
+
+	*zr = zdet;
+}
+
+static inline void wcd9378_wcd_mbhc_qfuse_cal(
+					struct snd_soc_component *component,
+					int32_t *z_val, int flag_l_r)
+{
+	s16 q1;
+	int q1_cal;
+
+	if (*z_val < (WCD9378_ZDET_VAL_400/1000))
+		q1 = snd_soc_component_read(component,
+			WCD9378_EFUSE_REG_23 + (2 * flag_l_r));
+	else
+		q1 = snd_soc_component_read(component,
+			WCD9378_EFUSE_REG_24 + (2 * flag_l_r));
+	if (q1 & 0x80)
+		q1_cal = (10000 - ((q1 & 0x7F) * 25));
+	else
+		q1_cal = (10000 + (q1 * 25));
+	if (q1_cal > 0)
+		*z_val = ((*z_val) * 10000) / q1_cal;
+}
+
+static void wcd9378_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl,
+					  uint32_t *zr)
+{
+	struct snd_soc_component *component = mbhc->component;
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(component->dev);
+	s16 reg0, reg1, reg2, reg3, reg4;
+	int32_t z1L, z1R, z1Ls;
+	int zMono, z_diff1, z_diff2;
+	bool is_fsm_disable = false;
+	struct wcd9378_mbhc_zdet_param zdet_param[] = {
+		{4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
+		{2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
+		{1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
+		{1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
+	};
+	struct wcd9378_mbhc_zdet_param *zdet_param_ptr = NULL;
+	s16 d1_a[][4] = {
+		{0, 30, 90, 30},
+		{0, 30, 30, 5},
+		{0, 30, 30, 5},
+		{0, 30, 30, 5},
+	};
+	s16 *d1 = NULL;
+
+	WCD_MBHC_RSC_ASSERT_LOCKED(mbhc);
+
+	reg0 = snd_soc_component_read(component, WCD9378_ANA_MBHC_BTN5);
+	reg1 = snd_soc_component_read(component, WCD9378_ANA_MBHC_BTN6);
+	reg2 = snd_soc_component_read(component, WCD9378_ANA_MBHC_BTN7);
+	reg3 = snd_soc_component_read(component, WCD9378_MBHC_CTL_CLK);
+	reg4 = snd_soc_component_read(component, WCD9378_MBHC_NEW_ZDET_ANA_CTL);
+
+	if (snd_soc_component_read(component, WCD9378_ANA_MBHC_ELECT) & 0x80) {
+		is_fsm_disable = true;
+		regmap_update_bits(wcd9378->regmap,
+				   WCD9378_ANA_MBHC_ELECT, 0x80, 0x00);
+	}
+
+	/* For NO-jack, disable L_DET_EN before Z-det measurements */
+	if (mbhc->hphl_swh)
+		regmap_update_bits(wcd9378->regmap,
+				   WCD9378_ANA_MBHC_MECH, 0x80, 0x00);
+
+	/* Turn off 100k pull down on HPHL */
+	regmap_update_bits(wcd9378->regmap,
+			   WCD9378_ANA_MBHC_MECH, 0x01, 0x00);
+
+	/* Disable surge protection before impedance detection.
+	 * This is done to give correct value for high impedance.
+	 */
+	regmap_update_bits(wcd9378->regmap,
+				WCD9378_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
+	/* 1ms delay needed after disable surge protection */
+	usleep_range(1000, 1010);
+
+	/* First get impedance on Left */
+	d1 = d1_a[1];
+	zdet_param_ptr = &zdet_param[1];
+	wcd9378_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
+
+	if (!WCD9378_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
+		goto left_ch_impedance;
+
+	/* Second ramp for left ch */
+	if (z1L < WCD9378_ZDET_VAL_32) {
+		zdet_param_ptr = &zdet_param[0];
+		d1 = d1_a[0];
+	} else if ((z1L > WCD9378_ZDET_VAL_400) &&
+		  (z1L <= WCD9378_ZDET_VAL_1200)) {
+		zdet_param_ptr = &zdet_param[2];
+		d1 = d1_a[2];
+	} else if (z1L > WCD9378_ZDET_VAL_1200) {
+		zdet_param_ptr = &zdet_param[3];
+		d1 = d1_a[3];
+	}
+	wcd9378_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
+
+left_ch_impedance:
+	if ((z1L == WCD9378_ZDET_FLOATING_IMPEDANCE) ||
+		(z1L > WCD9378_ZDET_VAL_100K)) {
+		*zl = WCD9378_ZDET_FLOATING_IMPEDANCE;
+		zdet_param_ptr = &zdet_param[1];
+		d1 = d1_a[1];
+	} else {
+		*zl = z1L/1000;
+		wcd9378_wcd_mbhc_qfuse_cal(component, zl, 0);
+	}
+	dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
+		__func__, *zl);
+
+	/* Start of right impedance ramp and calculation */
+	wcd9378_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
+	if (WCD9378_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
+		if (((z1R > WCD9378_ZDET_VAL_1200) &&
+			(zdet_param_ptr->noff == 0x6)) ||
+			((*zl) != WCD9378_ZDET_FLOATING_IMPEDANCE))
+			goto right_ch_impedance;
+		/* Second ramp for right ch */
+		if (z1R < WCD9378_ZDET_VAL_32) {
+			zdet_param_ptr = &zdet_param[0];
+			d1 = d1_a[0];
+		} else if ((z1R > WCD9378_ZDET_VAL_400) &&
+			(z1R <= WCD9378_ZDET_VAL_1200)) {
+			zdet_param_ptr = &zdet_param[2];
+			d1 = d1_a[2];
+		} else if (z1R > WCD9378_ZDET_VAL_1200) {
+			zdet_param_ptr = &zdet_param[3];
+			d1 = d1_a[3];
+		}
+		wcd9378_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
+	}
+right_ch_impedance:
+	if ((z1R == WCD9378_ZDET_FLOATING_IMPEDANCE) ||
+		(z1R > WCD9378_ZDET_VAL_100K)) {
+		*zr = WCD9378_ZDET_FLOATING_IMPEDANCE;
+	} else {
+		*zr = z1R/1000;
+		wcd9378_wcd_mbhc_qfuse_cal(component, zr, 1);
+	}
+	dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
+		__func__, *zr);
+
+	/* Mono/stereo detection */
+	if ((*zl == WCD9378_ZDET_FLOATING_IMPEDANCE) &&
+		(*zr == WCD9378_ZDET_FLOATING_IMPEDANCE)) {
+		dev_dbg(component->dev,
+			"%s: plug type is invalid or extension cable\n",
+			__func__);
+		goto zdet_complete;
+	}
+	if ((*zl == WCD9378_ZDET_FLOATING_IMPEDANCE) ||
+	    (*zr == WCD9378_ZDET_FLOATING_IMPEDANCE) ||
+	    ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
+	    ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
+		dev_dbg(component->dev,
+			"%s: Mono plug type with one ch floating or shorted to GND\n",
+			__func__);
+		mbhc->hph_type = WCD_MBHC_HPH_MONO;
+		goto zdet_complete;
+	}
+	snd_soc_component_update_bits(component, WCD9378_HPH_R_ATEST, 0x01, 0x01);
+	snd_soc_component_update_bits(component, WCD9378_HPH_PA_CTL2, 0x40, 0x01);
+	if (*zl < (WCD9378_ZDET_VAL_32/1000))
+		wcd9378_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
+	else
+		wcd9378_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
+	snd_soc_component_update_bits(component, WCD9378_HPH_PA_CTL2, 0x40, 0x00);
+	snd_soc_component_update_bits(component, WCD9378_HPH_R_ATEST, 0x01, 0x00);
+	z1Ls /= 1000;
+	wcd9378_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
+	/* Parallel of left Z and 9 ohm pull down resistor */
+	zMono = ((*zl) * 9) / ((*zl) + 9);
+	z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
+	z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
+	if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
+		dev_dbg(component->dev, "%s: stereo plug type detected\n",
+			__func__);
+		mbhc->hph_type = WCD_MBHC_HPH_STEREO;
+	} else {
+		dev_dbg(component->dev, "%s: MONO plug type detected\n",
+			__func__);
+		mbhc->hph_type = WCD_MBHC_HPH_MONO;
+	}
+
+	/* Enable surge protection again after impedance detection */
+	regmap_update_bits(wcd9378->regmap,
+			   WCD9378_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
+zdet_complete:
+	snd_soc_component_write(component, WCD9378_ANA_MBHC_BTN5, reg0);
+	snd_soc_component_write(component, WCD9378_ANA_MBHC_BTN6, reg1);
+	snd_soc_component_write(component, WCD9378_ANA_MBHC_BTN7, reg2);
+	/* Turn on 100k pull down on HPHL */
+	regmap_update_bits(wcd9378->regmap,
+			   WCD9378_ANA_MBHC_MECH, 0x01, 0x01);
+
+	/* For NO-jack, re-enable L_DET_EN after Z-det measurements */
+	if (mbhc->hphl_swh)
+		regmap_update_bits(wcd9378->regmap,
+				   WCD9378_ANA_MBHC_MECH, 0x80, 0x80);
+
+	snd_soc_component_write(component, WCD9378_MBHC_NEW_ZDET_ANA_CTL, reg4);
+	snd_soc_component_write(component, WCD9378_MBHC_CTL_CLK, reg3);
+	if (is_fsm_disable)
+		regmap_update_bits(wcd9378->regmap,
+				   WCD9378_ANA_MBHC_ELECT, 0x80, 0x80);
+}
+
+static void wcd9378_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
+			bool enable)
+{
+	if (enable) {
+		snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_MECH,
+				    0x02, 0x02);
+		snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_MECH,
+				    0x40, 0x40);
+	} else {
+		snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_MECH,
+				    0x40, 0x00);
+		snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_MECH,
+				    0x02, 0x00);
+	}
+}
+
+static void wcd9378_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
+					  bool enable)
+{
+	if (enable) {
+		snd_soc_component_update_bits(component, WCD9378_HPH_PA_CTL2,
+				    0x40, 0x40);
+		snd_soc_component_update_bits(component, WCD9378_HPH_PA_CTL2,
+				    0x10, 0x10);
+	} else {
+		snd_soc_component_update_bits(component, WCD9378_HPH_PA_CTL2,
+				    0x40, 0x00);
+		snd_soc_component_update_bits(component, WCD9378_HPH_PA_CTL2,
+				    0x10, 0x00);
+	}
+}
+
+static void wcd9378_mbhc_moisture_config(struct wcd_mbhc *mbhc)
+{
+	struct snd_soc_component *component = mbhc->component;
+
+	if ((mbhc->moist_rref == R_OFF) ||
+	    (mbhc->mbhc_cfg->enable_usbc_analog)) {
+		snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_2,
+				    0x0C, R_OFF << 2);
+		return;
+	}
+
+	/* Do not enable moisture detection if jack type is NC */
+	if (!mbhc->hphl_swh) {
+		dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
+			__func__);
+		snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_2,
+				    0x0C, R_OFF << 2);
+		return;
+	}
+
+	snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_2,
+			    0x0C, mbhc->moist_rref << 2);
+}
+
+static void wcd9378_mbhc_moisture_detect_en(struct wcd_mbhc *mbhc, bool enable)
+{
+	struct snd_soc_component *component = mbhc->component;
+
+	if (enable)
+		snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_2,
+					0x0C, mbhc->moist_rref << 2);
+	else
+		snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_2,
+				    0x0C, R_OFF << 2);
+}
+
+static bool wcd9378_mbhc_get_moisture_status(struct wcd_mbhc *mbhc)
+{
+	struct snd_soc_component *component = mbhc->component;
+	bool ret = false;
+
+	if ((mbhc->moist_rref == R_OFF) ||
+	    (mbhc->mbhc_cfg->enable_usbc_analog)) {
+		snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_2,
+				    0x0C, R_OFF << 2);
+		goto done;
+	}
+
+	/* Do not enable moisture detection if jack type is NC */
+	if (!mbhc->hphl_swh) {
+		dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
+			__func__);
+		snd_soc_component_update_bits(component, WCD9378_MBHC_NEW_CTL_2,
+				    0x0C, R_OFF << 2);
+		goto done;
+	}
+
+	/*
+	 * If moisture_en is already enabled, then skip to plug type
+	 * detection.
+	 */
+	if ((snd_soc_component_read(component, WCD9378_MBHC_NEW_CTL_2) & 0x0C))
+		goto done;
+
+	wcd9378_mbhc_moisture_detect_en(mbhc, true);
+	/* Read moisture comparator status */
+	ret = ((snd_soc_component_read(component, WCD9378_MBHC_NEW_FSM_STATUS)
+				& 0x20) ? 0 : 1);
+
+done:
+	return ret;
+
+}
+
+static void wcd9378_mbhc_moisture_polling_ctrl(struct wcd_mbhc *mbhc,
+						bool enable)
+{
+	struct snd_soc_component *component = mbhc->component;
+
+	snd_soc_component_update_bits(component,
+			WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
+			0x04, (enable << 2));
+}
+
+static void wcd9378_mbhc_bcs_enable(struct wcd_mbhc *mbhc,
+						  bool bcs_enable)
+{
+	if (bcs_enable)
+		wcd9378_disable_bcs_before_slow_insert(mbhc->component, false);
+	else
+		wcd9378_disable_bcs_before_slow_insert(mbhc->component, true);
+}
+
+static const struct wcd_mbhc_cb mbhc_cb = {
+	.request_irq = wcd9378_mbhc_request_irq,
+	.irq_control = wcd9378_mbhc_irq_control,
+	.free_irq = wcd9378_mbhc_free_irq,
+	.clk_setup = wcd9378_mbhc_clk_setup,
+	.map_btn_code_to_num = wcd9378_mbhc_btn_to_num,
+	.mbhc_bias = wcd9378_mbhc_mbhc_bias_control,
+	.set_btn_thr = wcd9378_mbhc_program_btn_thr,
+	.lock_sleep = wcd9378_mbhc_lock_sleep,
+	.register_notifier = wcd9378_mbhc_register_notifier,
+	.micbias_enable_status = wcd9378_mbhc_micb_en_status,
+	.hph_pa_on_status = wcd9378_mbhc_hph_pa_on_status,
+	.hph_pull_up_control_v2 = wcd9378_mbhc_hph_l_pull_up_control,
+	.mbhc_micbias_control = wcd9378_mbhc_request_micbias,
+	.mbhc_micb_ramp_control = wcd9378_mbhc_micb_ramp_control,
+	.get_hwdep_fw_cal = wcd9378_get_hwdep_fw_cal,
+	.mbhc_micb_ctrl_thr_mic = wcd9378_mbhc_micb_ctrl_threshold_mic,
+	.compute_impedance = wcd9378_wcd_mbhc_calc_impedance,
+	.mbhc_gnd_det_ctrl = wcd9378_mbhc_gnd_det_ctrl,
+	.hph_pull_down_ctrl = wcd9378_mbhc_hph_pull_down_ctrl,
+	.mbhc_moisture_config = wcd9378_mbhc_moisture_config,
+	.mbhc_get_moisture_status = wcd9378_mbhc_get_moisture_status,
+	.mbhc_moisture_polling_ctrl = wcd9378_mbhc_moisture_polling_ctrl,
+	.mbhc_moisture_detect_en = wcd9378_mbhc_moisture_detect_en,
+	.bcs_enable = wcd9378_mbhc_bcs_enable,
+};
+
+static int wcd9378_get_hph_type(struct snd_kcontrol *kcontrol,
+			      struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+					snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_mbhc *wcd9378_mbhc = wcd9378_soc_get_mbhc(component);
+	struct wcd_mbhc *mbhc;
+
+	if (!wcd9378_mbhc) {
+		dev_err(component->dev, "%s: mbhc not initialized!\n", __func__);
+		return -EINVAL;
+	}
+
+	mbhc = &wcd9378_mbhc->wcd_mbhc;
+
+	ucontrol->value.integer.value[0] = (u32) mbhc->hph_type;
+	dev_dbg(component->dev, "%s: hph_type = %u\n", __func__, mbhc->hph_type);
+
+	return 0;
+}
+
+static int wcd9378_hph_impedance_get(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	uint32_t zl, zr;
+	bool hphr;
+	struct soc_multi_mixer_control *mc;
+	struct snd_soc_component *component =
+					snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_mbhc *wcd9378_mbhc = wcd9378_soc_get_mbhc(component);
+
+	if (!wcd9378_mbhc) {
+		dev_err(component->dev, "%s: mbhc not initialized!\n", __func__);
+		return -EINVAL;
+	}
+
+	mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
+	hphr = mc->shift;
+	wcd_mbhc_get_impedance(&wcd9378_mbhc->wcd_mbhc, &zl, &zr);
+	dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
+	ucontrol->value.integer.value[0] = hphr ? zr : zl;
+
+	return 0;
+}
+
+static const struct snd_kcontrol_new hph_type_detect_controls[] = {
+	SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
+		       wcd9378_get_hph_type, NULL),
+};
+
+static const struct snd_kcontrol_new impedance_detect_controls[] = {
+	SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
+		       wcd9378_hph_impedance_get, NULL),
+	SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
+		       wcd9378_hph_impedance_get, NULL),
+};
+
+/*
+ * wcd9378_mbhc_get_impedance: get impedance of headphone
+ * left and right channels
+ * @wcd9378_mbhc: handle to struct wcd9378_mbhc *
+ * @zl: handle to left-ch impedance
+ * @zr: handle to right-ch impedance
+ * return 0 for success or error code in case of failure
+ */
+int wcd9378_mbhc_get_impedance(struct wcd9378_mbhc *wcd9378_mbhc,
+			     uint32_t *zl, uint32_t *zr)
+{
+	if (!wcd9378_mbhc) {
+		pr_err("%s: mbhc not initialized!\n", __func__);
+		return -EINVAL;
+	}
+	if (!zl || !zr) {
+		pr_err("%s: zl or zr null!\n", __func__);
+		return -EINVAL;
+	}
+
+	return wcd_mbhc_get_impedance(&wcd9378_mbhc->wcd_mbhc, zl, zr);
+}
+EXPORT_SYMBOL_GPL(wcd9378_mbhc_get_impedance);
+
+/*
+ * wcd9378_mbhc_hs_detect: starts mbhc insertion/removal functionality
+ * @codec: handle to snd_soc_component *
+ * @mbhc_cfg: handle to mbhc configuration structure
+ * return 0 if mbhc_start is success or error code in case of failure
+ */
+int wcd9378_mbhc_hs_detect(struct snd_soc_component *component,
+			 struct wcd_mbhc_config *mbhc_cfg)
+{
+	struct wcd9378_priv *wcd9378 = NULL;
+	struct wcd9378_mbhc *wcd9378_mbhc = NULL;
+
+	if (!component) {
+		pr_err("%s: component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+	if (!wcd9378) {
+		pr_err("%s: wcd9378 is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd9378_mbhc = wcd9378->mbhc;
+	if (!wcd9378_mbhc) {
+		dev_err(component->dev, "%s: mbhc not initialized!\n", __func__);
+		return -EINVAL;
+	}
+
+	return wcd_mbhc_start(&wcd9378_mbhc->wcd_mbhc, mbhc_cfg);
+}
+EXPORT_SYMBOL_GPL(wcd9378_mbhc_hs_detect);
+
+/*
+ * wcd9378_mbhc_hs_detect_exit: stop mbhc insertion/removal functionality
+ * @component: handle to snd_soc_component *
+ */
+void wcd9378_mbhc_hs_detect_exit(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 = NULL;
+	struct wcd9378_mbhc *wcd9378_mbhc = NULL;
+
+	if (!component) {
+		pr_err("%s: component is NULL\n", __func__);
+		return;
+	}
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+	if (!wcd9378) {
+		pr_err("%s: wcd9378 is NULL\n", __func__);
+		return;
+	}
+
+	wcd9378_mbhc = wcd9378->mbhc;
+	if (!wcd9378_mbhc) {
+		dev_err(component->dev, "%s: mbhc not initialized!\n", __func__);
+		return;
+	}
+	wcd_mbhc_stop(&wcd9378_mbhc->wcd_mbhc);
+}
+EXPORT_SYMBOL_GPL(wcd9378_mbhc_hs_detect_exit);
+
+/*
+ * wcd9378_mbhc_ssr_down: stop mbhc during
+ * wcd9378 subsystem restart
+ * mbhc: pointer to wcd937x_mbhc structure
+ * component: handle to snd_soc_component *
+ */
+void wcd9378_mbhc_ssr_down(struct wcd9378_mbhc *mbhc,
+			struct snd_soc_component *component)
+{
+	struct wcd_mbhc *wcd_mbhc = NULL;
+
+	if (!mbhc || !component)
+		return;
+
+	wcd_mbhc = &mbhc->wcd_mbhc;
+	if (!wcd_mbhc) {
+		dev_err(component->dev, "%s: wcd_mbhc is NULL\n", __func__);
+		return;
+	}
+
+	wcd9378_mbhc_hs_detect_exit(component);
+	wcd_mbhc_deinit(wcd_mbhc);
+}
+EXPORT_SYMBOL_GPL(wcd9378_mbhc_ssr_down);
+
+/*
+ * wcd9378_mbhc_post_ssr_init: initialize mbhc for
+ * wcd9378 post subsystem restart
+ * @mbhc: poniter to wcd9378_mbhc structure
+ * @component: handle to snd_soc_component *
+ *
+ * return 0 if mbhc_init is success or error code in case of failure
+ */
+int wcd9378_mbhc_post_ssr_init(struct wcd9378_mbhc *mbhc,
+			     struct snd_soc_component *component)
+{
+	int ret = 0;
+	struct wcd_mbhc *wcd_mbhc = NULL;
+
+	if (!mbhc || !component)
+		return -EINVAL;
+
+	wcd_mbhc = &mbhc->wcd_mbhc;
+	if (wcd_mbhc == NULL) {
+		pr_err("%s: wcd_mbhc is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Reset detection type to insertion after SSR recovery */
+	snd_soc_component_update_bits(component, WCD9378_ANA_MBHC_MECH,
+				0x20, 0x20);
+	ret = wcd_mbhc_init(wcd_mbhc, component, &mbhc_cb, &intr_ids,
+			    wcd_mbhc_registers, WCD9378_ZDET_SUPPORTED);
+	if (ret) {
+		dev_err(component->dev, "%s: mbhc initialization failed\n",
+			__func__);
+		goto done;
+	}
+
+done:
+	return ret;
+}
+EXPORT_SYMBOL_GPL(wcd9378_mbhc_post_ssr_init);
+
+/*
+ * wcd9378_mbhc_init: initialize mbhc for wcd9378
+ * @mbhc: poniter to wcd9378_mbhc struct pointer to store the configs
+ * @codec: handle to snd_soc_component *
+ * @fw_data: handle to firmware data
+ *
+ * return 0 if mbhc_init is success or error code in case of failure
+ */
+int wcd9378_mbhc_init(struct wcd9378_mbhc **mbhc,
+				struct snd_soc_component *component)
+{
+	struct wcd9378_mbhc *wcd9378_mbhc = NULL;
+	struct wcd_mbhc *wcd_mbhc = NULL;
+	int ret = 0;
+	struct wcd9378_pdata *pdata;
+
+	if (!component) {
+		pr_err("%s: component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd9378_mbhc = devm_kzalloc(component->dev, sizeof(struct wcd9378_mbhc),
+				    GFP_KERNEL);
+	if (!wcd9378_mbhc)
+		return -ENOMEM;
+
+	BLOCKING_INIT_NOTIFIER_HEAD(&wcd9378_mbhc->notifier);
+	wcd_mbhc = &wcd9378_mbhc->wcd_mbhc;
+	if (wcd_mbhc == NULL) {
+		pr_err("%s: wcd_mbhc is NULL\n", __func__);
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* Setting default mbhc detection logic to ADC */
+	wcd_mbhc->mbhc_detection_logic = WCD_DETECTION_ADC;
+
+	pdata = dev_get_platdata(component->dev);
+	if (!pdata) {
+		dev_err(component->dev, "%s: pdata pointer is NULL\n",
+			__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	wcd_mbhc->micb_mv = pdata->micbias.micb2_mv;
+
+	ret = wcd_mbhc_init(wcd_mbhc, component, &mbhc_cb,
+				&intr_ids, wcd_mbhc_registers,
+				WCD9378_ZDET_SUPPORTED);
+	if (ret) {
+		dev_err(component->dev, "%s: mbhc initialization failed\n",
+			__func__);
+		goto err;
+	}
+
+	(*mbhc) = wcd9378_mbhc;
+	snd_soc_add_component_controls(component, impedance_detect_controls,
+				   ARRAY_SIZE(impedance_detect_controls));
+	snd_soc_add_component_controls(component, hph_type_detect_controls,
+				   ARRAY_SIZE(hph_type_detect_controls));
+
+	return 0;
+err:
+	return ret;
+}
+EXPORT_SYMBOL_GPL(wcd9378_mbhc_init);
+
+/*
+ * wcd9378_mbhc_deinit: deinitialize mbhc for wcd9378
+ * @codec: handle to snd_soc_component *
+ */
+void wcd9378_mbhc_deinit(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378;
+	struct wcd9378_mbhc *wcd9378_mbhc;
+
+	if (!component) {
+		pr_err("%s: component is NULL\n", __func__);
+		return;
+	}
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+	if (!wcd9378) {
+		pr_err("%s: wcd9378 is NULL\n", __func__);
+		return;
+	}
+
+	wcd9378_mbhc = wcd9378->mbhc;
+	if (wcd9378_mbhc)
+		wcd_mbhc_deinit(&wcd9378_mbhc->wcd_mbhc);
+}
+EXPORT_SYMBOL_GPL(wcd9378_mbhc_deinit);

asoc/codecs/wcd9378/wcd9378-mbhc.h

@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#ifndef __WCD9378_MBHC_H__
+#define __WCD9378_MBHC_H__
+#include <asoc/wcd-mbhc-v2.h>
+
+struct wcd9378_mbhc {
+	struct wcd_mbhc wcd_mbhc;
+	struct blocking_notifier_head notifier;
+	struct fw_info *fw_data;
+};
+
+#if IS_ENABLED(CONFIG_SND_SOC_WCD9378)
+extern int wcd9378_mbhc_init(struct wcd9378_mbhc **mbhc,
+			   struct snd_soc_component *component);
+extern void wcd9378_mbhc_hs_detect_exit(struct snd_soc_component *component);
+extern int wcd9378_mbhc_hs_detect(struct snd_soc_component *component,
+				struct wcd_mbhc_config *mbhc_cfg);
+extern void wcd9378_mbhc_deinit(struct snd_soc_component *component);
+extern void wcd9378_mbhc_ssr_down(struct wcd9378_mbhc *mbhc,
+				struct snd_soc_component *component);
+extern int wcd9378_mbhc_post_ssr_init(struct wcd9378_mbhc *mbhc,
+				    struct snd_soc_component *component);
+extern int wcd9378_mbhc_get_impedance(struct wcd9378_mbhc *wcd9378_mbhc,
+				    uint32_t *zl, uint32_t *zr);
+#else
+static inline int wcd9378_mbhc_init(struct wcd9378_mbhc **mbhc,
+				  struct snd_soc_component *component)
+{
+	return 0;
+}
+static inline void wcd9378_mbhc_hs_detect_exit(
+					struct snd_soc_component *component)
+{
+}
+static inline int wcd9378_mbhc_hs_detect(struct snd_soc_component *component,
+				       struct wcd_mbhc_config *mbhc_cfg)
+{
+		return 0;
+}
+static inline void wcd9378_mbhc_deinit(struct snd_soc_component *component)
+{
+}
+static inline void wcd9378_mbhc_ssr_down(struct wcd9378_mbhc *mbhc,
+					struct snd_soc_component *component)
+{
+}
+static inline int wcd9378_mbhc_post_ssr_init(struct wcd9378_mbhc *mbhc,
+					   struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static inline int wcd9378_mbhc_get_impedance(struct wcd9378_mbhc *wcd9378_mbhc,
+					   uint32_t *zl, uint32_t *zr)
+{
+	if (zl)
+		*zl = 0;
+	if (zr)
+		*zr = 0;
+	return -EINVAL;
+}
+#endif
+
+#endif /* __WCD9378_MBHC_H__ */

asoc/codecs/wcd9378/wcd9378-reg-masks.h

@@ -0,0 +1,3414 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef WCD9378_REG_MASKS_H
+#define WCD9378_REG_MASKS_H
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd9378-registers.h"
+
+/* Use in conjunction with wcd9378-reg-shifts.c for field values. */
+/* field_value = (register_value & field_mask) >> field_shift */
+
+#define FIELD_MASK(register_name, field_name) \
+WCD9378_##register_name##_##field_name##_MASK
+
+/* WCD9378_FUNC_EXT_ID_0 Fields: */
+#define WCD9378_FUNC_EXT_ID_0_FUNC_EXT_ID_0_MASK                         0xff
+
+/* WCD9378_FUNC_EXT_ID_1 Fields: */
+#define WCD9378_FUNC_EXT_ID_1_FUNC_EXT_ID_1_MASK                         0xff
+
+/* WCD9378_FUNC_EXT_VER Fields: */
+#define WCD9378_FUNC_EXT_VER_FUNC_EXT_VER_MASK                           0xff
+
+/* WCD9378_FUNC_STAT Fields: */
+#define WCD9378_FUNC_STAT_FUNC_STAT_MASK                                 0xff
+
+/* WCD9378_DEV_MANU_ID_0 Fields: */
+#define WCD9378_DEV_MANU_ID_0_DEV_MANU_ID_0_MASK                         0xff
+
+/* WCD9378_DEV_MANU_ID_1 Fields: */
+#define WCD9378_DEV_MANU_ID_1_DEV_MANU_ID_1_MASK                         0xff
+
+/* WCD9378_DEV_PART_ID_0 Fields: */
+#define WCD9378_DEV_PART_ID_0_DEV_PART_ID_0_MASK                         0xff
+
+/* WCD9378_DEV_PART_ID_1 Fields: */
+#define WCD9378_DEV_PART_ID_1_DEV_PART_ID_1_MASK                         0xff
+
+/* WCD9378_DEV_VER Fields: */
+#define WCD9378_DEV_VER_DEV_VER_MASK                                     0xff
+
+
+/* WCD9378_A_PAGE Fields: */
+#define WCD9378_A_PAGE_VALUE_MASK                                        0xff
+
+/* WCD9378_ANA_BIAS Fields: */
+#define WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK                             0x80
+#define WCD9378_ANA_BIAS_PRECHRG_EN_MASK                                 0x40
+#define WCD9378_ANA_BIAS_PRECHRG_CTL_MODE_MASK                           0x20
+
+/* WCD9378_ANA_RX_SUPPLIES Fields: */
+#define WCD9378_ANA_RX_SUPPLIES_CLASSG_CP_EN_MASK                        0x80
+#define WCD9378_ANA_RX_SUPPLIES_NCP_EN_MASK                              0x40
+#define WCD9378_ANA_RX_SUPPLIES_SEQ_BYPASS_MASK                          0x20
+#define WCD9378_ANA_RX_SUPPLIES_SDCA_BYPASS_MASK                         0x10
+#define WCD9378_ANA_RX_SUPPLIES_SYS_USAGE_BYP_MASK                       0x08
+#define WCD9378_ANA_RX_SUPPLIES_ANA_SEQ_BYPASS_MASK                      0x02
+#define WCD9378_ANA_RX_SUPPLIES_RX_BIAS_ENABLE_MASK                      0x01
+
+/* WCD9378_ANA_HPH Fields: */
+#define WCD9378_ANA_HPH_HPHL_ENABLE_MASK                                 0x80
+#define WCD9378_ANA_HPH_HPHR_ENABLE_MASK                                 0x40
+#define WCD9378_ANA_HPH_HPHL_REF_ENABLE_MASK                             0x20
+#define WCD9378_ANA_HPH_HPHR_REF_ENABLE_MASK                             0x10
+#define WCD9378_ANA_HPH_PWR_LEVEL_MASK                                   0x0c
+#define WCD9378_ANA_HPH_LOW_HIFI_CTL_MASK                                0x02
+
+/* WCD9378_ANA_EAR Fields: */
+#define WCD9378_ANA_EAR_ENABLE_MASK                                      0x80
+#define WCD9378_ANA_EAR_SHORT_PROT_EN_MASK                               0x40
+#define WCD9378_ANA_EAR_OUT_IMPEDANCE_MASK                               0x20
+#define WCD9378_ANA_EAR_DAC_CLK_SEL_MASK                                 0x01
+
+/* WCD9378_ANA_EAR_COMPANDER_CTL Fields: */
+#define WCD9378_ANA_EAR_COMPANDER_CTL_GAIN_OVRD_REG_MASK                 0x80
+#define WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK                      0x7c
+#define WCD9378_ANA_EAR_COMPANDER_CTL_COMP_DFF_BYP_MASK                  0x02
+#define WCD9378_ANA_EAR_COMPANDER_CTL_COMP_DFF_CLK_EDGE_MASK             0x01
+
+/* WCD9378_ANA_TX_CH1 Fields: */
+#define WCD9378_ANA_TX_CH1_ENABLE_MASK                                   0x80
+#define WCD9378_ANA_TX_CH1_PWR_LEVEL_MASK                                0x60
+#define WCD9378_ANA_TX_CH1_GAIN_MASK                                     0x1f
+
+/* WCD9378_ANA_TX_CH2 Fields: */
+#define WCD9378_ANA_TX_CH2_ENABLE_MASK                                   0x80
+#define WCD9378_ANA_TX_CH2_HPF1_INIT_MASK                                0x40
+#define WCD9378_ANA_TX_CH2_HPF2_INIT_MASK                                0x20
+#define WCD9378_ANA_TX_CH2_GAIN_MASK                                     0x1f
+
+/* WCD9378_ANA_TX_CH3 Fields: */
+#define WCD9378_ANA_TX_CH3_ENABLE_MASK                                   0x80
+#define WCD9378_ANA_TX_CH3_PWR_LEVEL_MASK                                0x60
+#define WCD9378_ANA_TX_CH3_GAIN_MASK                                     0x1f
+
+/* WCD9378_ANA_TX_CH3_HPF Fields: */
+#define WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK                            0x40
+
+/* WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC Fields: */
+#define WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC_MICB1_DSP_OVERRIDE_MASK     0x80
+#define WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC_MICB1_DSP_CTRL_MASK         0x60
+#define WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC_MICB2_DSP_OVERRIDE_MASK     0x10
+#define WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC_MICB2_DSP_CTRL_MASK         0x0c
+
+/* WCD9378_ANA_MICB3_DSP_EN_LOGIC Fields: */
+#define WCD9378_ANA_MICB3_DSP_EN_LOGIC_MICB3_DSP_OVERRIDE_MASK           0x80
+#define WCD9378_ANA_MICB3_DSP_EN_LOGIC_MICB3_DSP_CTRL_MASK               0x60
+
+/* WCD9378_ANA_MBHC_MECH Fields: */
+#define WCD9378_ANA_MBHC_MECH_L_DET_EN_MASK                              0x80
+#define WCD9378_ANA_MBHC_MECH_GND_DET_EN_MASK                            0x40
+#define WCD9378_ANA_MBHC_MECH_MECH_DETECT_TYPE_MASK                      0x20
+#define WCD9378_ANA_MBHC_MECH_HPHL_PLUG_TYPE_MASK                        0x10
+#define WCD9378_ANA_MBHC_MECH_GND_PLUG_TYPE_MASK                         0x08
+#define WCD9378_ANA_MBHC_MECH_MECH_HS_L_PULLUP_COMP_EN_MASK              0x04
+#define WCD9378_ANA_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN_MASK              0x02
+#define WCD9378_ANA_MBHC_MECH_SW_HPH_L_P_100K_TO_GND_MASK                0x01
+
+/* WCD9378_ANA_MBHC_ELECT Fields: */
+#define WCD9378_ANA_MBHC_ELECT_FSM_EN_MASK                               0x80
+#define WCD9378_ANA_MBHC_ELECT_BTNDET_ISRC_CTL_MASK                      0x70
+#define WCD9378_ANA_MBHC_ELECT_ELECT_DET_TYPE_MASK                       0x08
+#define WCD9378_ANA_MBHC_ELECT_ELECT_SCHMT_ISRC_CTL_MASK                 0x06
+#define WCD9378_ANA_MBHC_ELECT_BIAS_EN_MASK                              0x01
+
+/* WCD9378_ANA_MBHC_ZDET Fields: */
+#define WCD9378_ANA_MBHC_ZDET_ZDET_L_MEAS_EN_MASK                        0x80
+#define WCD9378_ANA_MBHC_ZDET_ZDET_R_MEAS_EN_MASK                        0x40
+#define WCD9378_ANA_MBHC_ZDET_ZDET_CHG_EN_MASK                           0x20
+#define WCD9378_ANA_MBHC_ZDET_ELECT_ISRC_EN_MASK                         0x02
+
+/* WCD9378_ANA_MBHC_RESULT_1 Fields: */
+#define WCD9378_ANA_MBHC_RESULT_1_Z_RESULT_MSB_MASK                      0xff
+
+/* WCD9378_ANA_MBHC_RESULT_2 Fields: */
+#define WCD9378_ANA_MBHC_RESULT_2_Z_RESULT_LSB_MASK                      0xff
+
+/* WCD9378_ANA_MBHC_RESULT_3 Fields: */
+#define WCD9378_ANA_MBHC_RESULT_3_MIC_SCHMT_RESULT_MASK                  0x20
+#define WCD9378_ANA_MBHC_RESULT_3_IN2P_CLAMP_STATE_MASK                  0x10
+#define WCD9378_ANA_MBHC_RESULT_3_BTN_RESULT_MASK                        0x07
+
+/* WCD9378_ANA_MBHC_BTN0 Fields: */
+#define WCD9378_ANA_MBHC_BTN0_VTH_MASK                                   0xfc
+
+/* WCD9378_ANA_MBHC_BTN1 Fields: */
+#define WCD9378_ANA_MBHC_BTN1_VTH_MASK                                   0xfc
+
+/* WCD9378_ANA_MBHC_BTN2 Fields: */
+#define WCD9378_ANA_MBHC_BTN2_VTH_MASK                                   0xfc
+
+/* WCD9378_ANA_MBHC_BTN3 Fields: */
+#define WCD9378_ANA_MBHC_BTN3_VTH_MASK                                   0xfc
+
+/* WCD9378_ANA_MBHC_BTN4 Fields: */
+#define WCD9378_ANA_MBHC_BTN4_VTH_MASK                                   0xfc
+#define WCD9378_ANA_MBHC_BTN4_VDD_SW_IO_SEL_MASK                         0x02
+#define WCD9378_ANA_MBHC_BTN4_LKGCOMP_EN_MASK                            0x01
+
+/* WCD9378_ANA_MBHC_BTN5 Fields: */
+#define WCD9378_ANA_MBHC_BTN5_VTH_MASK                                   0xfc
+
+/* WCD9378_ANA_MBHC_BTN6 Fields: */
+#define WCD9378_ANA_MBHC_BTN6_VTH_MASK                                   0xfc
+
+/* WCD9378_ANA_MBHC_BTN7 Fields: */
+#define WCD9378_ANA_MBHC_BTN7_VTH_MASK                                   0xfc
+
+/* WCD9378_ANA_MICB1 Fields: */
+#define WCD9378_ANA_MICB1_ENABLE_MASK                                    0xc0
+#define WCD9378_ANA_MICB1_VOUT_CTL_MASK                                  0x3f
+
+/* WCD9378_ANA_MICB2 Fields: */
+#define WCD9378_ANA_MICB2_ENABLE_MASK                                    0xc0
+#define WCD9378_ANA_MICB2_VOUT_CTL_MASK                                  0x3f
+
+/* WCD9378_ANA_MICB2_RAMP Fields: */
+#define WCD9378_ANA_MICB2_RAMP_RAMP_ENABLE_MASK                          0x80
+#define WCD9378_ANA_MICB2_RAMP_MB2_IN2P_SHORT_ENABLE_MASK                0x40
+#define WCD9378_ANA_MICB2_RAMP_ALLSW_OVRD_ENABLE_MASK                    0x20
+#define WCD9378_ANA_MICB2_RAMP_SHIFT_CTL_MASK                            0x1c
+
+/* WCD9378_ANA_MICB3 Fields: */
+#define WCD9378_ANA_MICB3_ENABLE_MASK                                    0xc0
+#define WCD9378_ANA_MICB3_PRECHARGE_OVERRIDE_MICB3_MASK                  0x20
+#define WCD9378_ANA_MICB3_PRECHARGE_CLK_SEL_MICB3_MASK                   0x18
+#define WCD9378_ANA_MICB3_SDCA_BYPASS_MASK                               0x04
+
+/* WCD9378_BIAS_CTL Fields: */
+#define WCD9378_BIAS_CTL_BG_FAST_MODE_EN_MASK                            0x80
+#define WCD9378_BIAS_CTL_DC_START_UP_EN_MASK                             0x20
+#define WCD9378_BIAS_CTL_TRAN_START_UP_EN_MASK                           0x10
+#define WCD9378_BIAS_CTL_OTA_BIAS_CTL_MASK                               0x08
+#define WCD9378_BIAS_CTL_ATEST_CTL_MASK                                  0x04
+#define WCD9378_BIAS_CTL_EFUSE_EN_MASK                                   0x02
+
+/* WCD9378_BIAS_VBG_FINE_ADJ Fields: */
+#define WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK                      0xf0
+#define WCD9378_BIAS_VBG_FINE_ADJ_EN_DTEST_BG_STATUS_MASK                0x08
+#define WCD9378_BIAS_VBG_FINE_ADJ_PRECHARGE_TIMER_COUNT_MASK             0x07
+
+/* WCD9378_LDOL_VDDCX_ADJUST Fields: */
+#define WCD9378_LDOL_VDDCX_ADJUST_RC_ZERO_FREQ_TUNE_MASK                 0x0c
+#define WCD9378_LDOL_VDDCX_ADJUST_VDDCX_ADJUST_MASK                      0x03
+
+/* WCD9378_LDOL_DISABLE_LDOL Fields: */
+#define WCD9378_LDOL_DISABLE_LDOL_DISABLE_LDOL_MASK                      0x01
+
+/* WCD9378_MBHC_CTL_CLK Fields: */
+#define WCD9378_MBHC_CTL_CLK_CLK_SEL_MASK                                0x40
+#define WCD9378_MBHC_CTL_CLK_COMP_CLK_CTL_MASK                           0x30
+#define WCD9378_MBHC_CTL_CLK_COMP_AZ_CTL_MASK                            0x0c
+#define WCD9378_MBHC_CTL_CLK_TEST_CLK_EN_MASK                            0x02
+#define WCD9378_MBHC_CTL_CLK_COMP_AVG_BYP_EN_MASK                        0x01
+
+/* WCD9378_MBHC_CTL_ANA Fields: */
+#define WCD9378_MBHC_CTL_ANA_BIAS_SEL_MASK                               0x80
+
+/* WCD9378_MBHC_CTL_SPARE_1 Fields: */
+#define WCD9378_MBHC_CTL_SPARE_1_SPARE_BITS_MASK                         0xfc
+#define WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK                   0x03
+
+/* WCD9378_MBHC_CTL_SPARE_2 Fields: */
+#define WCD9378_MBHC_CTL_SPARE_2_SPARE_BITS_MASK                         0xff
+
+/* WCD9378_MBHC_CTL_BCS Fields: */
+#define WCD9378_MBHC_CTL_BCS_FAST_INT_OVRD_EN_MASK                       0x80
+#define WCD9378_MBHC_CTL_BCS_ELECT_REM_FAST_REG_OVRD_MASK                0x40
+#define WCD9378_MBHC_CTL_BCS_BTN_RELEASE_FAST_REG_OVRD_MASK              0x20
+#define WCD9378_MBHC_CTL_BCS_BTN_PRESS_FAST_REG_OVRD_MASK                0x10
+#define WCD9378_MBHC_CTL_BCS_ANC_DET_EN_MASK                             0x02
+#define WCD9378_MBHC_CTL_BCS_DEBUG_1_MASK                                0x01
+
+/* WCD9378_MBHC_MOISTURE_DET_FSM_STATUS Fields: */
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS_ELECT_IN2P_COMP_MASK        0x80
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS_MECH_HS_G_COMP_MASK         0x40
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS_MECH_HS_M_COMP_MASK         0x20
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS_MECH_HS_L_COMP_MASK         0x10
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS_MOISTURE_INTR_MASK          0x08
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS_MOISTURE_GTPOLLING_STATUS_MASK 0x04
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS_MOISTURE_DET_STATUS_MASK    0x02
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS_SAMPLE_CLK_LDET_MASK        0x01
+
+/* WCD9378_MBHC_TEST_CTL Fields: */
+#define WCD9378_MBHC_TEST_CTL_FAST_DBNC_TIMER_MASK                       0x30
+#define WCD9378_MBHC_TEST_CTL_ATEST_MASK                                 0x0f
+
+/* WCD9378_LDOH_MODE Fields: */
+#define WCD9378_LDOH_MODE_LDOH_EN_MASK                                   0x80
+#define WCD9378_LDOH_MODE_PWRDN_STATE_MASK                               0x40
+#define WCD9378_LDOH_MODE_SLOWRAMP_EN_MASK                               0x20
+#define WCD9378_LDOH_MODE_VOUT_ADJUST_MASK                               0x18
+#define WCD9378_LDOH_MODE_VOUT_COARSE_ADJ_MASK                           0x07
+
+/* WCD9378_LDOH_BIAS Fields: */
+#define WCD9378_LDOH_BIAS_IBIAS_REF_MASK                                 0xe0
+#define WCD9378_LDOH_BIAS_IBIAS_ERR_AMP_MASK                             0x18
+#define WCD9378_LDOH_BIAS_IBIAS_NATIVE_DEVICE_MASK                       0x04
+#define WCD9378_LDOH_BIAS_IBIAS_BUFFER_BLEED_MASK                        0x02
+
+/* WCD9378_LDOH_STB_LOADS Fields: */
+#define WCD9378_LDOH_STB_LOADS_STB_LOADS_1_UA_MASK                       0xf0
+#define WCD9378_LDOH_STB_LOADS_STB_LOAD_10_UA_MASK                       0x08
+
+/* WCD9378_LDOH_SLOWRAMP Fields: */
+#define WCD9378_LDOH_SLOWRAMP_SLOWRAMP_IBIAS_MASK                        0xc0
+#define WCD9378_LDOH_SLOWRAMP_SLOWRAMP_RESET_TIME_MASK                   0x30
+
+/* WCD9378_MICB1_TEST_CTL_1 Fields: */
+#define WCD9378_MICB1_TEST_CTL_1_NOISE_FILT_RES_VAL_MASK                 0xe0
+#define WCD9378_MICB1_TEST_CTL_1_EN_VREFGEN_MASK                         0x10
+#define WCD9378_MICB1_TEST_CTL_1_EN_LDO_MASK                             0x08
+#define WCD9378_MICB1_TEST_CTL_1_LDO_BLEEDER_CTRL_MASK                   0x07
+
+/* WCD9378_MICB1_TEST_CTL_2 Fields: */
+#define WCD9378_MICB1_TEST_CTL_2_IBIAS_VREFGEN_MASK                      0xc0
+#define WCD9378_MICB1_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_MASK             0x20
+#define WCD9378_MICB1_TEST_CTL_2_SPARE_BITS_MASK                         0x18
+#define WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK                   0x07
+
+/* WCD9378_MICB1_TEST_CTL_3 Fields: */
+#define WCD9378_MICB1_TEST_CTL_3_CFILT_REF_EN_MASK                       0x80
+#define WCD9378_MICB1_TEST_CTL_3_RZ_LDO_VAL_MASK                         0x70
+#define WCD9378_MICB1_TEST_CTL_3_IBIAS_LDO_STG3_MASK                     0x0c
+#define WCD9378_MICB1_TEST_CTL_3_ATEST_CTRL_MASK                         0x03
+
+/* WCD9378_MICB2_TEST_CTL_1 Fields: */
+#define WCD9378_MICB2_TEST_CTL_1_NOISE_FILT_RES_VAL_MASK                 0xe0
+#define WCD9378_MICB2_TEST_CTL_1_EN_VREFGEN_MASK                         0x10
+#define WCD9378_MICB2_TEST_CTL_1_EN_LDO_MASK                             0x08
+#define WCD9378_MICB2_TEST_CTL_1_LDO_BLEEDER_CTRL_MASK                   0x07
+
+/* WCD9378_MICB2_TEST_CTL_2 Fields: */
+#define WCD9378_MICB2_TEST_CTL_2_IBIAS_VREFGEN_MASK                      0xc0
+#define WCD9378_MICB2_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_MASK             0x20
+#define WCD9378_MICB2_TEST_CTL_2_SPARE_BITS_MASK                         0x18
+#define WCD9378_MICB2_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK                   0x07
+
+/* WCD9378_MICB2_TEST_CTL_3 Fields: */
+#define WCD9378_MICB2_TEST_CTL_3_CFILT_REF_EN_MASK                       0x80
+#define WCD9378_MICB2_TEST_CTL_3_RZ_LDO_VAL_MASK                         0x70
+#define WCD9378_MICB2_TEST_CTL_3_IBIAS_LDO_STG3_MASK                     0x0c
+#define WCD9378_MICB2_TEST_CTL_3_ATEST_CTRL_MASK                         0x03
+
+/* WCD9378_MICB3_TEST_CTL_1 Fields: */
+#define WCD9378_MICB3_TEST_CTL_1_PRECHARGE_OVERRIDE_MICB1_MASK           0x80
+#define WCD9378_MICB3_TEST_CTL_1_PRECHARGE_CLK_SEL_MICB1_MASK            0x60
+#define WCD9378_MICB3_TEST_CTL_1_EN_VREFGEN3_MASK                        0x10
+#define WCD9378_MICB3_TEST_CTL_1_EN_LDO3_MASK                            0x08
+#define WCD9378_MICB3_TEST_CTL_1_LDO_BLEEDER_CTRL3_MASK                  0x07
+
+/* WCD9378_MICB3_TEST_CTL_2 Fields: */
+#define WCD9378_MICB3_TEST_CTL_2_FILTER_POLYRES_EN_MICB2_MASK            0x80
+#define WCD9378_MICB3_TEST_CTL_2_PRECHARGE_OVERRIDE_MICB2_MASK           0x40
+#define WCD9378_MICB3_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS3_MASK            0x20
+#define WCD9378_MICB3_TEST_CTL_2_PRECHARGE_CLK_SEL_MICB2_MASK            0x18
+#define WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK                   0x07
+
+/* WCD9378_MICB3_TEST_CTL_3 Fields: */
+#define WCD9378_MICB3_TEST_CTL_3_FILTER_MOSRES_EN_MICB2_MASK             0x80
+#define WCD9378_MICB3_TEST_CTL_3_RZ_LDO_VAL_MASK                         0x70
+#define WCD9378_MICB3_TEST_CTL_3_IBIAS_LDO_STG3_MASK                     0x0c
+#define WCD9378_MICB3_TEST_CTL_3_ATEST_CTRL_MASK                         0x03
+
+/* WCD9378_TX_COM_ADC_VCM Fields: */
+#define WCD9378_TX_COM_ADC_VCM_VCM_L2_12P288_MASK                        0x30
+#define WCD9378_TX_COM_ADC_VCM_VCM_L2_9P6_MASK                           0x0c
+#define WCD9378_TX_COM_ADC_VCM_VCM_DEFAULT_MASK                          0x03
+
+/* WCD9378_TX_COM_BIAS_ATEST Fields: */
+#define WCD9378_TX_COM_BIAS_ATEST_TX_CURR_EN_MASK                        0x80
+#define WCD9378_TX_COM_BIAS_ATEST_SC_BIAS_EN_MASK                        0x40
+#define WCD9378_TX_COM_BIAS_ATEST_SC_BIAS_VREF_SEL_MASK                  0x20
+#define WCD9378_TX_COM_BIAS_ATEST_ATEST4_EN_MASK                         0x08
+#define WCD9378_TX_COM_BIAS_ATEST_ATEST3_EN_MASK                         0x04
+#define WCD9378_TX_COM_BIAS_ATEST_ATEST2_EN_MASK                         0x02
+#define WCD9378_TX_COM_BIAS_ATEST_ATEST1_EN_MASK                         0x01
+
+/* WCD9378_TX_COM_SPARE1 Fields: */
+#define WCD9378_TX_COM_SPARE1_SPARE_BITS_7_0_MASK                        0xff
+
+/* WCD9378_TX_COM_SPARE2 Fields: */
+#define WCD9378_TX_COM_SPARE2_SPARE_BITS_7_0_MASK                        0xff
+
+/* WCD9378_TX_COM_TXFE_DIV_CTL Fields: */
+#define WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK                      0x80
+#define WCD9378_TX_COM_TXFE_DIV_CTL_FB_SW_DRIVE_MASK                     0x20
+#define WCD9378_TX_COM_TXFE_DIV_CTL_EN_CKGEN_INIT_MASK                   0x10
+#define WCD9378_TX_COM_TXFE_DIV_CTL_N_PAUSE_MASK                         0x03
+
+/* WCD9378_TX_COM_TXFE_DIV_START Fields: */
+#define WCD9378_TX_COM_TXFE_DIV_START_DIV_MASK                           0xff
+
+/* WCD9378_TX_COM_SPARE3 Fields: */
+#define WCD9378_TX_COM_SPARE3_SPARE_BITS_7_0_MASK                        0xff
+
+/* WCD9378_TX_COM_SPARE4 Fields: */
+#define WCD9378_TX_COM_SPARE4_SPARE_BITS_7_0_MASK                        0xff
+
+/* WCD9378_TX_1_2_TEST_EN Fields: */
+#define WCD9378_TX_1_2_TEST_EN_TXFE1_EN_MASK                             0x80
+#define WCD9378_TX_1_2_TEST_EN_ADC1_EN_MASK                              0x40
+#define WCD9378_TX_1_2_TEST_EN_TXFE1_BYPASS_MASK                         0x20
+#define WCD9378_TX_1_2_TEST_EN_TXFE1_CLK_MODE_MASK                       0x10
+#define WCD9378_TX_1_2_TEST_EN_TXFE2_EN_MASK                             0x08
+#define WCD9378_TX_1_2_TEST_EN_ADC2_EN_MASK                              0x04
+#define WCD9378_TX_1_2_TEST_EN_TXFE2_BYPASS_MASK                         0x02
+#define WCD9378_TX_1_2_TEST_EN_TXFE2_CLK_MODE_MASK                       0x01
+
+/* WCD9378_TX_1_2_ADC_IB Fields: */
+#define WCD9378_TX_1_2_ADC_IB_ADC2_DEM_MODE_MASK                         0xc0
+#define WCD9378_TX_1_2_ADC_IB_ADC2_DEM_OPERATION_MASK                    0x30
+#define WCD9378_TX_1_2_ADC_IB_L2_DAC_DLY_MASK                            0x0c
+#define WCD9378_TX_1_2_ADC_IB_DEFAULT_DAC_DLY_MASK                       0x03
+
+/* WCD9378_TX_1_2_ATEST_REFCTL Fields: */
+#define WCD9378_TX_1_2_ATEST_REFCTL_ATEST_CTL_MASK                       0xf0
+#define WCD9378_TX_1_2_ATEST_REFCTL_TXFE_INCM_REF_MASK                   0x0c
+#define WCD9378_TX_1_2_ATEST_REFCTL_TXFE_HP_GAIN_MODE_MASK               0x02
+#define WCD9378_TX_1_2_ATEST_REFCTL_SPARE_BITS_0_0_MASK                  0x01
+
+/* WCD9378_TX_1_2_TEST_CTL Fields: */
+#define WCD9378_TX_1_2_TEST_CTL_TXFE_HP_GAIN_MASK                        0x80
+#define WCD9378_TX_1_2_TEST_CTL_REF_CAP_MASK                             0x40
+#define WCD9378_TX_1_2_TEST_CTL_ADC1_DEM_MODE_MASK                       0x30
+#define WCD9378_TX_1_2_TEST_CTL_ADC1_DEM_OPERATION_MASK                  0x0c
+#define WCD9378_TX_1_2_TEST_CTL_SAR_ERR_DET_EN_MASK                      0x02
+#define WCD9378_TX_1_2_TEST_CTL_SAR_EXT_DELAY_EN_MASK                    0x01
+
+/* WCD9378_TX_1_2_TEST_BLK_EN1 Fields: */
+#define WCD9378_TX_1_2_TEST_BLK_EN1_ADC1_INT1_EN_MASK                    0x80
+#define WCD9378_TX_1_2_TEST_BLK_EN1_ADC1_INT2_EN_MASK                    0x40
+#define WCD9378_TX_1_2_TEST_BLK_EN1_ADC1_SAR_EN_MASK                     0x20
+#define WCD9378_TX_1_2_TEST_BLK_EN1_ADC1_CMGEN_EN_MASK                   0x10
+#define WCD9378_TX_1_2_TEST_BLK_EN1_ADC1_CLKGEN_EN_MASK                  0x08
+#define WCD9378_TX_1_2_TEST_BLK_EN1_REF_EN_MASK                          0x04
+#define WCD9378_TX_1_2_TEST_BLK_EN1_TXFE1_CLKDIV_EN_MASK                 0x02
+#define WCD9378_TX_1_2_TEST_BLK_EN1_TXFE2_CLKDIV_EN_MASK                 0x01
+
+/* WCD9378_TX_1_2_TXFE1_CLKDIV Fields: */
+#define WCD9378_TX_1_2_TXFE1_CLKDIV_DIV_MASK                             0xff
+
+/* WCD9378_TX_1_2_SAR2_ERR Fields: */
+#define WCD9378_TX_1_2_SAR2_ERR_SAR_ERR_COUNT_MASK                       0xff
+
+/* WCD9378_TX_1_2_SAR1_ERR Fields: */
+#define WCD9378_TX_1_2_SAR1_ERR_SAR_ERR_COUNT_MASK                       0xff
+
+/* WCD9378_TX_3_TEST_EN Fields: */
+#define WCD9378_TX_3_TEST_EN_TXFE3_EN_MASK                               0x80
+#define WCD9378_TX_3_TEST_EN_ADC3_EN_MASK                                0x40
+#define WCD9378_TX_3_TEST_EN_TXFE3_BYPASS_MASK                           0x20
+#define WCD9378_TX_3_TEST_EN_TXFE3_CLK_MODE_MASK                         0x10
+#define WCD9378_TX_3_TEST_EN_SPARE_BITS_3_0_MASK                         0x0f
+
+/* WCD9378_TX_3_ADC_IB Fields: */
+#define WCD9378_TX_3_ADC_IB_SPARE_BITS_3_0_MASK                          0xf0
+#define WCD9378_TX_3_ADC_IB_L2_DAC_DLY_MASK                              0x0c
+#define WCD9378_TX_3_ADC_IB_DEFAULT_DAC_DLY_MASK                         0x03
+
+/* WCD9378_TX_3_ATEST_REFCTL Fields: */
+#define WCD9378_TX_3_ATEST_REFCTL_ATEST_CTL_MASK                         0xf0
+#define WCD9378_TX_3_ATEST_REFCTL_TXFE_INCM_REF_MASK                     0x0c
+#define WCD9378_TX_3_ATEST_REFCTL_TXFE_HP_GAIN_MODE_MASK                 0x02
+#define WCD9378_TX_3_ATEST_REFCTL_SPARE_BITS_0_0_MASK                    0x01
+
+/* WCD9378_TX_3_TEST_CTL Fields: */
+#define WCD9378_TX_3_TEST_CTL_TXFE_HP_GAIN_MASK                          0x80
+#define WCD9378_TX_3_TEST_CTL_REF_CAP_MASK                               0x40
+#define WCD9378_TX_3_TEST_CTL_ADC3_DEM_MODE_MASK                         0x30
+#define WCD9378_TX_3_TEST_CTL_ADC3_DEM_OPERATION_MASK                    0x0c
+#define WCD9378_TX_3_TEST_CTL_SAR_ERR_DET_EN_MASK                        0x02
+#define WCD9378_TX_3_TEST_CTL_SAR_EXT_DELAY_EN_MASK                      0x01
+
+/* WCD9378_TX_3_TEST_BLK_EN3 Fields: */
+#define WCD9378_TX_3_TEST_BLK_EN3_ADC3_INT1_EN_MASK                      0x80
+#define WCD9378_TX_3_TEST_BLK_EN3_ADC3_INT2_EN_MASK                      0x40
+#define WCD9378_TX_3_TEST_BLK_EN3_ADC3_SAR_EN_MASK                       0x20
+#define WCD9378_TX_3_TEST_BLK_EN3_ADC3_CMGEN_EN_MASK                     0x10
+#define WCD9378_TX_3_TEST_BLK_EN3_ADC3_CLKGEN_EN_MASK                    0x08
+#define WCD9378_TX_3_TEST_BLK_EN3_REF_EN_MASK                            0x04
+#define WCD9378_TX_3_TEST_BLK_EN3_TXFE3_CLKDIV_EN_MASK                   0x02
+#define WCD9378_TX_3_TEST_BLK_EN3_SPARE_BITS_0_0_MASK                    0x01
+
+/* WCD9378_TX_3_TXFE3_CLKDIV Fields: */
+#define WCD9378_TX_3_TXFE3_CLKDIV_DIV_MASK                               0xff
+
+/* WCD9378_TX_3_SAR4_ERR Fields: */
+#define WCD9378_TX_3_SAR4_ERR_SAR_ERR_COUNT_MASK                         0xff
+
+/* WCD9378_TX_3_SAR3_ERR Fields: */
+#define WCD9378_TX_3_SAR3_ERR_SAR_ERR_COUNT_MASK                         0xff
+
+/* WCD9378_TX_3_TEST_BLK_EN2 Fields: */
+#define WCD9378_TX_3_TEST_BLK_EN2_ADC2_INT1_EN_MASK                      0x80
+#define WCD9378_TX_3_TEST_BLK_EN2_ADC2_INT2_EN_MASK                      0x40
+#define WCD9378_TX_3_TEST_BLK_EN2_ADC2_SAR_EN_MASK                       0x20
+#define WCD9378_TX_3_TEST_BLK_EN2_ADC2_CMGEN_EN_MASK                     0x10
+#define WCD9378_TX_3_TEST_BLK_EN2_ADC2_CLKGEN_EN_MASK                    0x08
+#define WCD9378_TX_3_TEST_BLK_EN2_ADC12_VREF_NONL2_MASK                  0x06
+#define WCD9378_TX_3_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN_MASK              0x01
+
+/* WCD9378_TX_3_TXFE2_CLKDIV Fields: */
+#define WCD9378_TX_3_TXFE2_CLKDIV_DIV_MASK                               0xff
+
+/* WCD9378_TX_3_SPARE1 Fields: */
+#define WCD9378_TX_3_SPARE1_SPARE_BITS_7_0_MASK                          0xff
+
+/* WCD9378_TX_3_TEST_BLK_EN4 Fields: */
+#define WCD9378_TX_3_TEST_BLK_EN4_SPARE_BITS_7_3_MASK                    0xf8
+#define WCD9378_TX_3_TEST_BLK_EN4_ADC34_VREF_NONL2_MASK                  0x06
+#define WCD9378_TX_3_TEST_BLK_EN4_SPARE_BITS_0_0_MASK                    0x01
+
+/* WCD9378_TX_3_SPARE2 Fields: */
+#define WCD9378_TX_3_SPARE2_SPARE_BITS_7_0_MASK                          0xff
+
+/* WCD9378_TX_3_SPARE3 Fields: */
+#define WCD9378_TX_3_SPARE3_SPARE_BITS_7_0_MASK                          0xff
+
+/* WCD9378_RX_AUX_SW_CTL Fields: */
+#define WCD9378_RX_AUX_SW_CTL_AUXL_SW_EN_MASK                            0x80
+#define WCD9378_RX_AUX_SW_CTL_AUXR_SW_EN_MASK                            0x40
+#define WCD9378_RX_AUX_SW_CTL_AUXL2R_SW_EN_MASK                          0x20
+
+/* WCD9378_RX_PA_AUX_IN_CONN Fields: */
+#define WCD9378_RX_PA_AUX_IN_CONN_HPHL_AUX_IN_MASK                       0x80
+#define WCD9378_RX_PA_AUX_IN_CONN_HPHR_AUX_IN_MASK                       0x40
+#define WCD9378_RX_PA_AUX_IN_CONN_EAR_AUX_IN_MASK                        0x20
+#define WCD9378_RX_PA_AUX_IN_CONN_AUX_AUX_IN_MASK                        0x10
+
+/* WCD9378_RX_TIMER_DIV Fields: */
+#define WCD9378_RX_TIMER_DIV_RX_CLK_DIVIDER_OVWT_MASK                    0x80
+#define WCD9378_RX_TIMER_DIV_RX_CLK_DIVIDER_MASK                         0x7f
+
+/* WCD9378_RX_OCP_CTL Fields: */
+#define WCD9378_RX_OCP_CTL_SPARE_BITS_MASK                               0xf0
+#define WCD9378_RX_OCP_CTL_N_CONNECTION_ATTEMPTS_MASK                    0x0f
+
+/* WCD9378_RX_OCP_COUNT Fields: */
+#define WCD9378_RX_OCP_COUNT_RUN_N_CYCLES_MASK                           0xf0
+#define WCD9378_RX_OCP_COUNT_WAIT_N_CYCLES_MASK                          0x0f
+
+/* WCD9378_RX_BIAS_EAR_DAC Fields: */
+#define WCD9378_RX_BIAS_EAR_DAC_EAR_DAC_5_UA_MASK                        0xf0
+#define WCD9378_RX_BIAS_EAR_DAC_ATEST_RX_BIAS_MASK                       0x0f
+
+/* WCD9378_RX_BIAS_EAR_AMP Fields: */
+#define WCD9378_RX_BIAS_EAR_AMP_EAR_AMP_10_UA_MASK                       0xf0
+#define WCD9378_RX_BIAS_EAR_AMP_EAR_AMP_5_UA_MASK                        0x0f
+
+/* WCD9378_RX_BIAS_HPH_LDO Fields: */
+#define WCD9378_RX_BIAS_HPH_LDO_HPH_NVLDO2_5_UA_MASK                     0xf0
+#define WCD9378_RX_BIAS_HPH_LDO_HPH_NVLDO1_4P5_UA_MASK                   0x0f
+
+/* WCD9378_RX_BIAS_HPH_PA Fields: */
+#define WCD9378_RX_BIAS_HPH_PA_HPH_CONSTOP_5_UA_MASK                     0xf0
+#define WCD9378_RX_BIAS_HPH_PA_HPH_AMP_5_UA_MASK                         0x0f
+
+/* WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2 Fields: */
+#define WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2_RDAC_BUF_4_UA_MASK             0xf0
+#define WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2_HPH_CNP_10_UA_MASK             0x0f
+
+/* WCD9378_RX_BIAS_HPH_RDAC_LDO Fields: */
+#define WCD9378_RX_BIAS_HPH_RDAC_LDO_RDAC_LDO_1P65_4_UA_MASK             0xf0
+#define WCD9378_RX_BIAS_HPH_RDAC_LDO_RDAC_LDO_N1P65_4_UA_MASK            0x0f
+
+/* WCD9378_RX_BIAS_HPH_CNP1 Fields: */
+#define WCD9378_RX_BIAS_HPH_CNP1_HPH_CNP_4_UA_MASK                       0xf0
+#define WCD9378_RX_BIAS_HPH_CNP1_HPH_CNP_3_UA_MASK                       0x0f
+
+/* WCD9378_RX_BIAS_HPH_LOWPOWER Fields: */
+#define WCD9378_RX_BIAS_HPH_LOWPOWER_HPH_AMP_LP_1P5_UA_MASK              0xf0
+#define WCD9378_RX_BIAS_HPH_LOWPOWER_RDAC_BUF_LP_0P5_UA_MASK             0x0f
+
+/* WCD9378_RX_BIAS_AUX_DAC Fields: */
+#define WCD9378_RX_BIAS_AUX_DAC_AUX_DAC_5_UA_MASK                        0xf0
+
+/* WCD9378_RX_BIAS_AUX_AMP Fields: */
+#define WCD9378_RX_BIAS_AUX_AMP_AUX_AMP_10_UA_MASK                       0xf0
+#define WCD9378_RX_BIAS_AUX_AMP_AUX_AMP_5_UA_MASK                        0x0f
+
+/* WCD9378_RX_SPARE_1 Fields: */
+#define WCD9378_RX_SPARE_1_SPARE_BITS_7_0_MASK                           0xff
+
+/* WCD9378_RX_SPARE_2 Fields: */
+#define WCD9378_RX_SPARE_2_SPARE_BITS_7_0_MASK                           0xff
+
+/* WCD9378_RX_SPARE_3 Fields: */
+#define WCD9378_RX_SPARE_3_SPARE_BITS_7_0_MASK                           0xff
+
+/* WCD9378_RX_SPARE_4 Fields: */
+#define WCD9378_RX_SPARE_4_SPARE_BITS_7_0_MASK                           0xff
+
+/* WCD9378_RX_SPARE_5 Fields: */
+#define WCD9378_RX_SPARE_5_SPARE_BITS_7_0_MASK                           0xff
+
+/* WCD9378_RX_SPARE_6 Fields: */
+#define WCD9378_RX_SPARE_6_SPARE_BITS_7_0_MASK                           0xff
+
+/* WCD9378_RX_SPARE_7 Fields: */
+#define WCD9378_RX_SPARE_7_SPARE_BITS_7_0_MASK                           0xff
+
+/* WCD9378_HPH_L_STATUS Fields: */
+#define WCD9378_HPH_L_STATUS_CMPDR_GAIN_MASK                             0xf8
+#define WCD9378_HPH_L_STATUS_OCP_COMP_DETECT_MASK                        0x04
+#define WCD9378_HPH_L_STATUS_OCP_LIMIT_MASK                              0x02
+#define WCD9378_HPH_L_STATUS_PA_READY_MASK                               0x01
+
+/* WCD9378_HPH_R_STATUS Fields: */
+#define WCD9378_HPH_R_STATUS_CMPDR_GAIN_MASK                             0xf8
+#define WCD9378_HPH_R_STATUS_OCP_COMP_DETECT_MASK                        0x04
+#define WCD9378_HPH_R_STATUS_OCP_LIMIT_MASK                              0x02
+#define WCD9378_HPH_R_STATUS_PA_READY_MASK                               0x01
+
+/* WCD9378_HPH_CNP_EN Fields: */
+#define WCD9378_HPH_CNP_EN_FSM_CLK_EN_MASK                               0x80
+#define WCD9378_HPH_CNP_EN_FSM_RESET_MASK                                0x40
+#define WCD9378_HPH_CNP_EN_CNP_IREF_SEL_MASK                             0x20
+#define WCD9378_HPH_CNP_EN_FSM_OVERRIDE_EN_MASK                          0x08
+#define WCD9378_HPH_CNP_EN_WG_LR_SEL_MASK                                0x04
+#define WCD9378_HPH_CNP_EN_DBG_CURR_DIRECTION_R_MASK                     0x02
+#define WCD9378_HPH_CNP_EN_DBG_VREF_EN_MASK                              0x01
+
+/* WCD9378_HPH_CNP_WG_CTL Fields: */
+#define WCD9378_HPH_CNP_WG_CTL_GM3_BOOST_EN_MASK                         0x80
+#define WCD9378_HPH_CNP_WG_CTL_NO_PD_SEQU_MASK                           0x40
+#define WCD9378_HPH_CNP_WG_CTL_VREF_TIMER_MASK                           0x38
+#define WCD9378_HPH_CNP_WG_CTL_CURR_LDIV_CTL_MASK                        0x07
+
+/* WCD9378_HPH_CNP_WG_TIME Fields: */
+#define WCD9378_HPH_CNP_WG_TIME_WG_FINE_TIMER_MASK                       0xff
+
+/* WCD9378_HPH_OCP_CTL Fields: */
+#define WCD9378_HPH_OCP_CTL_OCP_CURR_LIMIT_MASK                          0xe0
+#define WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK                              0x10
+#define WCD9378_HPH_OCP_CTL_SPARE_BITS_MASK                              0x08
+#define WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK                               0x02
+
+/* WCD9378_HPH_AUTO_CHOP Fields: */
+#define WCD9378_HPH_AUTO_CHOP_AUTO_CHOPPER_MODE_MASK                     0x20
+#define WCD9378_HPH_AUTO_CHOP_GAIN_THRESHOLD_MASK                        0x1f
+
+/* WCD9378_HPH_CHOP_CTL Fields: */
+#define WCD9378_HPH_CHOP_CTL_CHOPPER_EN_MASK                             0x80
+#define WCD9378_HPH_CHOP_CTL_CLK_INV_MASK                                0x40
+#define WCD9378_HPH_CHOP_CTL_DIV2_DIV_BY_2_MASK                          0x04
+#define WCD9378_HPH_CHOP_CTL_DIV2_DIV_BY_2_4_6_8_MASK                    0x03
+
+/* WCD9378_HPH_PA_CTL1 Fields: */
+#define WCD9378_HPH_PA_CTL1_GM3_IBIAS_CTL_MASK                           0xf0
+#define WCD9378_HPH_PA_CTL1_GM3_IB_SCALE_MASK                            0x0e
+
+/* WCD9378_HPH_PA_CTL2 Fields: */
+#define WCD9378_HPH_PA_CTL2_SPARE_BITS_MASK                              0x80
+#define WCD9378_HPH_PA_CTL2_HPHPA_GND_R_MASK                             0x40
+#define WCD9378_HPH_PA_CTL2_HPHPA_GND_L_MASK                             0x10
+
+/* WCD9378_HPH_L_EN Fields: */
+#define WCD9378_HPH_L_EN_CONST_SEL_L_MASK                                0xc0
+#define WCD9378_HPH_L_EN_GAIN_SOURCE_SEL_MASK                            0x20
+#define WCD9378_HPH_L_EN_PA_GAIN_MASK                                    0x1f
+
+/* WCD9378_HPH_L_TEST Fields: */
+#define WCD9378_HPH_L_TEST_PDN_EN_MASK                                   0x80
+#define WCD9378_HPH_L_TEST_PDN_AMP2_EN_MASK                              0x40
+#define WCD9378_HPH_L_TEST_PDN_AMP_EN_MASK                               0x20
+#define WCD9378_HPH_L_TEST_PA_CNP_SW_CONN_MASK                           0x10
+#define WCD9378_HPH_L_TEST_PA_CNP_SW_OFF_MASK                            0x08
+#define WCD9378_HPH_L_TEST_PA_CNP_SW_ON_MASK                             0x04
+#define WCD9378_HPH_L_TEST_OCP_DET_EN_MASK                               0x01
+
+/* WCD9378_HPH_L_ATEST Fields: */
+#define WCD9378_HPH_L_ATEST_DACL_REF_ATEST1_CONN_MASK                    0x80
+#define WCD9378_HPH_L_ATEST_LDO1_L_ATEST2_CONN_MASK                      0x40
+#define WCD9378_HPH_L_ATEST_LDO_L_ATEST2_CAL_MASK                        0x20
+#define WCD9378_HPH_L_ATEST_LDO2_L_ATEST2_CONN_MASK                      0x10
+#define WCD9378_HPH_L_ATEST_HPHPA_GND_OVR_MASK                           0x08
+#define WCD9378_HPH_L_ATEST_CNP_EXD2_MASK                                0x02
+#define WCD9378_HPH_L_ATEST_CNP_EXD1_MASK                                0x01
+
+/* WCD9378_HPH_R_EN Fields: */
+#define WCD9378_HPH_R_EN_CONST_SEL_R_MASK                                0xc0
+#define WCD9378_HPH_R_EN_GAIN_SOURCE_SEL_MASK                            0x20
+#define WCD9378_HPH_R_EN_PA_GAIN_MASK                                    0x1f
+
+/* WCD9378_HPH_R_TEST Fields: */
+#define WCD9378_HPH_R_TEST_PDN_EN_MASK                                   0x80
+#define WCD9378_HPH_R_TEST_PDN_AMP2_EN_MASK                              0x40
+#define WCD9378_HPH_R_TEST_PDN_AMP_EN_MASK                               0x20
+#define WCD9378_HPH_R_TEST_PA_CNP_SW_CONN_MASK                           0x10
+#define WCD9378_HPH_R_TEST_PA_CNP_SW_OFF_MASK                            0x08
+#define WCD9378_HPH_R_TEST_PA_CNP_SW_ON_MASK                             0x04
+#define WCD9378_HPH_R_TEST_OCP_DET_EN_MASK                               0x01
+
+/* WCD9378_HPH_R_ATEST Fields: */
+#define WCD9378_HPH_R_ATEST_DACR_REF_ATEST1_CONN_MASK                    0x80
+#define WCD9378_HPH_R_ATEST_LDO1_R_ATEST2_CONN_MASK                      0x40
+#define WCD9378_HPH_R_ATEST_LDO_R_ATEST2_CAL_MASK                        0x20
+#define WCD9378_HPH_R_ATEST_LDO2_R_ATEST2_CONN_MASK                      0x10
+#define WCD9378_HPH_R_ATEST_LDO_1P65V_ATEST1_CONN_MASK                   0x08
+#define WCD9378_HPH_R_ATEST_HPH_GE_EFUSE_MASK                            0x04
+#define WCD9378_HPH_R_ATEST_HPHPA_GND_OVR_MASK                           0x02
+
+/* WCD9378_HPH_RDAC_CLK_CTL1 Fields: */
+#define WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK                 0x80
+#define WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_DIV_CTRL_MASK           0x70
+#define WCD9378_HPH_RDAC_CLK_CTL1_SPARE_BITS_MASK                        0x0f
+
+/* WCD9378_HPH_RDAC_CLK_CTL2 Fields: */
+#define WCD9378_HPH_RDAC_CLK_CTL2_SPARE_BITS_MASK                        0xf0
+#define WCD9378_HPH_RDAC_CLK_CTL2_PREREF_SC_CLK_EN_MASK                  0x08
+#define WCD9378_HPH_RDAC_CLK_CTL2_PREREF_SC_CLK_DIVIDER_CTRL_MASK        0x07
+
+/* WCD9378_HPH_RDAC_LDO_CTL Fields: */
+#define WCD9378_HPH_RDAC_LDO_CTL_LDO_1P65_BYPASS_MASK                    0x80
+#define WCD9378_HPH_RDAC_LDO_CTL_LDO_1P65_OUTCTL_MASK                    0x70
+#define WCD9378_HPH_RDAC_LDO_CTL_N1P65V_LDO_BYPASS_MASK                  0x08
+#define WCD9378_HPH_RDAC_LDO_CTL_N1P65_LDO_OUTCTL_MASK                   0x07
+
+/* WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL Fields: */
+#define WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL_OPAMP_CHOP_CLK_EN_LP_MASK       0x80
+
+/* WCD9378_HPH_REFBUFF_UHQA_CTL Fields: */
+#define WCD9378_HPH_REFBUFF_UHQA_CTL_OPAMP_IQ_PROG_MASK                  0xc0
+#define WCD9378_HPH_REFBUFF_UHQA_CTL_SPARE_BITS_MASK                     0x3f
+
+/* WCD9378_HPH_REFBUFF_LP_CTL Fields: */
+#define WCD9378_HPH_REFBUFF_LP_CTL_SPARE_BITS_MASK                       0xc0
+#define WCD9378_HPH_REFBUFF_LP_CTL_OPAMP_IQ_PROG_MASK                    0x30
+#define WCD9378_HPH_REFBUFF_LP_CTL_EN_PREREF_FILT_STARTUP_CLKDIV_MASK    0x08
+#define WCD9378_HPH_REFBUFF_LP_CTL_PREREF_FILT_STARTUP_CLKDIV_CTL_MASK   0x06
+#define WCD9378_HPH_REFBUFF_LP_CTL_PREREF_FILT_BYPASS_MASK               0x01
+
+/* WCD9378_HPH_L_DAC_CTL Fields: */
+#define WCD9378_HPH_L_DAC_CTL_DAC_REF_EN_MASK                            0x40
+#define WCD9378_HPH_L_DAC_CTL_DAC_SAMPLE_EDGE_SELECT_MASK                0x20
+#define WCD9378_HPH_L_DAC_CTL_DATA_RESET_MASK                            0x10
+#define WCD9378_HPH_L_DAC_CTL_INV_DATA_MASK                              0x08
+#define WCD9378_HPH_L_DAC_CTL_DAC_L_EN_OV_MASK                           0x04
+#define WCD9378_HPH_L_DAC_CTL_DAC_LDO_UHQA_OV_MASK                       0x02
+#define WCD9378_HPH_L_DAC_CTL_DAC_LDO_POWERMODE_MASK                     0x01
+
+/* WCD9378_HPH_R_DAC_CTL Fields: */
+#define WCD9378_HPH_R_DAC_CTL_DAC_REF_EN_MASK                            0x40
+#define WCD9378_HPH_R_DAC_CTL_DAC_SAMPLE_EDGE_SELECT_MASK                0x20
+#define WCD9378_HPH_R_DAC_CTL_DATA_RESET_MASK                            0x10
+#define WCD9378_HPH_R_DAC_CTL_INV_DATA_MASK                              0x08
+#define WCD9378_HPH_R_DAC_CTL_DAC_R_EN_OV_MASK                           0x04
+#define WCD9378_HPH_R_DAC_CTL_DAC_PREREF_UHQA_OV_MASK                    0x02
+#define WCD9378_HPH_R_DAC_CTL_DAC_PREREF_POWERMODE_MASK                  0x01
+
+/* WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL Fields: */
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHL_PSURGE_MASK 0xc0
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHL_NSURGE_MASK 0x30
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHR_PSURGE_MASK 0x0c
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHR_NSURGE_MASK 0x03
+
+/* WCD9378_HPH_SURGE_HPHLR_SURGE_EN Fields: */
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN_EN_SURGE_PROTECTION_HPHL_MASK   0x80
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN_EN_SURGE_PROTECTION_HPHR_MASK   0x40
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN_SEL_SURGE_COMP_IQ_MASK          0x30
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN_SURGE_VOLT_MODE_SHUTOFF_EN_MASK 0x08
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN_LATCH_INTR_OP_STG_HIZ_EN_MASK   0x04
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN_SURGE_LATCH_REG_RESET_MASK      0x02
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN_SWTICH_VN_VNDAC_NSURGE_EN_MASK  0x01
+
+/* WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1 Fields: */
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1_EN_VNEG_PULLDN_MASK          0x80
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1_EN_OFFSET_36MV_NSURGE_RESLADDER_MASK 0x40
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1_EN_NMOS_LAMP_MASK            0x20
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1_SPARE_BITS_MASK              0x1f
+
+/* WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS Fields: */
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS_HPHL_CLAMP_SW_STATUS_MASK   0x80
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS_HPHR_CLAMP_SW_STATUS_MASK   0x40
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS_HPHL_PSURGE_COMP_STATUS_MASK 0x20
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS_HPHL_NSURGE_COMP_STATUS_MASK 0x10
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS_HPHR_PSURGE_COMP_STATUS_MASK 0x08
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS_HPHR_NSURGE_COMP_STATUS_MASK 0x04
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS_HPHL_SURGE_DET_INTR_EN_MASK 0x02
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS_HPHR_SURGE_DET_INTR_EN_MASK 0x01
+
+/* WCD9378_EAR_EAR_EN_REG Fields: */
+#define WCD9378_EAR_EAR_EN_REG_EAR_DAC_DATA_RESET_MASK                   0x80
+#define WCD9378_EAR_EAR_EN_REG_EAR_DAC_DATA_EN_MASK                      0x40
+#define WCD9378_EAR_EAR_EN_REG_EAR_DAC_REF_EN_MASK                       0x20
+#define WCD9378_EAR_EAR_EN_REG_EAR_VCM_EN_MASK                           0x10
+#define WCD9378_EAR_EAR_EN_REG_EAR_AMP_EN_MASK                           0x08
+#define WCD9378_EAR_EAR_EN_REG_EAR_BIAS_EN_MASK                          0x04
+#define WCD9378_EAR_EAR_EN_REG_EAR_CNP_FSM_EN_MASK                       0x02
+#define WCD9378_EAR_EAR_EN_REG_EAR_OUTPUT_SHORT_MASK                     0x01
+
+/* WCD9378_EAR_EAR_PA_CON Fields: */
+#define WCD9378_EAR_EAR_PA_CON_EAR_ANA_AUX_EN_MASK                       0x80
+#define WCD9378_EAR_EAR_PA_CON_EAR_CMFB_SF_BYPASS_MASK                   0x40
+#define WCD9378_EAR_EAR_PA_CON_EAR_SF_CURR_MASK                          0x20
+#define WCD9378_EAR_EAR_PA_CON_EAR_BTI_CTL_MASK                          0x10
+#define WCD9378_EAR_EAR_PA_CON_EAR_GM3_IBIAS_CTL_MASK                    0x0f
+
+/* WCD9378_EAR_EAR_SP_CON Fields: */
+#define WCD9378_EAR_EAR_SP_CON_EAR_SP_INT_EN_MASK                        0x80
+#define WCD9378_EAR_EAR_SP_CON_EAR_SP_AUTO_SHT_DWN_MASK                  0x40
+#define WCD9378_EAR_EAR_SP_CON_SP_LIMIT_CURR_NMOS_MASK                   0x38
+#define WCD9378_EAR_EAR_SP_CON_SP_LIMIT_CURR_PMOS_MASK                   0x07
+
+/* WCD9378_EAR_EAR_DAC_CON Fields: */
+#define WCD9378_EAR_EAR_DAC_CON_DAC_SAMPLE_EDGE_SEL_MASK                 0x80
+#define WCD9378_EAR_EAR_DAC_CON_REF_DBG_EN_MASK                          0x40
+#define WCD9378_EAR_EAR_DAC_CON_REF_DBG_GAIN_MASK                        0x38
+#define WCD9378_EAR_EAR_DAC_CON_GAIN_DAC_MASK                            0x06
+#define WCD9378_EAR_EAR_DAC_CON_INV_DATA_MASK                            0x01
+
+/* WCD9378_EAR_EAR_CNP_FSM_CON Fields: */
+#define WCD9378_EAR_EAR_CNP_FSM_CON_CNP_FSM_CLK_DIV1_MASK                0xf0
+#define WCD9378_EAR_EAR_CNP_FSM_CON_CNP_FSM_CLK_DIV2_MASK                0x0c
+#define WCD9378_EAR_EAR_CNP_FSM_CON_SCD_FSM_DEGLITCH_SEL_MASK            0x03
+
+/* WCD9378_EAR_TEST_CTL Fields: */
+#define WCD9378_EAR_TEST_CTL_DTEST_EN_MASK                               0x80
+#define WCD9378_EAR_TEST_CTL_DTEST_SEL_2_MASK                            0x40
+#define WCD9378_EAR_TEST_CTL_EAR_RDAC_ATEST_EN_MASK                      0x20
+#define WCD9378_EAR_TEST_CTL_EAR_PA_ATEST_SEL_MASK                       0x1f
+
+/* WCD9378_EAR_STATUS_REG_1 Fields: */
+#define WCD9378_EAR_STATUS_REG_1_SP_INT_MASK                             0x80
+#define WCD9378_EAR_STATUS_REG_1_SP_ALL_OUT_MASK                         0x40
+#define WCD9378_EAR_STATUS_REG_1_SP_NMOS_OUT_MASK                        0x20
+#define WCD9378_EAR_STATUS_REG_1_SP_PMOS_OUT_MASK                        0x10
+#define WCD9378_EAR_STATUS_REG_1_PA_READY_MASK                           0x08
+#define WCD9378_EAR_STATUS_REG_1_CNP_FSM_STATUS_MASK                     0x04
+
+/* WCD9378_EAR_STATUS_REG_2 Fields: */
+#define WCD9378_EAR_STATUS_REG_2_PA_EN_MASK                              0x80
+#define WCD9378_EAR_STATUS_REG_2_BIAS_EN_MASK                            0x40
+#define WCD9378_EAR_STATUS_REG_2_DAC_EN_MASK                             0x20
+#define WCD9378_EAR_STATUS_REG_2_VCM_EN_MASK                             0x10
+#define WCD9378_EAR_STATUS_REG_2_CLK_EN_MASK                             0x08
+#define WCD9378_EAR_STATUS_REG_2_SCD_EN_MASK                             0x04
+#define WCD9378_EAR_STATUS_REG_2_SHORT_EN_MASK                           0x02
+#define WCD9378_EAR_STATUS_REG_2_DAC_RESET_MASK                          0x01
+
+/* WCD9378_A_PAGE Fields: */
+#define WCD9378_A_PAGE_VALUE_MASK                                        0xff
+
+/* WCD9378_HPH_NEW_ANA_HPH2 Fields: */
+#define WCD9378_HPH_NEW_ANA_HPH2_LP_PWR_CTL_MASK                         0xc0
+#define WCD9378_HPH_NEW_ANA_HPH2_SPARE_BITS_MASK                         0x3f
+
+/* WCD9378_HPH_NEW_ANA_HPH3 Fields: */
+#define WCD9378_HPH_NEW_ANA_HPH3_SPARE_BITS_MASK                         0xff
+
+/* WCD9378_SLEEP_CTL Fields: */
+#define WCD9378_SLEEP_CTL_BG_EN_MASK                                     0x80
+#define WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK                               0x40
+#define WCD9378_SLEEP_CTL_LDORT_REF_SEL_MASK                             0x30
+#define WCD9378_SLEEP_CTL_BG_CTL_MASK                                    0x0e
+#define WCD9378_SLEEP_CTL_DUALVIO_DTEST_EN_MASK                          0x01
+
+/* WCD9378_SLEEP_WATCHDOG_CTL Fields: */
+#define WCD9378_SLEEP_WATCHDOG_CTL_EN_WATCHDOG_MASK                      0x80
+#define WCD9378_SLEEP_WATCHDOG_CTL_EN_WATCHDOG_VREFGEN_MASK              0x40
+#define WCD9378_SLEEP_WATCHDOG_CTL_BYPASS_WATCHDOG_MASK                  0x20
+#define WCD9378_SLEEP_WATCHDOG_CTL_ATEST_CTL_MASK                        0x1c
+
+/* WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL Fields: */
+#define WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL_FSM_ELECT_CLAMP_EN_MASK     0x80
+#define WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL_SLNQ_ELECT_CLAMP_EN_MASK    0x40
+#define WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL_SLNQ_FAIL_CLAMP_EN_MASK     0x20
+#define WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL_SLNQ_ELECT_REM_RST_MASK     0x10
+
+/* WCD9378_MBHC_NEW_CTL_1 Fields: */
+#define WCD9378_MBHC_NEW_CTL_1_RCO_EN_MASK                               0x80
+#define WCD9378_MBHC_NEW_CTL_1_ADC_MODE_MASK                             0x40
+#define WCD9378_MBHC_NEW_CTL_1_DETECTION_DONE_MASK                       0x20
+#define WCD9378_MBHC_NEW_CTL_1_ADC_ENABLE_MASK                           0x10
+#define WCD9378_MBHC_NEW_CTL_1_BTN_DBNC_CTL_MASK                         0x0f
+
+/* WCD9378_MBHC_NEW_CTL_2 Fields: */
+#define WCD9378_MBHC_NEW_CTL_2_MUX_CTL_MASK                              0x70
+#define WCD9378_MBHC_NEW_CTL_2_M_RTH_CTL_MASK                            0x0c
+#define WCD9378_MBHC_NEW_CTL_2_HS_VREF_CTL_MASK                          0x03
+
+/* WCD9378_MBHC_NEW_PLUG_DETECT_CTL Fields: */
+#define WCD9378_MBHC_NEW_PLUG_DETECT_CTL_SPARE_BITS_7_6_MASK             0xc0
+#define WCD9378_MBHC_NEW_PLUG_DETECT_CTL_MIC_CLAMP_CTL_MASK              0x30
+#define WCD9378_MBHC_NEW_PLUG_DETECT_CTL_INSREM_DBNC_CTL_MASK            0x0f
+
+/* WCD9378_MBHC_NEW_ZDET_ANA_CTL Fields: */
+#define WCD9378_MBHC_NEW_ZDET_ANA_CTL_AVERAGING_EN_MASK                  0x80
+#define WCD9378_MBHC_NEW_ZDET_ANA_CTL_ZDET_MAXV_CTL_MASK                 0x70
+#define WCD9378_MBHC_NEW_ZDET_ANA_CTL_ZDET_RANGE_CTL_MASK                0x0f
+
+/* WCD9378_MBHC_NEW_ZDET_RAMP_CTL Fields: */
+#define WCD9378_MBHC_NEW_ZDET_RAMP_CTL_ZDET_RAMP_TIME_CTL_MASK           0x0f
+
+/* WCD9378_MBHC_NEW_FSM_STATUS Fields: */
+#define WCD9378_MBHC_NEW_FSM_STATUS_ADC_TIMEOUT_MASK                     0x80
+#define WCD9378_MBHC_NEW_FSM_STATUS_ADC_COMPLETE_MASK                    0x40
+#define WCD9378_MBHC_NEW_FSM_STATUS_HS_M_COMP_STATUS_MASK                0x20
+#define WCD9378_MBHC_NEW_FSM_STATUS_FAST_PRESS_FLAG_STATUS_MASK          0x10
+#define WCD9378_MBHC_NEW_FSM_STATUS_FAST_REMOVAL_FLAG_STATUS_MASK        0x08
+#define WCD9378_MBHC_NEW_FSM_STATUS_REMOVAL_FLAG_STATUS_MASK             0x04
+#define WCD9378_MBHC_NEW_FSM_STATUS_ELECT_REM_RT_STATUS_MASK             0x02
+#define WCD9378_MBHC_NEW_FSM_STATUS_BTN_STATUS_MASK                      0x01
+
+/* WCD9378_MBHC_NEW_ADC_RESULT Fields: */
+#define WCD9378_MBHC_NEW_ADC_RESULT_ADC_RESULT_MASK                      0xff
+
+/* WCD9378_AUX_AUXPA Fields: */
+#define WCD9378_AUX_AUXPA_AUX_PA_EN_MASK                                 0x80
+#define WCD9378_AUX_AUXPA_AUX_PA_SHORT_PROT_EN_MASK                      0x40
+#define WCD9378_AUX_AUXPA_AUX_PA_OUT_IMP_MASK                            0x20
+#define WCD9378_AUX_AUXPA_AUX_PA_CLK_SEL_MASK                            0x10
+
+/* WCD9378_DIE_CRACK_DIE_CRK_DET_EN Fields: */
+#define WCD9378_DIE_CRACK_DIE_CRK_DET_EN_DIE_CRK_DET_EN_MASK             0x80
+#define WCD9378_DIE_CRACK_DIE_CRK_DET_EN_SEL_CURR_INJCT_PT_MRING_MASK    0x40
+
+/* WCD9378_DIE_CRACK_DIE_CRK_DET_OUT Fields: */
+#define WCD9378_DIE_CRACK_DIE_CRK_DET_OUT_DIE_CRK_DET_OUT_MASK           0x80
+
+/* WCD9378_TX_NEW_TX_CH12_MUX Fields: */
+#define WCD9378_TX_NEW_TX_CH12_MUX_SPARE_BITS_MASK                       0x80
+#define WCD9378_TX_NEW_TX_CH12_MUX_SYS_USAGE_BYP_MASK                    0x40
+#define WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK                          0x38
+#define WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_MASK                          0x07
+
+/* WCD9378_TX_NEW_TX_CH34_MUX Fields: */
+#define WCD9378_TX_NEW_TX_CH34_MUX_SPARE_BITS_MASK                       0xf8
+#define WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_MASK                          0x07
+
+/* WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL Fields: */
+#define WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK              0xf0
+#define WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_REFBUF_CMFB2_ZERO_PROG_MASK    0x08
+#define WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_SPARE_BITS_MASK                0x07
+
+/* WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L Fields: */
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_EN_HD2_RES_DIV_L_MASK         0x80
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_PULLGND_L_MASK    0x40
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_SPARE_BITS_MASK               0x20
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_SELECT_HD2_RES_DIV_L_MASK     0x10
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK        0x0f
+
+/* WCD9378_HPH_NEW_INT_RDAC_VREF_CTL Fields: */
+#define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL_EN_REFCURRENT_RDEG_SHORT_MASK  0x80
+#define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL_RDAC_REFBUF_RFB_9K_MASK        0x40
+#define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL_LP_RDAC_REFBUF_RFB_CTL_MASK    0x30
+#define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL_RDAC_REFCURRENT_IREF_2UA_MASK  0x08
+#define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL_SPARE_BITS_MASK                0x07
+
+/* WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL Fields: */
+#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL_REFBUF_RFB_OVRIDE_MASK     0x80
+#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL_REFBUF_IREF_OVRIDE_MASK    0x40
+#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL_REFCURRENT_RDEG_CTL_OVRIDE_MASK 0x20
+#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL_REFBUF_CMFB2_ZERO_OVRIDE_MASK 0x10
+#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL_RDAC_IDLE_DETECT_OVERRIDE_MASK 0x08
+#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL_SPARE_BITS_MASK            0x07
+
+/* WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R Fields: */
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_EN_HD2_RES_DIV_R_MASK         0x80
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_PULLGND_R_MASK    0x40
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_SPARE_BITS_MASK               0x20
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_SELECT_HD2_RES_DIV_R_MASK     0x10
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK        0x0f
+
+/* WCD9378_HPH_NEW_INT_PA_MISC1 Fields: */
+#define WCD9378_HPH_NEW_INT_PA_MISC1_EN_AUTO_CMPDR_DETECTION_MASK        0x80
+#define WCD9378_HPH_NEW_INT_PA_MISC1_EN_PA_IDLE_DETECT_OVERRIDE_MASK     0x40
+#define WCD9378_HPH_NEW_INT_PA_MISC1_D_PZ_INF_EN_MASK                    0x20
+#define WCD9378_HPH_NEW_INT_PA_MISC1_SPARE_BITS_MASK                     0x18
+#define WCD9378_HPH_NEW_INT_PA_MISC1_PA_CHOP_EN_OVERRIDE_MASK            0x04
+#define WCD9378_HPH_NEW_INT_PA_MISC1_OCP_FSM_LOCK_EN_MASK                0x02
+#define WCD9378_HPH_NEW_INT_PA_MISC1_AUTOCHOP_PDN_SEQ_OVERRIDE_MASK      0x01
+
+/* WCD9378_HPH_NEW_INT_PA_MISC2 Fields: */
+#define WCD9378_HPH_NEW_INT_PA_MISC2_HPHPA_HI_Z_MASK                     0x80
+#define WCD9378_HPH_NEW_INT_PA_MISC2_HPH_PSRR_ENH_MASK                   0x40
+#define WCD9378_HPH_NEW_INT_PA_MISC2_FORCE_IQCTRL_MASK                   0x20
+#define WCD9378_HPH_NEW_INT_PA_MISC2_FORCE_PSRREH_MASK                   0x10
+#define WCD9378_HPH_NEW_INT_PA_MISC2_CHOP_CLKLAP_SEL_MASK                0x08
+#define WCD9378_HPH_NEW_INT_PA_MISC2_SPARE_BITS_MASK                     0x04
+#define WCD9378_HPH_NEW_INT_PA_MISC2_IDLE_DETECT_L_DTEST_ENABLE_MASK     0x02
+#define WCD9378_HPH_NEW_INT_PA_MISC2_IDLE_DETECT_R_DTEST_ENABLE_MASK     0x01
+
+/* WCD9378_HPH_NEW_INT_PA_RDAC_MISC Fields: */
+#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC_CNP_WG_FINE_TIME_LSB_CTL_MASK   0xf0
+#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC_SPARE_BITS_MASK                 0x0c
+#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC_RDAC_PSW_REG_CTL_MASK           0x03
+
+/* WCD9378_HPH_NEW_INT_HPH_TIMER1 Fields: */
+#define WCD9378_HPH_NEW_INT_HPH_TIMER1_CURR_IDIV_CTL_CMPDR_OFF_MASK      0xe0
+#define WCD9378_HPH_NEW_INT_HPH_TIMER1_CURR_IDIV_CTL_AUTOCHOP_MASK       0x1c
+#define WCD9378_HPH_NEW_INT_HPH_TIMER1_AUTOCHOP_TIMER_CTL_EN_MASK        0x02
+#define WCD9378_HPH_NEW_INT_HPH_TIMER1_SPARE_BITS_MASK                   0x01
+
+/* WCD9378_HPH_NEW_INT_HPH_TIMER2 Fields: */
+#define WCD9378_HPH_NEW_INT_HPH_TIMER2_VREF_TIMER_IDLESTATE_MASK         0xe0
+#define WCD9378_HPH_NEW_INT_HPH_TIMER2_CNP_WG_FINE_TIME_LSB_CTL_IDLE_MASK 0x1e
+#define WCD9378_HPH_NEW_INT_HPH_TIMER2_SPARE_BITS_MASK                   0x01
+
+/* WCD9378_HPH_NEW_INT_HPH_TIMER3 Fields: */
+#define WCD9378_HPH_NEW_INT_HPH_TIMER3_WG_FINE_TIMER_CMPDR_OFF_MASK      0xff
+
+/* WCD9378_HPH_NEW_INT_HPH_TIMER4 Fields: */
+#define WCD9378_HPH_NEW_INT_HPH_TIMER4_WG_FINE_TIMER_AUTOCHOP_MASK       0xff
+
+/* WCD9378_HPH_NEW_INT_PA_RDAC_MISC2 Fields: */
+#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC2_SPARE_BITS_MASK                0xff
+
+/* WCD9378_HPH_NEW_INT_PA_RDAC_MISC3 Fields: */
+#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC3_SPARE_BITS_MASK                0xff
+
+/* WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI Fields: */
+#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI_HPHPA_BIAS_LOHIFI_MASK   0xf0
+#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI_HPHRDAC_BIAS_LOHIFI_MASK 0x0f
+
+/* WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP Fields: */
+#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP_SPARE_BITS_MASK             0xf0
+#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP_HPHRDAC_BIAS_ULP_MASK       0x0f
+
+/* WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP Fields: */
+#define WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP_HPHRDAC_1P6VLDO_BIAS_LP_MASK  0xf0
+#define WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP_HPHRDAC_N1P6VLDO_BIAS_LP_MASK 0x0f
+
+/* WCD9378_CP_CLASSG_CP_CTRL_0 Fields: */
+#define WCD9378_CP_CLASSG_CP_CTRL_0_DIS_CP_LDO_MASK                      0x10
+#define WCD9378_CP_CLASSG_CP_CTRL_0_EN_VPOS_CMP_MASK                     0x08
+#define WCD9378_CP_CLASSG_CP_CTRL_0_EN_VPOS_CMP_OV_MASK                  0x04
+#define WCD9378_CP_CLASSG_CP_CTRL_0_EN_CP_VAL_MASK                       0x02
+#define WCD9378_CP_CLASSG_CP_CTRL_0_EN_CP_OV_MASK                        0x01
+
+/* WCD9378_CP_CLASSG_CP_CTRL_1 Fields: */
+#define WCD9378_CP_CLASSG_CP_CTRL_1_TNOV_SEL_MASK                        0x01
+
+/* WCD9378_CP_CLASSG_CP_CTRL_2 Fields: */
+#define WCD9378_CP_CLASSG_CP_CTRL_2_IB_LDO_SEL_MASK                      0xc0
+#define WCD9378_CP_CLASSG_CP_CTRL_2_VGN_LDO_SEL_MASK                     0x3c
+#define WCD9378_CP_CLASSG_CP_CTRL_2_SW_SIZE_MASK                         0x03
+
+/* WCD9378_CP_CLASSG_CP_CTRL_3 Fields: */
+#define WCD9378_CP_CLASSG_CP_CTRL_3_IB_CMP_SEL_MASK                      0x60
+#define WCD9378_CP_CLASSG_CP_CTRL_3_VHYST_CMP_SEL_MASK                   0x18
+#define WCD9378_CP_CLASSG_CP_CTRL_3_VTH_CMP_SEL_MASK                     0x07
+
+/* WCD9378_CP_CLASSG_CP_CTRL_4 Fields: */
+#define WCD9378_CP_CLASSG_CP_CTRL_4_DTEST_EN_MASK                        0x80
+#define WCD9378_CP_CLASSG_CP_CTRL_4_DTEST_SEL_MASK                       0x70
+#define WCD9378_CP_CLASSG_CP_CTRL_4_ATEST_EN_MASK                        0x08
+#define WCD9378_CP_CLASSG_CP_CTRL_4_ATEST_SEL_MASK                       0x07
+
+/* WCD9378_CP_CLASSG_CP_CTRL_5 Fields: */
+#define WCD9378_CP_CLASSG_CP_CTRL_5_VPOS_FILT_RSEL_MASK                  0x0c
+#define WCD9378_CP_CLASSG_CP_CTRL_5_VDD_CP_LPF_R_SEL_MASK                0x03
+
+/* WCD9378_CP_CLASSG_CP_CTRL_6 Fields: */
+#define WCD9378_CP_CLASSG_CP_CTRL_6_SPARE_BITS_7_0_MASK                  0xff
+
+/* WCD9378_CP_CLASSG_CP_CTRL_7 Fields: */
+#define WCD9378_CP_CLASSG_CP_CTRL_7_SPARE_BITS_7_0_MASK                  0xff
+
+/* WCD9378_CP_VNEGDAC_CTRL_0 Fields: */
+#define WCD9378_CP_VNEGDAC_CTRL_0_IB_LDO_SEL_MASK                        0xc0
+#define WCD9378_CP_VNEGDAC_CTRL_0_VGN_LDO_SEL_MASK                       0x3c
+#define WCD9378_CP_VNEGDAC_CTRL_0_SW_SIZE_MASK                           0x03
+
+/* WCD9378_CP_VNEGDAC_CTRL_1 Fields: */
+#define WCD9378_CP_VNEGDAC_CTRL_1_TNOV_SEL_NCP_MASK                      0x01
+
+/* WCD9378_CP_VNEGDAC_CTRL_2 Fields: */
+#define WCD9378_CP_VNEGDAC_CTRL_2_SPARE_BITS_7_0_MASK                    0xff
+
+/* WCD9378_CP_VNEGDAC_CTRL_3 Fields: */
+#define WCD9378_CP_VNEGDAC_CTRL_3_SPARE_BITS_7_0_MASK                    0xff
+
+/* WCD9378_CP_CP_DTOP_CTRL_0 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_0_SWR_CLK_RATE_MASK                      0x80
+#define WCD9378_CP_CP_DTOP_CTRL_0_CP_CLK_EDGE_SEL_MASK                   0x40
+#define WCD9378_CP_CP_DTOP_CTRL_0_TEST_INT_CLK_MASK                      0x20
+#define WCD9378_CP_CP_DTOP_CTRL_0_NCP_CLK_EDGE_SEL_MASK                  0x10
+#define WCD9378_CP_CP_DTOP_CTRL_0_NCP_TEST_INT_CLK_MASK                  0x08
+#define WCD9378_CP_CP_DTOP_CTRL_0_OVERRIDE_SWR_CLK_RATE_MASK             0x04
+
+/* WCD9378_CP_CP_DTOP_CTRL_1 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_1_VTH_1_SEL_MASK                         0x38
+#define WCD9378_CP_CP_DTOP_CTRL_1_VTH_0_SEL_MASK                         0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_2 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_2_VTH_3_SEL_MASK                         0x38
+#define WCD9378_CP_CP_DTOP_CTRL_2_VTH_2_SEL_MASK                         0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_3 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_3_VTH_5_SEL_MASK                         0x38
+#define WCD9378_CP_CP_DTOP_CTRL_3_VTH_4_SEL_MASK                         0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_4 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_4_VTH_7_SEL_MASK                         0x38
+#define WCD9378_CP_CP_DTOP_CTRL_4_VTH_6_SEL_MASK                         0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_5 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_5_VTH_9_SEL_MASK                         0x38
+#define WCD9378_CP_CP_DTOP_CTRL_5_VTH_8_SEL_MASK                         0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_6 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_6_VTH_11_SEL_MASK                        0x38
+#define WCD9378_CP_CP_DTOP_CTRL_6_VTH_10_SEL_MASK                        0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_7 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_7_VTH_12_SEL_MASK                        0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_8 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_8_TPW_G0P5_PH1_SEL_MASK                  0xf0
+#define WCD9378_CP_CP_DTOP_CTRL_8_TPW_G0P5_PH2_SEL_MASK                  0x0f
+
+/* WCD9378_CP_CP_DTOP_CTRL_9 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_9_TPW_G1_PH1_SEL_MASK                    0xf0
+#define WCD9378_CP_CP_DTOP_CTRL_9_DISABLE_TWAIT_MASK                     0x08
+#define WCD9378_CP_CP_DTOP_CTRL_9_TWAIT_G1_STEP3_MASK                    0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_10 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_10_TWAIT_G1_STEP2_MASK                   0x38
+#define WCD9378_CP_CP_DTOP_CTRL_10_TWAIT_G1_STEP1_MASK                   0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_11 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_11_TWAIT_G0P5_STEP3_MASK                 0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_12 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_12_TWAIT_G0P5_STEP2_MASK                 0x38
+#define WCD9378_CP_CP_DTOP_CTRL_12_TWAIT_G0P5_STEP1_MASK                 0x07
+
+/* WCD9378_CP_CP_DTOP_CTRL_13 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_13_INVERT_CP_CLKS_MASK                   0x80
+#define WCD9378_CP_CP_DTOP_CTRL_13_GATE_OFF_S10P_MASK                    0x40
+#define WCD9378_CP_CP_DTOP_CTRL_13_GATE_OFF_S6P_MASK                     0x20
+#define WCD9378_CP_CP_DTOP_CTRL_13_GATE_OFF_S5N_MASK                     0x10
+#define WCD9378_CP_CP_DTOP_CTRL_13_GATE_OFF_S4N_MASK                     0x08
+#define WCD9378_CP_CP_DTOP_CTRL_13_GATE_OFF_S3P_MASK                     0x04
+#define WCD9378_CP_CP_DTOP_CTRL_13_GATE_OFF_S2N_MASK                     0x02
+#define WCD9378_CP_CP_DTOP_CTRL_13_GATE_OFF_S1P_MASK                     0x01
+
+/* WCD9378_CP_CP_DTOP_CTRL_14 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK                    0x80
+#define WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_FSW_VAL_MASK                 0x78
+#define WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_FSW_MASK                     0x04
+#define WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_G_VAL_MASK                   0x02
+#define WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_G_MASK                       0x01
+
+/* WCD9378_CP_CP_DTOP_CTRL_15 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_15_OVERRIDE_VREF_VAL_MASK                0xff
+
+/* WCD9378_CP_CP_DTOP_CTRL_16 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_16_OVERRIDE_SWSIZE_VAL_MASK              0x06
+#define WCD9378_CP_CP_DTOP_CTRL_16_OVERRIDE_SWSIZE_MASK                  0x01
+
+/* WCD9378_CP_CP_DTOP_CTRL_17 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_17_TPW_PH1_SEL_MASK                      0x0f
+
+/* WCD9378_CP_CP_DTOP_CTRL_18 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_18_OVERRIDE_NCP_FSW_VAL_MASK             0x78
+#define WCD9378_CP_CP_DTOP_CTRL_18_OVERRIDE_NCP_FSW_MASK                 0x04
+#define WCD9378_CP_CP_DTOP_CTRL_18_INVERT_CLKS_MASK                      0x02
+#define WCD9378_CP_CP_DTOP_CTRL_18_GATE_OFF_NCP_CLK_MASK                 0x01
+
+/* WCD9378_CP_CP_DTOP_CTRL_19 Fields: */
+#define WCD9378_CP_CP_DTOP_CTRL_19_SPARE_BITS_7_0_MASK                   0xff
+
+/* WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL Fields: */
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL_ONCOUNT_MASK           0x60
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL_OFFCOUNT_MASK          0x1f
+
+/* WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL Fields: */
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL_HPHL_PA_EN_MASK   0x40
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL_DTEST_EN_MASK     0x30
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL_MOISTURE_OVRD_POLLING_MASK 0x08
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL_MOISTURE_EN_POLLING_MASK 0x04
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL_MOISTURE_DBNC_TIME_MASK 0x03
+
+/* WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT Fields: */
+#define WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT_HSDET_PULLUP_CTL_MASK      0x1f
+
+/* WCD9378_MBHC_NEW_INT_SPARE_2 Fields: */
+#define WCD9378_MBHC_NEW_INT_SPARE_2_ZDET_TIMER_MASK                     0x80
+#define WCD9378_MBHC_NEW_INT_SPARE_2_SPARE_BITS_6_0_MASK                 0x7f
+
+/* WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON Fields: */
+#define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON_EAR_CHOPPER_EN_MASK          0x80
+#define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_DIV_MASK     0x78
+#define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_INV_MASK     0x04
+#define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_OVERLAP_MASK 0x02
+#define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON_SCD_SHTDWN_FAST_PATH_DIS_MASK 0x01
+
+/* WCD9378_EAR_INT_NEW_CNP_VCM_CON1 Fields: */
+#define WCD9378_EAR_INT_NEW_CNP_VCM_CON1_SCD_EN_TIME_SEL_MASK            0x80
+#define WCD9378_EAR_INT_NEW_CNP_VCM_CON1_NO_DYN_BIAS_DURING_STARTUP_MASK 0x40
+#define WCD9378_EAR_INT_NEW_CNP_VCM_CON1_CNP_VCM_GEN_START_MASK          0x3f
+
+/* WCD9378_EAR_INT_NEW_CNP_VCM_CON2 Fields: */
+#define WCD9378_EAR_INT_NEW_CNP_VCM_CON2_DTEST_SEL_MASK                  0xc0
+#define WCD9378_EAR_INT_NEW_CNP_VCM_CON2_CNP_VCM_GEN_STOP_MASK           0x3f
+
+/* WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS Fields: */
+#define WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS_EAR_DYN_BIAS_SEL_MASK       0xe0
+#define WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS_EAR_BIAS_CURR_MASK          0x1f
+
+/* WCD9378_AUX_INT_EN_REG Fields: */
+#define WCD9378_AUX_INT_EN_REG_DAC_DATA_RESET_MASK                       0x80
+#define WCD9378_AUX_INT_EN_REG_DAC_DATA_EN_MASK                          0x40
+#define WCD9378_AUX_INT_EN_REG_DAC_REF_EN_MASK                           0x20
+#define WCD9378_AUX_INT_EN_REG_AMP_EN_MASK                               0x10
+#define WCD9378_AUX_INT_EN_REG_BIAS_EN_MASK                              0x08
+#define WCD9378_AUX_INT_EN_REG_OUTPUT_SHORT_MASK                         0x04
+#define WCD9378_AUX_INT_EN_REG_CNP_FSM_RESET_MASK                        0x02
+#define WCD9378_AUX_INT_EN_REG_REG_OVERRIDE_EN_MASK                      0x01
+
+/* WCD9378_AUX_INT_PA_CTRL Fields: */
+#define WCD9378_AUX_INT_PA_CTRL_SPARE_BITS_7_6_MASK                      0xc0
+#define WCD9378_AUX_INT_PA_CTRL_CMFB_LSF_CURR_MASK                       0x20
+#define WCD9378_AUX_INT_PA_CTRL_BTI_CTL_MASK                             0x10
+#define WCD9378_AUX_INT_PA_CTRL_GM3_IBIAS_CTL_MASK                       0x0f
+
+/* WCD9378_AUX_INT_SP_CTRL Fields: */
+#define WCD9378_AUX_INT_SP_CTRL_SP_INT_EN_MASK                           0x80
+#define WCD9378_AUX_INT_SP_CTRL_SP_AUTO_SHUT_DOWN_MASK                   0x40
+#define WCD9378_AUX_INT_SP_CTRL_SP_LIMIT_CURR_NMOS_MASK                  0x38
+#define WCD9378_AUX_INT_SP_CTRL_SP_LIMIT_CURR_PMOS_MASK                  0x07
+
+/* WCD9378_AUX_INT_DAC_CTRL Fields: */
+#define WCD9378_AUX_INT_DAC_CTRL_DAC_SAMPLE_EDGE_SEL_MASK                0x80
+#define WCD9378_AUX_INT_DAC_CTRL_REF_DBG_EN_MASK                         0x40
+#define WCD9378_AUX_INT_DAC_CTRL_REF_DBG_GAIN_MASK                       0x38
+#define WCD9378_AUX_INT_DAC_CTRL_GAIN_DAC_MASK                           0x06
+#define WCD9378_AUX_INT_DAC_CTRL_INV_DATA_MASK                           0x01
+
+/* WCD9378_AUX_INT_CLK_CTRL Fields: */
+#define WCD9378_AUX_INT_CLK_CTRL_GNDSW_TIMER_MASK                        0xe0
+#define WCD9378_AUX_INT_CLK_CTRL_SCD_DEGLITCH_SEL_MASK                   0x18
+#define WCD9378_AUX_INT_CLK_CTRL_SPARE_BITS_2_0_MASK                     0x07
+
+/* WCD9378_AUX_INT_TEST_CTRL Fields: */
+#define WCD9378_AUX_INT_TEST_CTRL_SPARE_BITS_7_5_MASK                    0xe0
+#define WCD9378_AUX_INT_TEST_CTRL_DAC_ATEST_EN_MASK                      0x10
+#define WCD9378_AUX_INT_TEST_CTRL_PA_ATEST_EN_MASK                       0x08
+#define WCD9378_AUX_INT_TEST_CTRL_PA_ATEST_SEL_MASK                      0x07
+
+/* WCD9378_AUX_INT_STATUS_REG Fields: */
+#define WCD9378_AUX_INT_STATUS_REG_SP_INT_MASK                           0x80
+#define WCD9378_AUX_INT_STATUS_REG_SP_OUT_MASK                           0x40
+#define WCD9378_AUX_INT_STATUS_REG_SP_NMOS_OUT_MASK                      0x20
+#define WCD9378_AUX_INT_STATUS_REG_SP_PMOS_OUT_MASK                      0x10
+#define WCD9378_AUX_INT_STATUS_REG_PA_READY_MASK                         0x08
+#define WCD9378_AUX_INT_STATUS_REG_SPARE_BITS_2_0_MASK                   0x07
+
+/* WCD9378_AUX_INT_MISC Fields: */
+#define WCD9378_AUX_INT_MISC_SPARE_BITS_7_4_MASK                         0xf0
+#define WCD9378_AUX_INT_MISC_PA_GAIN_MASK                                0x0f
+
+/* WCD9378_SLEEP_INT_WATCHDOG_CTL_1 Fields: */
+#define WCD9378_SLEEP_INT_WATCHDOG_CTL_1_VREF_HI_CTL_MASK                0x1f
+
+/* WCD9378_SLEEP_INT_WATCHDOG_CTL_2 Fields: */
+#define WCD9378_SLEEP_INT_WATCHDOG_CTL_2_VREF_LO_CTL_MASK                0x1f
+
+/* WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1 Fields: */
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1_SEL_EDGE_DET_MASK         0xc0
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1_EN_RINGM_ATEST_MASK       0x20
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1_EN_RINGP_ATEST_MASK       0x10
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1_RING_CURR_SEL_MASK        0x0e
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1_EN_VREF_ATEST_MASK        0x01
+
+/* WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2 Fields: */
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2_REF_CURR_SEL_MASK         0xe0
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2_COMP_STG1_IBIAS_MASK      0x18
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2_COMP_STG2_IBIAS_MASK      0x06
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2_EN_ATEST_MASK             0x01
+
+/* WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2_DIV_L2_MASK               0xff
+
+/* WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1_DIV_L1_MASK               0xff
+
+/* WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0_DIV_L0_MASK               0xff
+
+/* WCD9378_TX_COM_NEW_INT_SPARE1 Fields: */
+#define WCD9378_TX_COM_NEW_INT_SPARE1_SPARE_BITS_7_0_MASK                0xff
+
+/* WCD9378_TX_COM_NEW_INT_SPARE2 Fields: */
+#define WCD9378_TX_COM_NEW_INT_SPARE2_SPARE_BITS_7_0_MASK                0xff
+
+/* WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2_NINIT_L2_MASK               0xc0
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2_SPARE_BITS_4_0_MASK         0x1f
+
+/* WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1_NINIT_L1_MASK               0xc0
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1_SPARE_BITS_4_0_MASK         0x1f
+
+/* WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0_NINIT_L0_MASK               0xc0
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0_SPARE_BITS_4_0_MASK         0x1f
+
+/* WCD9378_TX_COM_NEW_INT_SPARE3 Fields: */
+#define WCD9378_TX_COM_NEW_INT_SPARE3_SPARE_BITS_7_0_MASK                0xff
+
+/* WCD9378_TX_COM_NEW_INT_SPARE4 Fields: */
+#define WCD9378_TX_COM_NEW_INT_SPARE4_SPARE_BITS_7_0_MASK                0xff
+
+/* WCD9378_TX_COM_NEW_INT_SPARE5 Fields: */
+#define WCD9378_TX_COM_NEW_INT_SPARE5_SPARE_BITS_7_0_MASK                0xff
+
+/* WCD9378_TX_COM_NEW_INT_SPARE6 Fields: */
+#define WCD9378_TX_COM_NEW_INT_SPARE6_SPARE_BITS_7_0_MASK                0xff
+
+/* WCD9378_TX_COM_NEW_INT_SPARE7 Fields: */
+#define WCD9378_TX_COM_NEW_INT_SPARE7_SPARE_BITS_7_0_MASK                0xff
+
+/* WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1_ICTRL_SCBIAS_L2_MASK    0xf0
+#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1_ICTRL_SCBIAS_L1_MASK    0x0f
+
+/* WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0_ICTRL_SCBIAS_L0_MASK      0xf0
+#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0_SPARE_BITS_3_0_MASK       0x0f
+
+/* WCD9378_TX_COM_NEW_INT_TXADC_INT_L2 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L2_INT1_L2_MASK                 0xf0
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L2_INT2_L2_MASK                 0x0f
+
+/* WCD9378_TX_COM_NEW_INT_TXADC_INT_L1 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L1_INT1_L1_MASK                 0xf0
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L1_INT2_L1_MASK                 0x0f
+
+/* WCD9378_TX_COM_NEW_INT_TXADC_INT_L0 Fields: */
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L0_INT1_L0_MASK                 0xf0
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L0_INT2_L0_MASK                 0x0f
+
+/* WCD9378_TX_COM_NEW_INT_SPARE8 Fields: */
+#define WCD9378_TX_COM_NEW_INT_SPARE8_SPARE_BITS_7_0_MASK                0xff
+
+
+/* WCD9378_TAMBORA_PAGE Fields: */
+#define WCD9378_TAMBORA_PAGE_PAG_REG_MASK                                0xff
+
+/* WCD9378_CHIP_ID0 Fields: */
+#define WCD9378_CHIP_ID0_BYTE_0_MASK                                     0xff
+
+/* WCD9378_CHIP_ID1 Fields: */
+#define WCD9378_CHIP_ID1_BYTE_1_MASK                                     0xff
+
+/* WCD9378_CHIP_ID2 Fields: */
+#define WCD9378_CHIP_ID2_BYTE_2_MASK                                     0xff
+
+/* WCD9378_CHIP_ID3 Fields: */
+#define WCD9378_CHIP_ID3_BYTE_3_MASK                                     0xff
+
+/* WCD9378_SWR_TX_CLK_RATE Fields: */
+#define WCD9378_SWR_TX_CLK_RATE_CLK_RATE_BK_1_MASK                       0xf0
+#define WCD9378_SWR_TX_CLK_RATE_CLK_RATE_BK_0_MASK                       0x0f
+
+/* WCD9378_CDC_RST_CTL Fields: */
+#define WCD9378_CDC_RST_CTL_ANA_SW_RST_N_MASK                            0x02
+#define WCD9378_CDC_RST_CTL_DIG_SW_RST_N_MASK                            0x01
+
+/* WCD9378_TOP_CLK_CFG Fields: */
+#define WCD9378_TOP_CLK_CFG_RX_CLK_CFG_MASK                              0x06
+#define WCD9378_TOP_CLK_CFG_TX_CLK_CFG_MASK                              0x01
+
+/* WCD9378_CDC_ANA_CLK_CTL Fields: */
+#define WCD9378_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN_MASK                  0x04
+#define WCD9378_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN_MASK                  0x02
+#define WCD9378_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN_MASK                       0x01
+
+/* WCD9378_CDC_DIG_CLK_CTL Fields: */
+#define WCD9378_CDC_DIG_CLK_CTL_TXD2_CLK_EN_MASK                         0x40
+#define WCD9378_CDC_DIG_CLK_CTL_TXD1_CLK_EN_MASK                         0x20
+#define WCD9378_CDC_DIG_CLK_CTL_TXD0_CLK_EN_MASK                         0x10
+#define WCD9378_CDC_DIG_CLK_CTL_RXD2_CLK_EN_MASK                         0x04
+#define WCD9378_CDC_DIG_CLK_CTL_RXD1_CLK_EN_MASK                         0x02
+#define WCD9378_CDC_DIG_CLK_CTL_RXD0_CLK_EN_MASK                         0x01
+
+/* WCD9378_SWR_RST_EN Fields: */
+#define WCD9378_SWR_RST_EN_RX_RESET_SYNC_LOST_EN_MASK                    0x20
+#define WCD9378_SWR_RST_EN_RX_RESET_SWR_BUS_EN_MASK                      0x10
+#define WCD9378_SWR_RST_EN_RX_RESET_SWR_REG_EN_MASK                      0x08
+#define WCD9378_SWR_RST_EN_TX_RESET_SYNC_LOST_EN_MASK                    0x04
+#define WCD9378_SWR_RST_EN_TX_RESET_SWR_BUS_EN_MASK                      0x02
+#define WCD9378_SWR_RST_EN_TX_RESET_SWR_REG_EN_MASK                      0x01
+
+/* WCD9378_CDC_PATH_MODE Fields: */
+#define WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK                          0x40
+
+/* WCD9378_CDC_RX_RST Fields: */
+#define WCD9378_CDC_RX_RST_RX2_SOFT_RST_MASK                             0x04
+#define WCD9378_CDC_RX_RST_RX1_SOFT_RST_MASK                             0x02
+#define WCD9378_CDC_RX_RST_RX0_SOFT_RST_MASK                             0x01
+
+/* WCD9378_CDC_RX0_CTL Fields: */
+#define WCD9378_CDC_RX0_CTL_DSM_DITHER_ENABLE_MASK                       0x80
+#define WCD9378_CDC_RX0_CTL_DEM_DITHER_ENABLE_MASK                       0x40
+#define WCD9378_CDC_RX0_CTL_DEM_MID_ENABLE_MASK                          0x20
+#define WCD9378_CDC_RX0_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_MASK          0x10
+#define WCD9378_CDC_RX0_CTL_DEM_SWITCHING_BLOCK_ENABLE_MASK              0x08
+#define WCD9378_CDC_RX0_CTL_DEM_SEGMENTING_BLOCK_ENABLE_MASK             0x04
+#define WCD9378_CDC_RX0_CTL_DEM_BYPASS_MASK                              0x02
+
+/* WCD9378_CDC_RX1_CTL Fields: */
+#define WCD9378_CDC_RX1_CTL_DSM_DITHER_ENABLE_MASK                       0x80
+#define WCD9378_CDC_RX1_CTL_DEM_DITHER_ENABLE_MASK                       0x40
+#define WCD9378_CDC_RX1_CTL_DEM_MID_ENABLE_MASK                          0x20
+#define WCD9378_CDC_RX1_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_MASK          0x10
+#define WCD9378_CDC_RX1_CTL_DEM_SWITCHING_BLOCK_ENABLE_MASK              0x08
+#define WCD9378_CDC_RX1_CTL_DEM_SEGMENTING_BLOCK_ENABLE_MASK             0x04
+#define WCD9378_CDC_RX1_CTL_DEM_BYPASS_MASK                              0x02
+
+/* WCD9378_CDC_RX2_CTL Fields: */
+#define WCD9378_CDC_RX2_CTL_DSM_DITHER_ENABLE_MASK                       0x80
+#define WCD9378_CDC_RX2_CTL_DEM_DITHER_ENABLE_MASK                       0x40
+#define WCD9378_CDC_RX2_CTL_DEM_MID_ENABLE_MASK                          0x20
+#define WCD9378_CDC_RX2_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_MASK          0x10
+#define WCD9378_CDC_RX2_CTL_DEM_SWITCHING_BLOCK_ENABLE_MASK              0x08
+#define WCD9378_CDC_RX2_CTL_DEM_SEGMENTING_BLOCK_ENABLE_MASK             0x04
+#define WCD9378_CDC_RX2_CTL_DEM_BYPASS_MASK                              0x02
+
+/* WCD9378_CDC_TX_ANA_MODE_0_1 Fields: */
+#define WCD9378_CDC_TX_ANA_MODE_0_1_TXD1_MODE_MASK                       0xf0
+#define WCD9378_CDC_TX_ANA_MODE_0_1_TXD0_MODE_MASK                       0x0f
+
+/* WCD9378_CDC_TX_ANA_MODE_2_3 Fields: */
+#define WCD9378_CDC_TX_ANA_MODE_2_3_TXD2_MODE_MASK                       0x0f
+
+/* WCD9378_CDC_COMP_CTL_0 Fields: */
+#define WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK                          0x04
+#define WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK                         0x02
+#define WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK                         0x01
+
+/* WCD9378_CDC_ANA_TX_CLK_CTL Fields: */
+#define WCD9378_CDC_ANA_TX_CLK_CTL_ANA_TX2_ADC_CLK_EN_MASK               0x08
+#define WCD9378_CDC_ANA_TX_CLK_CTL_ANA_TX1_ADC_CLK_EN_MASK               0x04
+#define WCD9378_CDC_ANA_TX_CLK_CTL_ANA_TX0_ADC_CLK_EN_MASK               0x02
+#define WCD9378_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN_MASK              0x01
+
+/* WCD9378_CDC_HPH_DSM_A1_0 Fields: */
+#define WCD9378_CDC_HPH_DSM_A1_0_COEF_A1_MASK                            0xff
+
+/* WCD9378_CDC_HPH_DSM_A1_1 Fields: */
+#define WCD9378_CDC_HPH_DSM_A1_1_COEF_A1_MASK                            0x01
+
+/* WCD9378_CDC_HPH_DSM_A2_0 Fields: */
+#define WCD9378_CDC_HPH_DSM_A2_0_COEF_A2_MASK                            0xff
+
+/* WCD9378_CDC_HPH_DSM_A2_1 Fields: */
+#define WCD9378_CDC_HPH_DSM_A2_1_COEF_A2_MASK                            0x0f
+
+/* WCD9378_CDC_HPH_DSM_A3_0 Fields: */
+#define WCD9378_CDC_HPH_DSM_A3_0_COEF_A3_MASK                            0xff
+
+/* WCD9378_CDC_HPH_DSM_A3_1 Fields: */
+#define WCD9378_CDC_HPH_DSM_A3_1_COEF_A3_MASK                            0x07
+
+/* WCD9378_CDC_HPH_DSM_A4_0 Fields: */
+#define WCD9378_CDC_HPH_DSM_A4_0_COEF_A4_MASK                            0xff
+
+/* WCD9378_CDC_HPH_DSM_A4_1 Fields: */
+#define WCD9378_CDC_HPH_DSM_A4_1_COEF_A4_MASK                            0x03
+
+/* WCD9378_CDC_HPH_DSM_A5_0 Fields: */
+#define WCD9378_CDC_HPH_DSM_A5_0_COEF_A5_MASK                            0xff
+
+/* WCD9378_CDC_HPH_DSM_A5_1 Fields: */
+#define WCD9378_CDC_HPH_DSM_A5_1_COEF_A5_MASK                            0x03
+
+/* WCD9378_CDC_HPH_DSM_A6_0 Fields: */
+#define WCD9378_CDC_HPH_DSM_A6_0_COEF_A6_MASK                            0xff
+
+/* WCD9378_CDC_HPH_DSM_A7_0 Fields: */
+#define WCD9378_CDC_HPH_DSM_A7_0_COEF_A7_MASK                            0xff
+
+/* WCD9378_CDC_HPH_DSM_C_0 Fields: */
+#define WCD9378_CDC_HPH_DSM_C_0_COEF_C3_MASK                             0xf0
+#define WCD9378_CDC_HPH_DSM_C_0_COEF_C2_MASK                             0x0f
+
+/* WCD9378_CDC_HPH_DSM_C_1 Fields: */
+#define WCD9378_CDC_HPH_DSM_C_1_COEF_C5_MASK                             0xf0
+#define WCD9378_CDC_HPH_DSM_C_1_COEF_C4_MASK                             0x0f
+
+/* WCD9378_CDC_HPH_DSM_C_2 Fields: */
+#define WCD9378_CDC_HPH_DSM_C_2_COEF_C7_MASK                             0xf0
+#define WCD9378_CDC_HPH_DSM_C_2_COEF_C6_MASK                             0x0f
+
+/* WCD9378_CDC_HPH_DSM_C_3 Fields: */
+#define WCD9378_CDC_HPH_DSM_C_3_COEF_C7_MASK                             0x3f
+
+/* WCD9378_CDC_HPH_DSM_R1 Fields: */
+#define WCD9378_CDC_HPH_DSM_R1_SAT_LIMIT_R1_MASK                         0xff
+
+/* WCD9378_CDC_HPH_DSM_R2 Fields: */
+#define WCD9378_CDC_HPH_DSM_R2_SAT_LIMIT_R2_MASK                         0xff
+
+/* WCD9378_CDC_HPH_DSM_R3 Fields: */
+#define WCD9378_CDC_HPH_DSM_R3_SAT_LIMIT_R3_MASK                         0xff
+
+/* WCD9378_CDC_HPH_DSM_R4 Fields: */
+#define WCD9378_CDC_HPH_DSM_R4_SAT_LIMIT_R4_MASK                         0xff
+
+/* WCD9378_CDC_HPH_DSM_R5 Fields: */
+#define WCD9378_CDC_HPH_DSM_R5_SAT_LIMIT_R5_MASK                         0xff
+
+/* WCD9378_CDC_HPH_DSM_R6 Fields: */
+#define WCD9378_CDC_HPH_DSM_R6_SAT_LIMIT_R6_MASK                         0xff
+
+/* WCD9378_CDC_HPH_DSM_R7 Fields: */
+#define WCD9378_CDC_HPH_DSM_R7_SAT_LIMIT_R7_MASK                         0xff
+
+/* WCD9378_CDC_AUX_DSM_A1_0 Fields: */
+#define WCD9378_CDC_AUX_DSM_A1_0_COEF_A1_MASK                            0xff
+
+/* WCD9378_CDC_AUX_DSM_A1_1 Fields: */
+#define WCD9378_CDC_AUX_DSM_A1_1_COEF_A1_MASK                            0x01
+
+/* WCD9378_CDC_AUX_DSM_A2_0 Fields: */
+#define WCD9378_CDC_AUX_DSM_A2_0_COEF_A2_MASK                            0xff
+
+/* WCD9378_CDC_AUX_DSM_A2_1 Fields: */
+#define WCD9378_CDC_AUX_DSM_A2_1_COEF_A2_MASK                            0x0f
+
+/* WCD9378_CDC_AUX_DSM_A3_0 Fields: */
+#define WCD9378_CDC_AUX_DSM_A3_0_COEF_A3_MASK                            0xff
+
+/* WCD9378_CDC_AUX_DSM_A3_1 Fields: */
+#define WCD9378_CDC_AUX_DSM_A3_1_COEF_A3_MASK                            0x07
+
+/* WCD9378_CDC_AUX_DSM_A4_0 Fields: */
+#define WCD9378_CDC_AUX_DSM_A4_0_COEF_A4_MASK                            0xff
+
+/* WCD9378_CDC_AUX_DSM_A4_1 Fields: */
+#define WCD9378_CDC_AUX_DSM_A4_1_COEF_A4_MASK                            0x03
+
+/* WCD9378_CDC_AUX_DSM_A5_0 Fields: */
+#define WCD9378_CDC_AUX_DSM_A5_0_COEF_A5_MASK                            0xff
+
+/* WCD9378_CDC_AUX_DSM_A5_1 Fields: */
+#define WCD9378_CDC_AUX_DSM_A5_1_COEF_A5_MASK                            0x03
+
+/* WCD9378_CDC_AUX_DSM_A6_0 Fields: */
+#define WCD9378_CDC_AUX_DSM_A6_0_COEF_A6_MASK                            0xff
+
+/* WCD9378_CDC_AUX_DSM_A7_0 Fields: */
+#define WCD9378_CDC_AUX_DSM_A7_0_COEF_A7_MASK                            0xff
+
+/* WCD9378_CDC_AUX_DSM_C_0 Fields: */
+#define WCD9378_CDC_AUX_DSM_C_0_COEF_C3_MASK                             0xf0
+#define WCD9378_CDC_AUX_DSM_C_0_COEF_C2_MASK                             0x0f
+
+/* WCD9378_CDC_AUX_DSM_C_1 Fields: */
+#define WCD9378_CDC_AUX_DSM_C_1_COEF_C5_MASK                             0xf0
+#define WCD9378_CDC_AUX_DSM_C_1_COEF_C4_MASK                             0x0f
+
+/* WCD9378_CDC_AUX_DSM_C_2 Fields: */
+#define WCD9378_CDC_AUX_DSM_C_2_COEF_C7_MASK                             0xf0
+#define WCD9378_CDC_AUX_DSM_C_2_COEF_C6_MASK                             0x0f
+
+/* WCD9378_CDC_AUX_DSM_C_3 Fields: */
+#define WCD9378_CDC_AUX_DSM_C_3_COEF_C7_MASK                             0x3f
+
+/* WCD9378_CDC_AUX_DSM_R1 Fields: */
+#define WCD9378_CDC_AUX_DSM_R1_SAT_LIMIT_R1_MASK                         0xff
+
+/* WCD9378_CDC_AUX_DSM_R2 Fields: */
+#define WCD9378_CDC_AUX_DSM_R2_SAT_LIMIT_R2_MASK                         0xff
+
+/* WCD9378_CDC_AUX_DSM_R3 Fields: */
+#define WCD9378_CDC_AUX_DSM_R3_SAT_LIMIT_R3_MASK                         0xff
+
+/* WCD9378_CDC_AUX_DSM_R4 Fields: */
+#define WCD9378_CDC_AUX_DSM_R4_SAT_LIMIT_R4_MASK                         0xff
+
+/* WCD9378_CDC_AUX_DSM_R5 Fields: */
+#define WCD9378_CDC_AUX_DSM_R5_SAT_LIMIT_R5_MASK                         0xff
+
+/* WCD9378_CDC_AUX_DSM_R6 Fields: */
+#define WCD9378_CDC_AUX_DSM_R6_SAT_LIMIT_R6_MASK                         0xff
+
+/* WCD9378_CDC_AUX_DSM_R7 Fields: */
+#define WCD9378_CDC_AUX_DSM_R7_SAT_LIMIT_R7_MASK                         0xff
+
+/* WCD9378_CDC_HPH_GAIN_RX_0 Fields: */
+#define WCD9378_CDC_HPH_GAIN_RX_0_GAIN_RX_MASK                           0xff
+
+/* WCD9378_CDC_HPH_GAIN_RX_1 Fields: */
+#define WCD9378_CDC_HPH_GAIN_RX_1_GAIN_RX_MASK                           0xff
+
+/* WCD9378_CDC_HPH_GAIN_DSD_0 Fields: */
+#define WCD9378_CDC_HPH_GAIN_DSD_0_GAIN_DSD_MASK                         0xff
+
+/* WCD9378_CDC_HPH_GAIN_DSD_1 Fields: */
+#define WCD9378_CDC_HPH_GAIN_DSD_1_GAIN_DSD_MASK                         0xff
+
+/* WCD9378_CDC_HPH_GAIN_DSD_2 Fields: */
+#define WCD9378_CDC_HPH_GAIN_DSD_2_GAIN_LATCH_MASK                       0x02
+#define WCD9378_CDC_HPH_GAIN_DSD_2_GAIN_DSD_MASK                         0x01
+
+/* WCD9378_CDC_AUX_GAIN_DSD_0 Fields: */
+#define WCD9378_CDC_AUX_GAIN_DSD_0_GAIN_DSD_MASK                         0xff
+
+/* WCD9378_CDC_AUX_GAIN_DSD_1 Fields: */
+#define WCD9378_CDC_AUX_GAIN_DSD_1_GAIN_DSD_MASK                         0xff
+
+/* WCD9378_CDC_AUX_GAIN_DSD_2 Fields: */
+#define WCD9378_CDC_AUX_GAIN_DSD_2_GAIN_LATCH_MASK                       0x02
+#define WCD9378_CDC_AUX_GAIN_DSD_2_GAIN_DSD_MASK                         0x01
+
+/* WCD9378_CDC_HPH_GAIN_CTL Fields: */
+#define WCD9378_CDC_HPH_GAIN_CTL_HPH_STEREO_EN_MASK                      0x10
+#define WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK                         0x08
+#define WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK                         0x04
+#define WCD9378_CDC_HPH_GAIN_CTL_HPHR_DSD_EN_MASK                        0x02
+#define WCD9378_CDC_HPH_GAIN_CTL_HPHL_DSD_EN_MASK                        0x01
+
+/* WCD9378_CDC_AUX_GAIN_CTL Fields: */
+#define WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK                             0x01
+
+/* WCD9378_CDC_PATH_CTL Fields: */
+#define WCD9378_CDC_PATH_CTL_AUX_MUX_SEL_MASK                            0x10
+#define WCD9378_CDC_PATH_CTL_EAR_1BIT_MODE_MASK                          0x02
+#define WCD9378_CDC_PATH_CTL_EAR_MUX_SEL_MASK                            0x01
+
+/* WCD9378_CDC_SWR_CLG Fields: */
+#define WCD9378_CDC_SWR_CLG_CLG_CTL_MASK                                 0xff
+
+/* WCD9378_SWR_CLG_BYP Fields: */
+#define WCD9378_SWR_CLG_BYP_SWR_CLG_BYP_MASK                             0x01
+
+/* WCD9378_CDC_TX0_CTL Fields: */
+#define WCD9378_CDC_TX0_CTL_REQ_FB_SEL_MASK                              0x40
+#define WCD9378_CDC_TX0_CTL_TX_DITHER_EN_MASK                            0x20
+#define WCD9378_CDC_TX0_CTL_RANDOM_REGION_MASK                           0x1f
+
+/* WCD9378_CDC_TX1_CTL Fields: */
+#define WCD9378_CDC_TX1_CTL_REQ_FB_SEL_MASK                              0x40
+#define WCD9378_CDC_TX1_CTL_TX_DITHER_EN_MASK                            0x20
+#define WCD9378_CDC_TX1_CTL_RANDOM_REGION_MASK                           0x1f
+
+/* WCD9378_CDC_TX2_CTL Fields: */
+#define WCD9378_CDC_TX2_CTL_REQ_FB_SEL_MASK                              0x40
+#define WCD9378_CDC_TX2_CTL_TX_DITHER_EN_MASK                            0x20
+#define WCD9378_CDC_TX2_CTL_RANDOM_REGION_MASK                           0x1f
+
+/* WCD9378_CDC_TX_RST Fields: */
+#define WCD9378_CDC_TX_RST_TX2_SOFT_RST_MASK                             0x04
+#define WCD9378_CDC_TX_RST_TX1_SOFT_RST_MASK                             0x02
+#define WCD9378_CDC_TX_RST_TX0_SOFT_RST_MASK                             0x01
+
+/* WCD9378_CDC_REQ_CTL Fields: */
+#define WCD9378_CDC_REQ_CTL_TX2_WIDE_BAND_MASK                           0x10
+#define WCD9378_CDC_REQ_CTL_TX1_WIDE_BAND_MASK                           0x08
+#define WCD9378_CDC_REQ_CTL_TX0_WIDE_BAND_MASK                           0x04
+#define WCD9378_CDC_REQ_CTL_FS_RATE_4P8_MASK                             0x02
+#define WCD9378_CDC_REQ_CTL_DEM_BYPASS_MASK                              0x01
+
+/* WCD9378_CDC_RST Fields: */
+#define WCD9378_CDC_RST_TX_SOFT_RST_MASK                                 0x02
+#define WCD9378_CDC_RST_RX_SOFT_RST_MASK                                 0x01
+
+/* WCD9378_CDC_AMIC_CTL Fields: */
+#define WCD9378_CDC_AMIC_CTL_AMIC4_IN_SEL_MASK                           0x04
+#define WCD9378_CDC_AMIC_CTL_AMIC3_IN_SEL_MASK                           0x02
+#define WCD9378_CDC_AMIC_CTL_AMIC1_IN_SEL_MASK                           0x01
+
+/* WCD9378_CDC_DMIC_CTL Fields: */
+#define WCD9378_CDC_DMIC_CTL_DMIC_LEGACY_SW_MODE_MASK                    0x08
+#define WCD9378_CDC_DMIC_CTL_DMIC_DIV_BAK_EN_MASK                        0x04
+#define WCD9378_CDC_DMIC_CTL_CLK_SCALE_EN_MASK                           0x02
+#define WCD9378_CDC_DMIC_CTL_SOFT_RESET_MASK                             0x01
+
+/* WCD9378_CDC_DMIC1_CTL Fields: */
+#define WCD9378_CDC_DMIC1_CTL_DMIC_CLK_SCALE_SEL_MASK                    0x70
+#define WCD9378_CDC_DMIC1_CTL_DMIC_CLK_EN_MASK                           0x08
+#define WCD9378_CDC_DMIC1_CTL_DMIC_CLK_SEL_MASK                          0x07
+
+/* WCD9378_CDC_DMIC2_CTL Fields: */
+#define WCD9378_CDC_DMIC2_CTL_DMIC_LEFT_EN_MASK                          0x80
+#define WCD9378_CDC_DMIC2_CTL_DMIC_CLK_SCALE_SEL_MASK                    0x70
+#define WCD9378_CDC_DMIC2_CTL_DMIC_CLK_EN_MASK                           0x08
+#define WCD9378_CDC_DMIC2_CTL_DMIC_CLK_SEL_MASK                          0x07
+
+/* WCD9378_CDC_DMIC3_CTL Fields: */
+#define WCD9378_CDC_DMIC3_CTL_DMIC_CLK_SCALE_SEL_MASK                    0x70
+#define WCD9378_CDC_DMIC3_CTL_DMIC_CLK_EN_MASK                           0x08
+#define WCD9378_CDC_DMIC3_CTL_DMIC_CLK_SEL_MASK                          0x07
+
+/* WCD9378_EFUSE_PRG_CTL Fields: */
+#define WCD9378_EFUSE_PRG_CTL_PRG_ADDR_MASK                              0xff
+
+/* WCD9378_EFUSE_CTL Fields: */
+#define WCD9378_EFUSE_CTL_EFUSE_ST_CNT_MASK                              0x3c
+#define WCD9378_EFUSE_CTL_EFUSE_SOFT_RST_N_MASK                          0x02
+#define WCD9378_EFUSE_CTL_EFUSE_EN_MASK                                  0x01
+
+/* WCD9378_CDC_DMIC_RATE_1_2 Fields: */
+#define WCD9378_CDC_DMIC_RATE_1_2_DMIC2_RATE_MASK                        0xf0
+#define WCD9378_CDC_DMIC_RATE_1_2_DMIC1_RATE_MASK                        0x0f
+
+/* WCD9378_CDC_DMIC_RATE_3_4 Fields: */
+#define WCD9378_CDC_DMIC_RATE_3_4_DMIC3_RATE_MASK                        0x0f
+
+/* WCD9378_PDM_WD_EN_OVRD Fields: */
+#define WCD9378_PDM_WD_EN_OVRD_RX2_MASK                                  0x10
+#define WCD9378_PDM_WD_EN_OVRD_RX1_MASK                                  0x0c
+#define WCD9378_PDM_WD_EN_OVRD_RX0_MASK                                  0x03
+
+/* WCD9378_PDM_WD_CTL0 Fields: */
+#define WCD9378_PDM_WD_CTL0_HOLD_OFF_MASK                                0x80
+#define WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_DSD_MASK                        0x60
+#define WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK                        0x18
+#define WCD9378_PDM_WD_CTL0_PDM_WD_EN_MASK                               0x07
+
+/* WCD9378_PDM_WD_CTL1 Fields: */
+#define WCD9378_PDM_WD_CTL1_HOLD_OFF_MASK                                0x80
+#define WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_DSD_MASK                        0x60
+#define WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK                        0x18
+#define WCD9378_PDM_WD_CTL1_PDM_WD_EN_MASK                               0x07
+
+/* WCD9378_PDM_WD_CTL2 Fields: */
+#define WCD9378_PDM_WD_CTL2_HOLD_OFF_MASK                                0x08
+#define WCD9378_PDM_WD_CTL2_TIME_OUT_SEL_MASK                            0x06
+#define WCD9378_PDM_WD_CTL2_PDM_WD_EN_MASK                               0x01
+
+/* WCD9378_RAMP_CTL Fields: */
+#define WCD9378_RAMP_CTL_RX2_RAMP_EN_MASK                                0x04
+#define WCD9378_RAMP_CTL_RX1_RAMP_EN_MASK                                0x02
+#define WCD9378_RAMP_CTL_RX0_RAMP_EN_MASK                                0x01
+
+/* WCD9378_ACT_DET_CTL Fields: */
+#define WCD9378_ACT_DET_CTL_RX2_ACT_DET_EN_MASK                          0x04
+#define WCD9378_ACT_DET_CTL_RX1_ACT_DET_EN_MASK                          0x02
+#define WCD9378_ACT_DET_CTL_RX0_ACT_DET_EN_MASK                          0x01
+
+/* WCD9378_ACT_DET_HOOKUP0 Fields: */
+#define WCD9378_ACT_DET_HOOKUP0_RX2_INPUT_MUTE_MASK                      0x04
+#define WCD9378_ACT_DET_HOOKUP0_RX1_INPUT_MUTE_MASK                      0x02
+#define WCD9378_ACT_DET_HOOKUP0_RX0_INPUT_MUTE_MASK                      0x01
+
+/* WCD9378_ACT_DET_HOOKUP1 Fields: */
+#define WCD9378_ACT_DET_HOOKUP1_RX2_OUTPUT_MUTE_MASK                     0x04
+#define WCD9378_ACT_DET_HOOKUP1_RX1_OUTPUT_MUTE_MASK                     0x02
+#define WCD9378_ACT_DET_HOOKUP1_RX0_OUTPUT_MUTE_MASK                     0x01
+
+/* WCD9378_ACT_DET_HOOKUP2 Fields: */
+#define WCD9378_ACT_DET_HOOKUP2_RX2_DSD_GAIN_CSR_EN_MASK                 0x10
+#define WCD9378_ACT_DET_HOOKUP2_RX1_DSD_GAIN_CSR_EN_MASK                 0x08
+#define WCD9378_ACT_DET_HOOKUP2_RX1_PCM_GAIN_CSR_EN_MASK                 0x04
+#define WCD9378_ACT_DET_HOOKUP2_RX0_DSD_GAIN_CSR_EN_MASK                 0x02
+#define WCD9378_ACT_DET_HOOKUP2_RX0_PCM_GAIN_CSR_EN_MASK                 0x01
+
+/* WCD9378_ACT_DET_DLY_BUF_EN Fields: */
+#define WCD9378_ACT_DET_DLY_BUF_EN_RX2_DSD_DLY_BUF_EN_MASK               0x10
+#define WCD9378_ACT_DET_DLY_BUF_EN_RX1_DSD_DLY_BUF_EN_MASK               0x08
+#define WCD9378_ACT_DET_DLY_BUF_EN_RX1_PCM_DLY_BUF_EN_MASK               0x04
+#define WCD9378_ACT_DET_DLY_BUF_EN_RX0_DSD_DLY_BUF_EN_MASK               0x02
+#define WCD9378_ACT_DET_DLY_BUF_EN_RX0_PCM_DLY_BUF_EN_MASK               0x01
+
+/* WCD9378_INTR_MODE Fields: */
+#define WCD9378_INTR_MODE_SWR_PULSE_CLR_MASK                             0x20
+#define WCD9378_INTR_MODE_SWR_RX_INT_OUT_EN_MASK                         0x10
+#define WCD9378_INTR_MODE_GPIO_1_INT_OUT_EN_MASK                         0x08
+#define WCD9378_INTR_MODE_GPIO_0_INT_OUT_EN_MASK                         0x04
+#define WCD9378_INTR_MODE_SWR_INTR_LEVEL_MASK                            0x02
+#define WCD9378_INTR_MODE_INT_POLARITY_MASK                              0x01
+
+/* WCD9378_INTR_STATUS_0 Fields: */
+#define WCD9378_INTR_STATUS_0_HPHL_OCP_INT_MASK                          0x80
+#define WCD9378_INTR_STATUS_0_HPHR_CNP_INT_MASK                          0x40
+#define WCD9378_INTR_STATUS_0_HPHR_OCP_INT_MASK                          0x20
+#define WCD9378_INTR_STATUS_0_MBHC_SW_INT_MASK                           0x10
+#define WCD9378_INTR_STATUS_0_MBHC_ELECT_INS_REM_LEG_INT_MASK            0x08
+#define WCD9378_INTR_STATUS_0_MBHC_ELECT_INS_REM_INT_MASK                0x04
+#define WCD9378_INTR_STATUS_0_MBHC_BTN_RELEASE_INT_MASK                  0x02
+#define WCD9378_INTR_STATUS_0_MBHC_BTN_PRESS_INT_MASK                    0x01
+
+/* WCD9378_INTR_STATUS_1 Fields: */
+#define WCD9378_INTR_STATUS_1_AUX_PDM_WD_INT_MASK                        0x80
+#define WCD9378_INTR_STATUS_1_HPHR_PDM_WD_INT_MASK                       0x40
+#define WCD9378_INTR_STATUS_1_HPHL_PDM_WD_INT_MASK                       0x20
+#define WCD9378_INTR_STATUS_1_AUX_SCD_INT_MASK                           0x10
+#define WCD9378_INTR_STATUS_1_AUX_CNP_INT_MASK                           0x08
+#define WCD9378_INTR_STATUS_1_EAR_SCD_INT_MASK                           0x04
+#define WCD9378_INTR_STATUS_1_EAR_CNP_INT_MASK                           0x02
+#define WCD9378_INTR_STATUS_1_HPHL_CNP_INT_MASK                          0x01
+
+/* WCD9378_INTR_STATUS_2 Fields: */
+#define WCD9378_INTR_STATUS_2_HIDTX_CUR_OWNER_CHG_MASK                   0x80
+#define WCD9378_INTR_STATUS_2_SAPU_PROT_MODE_CHG_MASK                    0x40
+#define WCD9378_INTR_STATUS_2_GPIO_1_INT_MASK                            0x20
+#define WCD9378_INTR_STATUS_2_GPIO_0_INT_MASK                            0x10
+#define WCD9378_INTR_STATUS_2_HPHL_SURGE_DET_INT_MASK                    0x08
+#define WCD9378_INTR_STATUS_2_HPHR_SURGE_DET_INT_MASK                    0x04
+#define WCD9378_INTR_STATUS_2_MBHC_MOISTRUE_INT_MASK                     0x02
+#define WCD9378_INTR_STATUS_2_LDORT_SCD_INT_MASK                         0x01
+
+/* WCD9378_INTR_STATUS_3 Fields: */
+#define WCD9378_INTR_STATUS_3_SM2_STAT_ALERT_MASK                        0x20
+#define WCD9378_INTR_STATUS_3_SM1_STAT_ALERT_MASK                        0x10
+#define WCD9378_INTR_STATUS_3_SM0_STAT_ALERT_MASK                        0x08
+#define WCD9378_INTR_STATUS_3_SJ_STAT_ALERT_MASK                         0x04
+#define WCD9378_INTR_STATUS_3_SA_STAT_ALERT_MASK                         0x02
+
+/* WCD9378_INTR_MASK_0 Fields: */
+#define WCD9378_INTR_MASK_0_HPHL_OCP_INT_MASK                            0x80
+#define WCD9378_INTR_MASK_0_HPHR_CNP_INT_MASK                            0x40
+#define WCD9378_INTR_MASK_0_HPHR_OCP_INT_MASK                            0x20
+#define WCD9378_INTR_MASK_0_MBHC_SW_INT_MASK                             0x10
+#define WCD9378_INTR_MASK_0_MBHC_ELECT_INS_REM_LEG_INT_MASK              0x08
+#define WCD9378_INTR_MASK_0_MBHC_ELECT_INS_REM_INT_MASK                  0x04
+#define WCD9378_INTR_MASK_0_MBHC_BTN_RELEASE_INT_MASK                    0x02
+#define WCD9378_INTR_MASK_0_MBHC_BTN_PRESS_INT_MASK                      0x01
+
+/* WCD9378_INTR_MASK_1 Fields: */
+#define WCD9378_INTR_MASK_1_AUX_PDM_WD_INT_MASK                          0x80
+#define WCD9378_INTR_MASK_1_HPHR_PDM_WD_INT_MASK                         0x40
+#define WCD9378_INTR_MASK_1_HPHL_PDM_WD_INT_MASK                         0x20
+#define WCD9378_INTR_MASK_1_AUX_SCD_INT_MASK                             0x10
+#define WCD9378_INTR_MASK_1_AUX_CNP_INT_MASK                             0x08
+#define WCD9378_INTR_MASK_1_EAR_SCD_INT_MASK                             0x04
+#define WCD9378_INTR_MASK_1_EAR_CNP_INT_MASK                             0x02
+#define WCD9378_INTR_MASK_1_HPHL_CNP_INT_MASK                            0x01
+
+/* WCD9378_INTR_MASK_2 Fields: */
+#define WCD9378_INTR_MASK_2_HIDTX_CUR_OWNER_CHG_MASK                     0x80
+#define WCD9378_INTR_MASK_2_SAPU_PROT_MODE_CHG_MASK                      0x40
+#define WCD9378_INTR_MASK_2_GPIO_1_INT_MASK                              0x20
+#define WCD9378_INTR_MASK_2_GPIO_0_INT_MASK                              0x10
+#define WCD9378_INTR_MASK_2_HPHL_SURGE_DET_INT_MASK                      0x08
+#define WCD9378_INTR_MASK_2_HPHR_SURGE_DET_INT_MASK                      0x04
+#define WCD9378_INTR_MASK_2_MBHC_MOISTRUE_INT_MASK                       0x02
+#define WCD9378_INTR_MASK_2_LDORT_SCD_INT_MASK                           0x01
+
+/* WCD9378_INTR_MASK_3 Fields: */
+#define WCD9378_INTR_MASK_3_SM2_STAT_ALERT_MASK                          0x20
+#define WCD9378_INTR_MASK_3_SM1_STAT_ALERT_MASK                          0x10
+#define WCD9378_INTR_MASK_3_SM0_STAT_ALERT_MASK                          0x08
+#define WCD9378_INTR_MASK_3_SJ_STAT_ALERT_MASK                           0x04
+#define WCD9378_INTR_MASK_3_SA_STAT_ALERT_MASK                           0x02
+
+/* WCD9378_INTR_SET_0 Fields: */
+#define WCD9378_INTR_SET_0_HPHL_OCP_INT_MASK                             0x80
+#define WCD9378_INTR_SET_0_HPHR_CNP_INT_MASK                             0x40
+#define WCD9378_INTR_SET_0_HPHR_OCP_INT_MASK                             0x20
+#define WCD9378_INTR_SET_0_MBHC_SW_INT_MASK                              0x10
+#define WCD9378_INTR_SET_0_MBHC_ELECT_INS_REM_LEG_INT_MASK               0x08
+#define WCD9378_INTR_SET_0_MBHC_ELECT_INS_REM_INT_MASK                   0x04
+#define WCD9378_INTR_SET_0_MBHC_BTN_RELEASE_INT_MASK                     0x02
+#define WCD9378_INTR_SET_0_MBHC_BTN_PRESS_INT_MASK                       0x01
+
+/* WCD9378_INTR_SET_1 Fields: */
+#define WCD9378_INTR_SET_1_AUX_PDM_WD_INT_MASK                           0x80
+#define WCD9378_INTR_SET_1_HPHR_PDM_WD_INT_MASK                          0x40
+#define WCD9378_INTR_SET_1_HPHL_PDM_WD_INT_MASK                          0x20
+#define WCD9378_INTR_SET_1_AUX_SCD_INT_MASK                              0x10
+#define WCD9378_INTR_SET_1_AUX_CNP_INT_MASK                              0x08
+#define WCD9378_INTR_SET_1_EAR_SCD_INT_MASK                              0x04
+#define WCD9378_INTR_SET_1_EAR_CNP_INT_MASK                              0x02
+#define WCD9378_INTR_SET_1_HPHL_CNP_INT_MASK                             0x01
+
+/* WCD9378_INTR_SET_2 Fields: */
+#define WCD9378_INTR_SET_2_HIDTX_CUR_OWNER_CHG_MASK                      0x80
+#define WCD9378_INTR_SET_2_SAPU_PROT_MODE_CHG_MASK                       0x40
+#define WCD9378_INTR_SET_2_GPIO_1_INT_MASK                               0x20
+#define WCD9378_INTR_SET_2_GPIO_0_INT_MASK                               0x10
+#define WCD9378_INTR_SET_2_HPHL_SURGE_DET_INT_MASK                       0x08
+#define WCD9378_INTR_SET_2_HPHR_SURGE_DET_INT_MASK                       0x04
+#define WCD9378_INTR_SET_2_MBHC_MOISTRUE_INT_MASK                        0x02
+#define WCD9378_INTR_SET_2_LDORT_SCD_INT_MASK                            0x01
+
+/* WCD9378_INTR_SET_3 Fields: */
+#define WCD9378_INTR_SET_3_SM2_STAT_ALERT_MASK                           0x20
+#define WCD9378_INTR_SET_3_SM1_STAT_ALERT_MASK                           0x10
+#define WCD9378_INTR_SET_3_SM0_STAT_ALERT_MASK                           0x08
+#define WCD9378_INTR_SET_3_SJ_STAT_ALERT_MASK                            0x04
+#define WCD9378_INTR_SET_3_SA_STAT_ALERT_MASK                            0x02
+
+/* WCD9378_INTR_TEST_0 Fields: */
+#define WCD9378_INTR_TEST_0_HPHL_OCP_INT_MASK                            0x80
+#define WCD9378_INTR_TEST_0_HPHR_CNP_INT_MASK                            0x40
+#define WCD9378_INTR_TEST_0_HPHR_OCP_INT_MASK                            0x20
+#define WCD9378_INTR_TEST_0_MBHC_SW_INT_MASK                             0x10
+#define WCD9378_INTR_TEST_0_MBHC_ELECT_INS_REM_LEG_INT_MASK              0x08
+#define WCD9378_INTR_TEST_0_MBHC_ELECT_INS_REM_INT_MASK                  0x04
+#define WCD9378_INTR_TEST_0_MBHC_BTN_RELEASE_INT_MASK                    0x02
+#define WCD9378_INTR_TEST_0_MBHC_BTN_PRESS_INT_MASK                      0x01
+
+/* WCD9378_INTR_TEST_1 Fields: */
+#define WCD9378_INTR_TEST_1_AUX_PDM_WD_INT_MASK                          0x80
+#define WCD9378_INTR_TEST_1_HPHR_PDM_WD_INT_MASK                         0x40
+#define WCD9378_INTR_TEST_1_HPHL_PDM_WD_INT_MASK                         0x20
+#define WCD9378_INTR_TEST_1_AUX_SCD_INT_MASK                             0x10
+#define WCD9378_INTR_TEST_1_AUX_CNP_INT_MASK                             0x08
+#define WCD9378_INTR_TEST_1_EAR_SCD_INT_MASK                             0x04
+#define WCD9378_INTR_TEST_1_EAR_CNP_INT_MASK                             0x02
+#define WCD9378_INTR_TEST_1_HPHL_CNP_INT_MASK                            0x01
+
+/* WCD9378_INTR_TEST_2 Fields: */
+#define WCD9378_INTR_TEST_2_HIDTX_CUR_OWNER_CHG_MASK                     0x80
+#define WCD9378_INTR_TEST_2_SAPU_PROT_MODE_CHG_MASK                      0x40
+#define WCD9378_INTR_TEST_2_GPIO_1_INT_MASK                              0x20
+#define WCD9378_INTR_TEST_2_GPIO_0_INT_MASK                              0x10
+#define WCD9378_INTR_TEST_2_HPHL_SURGE_DET_INT_MASK                      0x08
+#define WCD9378_INTR_TEST_2_HPHR_SURGE_DET_INT_MASK                      0x04
+#define WCD9378_INTR_TEST_2_MBHC_MOISTRUE_INT_MASK                       0x02
+#define WCD9378_INTR_TEST_2_LDORT_SCD_INT_MASK                           0x01
+
+/* WCD9378_INTR_TEST_3 Fields: */
+#define WCD9378_INTR_TEST_3_SM2_STAT_ALERT_MASK                          0x20
+#define WCD9378_INTR_TEST_3_SM1_STAT_ALERT_MASK                          0x10
+#define WCD9378_INTR_TEST_3_SM0_STAT_ALERT_MASK                          0x08
+#define WCD9378_INTR_TEST_3_SJ_STAT_ALERT_MASK                           0x04
+#define WCD9378_INTR_TEST_3_SA_STAT_ALERT_MASK                           0x02
+
+/* WCD9378_TX_MODE_DBG_EN Fields: */
+#define WCD9378_TX_MODE_DBG_EN_TXD2_MODE_DBG_EN_MASK                     0x04
+#define WCD9378_TX_MODE_DBG_EN_TXD1_MODE_DBG_EN_MASK                     0x02
+#define WCD9378_TX_MODE_DBG_EN_TXD0_MODE_DBG_EN_MASK                     0x01
+
+/* WCD9378_TX_MODE_DBG_0_1 Fields: */
+#define WCD9378_TX_MODE_DBG_0_1_TXD1_MODE_DBG_MASK                       0xf0
+#define WCD9378_TX_MODE_DBG_0_1_TXD0_MODE_DBG_MASK                       0x0f
+
+/* WCD9378_TX_MODE_DBG_2_3 Fields: */
+#define WCD9378_TX_MODE_DBG_2_3_TXD2_MODE_DBG_MASK                       0x0f
+
+/* WCD9378_LB_IN_SEL_CTL Fields: */
+#define WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK                         0x0c
+#define WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK                         0x03
+
+/* WCD9378_LOOP_BACK_MODE Fields: */
+#define WCD9378_LOOP_BACK_MODE_TX_DATA_EDGE_MASK                         0x10
+#define WCD9378_LOOP_BACK_MODE_RX_DATA_EDGE_MASK                         0x08
+#define WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK                        0x07
+
+/* WCD9378_SWR_DAC_TEST Fields: */
+#define WCD9378_SWR_DAC_TEST_SWR_DAC_TEST_MASK                           0x01
+
+/* WCD9378_SWR_HM_TEST_RX_0 Fields: */
+#define WCD9378_SWR_HM_TEST_RX_0_ALT_MODE_MASK                           0x80
+#define WCD9378_SWR_HM_TEST_RX_0_IO_MODE_MASK                            0x40
+#define WCD9378_SWR_HM_TEST_RX_0_LN2_T_DATA_OE_MASK                      0x20
+#define WCD9378_SWR_HM_TEST_RX_0_LN2_T_DATA_OUT_MASK                     0x10
+#define WCD9378_SWR_HM_TEST_RX_0_LN2_T_KEEPER_EN_MASK                    0x08
+#define WCD9378_SWR_HM_TEST_RX_0_LN1_T_DATA_OE_MASK                      0x04
+#define WCD9378_SWR_HM_TEST_RX_0_LN1_T_DATA_OUT_MASK                     0x02
+#define WCD9378_SWR_HM_TEST_RX_0_LN1_T_KEEPER_EN_MASK                    0x01
+
+/* WCD9378_SWR_HM_TEST_TX_0 Fields: */
+#define WCD9378_SWR_HM_TEST_TX_0_ALT_MODE_MASK                           0x80
+#define WCD9378_SWR_HM_TEST_TX_0_IO_MODE_MASK                            0x40
+#define WCD9378_SWR_HM_TEST_TX_0_LN2_T_DATA_OE_MASK                      0x20
+#define WCD9378_SWR_HM_TEST_TX_0_LN2_T_DATA_OUT_MASK                     0x10
+#define WCD9378_SWR_HM_TEST_TX_0_LN2_T_KEEPER_EN_MASK                    0x08
+#define WCD9378_SWR_HM_TEST_TX_0_LN1_T_DATA_OE_MASK                      0x04
+#define WCD9378_SWR_HM_TEST_TX_0_LN1_T_DATA_OUT_MASK                     0x02
+#define WCD9378_SWR_HM_TEST_TX_0_LN1_T_KEEPER_EN_MASK                    0x01
+
+/* WCD9378_SWR_HM_TEST_RX_1 Fields: */
+#define WCD9378_SWR_HM_TEST_RX_1_DTEST_SEL_MASK                          0x1c
+#define WCD9378_SWR_HM_TEST_RX_1_LN2_DLY_CELL_TEST_EN_MASK               0x02
+#define WCD9378_SWR_HM_TEST_RX_1_LN1_DLY_CELL_TEST_EN_MASK               0x01
+
+/* WCD9378_SWR_HM_TEST_TX_1 Fields: */
+#define WCD9378_SWR_HM_TEST_TX_1_DTEST_SEL_MASK                          0x3c
+#define WCD9378_SWR_HM_TEST_TX_1_LN2_DLY_CELL_TEST_EN_MASK               0x02
+#define WCD9378_SWR_HM_TEST_TX_1_LN1_DLY_CELL_TEST_EN_MASK               0x01
+
+/* WCD9378_SWR_HM_TEST_0 Fields: */
+#define WCD9378_SWR_HM_TEST_0_TX_LN2_T_DATA_IN_MASK                      0x80
+#define WCD9378_SWR_HM_TEST_0_TX_LN2_T_CLK_IN_MASK                       0x40
+#define WCD9378_SWR_HM_TEST_0_TX_LN1_T_DATA_IN_MASK                      0x20
+#define WCD9378_SWR_HM_TEST_0_TX_LN1_T_CLK_IN_MASK                       0x10
+#define WCD9378_SWR_HM_TEST_0_RX_LN2_T_DATA_IN_MASK                      0x08
+#define WCD9378_SWR_HM_TEST_0_RX_LN2_T_CLK_IN_MASK                       0x04
+#define WCD9378_SWR_HM_TEST_0_RX_LN1_T_DATA_IN_MASK                      0x02
+#define WCD9378_SWR_HM_TEST_0_RX_LN1_T_CLK_IN_MASK                       0x01
+
+/* WCD9378_PAD_CTL_SWR_0 Fields: */
+#define WCD9378_PAD_CTL_SWR_0_SWR_SLEW_PRG_MASK                          0xf0
+#define WCD9378_PAD_CTL_SWR_0_SWR_DRIVE_PRG_MASK                         0x0f
+
+/* WCD9378_PAD_CTL_SWR_1 Fields: */
+#define WCD9378_PAD_CTL_SWR_1_SWR_TDZ_PRG_MASK                           0x0f
+
+/* WCD9378_I2C_CTL Fields: */
+#define WCD9378_I2C_CTL_ACTIVE_MODE_MASK                                 0x01
+
+/* WCD9378_LEGACY_SW_MODE Fields: */
+#define WCD9378_LEGACY_SW_MODE_USE_LOCAL_INTR_CTRL_MASK                  0x08
+#define WCD9378_LEGACY_SW_MODE_CDC_LEGACY_ACCESS_MASK                    0x04
+#define WCD9378_LEGACY_SW_MODE_MIPI_SWR_V1P1_MASK                        0x02
+#define WCD9378_LEGACY_SW_MODE_CDC_TX_TANGGU_SW_MODE_MASK                0x01
+
+/* WCD9378_EFUSE_TEST_CTL_0 Fields: */
+#define WCD9378_EFUSE_TEST_CTL_0_EFUSE_TEST_CTL_LSB_MASK                 0xff
+
+/* WCD9378_EFUSE_TEST_CTL_1 Fields: */
+#define WCD9378_EFUSE_TEST_CTL_1_EFUSE_TEST_CTL_MSB_MASK                 0xff
+
+/* WCD9378_EFUSE_T_DATA_0 Fields: */
+#define WCD9378_EFUSE_T_DATA_0_EFUSE_DATA_MASK                           0xff
+
+/* WCD9378_PAD_CTL_PDM_RX0 Fields: */
+#define WCD9378_PAD_CTL_PDM_RX0_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD9378_PAD_CTL_PDM_RX0_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD9378_PAD_CTL_PDM_RX1 Fields: */
+#define WCD9378_PAD_CTL_PDM_RX1_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD9378_PAD_CTL_PDM_RX1_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD9378_PAD_CTL_PDM_TX0 Fields: */
+#define WCD9378_PAD_CTL_PDM_TX0_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD9378_PAD_CTL_PDM_TX0_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD9378_PAD_CTL_PDM_TX1 Fields: */
+#define WCD9378_PAD_CTL_PDM_TX1_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD9378_PAD_CTL_PDM_TX1_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD9378_PAD_INP_DIS_0 Fields: */
+#define WCD9378_PAD_INP_DIS_0_DMIC3_CLK_MASK                             0x20
+#define WCD9378_PAD_INP_DIS_0_DMIC3_DATA_MASK                            0x10
+#define WCD9378_PAD_INP_DIS_0_DMIC2_CLK_MASK                             0x08
+#define WCD9378_PAD_INP_DIS_0_DMIC2_DATA_MASK                            0x04
+#define WCD9378_PAD_INP_DIS_0_DMIC1_CLK_MASK                             0x02
+#define WCD9378_PAD_INP_DIS_0_DMIC1_DATA_MASK                            0x01
+
+/* WCD9378_DRIVE_STRENGTH_0 Fields: */
+#define WCD9378_DRIVE_STRENGTH_0_DS_DMIC2_CLK_MASK                       0xc0
+#define WCD9378_DRIVE_STRENGTH_0_DS_DMIC2_DATA_MASK                      0x30
+#define WCD9378_DRIVE_STRENGTH_0_DS_DMIC1_CLK_MASK                       0x0c
+#define WCD9378_DRIVE_STRENGTH_0_DS_DMIC1_DATA_MASK                      0x03
+
+/* WCD9378_DRIVE_STRENGTH_1 Fields: */
+#define WCD9378_DRIVE_STRENGTH_1_DS_DMIC3_CLK_MASK                       0x0c
+#define WCD9378_DRIVE_STRENGTH_1_DS_DMIC3_DATA_MASK                      0x03
+
+/* WCD9378_RX_DATA_EDGE_CTL Fields: */
+#define WCD9378_RX_DATA_EDGE_CTL_HPH_CLH_EDGE_MASK                       0x20
+#define WCD9378_RX_DATA_EDGE_CTL_AUX_DOUT_EDGE_MASK                      0x10
+#define WCD9378_RX_DATA_EDGE_CTL_HPHR_DOUT_EDGE_MASK                     0x08
+#define WCD9378_RX_DATA_EDGE_CTL_HPHL_DOUT_EDGE_MASK                     0x04
+#define WCD9378_RX_DATA_EDGE_CTL_HPHR_GAIN_EDGE_MASK                     0x02
+#define WCD9378_RX_DATA_EDGE_CTL_HPHL_GAIN_EDGE_MASK                     0x01
+
+/* WCD9378_TX_DATA_EDGE_CTL Fields: */
+#define WCD9378_TX_DATA_EDGE_CTL_TX_WE_DLY_MASK                          0x18
+#define WCD9378_TX_DATA_EDGE_CTL_TX2_DIN_EDGE_MASK                       0x04
+#define WCD9378_TX_DATA_EDGE_CTL_TX1_DIN_EDGE_MASK                       0x02
+#define WCD9378_TX_DATA_EDGE_CTL_TX0_DIN_EDGE_MASK                       0x01
+
+/* WCD9378_GPIO_MODE Fields: */
+#define WCD9378_GPIO_MODE_GPIO_3_EN_MASK                                 0x10
+#define WCD9378_GPIO_MODE_GPIO_2_EN_MASK                                 0x08
+#define WCD9378_GPIO_MODE_GPIO_1_EN_MASK                                 0x04
+#define WCD9378_GPIO_MODE_GPIO_0_EN_MASK                                 0x02
+#define WCD9378_GPIO_MODE_TEST_MODE_MASK                                 0x01
+
+/* WCD9378_PIN_CTL_OE Fields: */
+#define WCD9378_PIN_CTL_OE_TEST_PIN_CTL_OE_MASK                          0x10
+#define WCD9378_PIN_CTL_OE_GPIO_3_PIN_CTL_OE_MASK                        0x08
+#define WCD9378_PIN_CTL_OE_GPIO_2_PIN_CTL_OE_MASK                        0x04
+#define WCD9378_PIN_CTL_OE_GPIO_1_PIN_CTL_OE_MASK                        0x02
+#define WCD9378_PIN_CTL_OE_GPIO_0_PIN_CTL_OE_MASK                        0x01
+
+/* WCD9378_PIN_CTL_DATA_0 Fields: */
+#define WCD9378_PIN_CTL_DATA_0_PAD_DMIC3_CLK_MASK                        0x20
+#define WCD9378_PIN_CTL_DATA_0_PAD_DMIC3_DATA_MASK                       0x10
+#define WCD9378_PIN_CTL_DATA_0_PAD_DMIC2_CLK_MASK                        0x08
+#define WCD9378_PIN_CTL_DATA_0_PAD_DMIC2_DATA_MASK                       0x04
+#define WCD9378_PIN_CTL_DATA_0_PAD_DMIC1_CLK_MASK                        0x02
+#define WCD9378_PIN_CTL_DATA_0_PAD_DMIC1_DATA_MASK                       0x01
+
+/* WCD9378_PIN_STATUS_0 Fields: */
+#define WCD9378_PIN_STATUS_0_PAD_DMIC3_CLK_MASK                          0x20
+#define WCD9378_PIN_STATUS_0_PAD_DMIC3_DATA_MASK                         0x10
+#define WCD9378_PIN_STATUS_0_PAD_DMIC2_CLK_MASK                          0x08
+#define WCD9378_PIN_STATUS_0_PAD_DMIC2_DATA_MASK                         0x04
+#define WCD9378_PIN_STATUS_0_PAD_DMIC1_CLK_MASK                          0x02
+#define WCD9378_PIN_STATUS_0_PAD_DMIC1_DATA_MASK                         0x01
+
+/* WCD9378_DIG_DEBUG_CTL Fields: */
+#define WCD9378_DIG_DEBUG_CTL_DIG_DEBUG_CTL_MASK                         0xff
+
+/* WCD9378_DIG_DEBUG_EN Fields: */
+#define WCD9378_DIG_DEBUG_EN_TX_DBG_MODE_MASK                            0x02
+#define WCD9378_DIG_DEBUG_EN_RX_DBG_MODE_MASK                            0x01
+
+/* WCD9378_ANA_CSR_DBG_ADD Fields: */
+#define WCD9378_ANA_CSR_DBG_ADD_ADD_MASK                                 0xff
+
+/* WCD9378_ANA_CSR_DBG_CTL Fields: */
+#define WCD9378_ANA_CSR_DBG_CTL_WR_VALUE_MASK                            0xc0
+#define WCD9378_ANA_CSR_DBG_CTL_RD_VALUE_MASK                            0x38
+#define WCD9378_ANA_CSR_DBG_CTL_DBG_PAGE_SEL_MASK                        0x06
+#define WCD9378_ANA_CSR_DBG_CTL_DBG_EN_MASK                              0x01
+
+/* WCD9378_SSP_DBG Fields: */
+#define WCD9378_SSP_DBG_RX_SSP_DBG_MASK                                  0x02
+#define WCD9378_SSP_DBG_TX_SSP_DBG_MASK                                  0x01
+
+/* WCD9378_MODE_STATUS_0 Fields: */
+#define WCD9378_MODE_STATUS_0_ATE_7_MASK                                 0x80
+#define WCD9378_MODE_STATUS_0_ATE_6_MASK                                 0x40
+#define WCD9378_MODE_STATUS_0_ATE_5_MASK                                 0x20
+#define WCD9378_MODE_STATUS_0_ATE_4_MASK                                 0x10
+#define WCD9378_MODE_STATUS_0_ATE_3_MASK                                 0x08
+#define WCD9378_MODE_STATUS_0_ATE_2_MASK                                 0x04
+#define WCD9378_MODE_STATUS_0_ATE_1_MASK                                 0x02
+#define WCD9378_MODE_STATUS_0_SWR_TEST_MASK                              0x01
+
+/* WCD9378_MODE_STATUS_1 Fields: */
+#define WCD9378_MODE_STATUS_1_SWR_PAD_TEST_MASK                          0x02
+#define WCD9378_MODE_STATUS_1_EFUSE_MODE_MASK                            0x01
+
+/* WCD9378_SPARE_0 Fields: */
+#define WCD9378_SPARE_0_SPARE_REG_0_MASK                                 0xffff
+
+/* WCD9378_SPARE_1 Fields: */
+#define WCD9378_SPARE_1_SPARE_REG_1_MASK                                 0xffffff
+
+/* WCD9378_SPARE_2 Fields: */
+#define WCD9378_SPARE_2_SPARE_REG_2_MASK                                 0xffffffff
+
+/* WCD9378_EFUSE_REG_0 Fields: */
+#define WCD9378_EFUSE_REG_0_SPARE_BITS_MASK                              0xe0
+#define WCD9378_EFUSE_REG_0_WCD9378_ID_MASK                              0x1e
+#define WCD9378_EFUSE_REG_0_EFUSE_BLOWN_MASK                             0x01
+
+/* WCD9378_EFUSE_REG_1 Fields: */
+#define WCD9378_EFUSE_REG_1_LOT_ID_0_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_2 Fields: */
+#define WCD9378_EFUSE_REG_2_LOT_ID_1_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_3 Fields: */
+#define WCD9378_EFUSE_REG_3_LOT_ID_2_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_4 Fields: */
+#define WCD9378_EFUSE_REG_4_LOT_ID_3_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_5 Fields: */
+#define WCD9378_EFUSE_REG_5_LOT_ID_4_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_6 Fields: */
+#define WCD9378_EFUSE_REG_6_LOT_ID_5_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_7 Fields: */
+#define WCD9378_EFUSE_REG_7_LOT_ID_6_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_8 Fields: */
+#define WCD9378_EFUSE_REG_8_LOT_ID_7_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_9 Fields: */
+#define WCD9378_EFUSE_REG_9_LOT_ID_8_MASK                                0xff
+
+/* WCD9378_EFUSE_REG_10 Fields: */
+#define WCD9378_EFUSE_REG_10_LOT_ID_9_MASK                               0xff
+
+/* WCD9378_EFUSE_REG_11 Fields: */
+#define WCD9378_EFUSE_REG_11_LOT_ID_10_MASK                              0xff
+
+/* WCD9378_EFUSE_REG_12 Fields: */
+#define WCD9378_EFUSE_REG_12_LOT_ID_11_MASK                              0xff
+
+/* WCD9378_EFUSE_REG_13 Fields: */
+#define WCD9378_EFUSE_REG_13_WAFER_ID_MASK                               0xff
+
+/* WCD9378_EFUSE_REG_14 Fields: */
+#define WCD9378_EFUSE_REG_14_X_DIE_LOCATION_MASK                         0xff
+
+/* WCD9378_EFUSE_REG_15 Fields: */
+#define WCD9378_EFUSE_REG_15_Y_DIE_LOCATION_MASK                         0xff
+
+/* WCD9378_EFUSE_REG_16 Fields: */
+#define WCD9378_EFUSE_REG_16_FAB_ID_MASK                                 0xff
+
+/* WCD9378_EFUSE_REG_17 Fields: */
+#define WCD9378_EFUSE_REG_17_TEST_PROGRAM_REV_MASK                       0xff
+
+/* WCD9378_EFUSE_REG_18 Fields: */
+#define WCD9378_EFUSE_REG_18_DIE_REVISION_MASK                           0xff
+
+/* WCD9378_EFUSE_REG_19 Fields: */
+#define WCD9378_EFUSE_REG_19_MFG_ID_SPARE_MASK                           0xff
+
+/* WCD9378_EFUSE_REG_20 Fields: */
+#define WCD9378_EFUSE_REG_20_I2C_SLV_ID_BLOWN_MASK                       0x80
+#define WCD9378_EFUSE_REG_20_I2C_SLAVE_ID_MASK                           0x7f
+
+/* WCD9378_EFUSE_REG_21 Fields: */
+#define WCD9378_EFUSE_REG_21_MBHC_IMP_DET_0_MASK                         0xff
+
+/* WCD9378_EFUSE_REG_22 Fields: */
+#define WCD9378_EFUSE_REG_22_MBHC_IMP_DET_1_MASK                         0xff
+
+/* WCD9378_EFUSE_REG_23 Fields: */
+#define WCD9378_EFUSE_REG_23_SWR_PAD_DRIVE_PRG_1P8V_MASK                 0xf0
+#define WCD9378_EFUSE_REG_23_SWR_SLEW_PRG_1P8V_MASK                      0x0f
+
+/* WCD9378_EFUSE_REG_24 Fields: */
+#define WCD9378_EFUSE_REG_24_SPARE_BITS_MASK                             0xe0
+#define WCD9378_EFUSE_REG_24_SWR_PAD_BLOWN_MASK                          0x10
+#define WCD9378_EFUSE_REG_24_SWR_TDZ_DELAY_PRG_1P8V_MASK                 0x0f
+
+/* WCD9378_EFUSE_REG_25 Fields: */
+#define WCD9378_EFUSE_REG_25_MBHC_IMP_DET_2_MASK                         0xff
+
+/* WCD9378_EFUSE_REG_26 Fields: */
+#define WCD9378_EFUSE_REG_26_MBHC_IMP_DET_3_MASK                         0xff
+
+/* WCD9378_EFUSE_REG_27 Fields: */
+#define WCD9378_EFUSE_REG_27_HPH_DSD_DIS_MASK                            0x80
+#define WCD9378_EFUSE_REG_27_BG_TUNE_BLOWN_MASK                          0x40
+#define WCD9378_EFUSE_REG_27_BG_TUNE_MASK                                0x30
+#define WCD9378_EFUSE_REG_27_EFUSE_HPH_MASK                              0x0f
+
+/* WCD9378_EFUSE_REG_28 Fields: */
+#define WCD9378_EFUSE_REG_28_SPARE_BITS_MASK                             0xff
+
+/* WCD9378_EFUSE_REG_29 Fields: */
+#define WCD9378_EFUSE_REG_29_SPARE_BITS_MASK                             0xe0
+#define WCD9378_EFUSE_REG_29_TX_LP_DIS_MASK                              0x10
+#define WCD9378_EFUSE_REG_29_TX_HP_DIS_MASK                              0x08
+#define WCD9378_EFUSE_REG_29_DMIC_DIS_MASK                               0x04
+#define WCD9378_EFUSE_REG_29_PLATFORM_MASK                               0x02
+#define WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK                         0x01
+
+/* WCD9378_EFUSE_REG_30 Fields: */
+#define WCD9378_EFUSE_REG_30_SPARE_BITS_MASK                             0xf0
+#define WCD9378_EFUSE_REG_30_SWR_SLEW_PRG_1P2V_MASK                      0x0f
+
+/* WCD9378_EFUSE_REG_31 Fields: */
+#define WCD9378_EFUSE_REG_31_SWR_PAD_DRIVE_PRG_1P2V_MASK                 0xf0
+#define WCD9378_EFUSE_REG_31_SWR_TDZ_DELAY_PRG_1P2V_MASK                 0x0f
+
+/* WCD9378_TX_REQ_FB_CTL_2 Fields: */
+#define WCD9378_TX_REQ_FB_CTL_2_L0_FB_T2_MASK                            0xf0
+#define WCD9378_TX_REQ_FB_CTL_2_L0_FB_T1_MASK                            0x0f
+
+/* WCD9378_TX_REQ_FB_CTL_3 Fields: */
+#define WCD9378_TX_REQ_FB_CTL_3_L1_FB_T2_MASK                            0xf0
+#define WCD9378_TX_REQ_FB_CTL_3_L1_FB_T1_MASK                            0x0f
+
+/* WCD9378_TX_REQ_FB_CTL_4 Fields: */
+#define WCD9378_TX_REQ_FB_CTL_4_L2_FB_T2_MASK                            0xf0
+#define WCD9378_TX_REQ_FB_CTL_4_L2_FB_T1_MASK                            0x0f
+
+/* WCD9378_DEM_BYPASS_DATA0 Fields: */
+#define WCD9378_DEM_BYPASS_DATA0_DEM_BYPASS_DATA0_MASK                   0xff
+
+/* WCD9378_DEM_BYPASS_DATA1 Fields: */
+#define WCD9378_DEM_BYPASS_DATA1_DEM_BYPASS_DATA0_MASK                   0xff
+
+/* WCD9378_DEM_BYPASS_DATA2 Fields: */
+#define WCD9378_DEM_BYPASS_DATA2_DEM_BYPASS_DATA0_MASK                   0xff
+
+/* WCD9378_DEM_BYPASS_DATA3 Fields: */
+#define WCD9378_DEM_BYPASS_DATA3_DEM_BYPASS_DATA0_MASK                   0x03
+
+/* WCD9378_RX0_PCM_RAMP_STEP Fields: */
+#define WCD9378_RX0_PCM_RAMP_STEP_RX0_RAMP_STEP_MASK                     0xff
+
+/* WCD9378_RX0_DSD_RAMP_STEP Fields: */
+#define WCD9378_RX0_DSD_RAMP_STEP_RX0_RAMP_STEP_MASK                     0xff
+
+/* WCD9378_RX1_PCM_RAMP_STEP Fields: */
+#define WCD9378_RX1_PCM_RAMP_STEP_RX1_RAMP_STEP_MASK                     0xff
+
+/* WCD9378_RX1_DSD_RAMP_STEP Fields: */
+#define WCD9378_RX1_DSD_RAMP_STEP_RX1_RAMP_STEP_MASK                     0xff
+
+/* WCD9378_RX2_RAMP_STEP Fields: */
+#define WCD9378_RX2_RAMP_STEP_RX2_RAMP_STEP_MASK                         0xff
+
+/* WCD9378_PLATFORM_CTL Fields: */
+#define WCD9378_PLATFORM_CTL_MODE_MASK                                   0x01
+
+/* WCD9378_CLK_DIV_CFG Fields: */
+#define WCD9378_CLK_DIV_CFG_TX_DIV_EN_MASK                               0x02
+#define WCD9378_CLK_DIV_CFG_RX_DIV_EN_MASK                               0x01
+
+/* WCD9378_DRE_DLY_VAL Fields: */
+#define WCD9378_DRE_DLY_VAL_SWR_HPHR_MASK                                0xf0
+#define WCD9378_DRE_DLY_VAL_SWR_HPHL_MASK                                0x0f
+
+
+/* WCD9378_SYS_USAGE_CTRL Fields: */
+#define WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK                       0x0f
+
+/* WCD9378_SURGE_CTL Fields: */
+#define WCD9378_SURGE_CTL_SURGE_EN_MASK                                  0x01
+
+/* WCD9378_SEQ_CTL Fields: */
+#define WCD9378_SEQ_CTL_TX2_SEQ_SOFT_RST_MASK                            0x10
+#define WCD9378_SEQ_CTL_TX1_SEQ_SOFT_RST_MASK                            0x08
+#define WCD9378_SEQ_CTL_TX0_SEQ_SOFT_RST_MASK                            0x04
+#define WCD9378_SEQ_CTL_SA_SEQ_SOFT_RST_MASK                             0x02
+#define WCD9378_SEQ_CTL_SJ_SEQ_SOFT_RST_MASK                             0x01
+
+/* WCD9378_HPH_UP_T0 Fields: */
+#define WCD9378_HPH_UP_T0_HPH_UP_T0_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T1 Fields: */
+#define WCD9378_HPH_UP_T1_HPH_UP_T1_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T2 Fields: */
+#define WCD9378_HPH_UP_T2_HPH_UP_T2_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T3 Fields: */
+#define WCD9378_HPH_UP_T3_HPH_UP_T3_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T4 Fields: */
+#define WCD9378_HPH_UP_T4_HPH_UP_T4_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T5 Fields: */
+#define WCD9378_HPH_UP_T5_HPH_UP_T5_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T6 Fields: */
+#define WCD9378_HPH_UP_T6_HPH_UP_T6_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T7 Fields: */
+#define WCD9378_HPH_UP_T7_HPH_UP_T7_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T8 Fields: */
+#define WCD9378_HPH_UP_T8_HPH_UP_T8_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T9 Fields: */
+#define WCD9378_HPH_UP_T9_HPH_UP_T9_MASK                                 0x07
+
+/* WCD9378_HPH_UP_T10 Fields: */
+#define WCD9378_HPH_UP_T10_HPH_UP_T10_MASK                               0x07
+
+/* WCD9378_HPH_DN_T0 Fields: */
+#define WCD9378_HPH_DN_T0_HPH_DN_T0_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T1 Fields: */
+#define WCD9378_HPH_DN_T1_HPH_DN_T1_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T2 Fields: */
+#define WCD9378_HPH_DN_T2_HPH_DN_T2_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T3 Fields: */
+#define WCD9378_HPH_DN_T3_HPH_DN_T3_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T4 Fields: */
+#define WCD9378_HPH_DN_T4_HPH_DN_T4_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T5 Fields: */
+#define WCD9378_HPH_DN_T5_HPH_DN_T5_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T6 Fields: */
+#define WCD9378_HPH_DN_T6_HPH_DN_T6_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T7 Fields: */
+#define WCD9378_HPH_DN_T7_HPH_DN_T7_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T8 Fields: */
+#define WCD9378_HPH_DN_T8_HPH_DN_T8_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T9 Fields: */
+#define WCD9378_HPH_DN_T9_HPH_DN_T9_MASK                                 0x07
+
+/* WCD9378_HPH_DN_T10 Fields: */
+#define WCD9378_HPH_DN_T10_HPH_DN_T10_MASK                               0x07
+
+/* WCD9378_HPH_UP_STAGE_LOC_0 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_0_HPH_UP_STAGE_LOC_0_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_1 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_1_HPH_UP_STAGE_LOC_1_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_2 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_2_HPH_UP_STAGE_LOC_2_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_3 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_3_HPH_UP_STAGE_LOC_3_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_4 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_4_HPH_UP_STAGE_LOC_4_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_5 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_5_HPH_UP_STAGE_LOC_5_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_6 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_6_HPH_UP_STAGE_LOC_6_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_7 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_7_HPH_UP_STAGE_LOC_7_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_8 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_8_HPH_UP_STAGE_LOC_8_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_9 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_9_HPH_UP_STAGE_LOC_9_MASK               0x0f
+
+/* WCD9378_HPH_UP_STAGE_LOC_10 Fields: */
+#define WCD9378_HPH_UP_STAGE_LOC_10_HPH_UP_STAGE_LOC_10_MASK             0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_0 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_0_HPH_DN_STAGE_LOC_0_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_1 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_1_HPH_DN_STAGE_LOC_1_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_2 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_2_HPH_DN_STAGE_LOC_2_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_3 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_3_HPH_DN_STAGE_LOC_3_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_4 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_4_HPH_DN_STAGE_LOC_4_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_5 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_5_HPH_DN_STAGE_LOC_5_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_6 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_6_HPH_DN_STAGE_LOC_6_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_7 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_7_HPH_DN_STAGE_LOC_7_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_8 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_8_HPH_DN_STAGE_LOC_8_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_9 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_9_HPH_DN_STAGE_LOC_9_MASK               0x0f
+
+/* WCD9378_HPH_DN_STAGE_LOC_10 Fields: */
+#define WCD9378_HPH_DN_STAGE_LOC_10_HPH_DN_STAGE_LOC_10_MASK             0x0f
+
+/* WCD9378_SA_UP_T0 Fields: */
+#define WCD9378_SA_UP_T0_SA_UP_T0_MASK                                   0x07
+
+/* WCD9378_SA_UP_T1 Fields: */
+#define WCD9378_SA_UP_T1_SA_UP_T1_MASK                                   0x07
+
+/* WCD9378_SA_UP_T2 Fields: */
+#define WCD9378_SA_UP_T2_SA_UP_T2_MASK                                   0x07
+
+/* WCD9378_SA_UP_T3 Fields: */
+#define WCD9378_SA_UP_T3_SA_UP_T3_MASK                                   0x07
+
+/* WCD9378_SA_UP_T4 Fields: */
+#define WCD9378_SA_UP_T4_SA_UP_T4_MASK                                   0x07
+
+/* WCD9378_SA_UP_T5 Fields: */
+#define WCD9378_SA_UP_T5_SA_UP_T5_MASK                                   0x07
+
+/* WCD9378_SA_UP_T6 Fields: */
+#define WCD9378_SA_UP_T6_SA_UP_T6_MASK                                   0x07
+
+/* WCD9378_SA_UP_T7 Fields: */
+#define WCD9378_SA_UP_T7_SA_UP_T7_MASK                                   0x07
+
+/* WCD9378_SA_DN_T0 Fields: */
+#define WCD9378_SA_DN_T0_SA_DN_T0_MASK                                   0x07
+
+/* WCD9378_SA_DN_T1 Fields: */
+#define WCD9378_SA_DN_T1_SA_DN_T1_MASK                                   0x07
+
+/* WCD9378_SA_DN_T2 Fields: */
+#define WCD9378_SA_DN_T2_SA_DN_T2_MASK                                   0x07
+
+/* WCD9378_SA_DN_T3 Fields: */
+#define WCD9378_SA_DN_T3_SA_DN_T3_MASK                                   0x07
+
+/* WCD9378_SA_DN_T4 Fields: */
+#define WCD9378_SA_DN_T4_SA_DN_T4_MASK                                   0x07
+
+/* WCD9378_SA_DN_T5 Fields: */
+#define WCD9378_SA_DN_T5_SA_DN_T5_MASK                                   0x07
+
+/* WCD9378_SA_DN_T6 Fields: */
+#define WCD9378_SA_DN_T6_SA_DN_T6_MASK                                   0x07
+
+/* WCD9378_SA_DN_T7 Fields: */
+#define WCD9378_SA_DN_T7_SA_DN_T7_MASK                                   0x07
+
+/* WCD9378_SA_UP_STAGE_LOC_0 Fields: */
+#define WCD9378_SA_UP_STAGE_LOC_0_SA_UP_STAGE_LOC_0_MASK                 0x07
+
+/* WCD9378_SA_UP_STAGE_LOC_1 Fields: */
+#define WCD9378_SA_UP_STAGE_LOC_1_SA_UP_STAGE_LOC_1_MASK                 0x07
+
+/* WCD9378_SA_UP_STAGE_LOC_2 Fields: */
+#define WCD9378_SA_UP_STAGE_LOC_2_SA_UP_STAGE_LOC_2_MASK                 0x07
+
+/* WCD9378_SA_UP_STAGE_LOC_3 Fields: */
+#define WCD9378_SA_UP_STAGE_LOC_3_SA_UP_STAGE_LOC_3_MASK                 0x07
+
+/* WCD9378_SA_UP_STAGE_LOC_4 Fields: */
+#define WCD9378_SA_UP_STAGE_LOC_4_SA_UP_STAGE_LOC_4_MASK                 0x07
+
+/* WCD9378_SA_UP_STAGE_LOC_5 Fields: */
+#define WCD9378_SA_UP_STAGE_LOC_5_SA_UP_STAGE_LOC_5_MASK                 0x07
+
+/* WCD9378_SA_UP_STAGE_LOC_6 Fields: */
+#define WCD9378_SA_UP_STAGE_LOC_6_SA_UP_STAGE_LOC_6_MASK                 0x07
+
+/* WCD9378_SA_UP_STAGE_LOC_7 Fields: */
+#define WCD9378_SA_UP_STAGE_LOC_7_SA_UP_STAGE_LOC_7_MASK                 0x07
+
+/* WCD9378_SA_DN_STAGE_LOC_0 Fields: */
+#define WCD9378_SA_DN_STAGE_LOC_0_SA_DN_STAGE_LOC_0_MASK                 0x07
+
+/* WCD9378_SA_DN_STAGE_LOC_1 Fields: */
+#define WCD9378_SA_DN_STAGE_LOC_1_SA_DN_STAGE_LOC_1_MASK                 0x07
+
+/* WCD9378_SA_DN_STAGE_LOC_2 Fields: */
+#define WCD9378_SA_DN_STAGE_LOC_2_SA_DN_STAGE_LOC_2_MASK                 0x07
+
+/* WCD9378_SA_DN_STAGE_LOC_3 Fields: */
+#define WCD9378_SA_DN_STAGE_LOC_3_SA_DN_STAGE_LOC_3_MASK                 0x07
+
+/* WCD9378_SA_DN_STAGE_LOC_4 Fields: */
+#define WCD9378_SA_DN_STAGE_LOC_4_SA_DN_STAGE_LOC_4_MASK                 0x07
+
+/* WCD9378_SA_DN_STAGE_LOC_5 Fields: */
+#define WCD9378_SA_DN_STAGE_LOC_5_SA_DN_STAGE_LOC_5_MASK                 0x07
+
+/* WCD9378_SA_DN_STAGE_LOC_6 Fields: */
+#define WCD9378_SA_DN_STAGE_LOC_6_SA_DN_STAGE_LOC_6_MASK                 0x07
+
+/* WCD9378_SA_DN_STAGE_LOC_7 Fields: */
+#define WCD9378_SA_DN_STAGE_LOC_7_SA_DN_STAGE_LOC_7_MASK                 0x07
+
+/* WCD9378_TX0_UP_T0 Fields: */
+#define WCD9378_TX0_UP_T0_TX0_UP_T0_MASK                                 0x07
+
+/* WCD9378_TX0_UP_T1 Fields: */
+#define WCD9378_TX0_UP_T1_TX0_UP_T1_MASK                                 0x07
+
+/* WCD9378_TX0_UP_T2 Fields: */
+#define WCD9378_TX0_UP_T2_TX0_UP_T2_MASK                                 0x07
+
+/* WCD9378_TX0_UP_T3 Fields: */
+#define WCD9378_TX0_UP_T3_TX0_UP_T3_MASK                                 0x07
+
+/* WCD9378_TX0_DN_T0 Fields: */
+#define WCD9378_TX0_DN_T0_TX0_DN_T0_MASK                                 0x07
+
+/* WCD9378_TX0_DN_T1 Fields: */
+#define WCD9378_TX0_DN_T1_TX0_DN_T1_MASK                                 0x07
+
+/* WCD9378_TX0_DN_T2 Fields: */
+#define WCD9378_TX0_DN_T2_TX0_DN_T2_MASK                                 0x07
+
+/* WCD9378_TX0_DN_T3 Fields: */
+#define WCD9378_TX0_DN_T3_TX0_DN_T3_MASK                                 0x07
+
+/* WCD9378_TX0_UP_STAGE_LOC_0 Fields: */
+#define WCD9378_TX0_UP_STAGE_LOC_0_TX0_UP_STAGE_LOC_0_MASK               0x03
+
+/* WCD9378_TX0_UP_STAGE_LOC_1 Fields: */
+#define WCD9378_TX0_UP_STAGE_LOC_1_TX0_UP_STAGE_LOC_1_MASK               0x03
+
+/* WCD9378_TX0_UP_STAGE_LOC_2 Fields: */
+#define WCD9378_TX0_UP_STAGE_LOC_2_TX0_UP_STAGE_LOC_2_MASK               0x03
+
+/* WCD9378_TX0_UP_STAGE_LOC_3 Fields: */
+#define WCD9378_TX0_UP_STAGE_LOC_3_TX0_UP_STAGE_LOC_3_MASK               0x03
+
+/* WCD9378_TX0_DN_STAGE_LOC_0 Fields: */
+#define WCD9378_TX0_DN_STAGE_LOC_0_TX0_DN_STAGE_LOC_0_MASK               0x03
+
+/* WCD9378_TX0_DN_STAGE_LOC_1 Fields: */
+#define WCD9378_TX0_DN_STAGE_LOC_1_TX0_DN_STAGE_LOC_1_MASK               0x03
+
+/* WCD9378_TX0_DN_STAGE_LOC_2 Fields: */
+#define WCD9378_TX0_DN_STAGE_LOC_2_TX0_DN_STAGE_LOC_2_MASK               0x03
+
+/* WCD9378_TX0_DN_STAGE_LOC_3 Fields: */
+#define WCD9378_TX0_DN_STAGE_LOC_3_TX0_DN_STAGE_LOC_3_MASK               0x03
+
+/* WCD9378_TX1_UP_T0 Fields: */
+#define WCD9378_TX1_UP_T0_TX1_UP_T0_MASK                                 0x07
+
+/* WCD9378_TX1_UP_T1 Fields: */
+#define WCD9378_TX1_UP_T1_TX1_UP_T1_MASK                                 0x07
+
+/* WCD9378_TX1_UP_T2 Fields: */
+#define WCD9378_TX1_UP_T2_TX1_UP_T2_MASK                                 0x07
+
+/* WCD9378_TX1_UP_T3 Fields: */
+#define WCD9378_TX1_UP_T3_TX1_UP_T3_MASK                                 0x07
+
+/* WCD9378_TX1_DN_T0 Fields: */
+#define WCD9378_TX1_DN_T0_TX1_DN_T0_MASK                                 0x07
+
+/* WCD9378_TX1_DN_T1 Fields: */
+#define WCD9378_TX1_DN_T1_TX1_DN_T1_MASK                                 0x07
+
+/* WCD9378_TX1_DN_T2 Fields: */
+#define WCD9378_TX1_DN_T2_TX1_DN_T2_MASK                                 0x07
+
+/* WCD9378_TX1_DN_T3 Fields: */
+#define WCD9378_TX1_DN_T3_TX1_DN_T3_MASK                                 0x07
+
+/* WCD9378_TX1_UP_STAGE_LOC_0 Fields: */
+#define WCD9378_TX1_UP_STAGE_LOC_0_TX1_UP_STAGE_LOC_0_MASK               0x03
+
+/* WCD9378_TX1_UP_STAGE_LOC_1 Fields: */
+#define WCD9378_TX1_UP_STAGE_LOC_1_TX1_UP_STAGE_LOC_1_MASK               0x03
+
+/* WCD9378_TX1_UP_STAGE_LOC_2 Fields: */
+#define WCD9378_TX1_UP_STAGE_LOC_2_TX1_UP_STAGE_LOC_2_MASK               0x03
+
+/* WCD9378_TX1_UP_STAGE_LOC_3 Fields: */
+#define WCD9378_TX1_UP_STAGE_LOC_3_TX1_UP_STAGE_LOC_3_MASK               0x03
+
+/* WCD9378_TX1_DN_STAGE_LOC_0 Fields: */
+#define WCD9378_TX1_DN_STAGE_LOC_0_TX1_DN_STAGE_LOC_0_MASK               0x03
+
+/* WCD9378_TX1_DN_STAGE_LOC_1 Fields: */
+#define WCD9378_TX1_DN_STAGE_LOC_1_TX1_DN_STAGE_LOC_1_MASK               0x03
+
+/* WCD9378_TX1_DN_STAGE_LOC_2 Fields: */
+#define WCD9378_TX1_DN_STAGE_LOC_2_TX1_DN_STAGE_LOC_2_MASK               0x03
+
+/* WCD9378_TX1_DN_STAGE_LOC_3 Fields: */
+#define WCD9378_TX1_DN_STAGE_LOC_3_TX1_DN_STAGE_LOC_3_MASK               0x03
+
+/* WCD9378_TX2_UP_T0 Fields: */
+#define WCD9378_TX2_UP_T0_TX2_UP_T0_MASK                                 0x07
+
+/* WCD9378_TX2_UP_T1 Fields: */
+#define WCD9378_TX2_UP_T1_TX2_UP_T1_MASK                                 0x07
+
+/* WCD9378_TX2_UP_T2 Fields: */
+#define WCD9378_TX2_UP_T2_TX2_UP_T2_MASK                                 0x07
+
+/* WCD9378_TX2_UP_T3 Fields: */
+#define WCD9378_TX2_UP_T3_TX2_UP_T3_MASK                                 0x07
+
+/* WCD9378_TX2_DN_T0 Fields: */
+#define WCD9378_TX2_DN_T0_TX2_DN_T0_MASK                                 0x07
+
+/* WCD9378_TX2_DN_T1 Fields: */
+#define WCD9378_TX2_DN_T1_TX2_DN_T1_MASK                                 0x07
+
+/* WCD9378_TX2_DN_T2 Fields: */
+#define WCD9378_TX2_DN_T2_TX2_DN_T2_MASK                                 0x07
+
+/* WCD9378_TX2_DN_T3 Fields: */
+#define WCD9378_TX2_DN_T3_TX2_DN_T3_MASK                                 0x07
+
+/* WCD9378_TX2_UP_STAGE_LOC_0 Fields: */
+#define WCD9378_TX2_UP_STAGE_LOC_0_TX2_UP_STAGE_LOC_0_MASK               0x03
+
+/* WCD9378_TX2_UP_STAGE_LOC_1 Fields: */
+#define WCD9378_TX2_UP_STAGE_LOC_1_TX2_UP_STAGE_LOC_1_MASK               0x03
+
+/* WCD9378_TX2_UP_STAGE_LOC_2 Fields: */
+#define WCD9378_TX2_UP_STAGE_LOC_2_TX2_UP_STAGE_LOC_2_MASK               0x03
+
+/* WCD9378_TX2_UP_STAGE_LOC_3 Fields: */
+#define WCD9378_TX2_UP_STAGE_LOC_3_TX2_UP_STAGE_LOC_3_MASK               0x03
+
+/* WCD9378_TX2_DN_STAGE_LOC_0 Fields: */
+#define WCD9378_TX2_DN_STAGE_LOC_0_TX2_DN_STAGE_LOC_0_MASK               0x03
+
+/* WCD9378_TX2_DN_STAGE_LOC_1 Fields: */
+#define WCD9378_TX2_DN_STAGE_LOC_1_TX2_DN_STAGE_LOC_1_MASK               0x03
+
+/* WCD9378_TX2_DN_STAGE_LOC_2 Fields: */
+#define WCD9378_TX2_DN_STAGE_LOC_2_TX2_DN_STAGE_LOC_2_MASK               0x03
+
+/* WCD9378_TX2_DN_STAGE_LOC_3 Fields: */
+#define WCD9378_TX2_DN_STAGE_LOC_3_TX2_DN_STAGE_LOC_3_MASK               0x03
+
+/* WCD9378_SEQ_HPH_STAT Fields: */
+#define WCD9378_SEQ_HPH_STAT_HPH_FUNC_FAULTY_MASK                        0x04
+#define WCD9378_SEQ_HPH_STAT_HPH_PWR_UP_RDY_MASK                         0x02
+#define WCD9378_SEQ_HPH_STAT_HPH_PWR_DN_RDY_MASK                         0x01
+
+/* WCD9378_SEQ_SA_STAT Fields: */
+#define WCD9378_SEQ_SA_STAT_SA_PWR_UP_RDY_MASK                           0x02
+#define WCD9378_SEQ_SA_STAT_SA_PWR_DN_RDY_MASK                           0x01
+
+/* WCD9378_SEQ_TX0_STAT Fields: */
+#define WCD9378_SEQ_TX0_STAT_TX0_PWR_UP_RDY_MASK                         0x02
+#define WCD9378_SEQ_TX0_STAT_TX0_PWR_DN_RDY_MASK                         0x01
+
+/* WCD9378_SEQ_TX1_STAT Fields: */
+#define WCD9378_SEQ_TX1_STAT_TX1_FUNC_FAULTY_MASK                        0x04
+#define WCD9378_SEQ_TX1_STAT_TX1_PWR_UP_RDY_MASK                         0x02
+#define WCD9378_SEQ_TX1_STAT_TX1_PWR_DN_RDY_MASK                         0x01
+
+/* WCD9378_SEQ_TX2_STAT Fields: */
+#define WCD9378_SEQ_TX2_STAT_TX2_PWR_UP_RDY_MASK                         0x02
+#define WCD9378_SEQ_TX2_STAT_TX2_PWR_DN_RDY_MASK                         0x01
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_0 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_0_MICB_REMAP_TABLE_VAL_0_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_1 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_1_MICB_REMAP_TABLE_VAL_1_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_2 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_2_MICB_REMAP_TABLE_VAL_2_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_3 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_4 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_5 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_6 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_6_MICB_REMAP_TABLE_VAL_6_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_7 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_7_MICB_REMAP_TABLE_VAL_7_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_8 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_8_MICB_REMAP_TABLE_VAL_8_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_9 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_9_MICB_REMAP_TABLE_VAL_9_MASK       0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_10 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_10_MICB_REMAP_TABLE_VAL_10_MASK     0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_11 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_11_MICB_REMAP_TABLE_VAL_11_MASK     0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_12 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_12_MICB_REMAP_TABLE_VAL_12_MASK     0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_13 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_13_MICB_REMAP_TABLE_VAL_13_MASK     0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_14 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_14_MICB_REMAP_TABLE_VAL_14_MASK     0xff
+
+/* WCD9378_MICB_REMAP_TABLE_VAL_15 Fields: */
+#define WCD9378_MICB_REMAP_TABLE_VAL_15_MICB_REMAP_TABLE_VAL_15_MASK     0xff
+
+/* WCD9378_SM0_MB_SEL Fields: */
+#define WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK                               0x03
+
+/* WCD9378_SM1_MB_SEL Fields: */
+#define WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK                               0x03
+
+/* WCD9378_SM2_MB_SEL Fields: */
+#define WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK                               0x03
+
+/* WCD9378_MB_PULLUP_EN Fields: */
+#define WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK                 0x04
+#define WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK                 0x02
+#define WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK                 0x01
+
+/* WCD9378_BYP_EN_CTL0 Fields: */
+#define WCD9378_BYP_EN_CTL0_TX2_SEQ_BYP_EN_MASK                          0x10
+#define WCD9378_BYP_EN_CTL0_TX1_SEQ_BYP_EN_MASK                          0x08
+#define WCD9378_BYP_EN_CTL0_TX0_SEQ_BYP_EN_MASK                          0x04
+#define WCD9378_BYP_EN_CTL0_SA_SEQ_BYP_EN_MASK                           0x02
+#define WCD9378_BYP_EN_CTL0_HPH_SEQ_BYP_EN_MASK                          0x01
+
+/* WCD9378_BYP_EN_CTL1 Fields: */
+#define WCD9378_BYP_EN_CTL1_SYS_USAGE_BYP_EN_MASK                        0x04
+#define WCD9378_BYP_EN_CTL1_SDCA_BYP_EN_MASK                             0x02
+#define WCD9378_BYP_EN_CTL1_DIG_SEQ_BYP_EN_MASK                          0x01
+
+/* WCD9378_BYP_EN_CTL2 Fields: */
+#define WCD9378_BYP_EN_CTL2_RX_CLK_BYP_EN_MASK                           0x80
+#define WCD9378_BYP_EN_CTL2_TX_CLK_BANK1_BYP_EN_MASK                     0x40
+#define WCD9378_BYP_EN_CTL2_TX_CLK_BANK0_BYP_EN_MASK                     0x20
+#define WCD9378_BYP_EN_CTL2_HPH_VALID_CFG_BYP_EN_MASK                    0x10
+#define WCD9378_BYP_EN_CTL2_SA_VALID_CFG_BYP_EN_MASK                     0x08
+#define WCD9378_BYP_EN_CTL2_TX2_VALID_CFG_BYP_EN_MASK                    0x04
+#define WCD9378_BYP_EN_CTL2_TX1_VALID_CFG_BYP_EN_MASK                    0x02
+#define WCD9378_BYP_EN_CTL2_TX0_VALID_CFG_BYP_EN_MASK                    0x01
+
+/* WCD9378_SEQ_OVRRIDE_CTL0 Fields: */
+#define WCD9378_SEQ_OVRRIDE_CTL0_HPHR_COMP_EN_OVR_MASK                   0x80
+#define WCD9378_SEQ_OVRRIDE_CTL0_HPHL_COMP_EN_OVR_MASK                   0x40
+#define WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK                     0x20
+#define WCD9378_SEQ_OVRRIDE_CTL0_TX2_SEQ_EN_OVR_MASK                     0x10
+#define WCD9378_SEQ_OVRRIDE_CTL0_TX1_SEQ_EN_OVR_MASK                     0x08
+#define WCD9378_SEQ_OVRRIDE_CTL0_TX0_SEQ_EN_OVR_MASK                     0x04
+#define WCD9378_SEQ_OVRRIDE_CTL0_SA_SEQ_EN_OVR_MASK                      0x02
+#define WCD9378_SEQ_OVRRIDE_CTL0_HPH_SEQ_EN_OVR_MASK                     0x01
+
+/* WCD9378_SEQ_OVRRIDE_CTL1 Fields: */
+#define WCD9378_SEQ_OVRRIDE_CTL1_RX2_MUTE_OVR_MASK                       0x80
+#define WCD9378_SEQ_OVRRIDE_CTL1_RX1_MUTE_OVR_MASK                       0x40
+#define WCD9378_SEQ_OVRRIDE_CTL1_RX0_MUTE_OVR_MASK                       0x20
+#define WCD9378_SEQ_OVRRIDE_CTL1_TX2_SEQ_TRIGGER_OVR_MASK                0x10
+#define WCD9378_SEQ_OVRRIDE_CTL1_TX1_SEQ_TRIGGER_OVR_MASK                0x08
+#define WCD9378_SEQ_OVRRIDE_CTL1_TX0_SEQ_TRIGGER_OVR_MASK                0x04
+#define WCD9378_SEQ_OVRRIDE_CTL1_SA_SEQ_TRIGGER_OVR_MASK                 0x02
+#define WCD9378_SEQ_OVRRIDE_CTL1_HPH_SEQ_TRIGGER_OVR_MASK                0x01
+
+/* WCD9378_SEQ_OVRRIDE_CTL2 Fields: */
+#define WCD9378_SEQ_OVRRIDE_CTL2_TX2_VALID_CFG_OVR_MASK                  0x40
+#define WCD9378_SEQ_OVRRIDE_CTL2_TX1_VALID_CFG_OVR_MASK                  0x20
+#define WCD9378_SEQ_OVRRIDE_CTL2_TX0_VALID_CFG_OVR_MASK                  0x10
+#define WCD9378_SEQ_OVRRIDE_CTL2_SA_VALID_CFG_OVR_MASK                   0x08
+#define WCD9378_SEQ_OVRRIDE_CTL2_HPH_VALID_CFG_OVR_MASK                  0x04
+#define WCD9378_SEQ_OVRRIDE_CTL2_SJ_USAGE_OVR_MASK                       0x03
+
+/* WCD9378_HPH_SEQ_OVRRIDE_CTL0 Fields: */
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0_ANA_CLKS_EN_MASK                    0x80
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0_DIG_CLKS_EN_MASK                    0x40
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0_RX_BIAS_EN_MASK                     0x20
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0_NCP_EN_MASK                         0x10
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0_CLASSG_CP_EN_MASK                   0x08
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0_ACT_DET_EN_MASK                     0x04
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0_PAS_EN_MASK                         0x02
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0_ACTUAL_PS_MASK                      0x01
+
+/* WCD9378_HPH_SEQ_OVRRIDE_CTL1 Fields: */
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL1_HREF_EN_MASK                        0x04
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL1_SET_POWER_LEVEL_MASK                0x02
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL1_AUTOCHOP_TIMER_CTL_EN_MASK          0x01
+
+/* WCD9378_SA_SEQ_OVRRIDE_CTL Fields: */
+#define WCD9378_SA_SEQ_OVRRIDE_CTL_ANA_CLKS_EN_MASK                      0x80
+#define WCD9378_SA_SEQ_OVRRIDE_CTL_DIG_CLKS_EN_MASK                      0x40
+#define WCD9378_SA_SEQ_OVRRIDE_CTL_RX_BIAS_EN_MASK                       0x20
+#define WCD9378_SA_SEQ_OVRRIDE_CTL_NCP_EN_MASK                           0x10
+#define WCD9378_SA_SEQ_OVRRIDE_CTL_CLASSG_CP_EN_MASK                     0x08
+#define WCD9378_SA_SEQ_OVRRIDE_CTL_ACT_DET_EN_MASK                       0x04
+#define WCD9378_SA_SEQ_OVRRIDE_CTL_PAS_EN_MASK                           0x02
+#define WCD9378_SA_SEQ_OVRRIDE_CTL_ACTUAL_PS_MASK                        0x01
+
+/* WCD9378_TX0_SEQ_OVRRIDE_CTL Fields: */
+#define WCD9378_TX0_SEQ_OVRRIDE_CTL_TX0_TXDN_CLK_EN_MASK                 0x08
+#define WCD9378_TX0_SEQ_OVRRIDE_CTL_TX0_SET_POWER_LEVEL_MASK             0x04
+#define WCD9378_TX0_SEQ_OVRRIDE_CTL_TX0_HPF_INIT_MASK                    0x02
+#define WCD9378_TX0_SEQ_OVRRIDE_CTL_ACTUAL_PS_MASK                       0x01
+
+/* WCD9378_TX1_SEQ_OVRRIDE_CTL Fields: */
+#define WCD9378_TX1_SEQ_OVRRIDE_CTL_TX1_TXDN_CLK_EN_MASK                 0x08
+#define WCD9378_TX1_SEQ_OVRRIDE_CTL_TX1_SET_POWER_LEVEL_MASK             0x04
+#define WCD9378_TX1_SEQ_OVRRIDE_CTL_TX1_HPF_INIT_MASK                    0x02
+#define WCD9378_TX1_SEQ_OVRRIDE_CTL_ACTUAL_PS_MASK                       0x01
+
+/* WCD9378_TX2_SEQ_OVRRIDE_CTL Fields: */
+#define WCD9378_TX2_SEQ_OVRRIDE_CTL_TX2_TXDN_CLK_EN_MASK                 0x08
+#define WCD9378_TX2_SEQ_OVRRIDE_CTL_TX2_SET_POWER_LEVEL_MASK             0x04
+#define WCD9378_TX2_SEQ_OVRRIDE_CTL_TX2_HPF_INIT_MASK                    0x02
+#define WCD9378_TX2_SEQ_OVRRIDE_CTL_ACTUAL_PS_MASK                       0x01
+
+/* WCD9378_FORCE_CTL Fields: */
+#define WCD9378_FORCE_CTL_FORCE_CLASSG_CP_EN_MASK                        0x20
+#define WCD9378_FORCE_CTL_FORCE_NCP_EN_MASK                              0x10
+#define WCD9378_FORCE_CTL_FORCE_RX_BIAS_EN_MASK                          0x08
+#define WCD9378_FORCE_CTL_FORCE_ANA_DIV4_EN_MASK                         0x04
+#define WCD9378_FORCE_CTL_FORCE_ANA_DIV2_EN_MASK                         0x02
+#define WCD9378_FORCE_CTL_FORCE_ANA_DIV1_EN_MASK                         0x01
+
+
+/* WCD9378_DEVICE_DET Fields: */
+#define WCD9378_DEVICE_DET_ACCESSORY_TYPE_MASK                           0x07
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0_TYPE0_WRAP_OSCNX_TPRESS_MIN_0_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0_TYPE0_WRAP_OSCNX_TPRESS_MAX_0_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0_MASK 0x0f
+
+/* WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0_MASK 0x01
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1_TYPE0_WRAP_OSCNX_TPRESS_MIN_1_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1_TYPE0_WRAP_OSCNX_TPRESS_MAX_1_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1_MASK 0x0f
+
+/* WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1_MASK 0x01
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2_TYPE0_WRAP_OSCNX_TPRESS_MIN_2_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2_TYPE0_WRAP_OSCNX_TPRESS_MAX_2_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2_MASK 0x0f
+
+/* WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2_MASK 0x01
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3_TYPE0_WRAP_OSCNX_TPRESS_MIN_3_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3_TYPE0_WRAP_OSCNX_TPRESS_MAX_3_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3_MASK 0xff
+
+/* WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3_MASK 0x0f
+
+/* WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3 Fields: */
+#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3_MASK 0x01
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0_TYPE1_WRAP_OSCNX_TPRESS_MIN_0_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0_TYPE1_WRAP_OSCNX_TPRESS_MAX_0_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0_MASK 0x01
+
+/* WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0_TYPE1_WRAP_HOLD_TPRESS_MIN_0_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0_TYPE1_WRAP_HOLD_TRELEASE_MIN_0_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0 Fields: */
+#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0_TYPE1_WRAP_RO_TDEBOUNCE_0_MASK 0x1f
+
+/* WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0 Fields: */
+#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0 Fields: */
+#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0_TYPE1_WRAP_RTC_OOC_SEL_0_MASK   0x01
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1_TYPE1_WRAP_OSCNX_TPRESS_MIN_1_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1_TYPE1_WRAP_OSCNX_TPRESS_MAX_1_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1_MASK 0x01
+
+/* WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1_TYPE1_WRAP_HOLD_TPRESS_MIN_1_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1_TYPE1_WRAP_HOLD_TRELEASE_MIN_1_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1 Fields: */
+#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1_TYPE1_WRAP_RO_TDEBOUNCE_1_MASK 0x1f
+
+/* WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1 Fields: */
+#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1 Fields: */
+#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1_TYPE1_WRAP_RTC_OOC_SEL_1_MASK   0x01
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2_TYPE1_WRAP_OSCNX_TPRESS_MIN_2_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2_TYPE1_WRAP_OSCNX_TPRESS_MAX_2_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2_MASK 0x01
+
+/* WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2_TYPE1_WRAP_HOLD_TPRESS_MIN_2_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2_TYPE1_WRAP_HOLD_TRELEASE_MIN_2_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2 Fields: */
+#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2_TYPE1_WRAP_RO_TDEBOUNCE_2_MASK 0x1f
+
+/* WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2 Fields: */
+#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2 Fields: */
+#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2_TYPE1_WRAP_RTC_OOC_SEL_2_MASK   0x01
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3_TYPE1_WRAP_OSCNX_TPRESS_MIN_3_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3_TYPE1_WRAP_OSCNX_TPRESS_MAX_3_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3 Fields: */
+#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3_MASK 0x01
+
+/* WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3_TYPE1_WRAP_HOLD_TPRESS_MIN_3_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3_TYPE1_WRAP_HOLD_TRELEASE_MIN_3_MASK 0xff
+
+/* WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3 Fields: */
+#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3 Fields: */
+#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3_TYPE1_WRAP_RO_TDEBOUNCE_3_MASK 0x1f
+
+/* WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3 Fields: */
+#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3_MASK 0x0f
+
+/* WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3 Fields: */
+#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3_TYPE1_WRAP_RTC_OOC_SEL_3_MASK   0x01
+
+/* WCD9378_SDCA_MESSAGE_GATE Fields: */
+#define WCD9378_SDCA_MESSAGE_GATE_CLAMP_ELEC_SEL_MASK                    0x01
+
+/* WCD9378_MBHC_DATA_IN_EDGE Fields: */
+#define WCD9378_MBHC_DATA_IN_EDGE_RISE_EDGE_EN_MASK                      0x01
+
+/* WCD9378_MBHC_RESET Fields: */
+#define WCD9378_MBHC_RESET_SOFT_RST_MASK                                 0x01
+
+/* WCD9378_MBHC_DEBUG Fields: */
+#define WCD9378_MBHC_DEBUG_UMP_WR_NO_STOP_EN_MASK                        0x02
+#define WCD9378_MBHC_DEBUG_UMP_RD_ALL_EN_MASK                            0x01
+
+/* WCD9378_MBHC_DEBUG_UMP_0 Fields: */
+#define WCD9378_MBHC_DEBUG_UMP_0_UMP_DATA_IN_7_0_MASK                    0xff
+
+/* WCD9378_MBHC_DEBUG_UMP_1 Fields: */
+#define WCD9378_MBHC_DEBUG_UMP_1_UMP_DATA_IN_15_8_MASK                   0xff
+
+/* WCD9378_MBHC_DEBUG_UMP_2 Fields: */
+#define WCD9378_MBHC_DEBUG_UMP_2_UMP_DATA_IN_23_16_MASK                  0xff
+
+
+/* WCD9378_HID_FUNC_EXT_ID_0 Fields: */
+#define WCD9378_HID_FUNC_EXT_ID_0_FUNC_EXT_ID_0_MASK                     0xff
+
+/* WCD9378_HID_FUNC_EXT_ID_1 Fields: */
+#define WCD9378_HID_FUNC_EXT_ID_1_FUNC_EXT_ID_1_MASK                     0xff
+
+/* WCD9378_HID_FUNC_EXT_VER Fields: */
+#define WCD9378_HID_FUNC_EXT_VER_FUNC_EXT_VER_MASK                       0xff
+
+/* WCD9378_HID_FUNC_STAT Fields: */
+#define WCD9378_HID_FUNC_STAT_FUNC_STAT_MASK                             0xff
+
+/* WCD9378_HID_CUR_OWNER Fields: */
+#define WCD9378_HID_CUR_OWNER_HID_CUR_OWNER_MASK                         0x01
+
+/* WCD9378_HID_MSG_OFFSET Fields: */
+#define WCD9378_HID_MSG_OFFSET_HID_MSG_OFFSET_MASK                       0xffffffff
+
+/* WCD9378_HID_MSG_LENGTH Fields: */
+#define WCD9378_HID_MSG_LENGTH_HID_MSG_LENGTH_MASK                       0xffffffff
+
+/* WCD9378_HID_DEV_MANU_ID_0 Fields: */
+#define WCD9378_HID_DEV_MANU_ID_0_DEV_MANU_ID_0_MASK                     0xff
+
+/* WCD9378_HID_DEV_MANU_ID_1 Fields: */
+#define WCD9378_HID_DEV_MANU_ID_1_DEV_MANU_ID_1_MASK                     0xff
+
+/* WCD9378_HID_DEV_PART_ID_0 Fields: */
+#define WCD9378_HID_DEV_PART_ID_0_DEV_PART_ID_0_MASK                     0xff
+
+/* WCD9378_HID_DEV_PART_ID_1 Fields: */
+#define WCD9378_HID_DEV_PART_ID_1_DEV_PART_ID_1_MASK                     0xff
+
+/* WCD9378_HID_DEV_VER Fields: */
+#define WCD9378_HID_DEV_VER_DEV_VER_MASK                                 0xff
+
+
+/* WCD9378_SMP_AMP_FUNC_EXT_ID_0 Fields: */
+#define WCD9378_SMP_AMP_FUNC_EXT_ID_0_FUNC_EXT_ID_0_MASK                 0xff
+
+/* WCD9378_SMP_AMP_FUNC_EXT_ID_1 Fields: */
+#define WCD9378_SMP_AMP_FUNC_EXT_ID_1_FUNC_EXT_ID_1_MASK                 0xff
+
+/* WCD9378_SMP_AMP_FUNC_EXT_VER Fields: */
+#define WCD9378_SMP_AMP_FUNC_EXT_VER_FUNC_EXT_VER_MASK                   0xff
+
+/* WCD9378_XU22_BYP Fields: */
+#define WCD9378_XU22_BYP_XU22_BYP_MASK                                   0x01
+
+/* WCD9378_PDE22_REQ_PS Fields: */
+#define WCD9378_PDE22_REQ_PS_PDE22_REQ_PS_MASK                           0xff
+
+/* WCD9378_FU23_MUTE Fields: */
+#define WCD9378_FU23_MUTE_FU23_MUTE_MASK                                 0x01
+
+/* WCD9378_PDE23_REQ_PS Fields: */
+#define WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK                           0xff
+
+/* WCD9378_SMP_AMP_FUNC_STAT Fields: */
+#define WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK                         0xff
+
+/* WCD9378_FUNC_ACT Fields: */
+#define WCD9378_FUNC_ACT_FUNC_ACT_MASK                                   0x01
+
+/* WCD9378_PDE22_ACT_PS Fields: */
+#define WCD9378_PDE22_ACT_PS_PDE22_ACT_PS_MASK                           0xff
+
+/* WCD9378_SAPU29_PROT_MODE Fields: */
+#define WCD9378_SAPU29_PROT_MODE_SAPU29_PROT_MODE_MASK                   0xff
+
+/* WCD9378_SAPU29_PROT_STAT Fields: */
+#define WCD9378_SAPU29_PROT_STAT_SAPU29_PROT_STAT_MASK                   0xff
+
+/* WCD9378_PDE23_ACT_PS Fields: */
+#define WCD9378_PDE23_ACT_PS_PDE23_ACT_PS_MASK                           0xff
+
+/* WCD9378_SMP_AMP_DEV_MANU_ID_0 Fields: */
+#define WCD9378_SMP_AMP_DEV_MANU_ID_0_DEV_MANU_ID_0_MASK                 0xff
+
+/* WCD9378_SMP_AMP_DEV_MANU_ID_1 Fields: */
+#define WCD9378_SMP_AMP_DEV_MANU_ID_1_DEV_MANU_ID_1_MASK                 0xff
+
+/* WCD9378_SMP_AMP_DEV_PART_ID_0 Fields: */
+#define WCD9378_SMP_AMP_DEV_PART_ID_0_DEV_PART_ID_0_MASK                 0xff
+
+/* WCD9378_SMP_AMP_DEV_PART_ID_1 Fields: */
+#define WCD9378_SMP_AMP_DEV_PART_ID_1_DEV_PART_ID_1_MASK                 0xff
+
+/* WCD9378_SMP_AMP_DEV_VER Fields: */
+#define WCD9378_SMP_AMP_DEV_VER_DEV_VER_MASK                             0xff
+
+
+/* WCD9378_CMT_GRP_MASK Fields: */
+#define WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK                           0xff
+
+/* WCD9378_SMP_JACK_FUNC_EXT_ID_0 Fields: */
+#define WCD9378_SMP_JACK_FUNC_EXT_ID_0_FUNC_EXT_ID_0_MASK                0xff
+
+/* WCD9378_SMP_JACK_FUNC_EXT_ID_1 Fields: */
+#define WCD9378_SMP_JACK_FUNC_EXT_ID_1_FUNC_EXT_ID_1_MASK                0xff
+
+/* WCD9378_SMP_JACK_FUNC_EXT_VER Fields: */
+#define WCD9378_SMP_JACK_FUNC_EXT_VER_FUNC_EXT_VER_MASK                  0xff
+
+/* WCD9378_IT41_USAGE Fields: */
+#define WCD9378_IT41_USAGE_IT41_USAGE_MASK                               0xff
+
+/* WCD9378_XU42_BYP Fields: */
+#define WCD9378_XU42_BYP_XU42_BYP_MASK                                   0x01
+
+/* WCD9378_PDE42_REQ_PS Fields: */
+#define WCD9378_PDE42_REQ_PS_PDE42_REQ_PS_MASK                           0xff
+
+/* WCD9378_FU42_MUTE_CH1 Fields: */
+#define WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK                         0x01
+
+/* WCD9378_FU42_MUTE_CH2 Fields: */
+#define WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK                         0x01
+
+/* WCD9378_FU42_CH_VOL_CH1 Fields: */
+#define WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK                     0xffff
+
+/* WCD9378_FU42_CH_VOL_CH2 Fields: */
+#define WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK                     0xffff
+
+/* WCD9378_SU43_SELECTOR Fields: */
+#define WCD9378_SU43_SELECTOR_SU43_SELECTOR_MASK                         0x01
+
+/* WCD9378_SU45_SELECTOR Fields: */
+#define WCD9378_SU45_SELECTOR_SU45_SELECTOR_MASK                         0x01
+
+/* WCD9378_PDE47_REQ_PS Fields: */
+#define WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK                           0xff
+
+/* WCD9378_GE35_SEL_MODE Fields: */
+#define WCD9378_GE35_SEL_MODE_GE35_SEL_MODE_MASK                         0xff
+
+/* WCD9378_GE35_DET_MODE Fields: */
+#define WCD9378_GE35_DET_MODE_GE35_DET_MODE_MASK                         0xff
+
+/* WCD9378_IT31_MICB Fields: */
+#define WCD9378_IT31_MICB_IT31_MICB_MASK                                 0xff
+
+/* WCD9378_IT31_USAGE Fields: */
+#define WCD9378_IT31_USAGE_IT31_USAGE_MASK                               0xff
+
+/* WCD9378_PDE34_REQ_PS Fields: */
+#define WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK                           0xff
+
+/* WCD9378_SU45_TX_SELECTOR Fields: */
+#define WCD9378_SU45_TX_SELECTOR_SU45_TX_SELECTOR_MASK                   0x01
+
+/* WCD9378_XU36_BYP Fields: */
+#define WCD9378_XU36_BYP_XU36_BYP_MASK                                   0x01
+
+/* WCD9378_PDE36_REQ_PS Fields: */
+#define WCD9378_PDE36_REQ_PS_PDE36_REQ_PS_MASK                           0xff
+
+/* WCD9378_OT36_USAGE Fields: */
+#define WCD9378_OT36_USAGE_OT36_USAGE_MASK                               0xff
+
+/* WCD9378_SMP_JACK_FUNC_STAT Fields: */
+#define WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK                        0xff
+
+/* WCD9378_SMP_JACK_FUNC_ACT Fields: */
+#define WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK                          0x01
+
+/* WCD9378_PDE42_ACT_PS Fields: */
+#define WCD9378_PDE42_ACT_PS_PDE42_ACT_PS_MASK                           0xff
+
+/* WCD9378_PDE47_ACT_PS Fields: */
+#define WCD9378_PDE47_ACT_PS_PDE47_ACT_PS_MASK                           0xff
+
+/* WCD9378_PDE34_ACT_PS Fields: */
+#define WCD9378_PDE34_ACT_PS_PDE34_ACT_PS_MASK                           0xff
+
+/* WCD9378_PDE36_ACT_PS Fields: */
+#define WCD9378_PDE36_ACT_PS_PDE36_ACT_PS_MASK                           0xff
+
+/* WCD9378_SMP_JACK_DEV_MANU_ID_0 Fields: */
+#define WCD9378_SMP_JACK_DEV_MANU_ID_0_DEV_MANU_ID_0_MASK                0xff
+
+/* WCD9378_SMP_JACK_DEV_MANU_ID_1 Fields: */
+#define WCD9378_SMP_JACK_DEV_MANU_ID_1_DEV_MANU_ID_1_MASK                0xff
+
+/* WCD9378_SMP_JACK_DEV_PART_ID_0 Fields: */
+#define WCD9378_SMP_JACK_DEV_PART_ID_0_DEV_PART_ID_0_MASK                0xff
+
+/* WCD9378_SMP_JACK_DEV_PART_ID_1 Fields: */
+#define WCD9378_SMP_JACK_DEV_PART_ID_1_DEV_PART_ID_1_MASK                0xff
+
+/* WCD9378_SMP_JACK_DEV_VER Fields: */
+#define WCD9378_SMP_JACK_DEV_VER_DEV_VER_MASK                            0xff
+
+
+/* WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0_FUNC_EXT_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1_FUNC_EXT_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER Fields: */
+#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER_FUNC_EXT_VER_MASK             0xff
+
+/* WCD9378_IT11_MICB Fields: */
+#define WCD9378_IT11_MICB_IT11_MICB_MASK                                 0xff
+
+/* WCD9378_IT11_USAGE Fields: */
+#define WCD9378_IT11_USAGE_IT11_USAGE_MASK                               0xff
+
+/* WCD9378_PDE11_REQ_PS Fields: */
+#define WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK                           0xff
+
+/* WCD9378_OT10_USAGE Fields: */
+#define WCD9378_OT10_USAGE_OT10_USAGE_MASK                               0xff
+
+/* WCD9378_SMP_MIC_CTRL0_FUNC_STAT Fields: */
+#define WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK                   0xff
+
+/* WCD9378_SMP_MIC_CTRL0_FUNC_ACT Fields: */
+#define WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK                     0x01
+
+/* WCD9378_PDE11_ACT_PS Fields: */
+#define WCD9378_PDE11_ACT_PS_PDE11_ACT_PS_MASK                           0xff
+
+/* WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0_DEV_MANU_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1_DEV_MANU_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0_DEV_PART_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1_DEV_PART_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL0_DEV_VER Fields: */
+#define WCD9378_SMP_MIC_CTRL0_DEV_VER_DEV_VER_MASK                       0xff
+
+
+/* WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0_FUNC_EXT_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1_FUNC_EXT_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER Fields: */
+#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER_FUNC_EXT_VER_MASK             0xff
+
+/* WCD9378_SMP_MIC_CTRL1_IT11_MICB Fields: */
+#define WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK                   0xff
+
+/* WCD9378_SMP_MIC_CTRL1_IT11_USAGE Fields: */
+#define WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK                 0xff
+
+/* WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS Fields: */
+#define WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK             0xff
+
+/* WCD9378_SMP_MIC_CTRL1_OT10_USAGE Fields: */
+#define WCD9378_SMP_MIC_CTRL1_OT10_USAGE_OT10_USAGE_MASK                 0xff
+
+/* WCD9378_SMP_MIC_CTRL1_FUNC_STAT Fields: */
+#define WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK                   0xff
+
+/* WCD9378_SMP_MIC_CTRL1_FUNC_ACT Fields: */
+#define WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK                     0x01
+
+/* WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS Fields: */
+#define WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS_PDE11_ACT_PS_MASK             0xff
+
+/* WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0_DEV_MANU_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1_DEV_MANU_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0_DEV_PART_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1_DEV_PART_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL1_DEV_VER Fields: */
+#define WCD9378_SMP_MIC_CTRL1_DEV_VER_DEV_VER_MASK                       0xff
+
+
+/* WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0_FUNC_EXT_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1_FUNC_EXT_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER Fields: */
+#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER_FUNC_EXT_VER_MASK             0xff
+
+/* WCD9378_SMP_MIC_CTRL2_IT11_MICB Fields: */
+#define WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK                   0xff
+
+/* WCD9378_SMP_MIC_CTRL2_IT11_USAGE Fields: */
+#define WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK                 0xff
+
+/* WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS Fields: */
+#define WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK             0xff
+
+/* WCD9378_SMP_MIC_CTRL2_OT10_USAGE Fields: */
+#define WCD9378_SMP_MIC_CTRL2_OT10_USAGE_OT10_USAGE_MASK                 0xff
+
+/* WCD9378_SMP_MIC_CTRL2_FUNC_STAT Fields: */
+#define WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK                   0xff
+
+/* WCD9378_SMP_MIC_CTRL2_FUNC_ACT Fields: */
+#define WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK                     0x01
+
+/* WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS Fields: */
+#define WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS_PDE11_ACT_PS_MASK             0xff
+
+/* WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0_DEV_MANU_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1_DEV_MANU_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0 Fields: */
+#define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0_DEV_PART_ID_0_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1 Fields: */
+#define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1_DEV_PART_ID_1_MASK           0xff
+
+/* WCD9378_SMP_MIC_CTRL2_DEV_VER Fields: */
+#define WCD9378_SMP_MIC_CTRL2_DEV_VER_DEV_VER_MASK                       0xff
+
+
+/* WCD9378_REPORT_ID Fields: */
+#define WCD9378_REPORT_ID_REPORT_ID_MASK                                 0xff
+
+/* WCD9378_MESSAGE0 Fields: */
+#define WCD9378_MESSAGE0_MESSAGE0_MASK                                   0xff
+
+/* WCD9378_MESSAGE1 Fields: */
+#define WCD9378_MESSAGE1_MESSAGE1_MASK                                   0xff
+
+/* WCD9378_MESSAGE2 Fields: */
+#define WCD9378_MESSAGE2_MESSAGE2_MASK                                   0xff
+
+
+#endif /* WCD9378_REG_MASKS_H */
+

asoc/codecs/wcd9378/wcd9378-registers.h

@@ -0,0 +1,894 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef WCD9378_REGISTERS_H
+#define WCD9378_REGISTERS_H
+
+enum {
+	REG_NO_ACCESS,
+	RD_REG,
+	WR_REG,
+	RD_WR_REG,
+};
+
+#define WCD9378_BASE 0x3fffffff
+
+#define WCD9378_REG(reg) (((reg & 0x0ff00000) >> 8) | (reg & 0xfff))
+
+#define WCD9378_FUNC0_BASE                     (WCD9378_BASE+0x01)
+#define WCD9378_FUNC_EXT_ID_0                  (WCD9378_FUNC0_BASE+0x48)
+#define WCD9378_FUNC_EXT_ID_1                  (WCD9378_FUNC0_BASE+0x49)
+#define WCD9378_FUNC_EXT_VER                   (WCD9378_FUNC0_BASE+0x50)
+#define WCD9378_FUNC_STAT                      (WCD9378_FUNC0_BASE+0x80000)
+#define WCD9378_DEV_MANU_ID_0                  (WCD9378_FUNC0_BASE+0x100060)
+#define WCD9378_DEV_MANU_ID_1                  (WCD9378_FUNC0_BASE+0x100061)
+#define WCD9378_DEV_PART_ID_0                  (WCD9378_FUNC0_BASE+0x100068)
+#define WCD9378_DEV_PART_ID_1                  (WCD9378_FUNC0_BASE+0x100069)
+#define WCD9378_DEV_VER                        (WCD9378_FUNC0_BASE+0x100070)
+
+#define WCD9378_A_BASE                         (WCD9378_BASE+0x180001)
+#define WCD9378_ANA_PAGE                         (WCD9378_A_BASE+0x00)
+#define WCD9378_ANA_BIAS                       (WCD9378_A_BASE+0x01)
+#define WCD9378_ANA_RX_SUPPLIES                (WCD9378_A_BASE+0x08)
+#define WCD9378_ANA_HPH                        (WCD9378_A_BASE+0x09)
+#define WCD9378_ANA_EAR                        (WCD9378_A_BASE+0x0a)
+#define WCD9378_ANA_EAR_COMPANDER_CTL          (WCD9378_A_BASE+0x0b)
+#define WCD9378_ANA_TX_CH1                     (WCD9378_A_BASE+0x0e)
+#define WCD9378_ANA_TX_CH2                     (WCD9378_A_BASE+0x0f)
+#define WCD9378_ANA_TX_CH3                     (WCD9378_A_BASE+0x10)
+#define WCD9378_ANA_TX_CH3_HPF                 (WCD9378_A_BASE+0x11)
+#define WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC   (WCD9378_A_BASE+0x12)
+#define WCD9378_ANA_MICB3_DSP_EN_LOGIC         (WCD9378_A_BASE+0x13)
+#define WCD9378_ANA_MBHC_MECH                  (WCD9378_A_BASE+0x14)
+#define WCD9378_ANA_MBHC_ELECT                 (WCD9378_A_BASE+0x15)
+#define WCD9378_ANA_MBHC_ZDET                  (WCD9378_A_BASE+0x16)
+#define WCD9378_ANA_MBHC_RESULT_1              (WCD9378_A_BASE+0x17)
+#define WCD9378_ANA_MBHC_RESULT_2              (WCD9378_A_BASE+0x18)
+#define WCD9378_ANA_MBHC_RESULT_3              (WCD9378_A_BASE+0x19)
+#define WCD9378_ANA_MBHC_BTN0                  (WCD9378_A_BASE+0x1a)
+#define WCD9378_ANA_MBHC_BTN1                  (WCD9378_A_BASE+0x1b)
+#define WCD9378_ANA_MBHC_BTN2                  (WCD9378_A_BASE+0x1c)
+#define WCD9378_ANA_MBHC_BTN3                  (WCD9378_A_BASE+0x1d)
+#define WCD9378_ANA_MBHC_BTN4                  (WCD9378_A_BASE+0x1e)
+#define WCD9378_ANA_MBHC_BTN5                  (WCD9378_A_BASE+0x1f)
+#define WCD9378_ANA_MBHC_BTN6                  (WCD9378_A_BASE+0x20)
+#define WCD9378_ANA_MBHC_BTN7                  (WCD9378_A_BASE+0x21)
+#define WCD9378_ANA_MICB1                      (WCD9378_A_BASE+0x22)
+#define WCD9378_ANA_MICB2                      (WCD9378_A_BASE+0x23)
+#define WCD9378_ANA_MICB2_RAMP                 (WCD9378_A_BASE+0x24)
+#define WCD9378_ANA_MICB3                      (WCD9378_A_BASE+0x25)
+#define WCD9378_BIAS_CTL                       (WCD9378_A_BASE+0x28)
+#define WCD9378_BIAS_VBG_FINE_ADJ              (WCD9378_A_BASE+0x29)
+#define WCD9378_LDOL_VDDCX_ADJUST              (WCD9378_A_BASE+0x40)
+#define WCD9378_LDOL_DISABLE_LDOL              (WCD9378_A_BASE+0x41)
+#define WCD9378_MBHC_CTL_CLK                   (WCD9378_A_BASE+0x56)
+#define WCD9378_MBHC_CTL_ANA                   (WCD9378_A_BASE+0x57)
+#define WCD9378_MBHC_CTL_SPARE_1               (WCD9378_A_BASE+0x58)
+#define WCD9378_MBHC_CTL_SPARE_2               (WCD9378_A_BASE+0x59)
+#define WCD9378_MBHC_CTL_BCS                   (WCD9378_A_BASE+0x5a)
+#define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS   (WCD9378_A_BASE+0x5b)
+#define WCD9378_MBHC_TEST_CTL                  (WCD9378_A_BASE+0x5c)
+#define WCD9378_LDOH_MODE                      (WCD9378_A_BASE+0x67)
+#define WCD9378_LDOH_BIAS                      (WCD9378_A_BASE+0x68)
+#define WCD9378_LDOH_STB_LOADS                 (WCD9378_A_BASE+0x69)
+#define WCD9378_LDOH_SLOWRAMP                  (WCD9378_A_BASE+0x6a)
+#define WCD9378_MICB1_TEST_CTL_1               (WCD9378_A_BASE+0x6b)
+#define WCD9378_MICB1_TEST_CTL_2               (WCD9378_A_BASE+0x6c)
+#define WCD9378_MICB1_TEST_CTL_3               (WCD9378_A_BASE+0x6d)
+#define WCD9378_MICB2_TEST_CTL_1               (WCD9378_A_BASE+0x6e)
+#define WCD9378_MICB2_TEST_CTL_2               (WCD9378_A_BASE+0x6f)
+#define WCD9378_MICB2_TEST_CTL_3               (WCD9378_A_BASE+0x70)
+#define WCD9378_MICB3_TEST_CTL_1               (WCD9378_A_BASE+0x71)
+#define WCD9378_MICB3_TEST_CTL_2               (WCD9378_A_BASE+0x72)
+#define WCD9378_MICB3_TEST_CTL_3               (WCD9378_A_BASE+0x73)
+#define WCD9378_TX_COM_ADC_VCM                 (WCD9378_A_BASE+0x77)
+#define WCD9378_TX_COM_BIAS_ATEST              (WCD9378_A_BASE+0x78)
+#define WCD9378_TX_COM_SPARE1                  (WCD9378_A_BASE+0x79)
+#define WCD9378_TX_COM_SPARE2                  (WCD9378_A_BASE+0x7a)
+#define WCD9378_TX_COM_TXFE_DIV_CTL            (WCD9378_A_BASE+0x7b)
+#define WCD9378_TX_COM_TXFE_DIV_START          (WCD9378_A_BASE+0x7c)
+#define WCD9378_TX_COM_SPARE3                  (WCD9378_A_BASE+0x7d)
+#define WCD9378_TX_COM_SPARE4                  (WCD9378_A_BASE+0x7e)
+#define WCD9378_TX_1_2_TEST_EN                 (WCD9378_A_BASE+0x7f)
+#define WCD9378_TX_1_2_ADC_IB                  (WCD9378_A_BASE+0x80)
+#define WCD9378_TX_1_2_ATEST_REFCTL            (WCD9378_A_BASE+0x81)
+#define WCD9378_TX_1_2_TEST_CTL                (WCD9378_A_BASE+0x82)
+#define WCD9378_TX_1_2_TEST_BLK_EN1            (WCD9378_A_BASE+0x83)
+#define WCD9378_TX_1_2_TXFE1_CLKDIV            (WCD9378_A_BASE+0x84)
+#define WCD9378_TX_1_2_SAR2_ERR                (WCD9378_A_BASE+0x85)
+#define WCD9378_TX_1_2_SAR1_ERR                (WCD9378_A_BASE+0x86)
+#define WCD9378_TX_3_TEST_EN                   (WCD9378_A_BASE+0x87)
+#define WCD9378_TX_3_ADC_IB                    (WCD9378_A_BASE+0x88)
+#define WCD9378_TX_3_ATEST_REFCTL              (WCD9378_A_BASE+0x89)
+#define WCD9378_TX_3_TEST_CTL                  (WCD9378_A_BASE+0x8a)
+#define WCD9378_TX_3_TEST_BLK_EN3              (WCD9378_A_BASE+0x8b)
+#define WCD9378_TX_3_TXFE3_CLKDIV              (WCD9378_A_BASE+0x8c)
+#define WCD9378_TX_3_SAR4_ERR                  (WCD9378_A_BASE+0x8d)
+#define WCD9378_TX_3_SAR3_ERR                  (WCD9378_A_BASE+0x8e)
+#define WCD9378_TX_3_TEST_BLK_EN2              (WCD9378_A_BASE+0x8f)
+#define WCD9378_TX_3_TXFE2_CLKDIV              (WCD9378_A_BASE+0x90)
+#define WCD9378_TX_3_SPARE1                    (WCD9378_A_BASE+0x91)
+#define WCD9378_TX_3_TEST_BLK_EN4              (WCD9378_A_BASE+0x92)
+#define WCD9378_TX_3_SPARE2                    (WCD9378_A_BASE+0x93)
+#define WCD9378_TX_3_SPARE3                    (WCD9378_A_BASE+0x94)
+#define WCD9378_RX_AUX_SW_CTL                  (WCD9378_A_BASE+0xb3)
+#define WCD9378_RX_PA_AUX_IN_CONN              (WCD9378_A_BASE+0xb4)
+#define WCD9378_RX_TIMER_DIV                   (WCD9378_A_BASE+0xb5)
+#define WCD9378_RX_OCP_CTL                     (WCD9378_A_BASE+0xb6)
+#define WCD9378_RX_OCP_COUNT                   (WCD9378_A_BASE+0xb7)
+#define WCD9378_RX_BIAS_EAR_DAC                (WCD9378_A_BASE+0xb8)
+#define WCD9378_RX_BIAS_EAR_AMP                (WCD9378_A_BASE+0xb9)
+#define WCD9378_RX_BIAS_HPH_LDO                (WCD9378_A_BASE+0xba)
+#define WCD9378_RX_BIAS_HPH_PA                 (WCD9378_A_BASE+0xbb)
+#define WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2      (WCD9378_A_BASE+0xbc)
+#define WCD9378_RX_BIAS_HPH_RDAC_LDO           (WCD9378_A_BASE+0xbd)
+#define WCD9378_RX_BIAS_HPH_CNP1               (WCD9378_A_BASE+0xbe)
+#define WCD9378_RX_BIAS_HPH_LOWPOWER           (WCD9378_A_BASE+0xbf)
+#define WCD9378_RX_BIAS_AUX_DAC                (WCD9378_A_BASE+0xc0)
+#define WCD9378_RX_BIAS_AUX_AMP                (WCD9378_A_BASE+0xc1)
+#define WCD9378_RX_SPARE_1                     (WCD9378_A_BASE+0xc2)
+#define WCD9378_RX_SPARE_2                     (WCD9378_A_BASE+0xc3)
+#define WCD9378_RX_SPARE_3                     (WCD9378_A_BASE+0xc4)
+#define WCD9378_RX_SPARE_4                     (WCD9378_A_BASE+0xc5)
+#define WCD9378_RX_SPARE_5                     (WCD9378_A_BASE+0xc6)
+#define WCD9378_RX_SPARE_6                     (WCD9378_A_BASE+0xc7)
+#define WCD9378_RX_SPARE_7                     (WCD9378_A_BASE+0xc8)
+#define WCD9378_HPH_L_STATUS                   (WCD9378_A_BASE+0xc9)
+#define WCD9378_HPH_R_STATUS                   (WCD9378_A_BASE+0xca)
+#define WCD9378_HPH_CNP_EN                     (WCD9378_A_BASE+0xcb)
+#define WCD9378_HPH_CNP_WG_CTL                 (WCD9378_A_BASE+0xcc)
+#define WCD9378_HPH_CNP_WG_TIME                (WCD9378_A_BASE+0xcd)
+#define WCD9378_HPH_OCP_CTL                    (WCD9378_A_BASE+0xce)
+#define WCD9378_HPH_AUTO_CHOP                  (WCD9378_A_BASE+0xcf)
+#define WCD9378_HPH_CHOP_CTL                   (WCD9378_A_BASE+0xd0)
+#define WCD9378_HPH_PA_CTL1                    (WCD9378_A_BASE+0xd1)
+#define WCD9378_HPH_PA_CTL2                    (WCD9378_A_BASE+0xd2)
+#define WCD9378_HPH_L_EN                       (WCD9378_A_BASE+0xd3)
+#define WCD9378_HPH_L_TEST                     (WCD9378_A_BASE+0xd4)
+#define WCD9378_HPH_L_ATEST                    (WCD9378_A_BASE+0xd5)
+#define WCD9378_HPH_R_EN                       (WCD9378_A_BASE+0xd6)
+#define WCD9378_HPH_R_TEST                     (WCD9378_A_BASE+0xd7)
+#define WCD9378_HPH_R_ATEST                    (WCD9378_A_BASE+0xd8)
+#define WCD9378_HPH_RDAC_CLK_CTL1              (WCD9378_A_BASE+0xd9)
+#define WCD9378_HPH_RDAC_CLK_CTL2              (WCD9378_A_BASE+0xda)
+#define WCD9378_HPH_RDAC_LDO_CTL               (WCD9378_A_BASE+0xdb)
+#define WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL       (WCD9378_A_BASE+0xdc)
+#define WCD9378_HPH_REFBUFF_UHQA_CTL           (WCD9378_A_BASE+0xdd)
+#define WCD9378_HPH_REFBUFF_LP_CTL             (WCD9378_A_BASE+0xde)
+#define WCD9378_HPH_L_DAC_CTL                  (WCD9378_A_BASE+0xdf)
+#define WCD9378_HPH_R_DAC_CTL                  (WCD9378_A_BASE+0xe0)
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL (WCD9378_A_BASE+0xe1)
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_EN       (WCD9378_A_BASE+0xe2)
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1    (WCD9378_A_BASE+0xe3)
+#define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS   (WCD9378_A_BASE+0xe4)
+#define WCD9378_EAR_EAR_EN_REG                 (WCD9378_A_BASE+0xe9)
+#define WCD9378_EAR_EAR_PA_CON                 (WCD9378_A_BASE+0xea)
+#define WCD9378_EAR_EAR_SP_CON                 (WCD9378_A_BASE+0xeb)
+#define WCD9378_EAR_EAR_DAC_CON                (WCD9378_A_BASE+0xec)
+#define WCD9378_EAR_EAR_CNP_FSM_CON            (WCD9378_A_BASE+0xed)
+#define WCD9378_EAR_TEST_CTL                   (WCD9378_A_BASE+0xee)
+#define WCD9378_EAR_STATUS_REG_1               (WCD9378_A_BASE+0xef)
+#define WCD9378_EAR_STATUS_REG_2               (WCD9378_A_BASE+0xf0)
+#define WCD9378_ANA_NEW_PAGE                   (WCD9378_A_BASE+0x100)
+#define WCD9378_HPH_NEW_ANA_HPH2               (WCD9378_A_BASE+0x101)
+#define WCD9378_HPH_NEW_ANA_HPH3               (WCD9378_A_BASE+0x102)
+#define WCD9378_SLEEP_CTL                      (WCD9378_A_BASE+0x103)
+#define WCD9378_SLEEP_WATCHDOG_CTL             (WCD9378_A_BASE+0x104)
+#define WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL   (WCD9378_A_BASE+0x11f)
+#define WCD9378_MBHC_NEW_CTL_1                 (WCD9378_A_BASE+0x120)
+#define WCD9378_MBHC_NEW_CTL_2                 (WCD9378_A_BASE+0x121)
+#define WCD9378_MBHC_NEW_PLUG_DETECT_CTL       (WCD9378_A_BASE+0x122)
+#define WCD9378_MBHC_NEW_ZDET_ANA_CTL          (WCD9378_A_BASE+0x123)
+#define WCD9378_MBHC_NEW_ZDET_RAMP_CTL         (WCD9378_A_BASE+0x124)
+#define WCD9378_MBHC_NEW_FSM_STATUS            (WCD9378_A_BASE+0x125)
+#define WCD9378_MBHC_NEW_ADC_RESULT            (WCD9378_A_BASE+0x126)
+#define WCD9378_AUX_AUXPA                      (WCD9378_A_BASE+0x128)
+#define WCD9378_DIE_CRACK_DIE_CRK_DET_EN       (WCD9378_A_BASE+0x12c)
+#define WCD9378_DIE_CRACK_DIE_CRK_DET_OUT      (WCD9378_A_BASE+0x12d)
+#define WCD9378_TX_NEW_TX_CH12_MUX             (WCD9378_A_BASE+0x12e)
+#define WCD9378_TX_NEW_TX_CH34_MUX             (WCD9378_A_BASE+0x12f)
+#define WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL      (WCD9378_A_BASE+0x132)
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L     (WCD9378_A_BASE+0x133)
+#define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL      (WCD9378_A_BASE+0x134)
+#define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL  (WCD9378_A_BASE+0x135)
+#define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R     (WCD9378_A_BASE+0x136)
+#define WCD9378_HPH_NEW_INT_PA_MISC1           (WCD9378_A_BASE+0x137)
+#define WCD9378_HPH_NEW_INT_PA_MISC2           (WCD9378_A_BASE+0x138)
+#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC       (WCD9378_A_BASE+0x139)
+#define WCD9378_HPH_NEW_INT_HPH_TIMER1         (WCD9378_A_BASE+0x13a)
+#define WCD9378_HPH_NEW_INT_HPH_TIMER2         (WCD9378_A_BASE+0x13b)
+#define WCD9378_HPH_NEW_INT_HPH_TIMER3         (WCD9378_A_BASE+0x13c)
+#define WCD9378_HPH_NEW_INT_HPH_TIMER4         (WCD9378_A_BASE+0x13d)
+#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC2      (WCD9378_A_BASE+0x13e)
+#define WCD9378_HPH_NEW_INT_PA_RDAC_MISC3      (WCD9378_A_BASE+0x13f)
+#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (WCD9378_A_BASE+0x145)
+#define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP   (WCD9378_A_BASE+0x146)
+#define WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP     (WCD9378_A_BASE+0x147)
+#define WCD9378_CP_CLASSG_CP_CTRL_0            (WCD9378_A_BASE+0x150)
+#define WCD9378_CP_CLASSG_CP_CTRL_1            (WCD9378_A_BASE+0x151)
+#define WCD9378_CP_CLASSG_CP_CTRL_2            (WCD9378_A_BASE+0x152)
+#define WCD9378_CP_CLASSG_CP_CTRL_3            (WCD9378_A_BASE+0x153)
+#define WCD9378_CP_CLASSG_CP_CTRL_4            (WCD9378_A_BASE+0x154)
+#define WCD9378_CP_CLASSG_CP_CTRL_5            (WCD9378_A_BASE+0x155)
+#define WCD9378_CP_CLASSG_CP_CTRL_6            (WCD9378_A_BASE+0x156)
+#define WCD9378_CP_CLASSG_CP_CTRL_7            (WCD9378_A_BASE+0x157)
+#define WCD9378_CP_VNEGDAC_CTRL_0              (WCD9378_A_BASE+0x158)
+#define WCD9378_CP_VNEGDAC_CTRL_1              (WCD9378_A_BASE+0x159)
+#define WCD9378_CP_VNEGDAC_CTRL_2              (WCD9378_A_BASE+0x15a)
+#define WCD9378_CP_VNEGDAC_CTRL_3              (WCD9378_A_BASE+0x15b)
+#define WCD9378_CP_CP_DTOP_CTRL_0              (WCD9378_A_BASE+0x15c)
+#define WCD9378_CP_CP_DTOP_CTRL_1              (WCD9378_A_BASE+0x15d)
+#define WCD9378_CP_CP_DTOP_CTRL_2              (WCD9378_A_BASE+0x15e)
+#define WCD9378_CP_CP_DTOP_CTRL_3              (WCD9378_A_BASE+0x15f)
+#define WCD9378_CP_CP_DTOP_CTRL_4              (WCD9378_A_BASE+0x160)
+#define WCD9378_CP_CP_DTOP_CTRL_5              (WCD9378_A_BASE+0x161)
+#define WCD9378_CP_CP_DTOP_CTRL_6              (WCD9378_A_BASE+0x162)
+#define WCD9378_CP_CP_DTOP_CTRL_7              (WCD9378_A_BASE+0x163)
+#define WCD9378_CP_CP_DTOP_CTRL_8              (WCD9378_A_BASE+0x164)
+#define WCD9378_CP_CP_DTOP_CTRL_9              (WCD9378_A_BASE+0x165)
+#define WCD9378_CP_CP_DTOP_CTRL_10             (WCD9378_A_BASE+0x166)
+#define WCD9378_CP_CP_DTOP_CTRL_11             (WCD9378_A_BASE+0x167)
+#define WCD9378_CP_CP_DTOP_CTRL_12             (WCD9378_A_BASE+0x168)
+#define WCD9378_CP_CP_DTOP_CTRL_13             (WCD9378_A_BASE+0x169)
+#define WCD9378_CP_CP_DTOP_CTRL_14             (WCD9378_A_BASE+0x16a)
+#define WCD9378_CP_CP_DTOP_CTRL_15             (WCD9378_A_BASE+0x16b)
+#define WCD9378_CP_CP_DTOP_CTRL_16             (WCD9378_A_BASE+0x16c)
+#define WCD9378_CP_CP_DTOP_CTRL_17             (WCD9378_A_BASE+0x16d)
+#define WCD9378_CP_CP_DTOP_CTRL_18             (WCD9378_A_BASE+0x16e)
+#define WCD9378_CP_CP_DTOP_CTRL_19             (WCD9378_A_BASE+0x16f)
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (WCD9378_A_BASE+0x1af)
+#define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (WCD9378_A_BASE+0x1b0)
+#define WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT  (WCD9378_A_BASE+0x1b1)
+#define WCD9378_MBHC_NEW_INT_SPARE_2           (WCD9378_A_BASE+0x1b2)
+#define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON    (WCD9378_A_BASE+0x1b7)
+#define WCD9378_EAR_INT_NEW_CNP_VCM_CON1       (WCD9378_A_BASE+0x1b8)
+#define WCD9378_EAR_INT_NEW_CNP_VCM_CON2       (WCD9378_A_BASE+0x1b9)
+#define WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS   (WCD9378_A_BASE+0x1ba)
+#define WCD9378_AUX_INT_EN_REG                 (WCD9378_A_BASE+0x1bd)
+#define WCD9378_AUX_INT_PA_CTRL                (WCD9378_A_BASE+0x1be)
+#define WCD9378_AUX_INT_SP_CTRL                (WCD9378_A_BASE+0x1bf)
+#define WCD9378_AUX_INT_DAC_CTRL               (WCD9378_A_BASE+0x1c0)
+#define WCD9378_AUX_INT_CLK_CTRL               (WCD9378_A_BASE+0x1c1)
+#define WCD9378_AUX_INT_TEST_CTRL              (WCD9378_A_BASE+0x1c2)
+#define WCD9378_AUX_INT_STATUS_REG             (WCD9378_A_BASE+0x1c3)
+#define WCD9378_AUX_INT_MISC                   (WCD9378_A_BASE+0x1c4)
+#define WCD9378_SLEEP_INT_WATCHDOG_CTL_1       (WCD9378_A_BASE+0x1d0)
+#define WCD9378_SLEEP_INT_WATCHDOG_CTL_2       (WCD9378_A_BASE+0x1d1)
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1 (WCD9378_A_BASE+0x1d3)
+#define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2 (WCD9378_A_BASE+0x1d4)
+#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2 (WCD9378_A_BASE+0x1d5)
+#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1 (WCD9378_A_BASE+0x1d6)
+#define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0 (WCD9378_A_BASE+0x1d7)
+#define WCD9378_TX_COM_NEW_INT_SPARE1          (WCD9378_A_BASE+0x1d8)
+#define WCD9378_TX_COM_NEW_INT_SPARE2          (WCD9378_A_BASE+0x1d9)
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2   (WCD9378_A_BASE+0x1da)
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1   (WCD9378_A_BASE+0x1db)
+#define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0   (WCD9378_A_BASE+0x1dc)
+#define WCD9378_TX_COM_NEW_INT_SPARE3          (WCD9378_A_BASE+0x1dd)
+#define WCD9378_TX_COM_NEW_INT_SPARE4          (WCD9378_A_BASE+0x1de)
+#define WCD9378_TX_COM_NEW_INT_SPARE5          (WCD9378_A_BASE+0x1df)
+#define WCD9378_TX_COM_NEW_INT_SPARE6          (WCD9378_A_BASE+0x1e0)
+#define WCD9378_TX_COM_NEW_INT_SPARE7          (WCD9378_A_BASE+0x1e1)
+#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1 (WCD9378_A_BASE+0x1e2)
+#define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0 (WCD9378_A_BASE+0x1e3)
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L2    (WCD9378_A_BASE+0x1e4)
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L1    (WCD9378_A_BASE+0x1e5)
+#define WCD9378_TX_COM_NEW_INT_TXADC_INT_L0    (WCD9378_A_BASE+0x1e6)
+#define WCD9378_TX_COM_NEW_INT_SPARE8          (WCD9378_A_BASE+0x1e7)
+
+#define WCD9378_TAMBORA_BASE                   (WCD9378_BASE+0x180401)
+#define WCD9378_TAMBORA_PAGE                   (WCD9378_TAMBORA_BASE+0x00)
+#define WCD9378_CHIP_ID0                       (WCD9378_TAMBORA_BASE+0x01)
+#define WCD9378_CHIP_ID1                       (WCD9378_TAMBORA_BASE+0x02)
+#define WCD9378_CHIP_ID2                       (WCD9378_TAMBORA_BASE+0x03)
+#define WCD9378_CHIP_ID3                       (WCD9378_TAMBORA_BASE+0x04)
+#define WCD9378_SWR_TX_CLK_RATE                (WCD9378_TAMBORA_BASE+0x05)
+#define WCD9378_CDC_RST_CTL                    (WCD9378_TAMBORA_BASE+0x06)
+#define WCD9378_TOP_CLK_CFG                    (WCD9378_TAMBORA_BASE+0x07)
+#define WCD9378_CDC_ANA_CLK_CTL                (WCD9378_TAMBORA_BASE+0x08)
+#define WCD9378_CDC_DIG_CLK_CTL                (WCD9378_TAMBORA_BASE+0x09)
+#define WCD9378_SWR_RST_EN                     (WCD9378_TAMBORA_BASE+0x0a)
+#define WCD9378_CDC_PATH_MODE                  (WCD9378_TAMBORA_BASE+0x0b)
+#define WCD9378_CDC_RX_RST                     (WCD9378_TAMBORA_BASE+0x0c)
+#define WCD9378_CDC_RX0_CTL                    (WCD9378_TAMBORA_BASE+0x0d)
+#define WCD9378_CDC_RX1_CTL                    (WCD9378_TAMBORA_BASE+0x0e)
+#define WCD9378_CDC_RX2_CTL                    (WCD9378_TAMBORA_BASE+0x0f)
+#define WCD9378_CDC_TX_ANA_MODE_0_1            (WCD9378_TAMBORA_BASE+0x10)
+#define WCD9378_CDC_TX_ANA_MODE_2_3            (WCD9378_TAMBORA_BASE+0x11)
+#define WCD9378_CDC_COMP_CTL_0                 (WCD9378_TAMBORA_BASE+0x14)
+#define WCD9378_CDC_ANA_TX_CLK_CTL             (WCD9378_TAMBORA_BASE+0x17)
+#define WCD9378_CDC_HPH_DSM_A1_0               (WCD9378_TAMBORA_BASE+0x18)
+#define WCD9378_CDC_HPH_DSM_A1_1               (WCD9378_TAMBORA_BASE+0x19)
+#define WCD9378_CDC_HPH_DSM_A2_0               (WCD9378_TAMBORA_BASE+0x1a)
+#define WCD9378_CDC_HPH_DSM_A2_1               (WCD9378_TAMBORA_BASE+0x1b)
+#define WCD9378_CDC_HPH_DSM_A3_0               (WCD9378_TAMBORA_BASE+0x1c)
+#define WCD9378_CDC_HPH_DSM_A3_1               (WCD9378_TAMBORA_BASE+0x1d)
+#define WCD9378_CDC_HPH_DSM_A4_0               (WCD9378_TAMBORA_BASE+0x1e)
+#define WCD9378_CDC_HPH_DSM_A4_1               (WCD9378_TAMBORA_BASE+0x1f)
+#define WCD9378_CDC_HPH_DSM_A5_0               (WCD9378_TAMBORA_BASE+0x20)
+#define WCD9378_CDC_HPH_DSM_A5_1               (WCD9378_TAMBORA_BASE+0x21)
+#define WCD9378_CDC_HPH_DSM_A6_0               (WCD9378_TAMBORA_BASE+0x22)
+#define WCD9378_CDC_HPH_DSM_A7_0               (WCD9378_TAMBORA_BASE+0x23)
+#define WCD9378_CDC_HPH_DSM_C_0                (WCD9378_TAMBORA_BASE+0x24)
+#define WCD9378_CDC_HPH_DSM_C_1                (WCD9378_TAMBORA_BASE+0x25)
+#define WCD9378_CDC_HPH_DSM_C_2                (WCD9378_TAMBORA_BASE+0x26)
+#define WCD9378_CDC_HPH_DSM_C_3                (WCD9378_TAMBORA_BASE+0x27)
+#define WCD9378_CDC_HPH_DSM_R1                 (WCD9378_TAMBORA_BASE+0x28)
+#define WCD9378_CDC_HPH_DSM_R2                 (WCD9378_TAMBORA_BASE+0x29)
+#define WCD9378_CDC_HPH_DSM_R3                 (WCD9378_TAMBORA_BASE+0x2a)
+#define WCD9378_CDC_HPH_DSM_R4                 (WCD9378_TAMBORA_BASE+0x2b)
+#define WCD9378_CDC_HPH_DSM_R5                 (WCD9378_TAMBORA_BASE+0x2c)
+#define WCD9378_CDC_HPH_DSM_R6                 (WCD9378_TAMBORA_BASE+0x2d)
+#define WCD9378_CDC_HPH_DSM_R7                 (WCD9378_TAMBORA_BASE+0x2e)
+#define WCD9378_CDC_AUX_DSM_A1_0               (WCD9378_TAMBORA_BASE+0x2f)
+#define WCD9378_CDC_AUX_DSM_A1_1               (WCD9378_TAMBORA_BASE+0x30)
+#define WCD9378_CDC_AUX_DSM_A2_0               (WCD9378_TAMBORA_BASE+0x31)
+#define WCD9378_CDC_AUX_DSM_A2_1               (WCD9378_TAMBORA_BASE+0x32)
+#define WCD9378_CDC_AUX_DSM_A3_0               (WCD9378_TAMBORA_BASE+0x33)
+#define WCD9378_CDC_AUX_DSM_A3_1               (WCD9378_TAMBORA_BASE+0x34)
+#define WCD9378_CDC_AUX_DSM_A4_0               (WCD9378_TAMBORA_BASE+0x35)
+#define WCD9378_CDC_AUX_DSM_A4_1               (WCD9378_TAMBORA_BASE+0x36)
+#define WCD9378_CDC_AUX_DSM_A5_0               (WCD9378_TAMBORA_BASE+0x37)
+#define WCD9378_CDC_AUX_DSM_A5_1               (WCD9378_TAMBORA_BASE+0x38)
+#define WCD9378_CDC_AUX_DSM_A6_0               (WCD9378_TAMBORA_BASE+0x39)
+#define WCD9378_CDC_AUX_DSM_A7_0               (WCD9378_TAMBORA_BASE+0x3a)
+#define WCD9378_CDC_AUX_DSM_C_0                (WCD9378_TAMBORA_BASE+0x3b)
+#define WCD9378_CDC_AUX_DSM_C_1                (WCD9378_TAMBORA_BASE+0x3c)
+#define WCD9378_CDC_AUX_DSM_C_2                (WCD9378_TAMBORA_BASE+0x3d)
+#define WCD9378_CDC_AUX_DSM_C_3                (WCD9378_TAMBORA_BASE+0x3e)
+#define WCD9378_CDC_AUX_DSM_R1                 (WCD9378_TAMBORA_BASE+0x3f)
+#define WCD9378_CDC_AUX_DSM_R2                 (WCD9378_TAMBORA_BASE+0x40)
+#define WCD9378_CDC_AUX_DSM_R3                 (WCD9378_TAMBORA_BASE+0x41)
+#define WCD9378_CDC_AUX_DSM_R4                 (WCD9378_TAMBORA_BASE+0x42)
+#define WCD9378_CDC_AUX_DSM_R5                 (WCD9378_TAMBORA_BASE+0x43)
+#define WCD9378_CDC_AUX_DSM_R6                 (WCD9378_TAMBORA_BASE+0x44)
+#define WCD9378_CDC_AUX_DSM_R7                 (WCD9378_TAMBORA_BASE+0x45)
+#define WCD9378_CDC_HPH_GAIN_RX_0              (WCD9378_TAMBORA_BASE+0x46)
+#define WCD9378_CDC_HPH_GAIN_RX_1              (WCD9378_TAMBORA_BASE+0x47)
+#define WCD9378_CDC_HPH_GAIN_DSD_0             (WCD9378_TAMBORA_BASE+0x48)
+#define WCD9378_CDC_HPH_GAIN_DSD_1             (WCD9378_TAMBORA_BASE+0x49)
+#define WCD9378_CDC_HPH_GAIN_DSD_2             (WCD9378_TAMBORA_BASE+0x4a)
+#define WCD9378_CDC_AUX_GAIN_DSD_0             (WCD9378_TAMBORA_BASE+0x4b)
+#define WCD9378_CDC_AUX_GAIN_DSD_1             (WCD9378_TAMBORA_BASE+0x4c)
+#define WCD9378_CDC_AUX_GAIN_DSD_2             (WCD9378_TAMBORA_BASE+0x4d)
+#define WCD9378_CDC_HPH_GAIN_CTL               (WCD9378_TAMBORA_BASE+0x4e)
+#define WCD9378_CDC_AUX_GAIN_CTL               (WCD9378_TAMBORA_BASE+0x4f)
+#define WCD9378_CDC_PATH_CTL                   (WCD9378_TAMBORA_BASE+0x50)
+#define WCD9378_CDC_SWR_CLG                    (WCD9378_TAMBORA_BASE+0x51)
+#define WCD9378_SWR_CLG_BYP                    (WCD9378_TAMBORA_BASE+0x52)
+#define WCD9378_CDC_TX0_CTL                    (WCD9378_TAMBORA_BASE+0x53)
+#define WCD9378_CDC_TX1_CTL                    (WCD9378_TAMBORA_BASE+0x54)
+#define WCD9378_CDC_TX2_CTL                    (WCD9378_TAMBORA_BASE+0x55)
+#define WCD9378_CDC_TX_RST                     (WCD9378_TAMBORA_BASE+0x56)
+#define WCD9378_CDC_REQ_CTL                    (WCD9378_TAMBORA_BASE+0x57)
+#define WCD9378_CDC_RST                        (WCD9378_TAMBORA_BASE+0x58)
+#define WCD9378_CDC_AMIC_CTL                   (WCD9378_TAMBORA_BASE+0x5a)
+#define WCD9378_CDC_DMIC_CTL                   (WCD9378_TAMBORA_BASE+0x5b)
+#define WCD9378_CDC_DMIC1_CTL                  (WCD9378_TAMBORA_BASE+0x5c)
+#define WCD9378_CDC_DMIC2_CTL                  (WCD9378_TAMBORA_BASE+0x5d)
+#define WCD9378_CDC_DMIC3_CTL                  (WCD9378_TAMBORA_BASE+0x5e)
+#define WCD9378_EFUSE_PRG_CTL                  (WCD9378_TAMBORA_BASE+0x60)
+#define WCD9378_EFUSE_CTL                      (WCD9378_TAMBORA_BASE+0x61)
+#define WCD9378_CDC_DMIC_RATE_1_2              (WCD9378_TAMBORA_BASE+0x62)
+#define WCD9378_CDC_DMIC_RATE_3_4              (WCD9378_TAMBORA_BASE+0x63)
+#define WCD9378_PDM_WD_EN_OVRD                 (WCD9378_TAMBORA_BASE+0x64)
+#define WCD9378_PDM_WD_CTL0                    (WCD9378_TAMBORA_BASE+0x65)
+#define WCD9378_PDM_WD_CTL1                    (WCD9378_TAMBORA_BASE+0x66)
+#define WCD9378_PDM_WD_CTL2                    (WCD9378_TAMBORA_BASE+0x67)
+#define WCD9378_RAMP_CTL                       (WCD9378_TAMBORA_BASE+0x68)
+#define WCD9378_ACT_DET_CTL                    (WCD9378_TAMBORA_BASE+0x69)
+#define WCD9378_ACT_DET_HOOKUP0                (WCD9378_TAMBORA_BASE+0x6a)
+#define WCD9378_ACT_DET_HOOKUP1                (WCD9378_TAMBORA_BASE+0x6b)
+#define WCD9378_ACT_DET_HOOKUP2                (WCD9378_TAMBORA_BASE+0x6c)
+#define WCD9378_ACT_DET_DLY_BUF_EN             (WCD9378_TAMBORA_BASE+0x6d)
+#define WCD9378_INTR_MODE                      (WCD9378_TAMBORA_BASE+0x6e)
+#define WCD9378_INTR_STATUS_0                  (WCD9378_TAMBORA_BASE+0x6f)
+#define WCD9378_INTR_STATUS_1                  (WCD9378_TAMBORA_BASE+0x70)
+#define WCD9378_INTR_STATUS_2                  (WCD9378_TAMBORA_BASE+0x71)
+#define WCD9378_INTR_STATUS_3                  (WCD9378_TAMBORA_BASE+0x72)
+#define WCD9378_INTR_MASK_0                    (WCD9378_TAMBORA_BASE+0x73)
+#define WCD9378_INTR_MASK_1                    (WCD9378_TAMBORA_BASE+0x74)
+#define WCD9378_INTR_MASK_2                    (WCD9378_TAMBORA_BASE+0x75)
+#define WCD9378_INTR_MASK_3                    (WCD9378_TAMBORA_BASE+0x76)
+#define WCD9378_INTR_SET_0                     (WCD9378_TAMBORA_BASE+0x77)
+#define WCD9378_INTR_SET_1                     (WCD9378_TAMBORA_BASE+0x78)
+#define WCD9378_INTR_SET_2                     (WCD9378_TAMBORA_BASE+0x79)
+#define WCD9378_INTR_SET_3                     (WCD9378_TAMBORA_BASE+0x7a)
+#define WCD9378_INTR_TEST_0                    (WCD9378_TAMBORA_BASE+0x7b)
+#define WCD9378_INTR_TEST_1                    (WCD9378_TAMBORA_BASE+0x7c)
+#define WCD9378_INTR_TEST_2                    (WCD9378_TAMBORA_BASE+0x7d)
+#define WCD9378_INTR_TEST_3                    (WCD9378_TAMBORA_BASE+0x7e)
+#define WCD9378_TX_MODE_DBG_EN                 (WCD9378_TAMBORA_BASE+0x7f)
+#define WCD9378_TX_MODE_DBG_0_1                (WCD9378_TAMBORA_BASE+0x80)
+#define WCD9378_TX_MODE_DBG_2_3                (WCD9378_TAMBORA_BASE+0x81)
+#define WCD9378_LB_IN_SEL_CTL                  (WCD9378_TAMBORA_BASE+0x82)
+#define WCD9378_LOOP_BACK_MODE                 (WCD9378_TAMBORA_BASE+0x83)
+#define WCD9378_SWR_DAC_TEST                   (WCD9378_TAMBORA_BASE+0x84)
+#define WCD9378_SWR_HM_TEST_RX_0               (WCD9378_TAMBORA_BASE+0x85)
+#define WCD9378_SWR_HM_TEST_TX_0               (WCD9378_TAMBORA_BASE+0x86)
+#define WCD9378_SWR_HM_TEST_RX_1               (WCD9378_TAMBORA_BASE+0x87)
+#define WCD9378_SWR_HM_TEST_TX_1               (WCD9378_TAMBORA_BASE+0x88)
+#define WCD9378_SWR_HM_TEST_0                  (WCD9378_TAMBORA_BASE+0x8a)
+#define WCD9378_PAD_CTL_SWR_0                  (WCD9378_TAMBORA_BASE+0x8c)
+#define WCD9378_PAD_CTL_SWR_1                  (WCD9378_TAMBORA_BASE+0x8d)
+#define WCD9378_I2C_CTL                        (WCD9378_TAMBORA_BASE+0x8e)
+#define WCD9378_LEGACY_SW_MODE                 (WCD9378_TAMBORA_BASE+0x8f)
+#define WCD9378_EFUSE_TEST_CTL_0               (WCD9378_TAMBORA_BASE+0x90)
+#define WCD9378_EFUSE_TEST_CTL_1               (WCD9378_TAMBORA_BASE+0x91)
+#define WCD9378_EFUSE_T_DATA_0                 (WCD9378_TAMBORA_BASE+0x92)
+#define WCD9378_PAD_CTL_PDM_RX0                (WCD9378_TAMBORA_BASE+0x94)
+#define WCD9378_PAD_CTL_PDM_RX1                (WCD9378_TAMBORA_BASE+0x95)
+#define WCD9378_PAD_CTL_PDM_TX0                (WCD9378_TAMBORA_BASE+0x96)
+#define WCD9378_PAD_CTL_PDM_TX1                (WCD9378_TAMBORA_BASE+0x97)
+#define WCD9378_PAD_INP_DIS_0                  (WCD9378_TAMBORA_BASE+0x99)
+#define WCD9378_DRIVE_STRENGTH_0               (WCD9378_TAMBORA_BASE+0x9b)
+#define WCD9378_DRIVE_STRENGTH_1               (WCD9378_TAMBORA_BASE+0x9c)
+#define WCD9378_RX_DATA_EDGE_CTL               (WCD9378_TAMBORA_BASE+0x9e)
+#define WCD9378_TX_DATA_EDGE_CTL               (WCD9378_TAMBORA_BASE+0x9f)
+#define WCD9378_GPIO_MODE                      (WCD9378_TAMBORA_BASE+0xa0)
+#define WCD9378_PIN_CTL_OE                     (WCD9378_TAMBORA_BASE+0xa1)
+#define WCD9378_PIN_CTL_DATA_0                 (WCD9378_TAMBORA_BASE+0xa2)
+#define WCD9378_PIN_STATUS_0                   (WCD9378_TAMBORA_BASE+0xa4)
+#define WCD9378_DIG_DEBUG_CTL                  (WCD9378_TAMBORA_BASE+0xa6)
+#define WCD9378_DIG_DEBUG_EN                   (WCD9378_TAMBORA_BASE+0xa7)
+#define WCD9378_ANA_CSR_DBG_ADD                (WCD9378_TAMBORA_BASE+0xa8)
+#define WCD9378_ANA_CSR_DBG_CTL                (WCD9378_TAMBORA_BASE+0xa9)
+#define WCD9378_SSP_DBG                        (WCD9378_TAMBORA_BASE+0xaa)
+#define WCD9378_MODE_STATUS_0                  (WCD9378_TAMBORA_BASE+0xab)
+#define WCD9378_MODE_STATUS_1                  (WCD9378_TAMBORA_BASE+0xac)
+#define WCD9378_SPARE_0                        (WCD9378_TAMBORA_BASE+0xad)
+#define WCD9378_SPARE_1                        (WCD9378_TAMBORA_BASE+0xae)
+#define WCD9378_SPARE_2                        (WCD9378_TAMBORA_BASE+0xaf)
+#define WCD9378_EFUSE_REG_0                    (WCD9378_TAMBORA_BASE+0xb0)
+#define WCD9378_EFUSE_REG_1                    (WCD9378_TAMBORA_BASE+0xb1)
+#define WCD9378_EFUSE_REG_2                    (WCD9378_TAMBORA_BASE+0xb2)
+#define WCD9378_EFUSE_REG_3                    (WCD9378_TAMBORA_BASE+0xb3)
+#define WCD9378_EFUSE_REG_4                    (WCD9378_TAMBORA_BASE+0xb4)
+#define WCD9378_EFUSE_REG_5                    (WCD9378_TAMBORA_BASE+0xb5)
+#define WCD9378_EFUSE_REG_6                    (WCD9378_TAMBORA_BASE+0xb6)
+#define WCD9378_EFUSE_REG_7                    (WCD9378_TAMBORA_BASE+0xb7)
+#define WCD9378_EFUSE_REG_8                    (WCD9378_TAMBORA_BASE+0xb8)
+#define WCD9378_EFUSE_REG_9                    (WCD9378_TAMBORA_BASE+0xb9)
+#define WCD9378_EFUSE_REG_10                   (WCD9378_TAMBORA_BASE+0xba)
+#define WCD9378_EFUSE_REG_11                   (WCD9378_TAMBORA_BASE+0xbb)
+#define WCD9378_EFUSE_REG_12                   (WCD9378_TAMBORA_BASE+0xbc)
+#define WCD9378_EFUSE_REG_13                   (WCD9378_TAMBORA_BASE+0xbd)
+#define WCD9378_EFUSE_REG_14                   (WCD9378_TAMBORA_BASE+0xbe)
+#define WCD9378_EFUSE_REG_15                   (WCD9378_TAMBORA_BASE+0xbf)
+#define WCD9378_EFUSE_REG_16                   (WCD9378_TAMBORA_BASE+0xc0)
+#define WCD9378_EFUSE_REG_17                   (WCD9378_TAMBORA_BASE+0xc1)
+#define WCD9378_EFUSE_REG_18                   (WCD9378_TAMBORA_BASE+0xc2)
+#define WCD9378_EFUSE_REG_19                   (WCD9378_TAMBORA_BASE+0xc3)
+#define WCD9378_EFUSE_REG_20                   (WCD9378_TAMBORA_BASE+0xc4)
+#define WCD9378_EFUSE_REG_21                   (WCD9378_TAMBORA_BASE+0xc5)
+#define WCD9378_EFUSE_REG_22                   (WCD9378_TAMBORA_BASE+0xc6)
+#define WCD9378_EFUSE_REG_23                   (WCD9378_TAMBORA_BASE+0xc7)
+#define WCD9378_EFUSE_REG_24                   (WCD9378_TAMBORA_BASE+0xc8)
+#define WCD9378_EFUSE_REG_25                   (WCD9378_TAMBORA_BASE+0xc9)
+#define WCD9378_EFUSE_REG_26                   (WCD9378_TAMBORA_BASE+0xca)
+#define WCD9378_EFUSE_REG_27                   (WCD9378_TAMBORA_BASE+0xcb)
+#define WCD9378_EFUSE_REG_28                   (WCD9378_TAMBORA_BASE+0xcc)
+#define WCD9378_EFUSE_REG_29                   (WCD9378_TAMBORA_BASE+0xcd)
+#define WCD9378_EFUSE_REG_30                   (WCD9378_TAMBORA_BASE+0xce)
+#define WCD9378_EFUSE_REG_31                   (WCD9378_TAMBORA_BASE+0xcf)
+#define WCD9378_TX_REQ_FB_CTL_2                (WCD9378_TAMBORA_BASE+0xd2)
+#define WCD9378_TX_REQ_FB_CTL_3                (WCD9378_TAMBORA_BASE+0xd3)
+#define WCD9378_TX_REQ_FB_CTL_4                (WCD9378_TAMBORA_BASE+0xd4)
+#define WCD9378_DEM_BYPASS_DATA0               (WCD9378_TAMBORA_BASE+0xd5)
+#define WCD9378_DEM_BYPASS_DATA1               (WCD9378_TAMBORA_BASE+0xd6)
+#define WCD9378_DEM_BYPASS_DATA2               (WCD9378_TAMBORA_BASE+0xd7)
+#define WCD9378_DEM_BYPASS_DATA3               (WCD9378_TAMBORA_BASE+0xd8)
+#define WCD9378_RX0_PCM_RAMP_STEP              (WCD9378_TAMBORA_BASE+0xd9)
+#define WCD9378_RX0_DSD_RAMP_STEP              (WCD9378_TAMBORA_BASE+0xda)
+#define WCD9378_RX1_PCM_RAMP_STEP              (WCD9378_TAMBORA_BASE+0xdb)
+#define WCD9378_RX1_DSD_RAMP_STEP              (WCD9378_TAMBORA_BASE+0xdc)
+#define WCD9378_RX2_RAMP_STEP                  (WCD9378_TAMBORA_BASE+0xdd)
+#define WCD9378_PLATFORM_CTL                   (WCD9378_TAMBORA_BASE+0xf0)
+#define WCD9378_CLK_DIV_CFG                    (WCD9378_TAMBORA_BASE+0xf1)
+#define WCD9378_DRE_DLY_VAL                    (WCD9378_TAMBORA_BASE+0xf2)
+
+#define WCD9378_SEQR_BASE                      (WCD9378_BASE+0x180501)
+#define WCD9378_SYS_USAGE_CTRL                 (WCD9378_SEQR_BASE+0x01)
+#define WCD9378_SURGE_CTL                      (WCD9378_SEQR_BASE+0x02)
+#define WCD9378_SEQ_CTL                        (WCD9378_SEQR_BASE+0x03)
+#define WCD9378_HPH_UP_T0                      (WCD9378_SEQR_BASE+0x10)
+#define WCD9378_HPH_UP_T1                      (WCD9378_SEQR_BASE+0x11)
+#define WCD9378_HPH_UP_T2                      (WCD9378_SEQR_BASE+0x12)
+#define WCD9378_HPH_UP_T3                      (WCD9378_SEQR_BASE+0x13)
+#define WCD9378_HPH_UP_T4                      (WCD9378_SEQR_BASE+0x14)
+#define WCD9378_HPH_UP_T5                      (WCD9378_SEQR_BASE+0x15)
+#define WCD9378_HPH_UP_T6                      (WCD9378_SEQR_BASE+0x16)
+#define WCD9378_HPH_UP_T7                      (WCD9378_SEQR_BASE+0x17)
+#define WCD9378_HPH_UP_T8                      (WCD9378_SEQR_BASE+0x18)
+#define WCD9378_HPH_UP_T9                      (WCD9378_SEQR_BASE+0x19)
+#define WCD9378_HPH_UP_T10                     (WCD9378_SEQR_BASE+0x1a)
+#define WCD9378_HPH_DN_T0                      (WCD9378_SEQR_BASE+0x1b)
+#define WCD9378_HPH_DN_T1                      (WCD9378_SEQR_BASE+0x1c)
+#define WCD9378_HPH_DN_T2                      (WCD9378_SEQR_BASE+0x1d)
+#define WCD9378_HPH_DN_T3                      (WCD9378_SEQR_BASE+0x1e)
+#define WCD9378_HPH_DN_T4                      (WCD9378_SEQR_BASE+0x1f)
+#define WCD9378_HPH_DN_T5                      (WCD9378_SEQR_BASE+0x20)
+#define WCD9378_HPH_DN_T6                      (WCD9378_SEQR_BASE+0x21)
+#define WCD9378_HPH_DN_T7                      (WCD9378_SEQR_BASE+0x22)
+#define WCD9378_HPH_DN_T8                      (WCD9378_SEQR_BASE+0x23)
+#define WCD9378_HPH_DN_T9                      (WCD9378_SEQR_BASE+0x24)
+#define WCD9378_HPH_DN_T10                     (WCD9378_SEQR_BASE+0x25)
+#define WCD9378_HPH_UP_STAGE_LOC_0             (WCD9378_SEQR_BASE+0x26)
+#define WCD9378_HPH_UP_STAGE_LOC_1             (WCD9378_SEQR_BASE+0x27)
+#define WCD9378_HPH_UP_STAGE_LOC_2             (WCD9378_SEQR_BASE+0x28)
+#define WCD9378_HPH_UP_STAGE_LOC_3             (WCD9378_SEQR_BASE+0x29)
+#define WCD9378_HPH_UP_STAGE_LOC_4             (WCD9378_SEQR_BASE+0x2a)
+#define WCD9378_HPH_UP_STAGE_LOC_5             (WCD9378_SEQR_BASE+0x2b)
+#define WCD9378_HPH_UP_STAGE_LOC_6             (WCD9378_SEQR_BASE+0x2c)
+#define WCD9378_HPH_UP_STAGE_LOC_7             (WCD9378_SEQR_BASE+0x2d)
+#define WCD9378_HPH_UP_STAGE_LOC_8             (WCD9378_SEQR_BASE+0x2e)
+#define WCD9378_HPH_UP_STAGE_LOC_9             (WCD9378_SEQR_BASE+0x2f)
+#define WCD9378_HPH_UP_STAGE_LOC_10            (WCD9378_SEQR_BASE+0x30)
+#define WCD9378_HPH_DN_STAGE_LOC_0             (WCD9378_SEQR_BASE+0x31)
+#define WCD9378_HPH_DN_STAGE_LOC_1             (WCD9378_SEQR_BASE+0x32)
+#define WCD9378_HPH_DN_STAGE_LOC_2             (WCD9378_SEQR_BASE+0x33)
+#define WCD9378_HPH_DN_STAGE_LOC_3             (WCD9378_SEQR_BASE+0x34)
+#define WCD9378_HPH_DN_STAGE_LOC_4             (WCD9378_SEQR_BASE+0x35)
+#define WCD9378_HPH_DN_STAGE_LOC_5             (WCD9378_SEQR_BASE+0x36)
+#define WCD9378_HPH_DN_STAGE_LOC_6             (WCD9378_SEQR_BASE+0x37)
+#define WCD9378_HPH_DN_STAGE_LOC_7             (WCD9378_SEQR_BASE+0x38)
+#define WCD9378_HPH_DN_STAGE_LOC_8             (WCD9378_SEQR_BASE+0x39)
+#define WCD9378_HPH_DN_STAGE_LOC_9             (WCD9378_SEQR_BASE+0x3a)
+#define WCD9378_HPH_DN_STAGE_LOC_10            (WCD9378_SEQR_BASE+0x3b)
+#define WCD9378_SA_UP_T0                       (WCD9378_SEQR_BASE+0x40)
+#define WCD9378_SA_UP_T1                       (WCD9378_SEQR_BASE+0x41)
+#define WCD9378_SA_UP_T2                       (WCD9378_SEQR_BASE+0x42)
+#define WCD9378_SA_UP_T3                       (WCD9378_SEQR_BASE+0x43)
+#define WCD9378_SA_UP_T4                       (WCD9378_SEQR_BASE+0x44)
+#define WCD9378_SA_UP_T5                       (WCD9378_SEQR_BASE+0x45)
+#define WCD9378_SA_UP_T6                       (WCD9378_SEQR_BASE+0x46)
+#define WCD9378_SA_UP_T7                       (WCD9378_SEQR_BASE+0x47)
+#define WCD9378_SA_DN_T0                       (WCD9378_SEQR_BASE+0x48)
+#define WCD9378_SA_DN_T1                       (WCD9378_SEQR_BASE+0x49)
+#define WCD9378_SA_DN_T2                       (WCD9378_SEQR_BASE+0x4a)
+#define WCD9378_SA_DN_T3                       (WCD9378_SEQR_BASE+0x4b)
+#define WCD9378_SA_DN_T4                       (WCD9378_SEQR_BASE+0x4c)
+#define WCD9378_SA_DN_T5                       (WCD9378_SEQR_BASE+0x4d)
+#define WCD9378_SA_DN_T6                       (WCD9378_SEQR_BASE+0x4e)
+#define WCD9378_SA_DN_T7                       (WCD9378_SEQR_BASE+0x4f)
+#define WCD9378_SA_UP_STAGE_LOC_0              (WCD9378_SEQR_BASE+0x50)
+#define WCD9378_SA_UP_STAGE_LOC_1              (WCD9378_SEQR_BASE+0x51)
+#define WCD9378_SA_UP_STAGE_LOC_2              (WCD9378_SEQR_BASE+0x52)
+#define WCD9378_SA_UP_STAGE_LOC_3              (WCD9378_SEQR_BASE+0x53)
+#define WCD9378_SA_UP_STAGE_LOC_4              (WCD9378_SEQR_BASE+0x54)
+#define WCD9378_SA_UP_STAGE_LOC_5              (WCD9378_SEQR_BASE+0x55)
+#define WCD9378_SA_UP_STAGE_LOC_6              (WCD9378_SEQR_BASE+0x56)
+#define WCD9378_SA_UP_STAGE_LOC_7              (WCD9378_SEQR_BASE+0x57)
+#define WCD9378_SA_DN_STAGE_LOC_0              (WCD9378_SEQR_BASE+0x58)
+#define WCD9378_SA_DN_STAGE_LOC_1              (WCD9378_SEQR_BASE+0x59)
+#define WCD9378_SA_DN_STAGE_LOC_2              (WCD9378_SEQR_BASE+0x5a)
+#define WCD9378_SA_DN_STAGE_LOC_3              (WCD9378_SEQR_BASE+0x5b)
+#define WCD9378_SA_DN_STAGE_LOC_4              (WCD9378_SEQR_BASE+0x5c)
+#define WCD9378_SA_DN_STAGE_LOC_5              (WCD9378_SEQR_BASE+0x5d)
+#define WCD9378_SA_DN_STAGE_LOC_6              (WCD9378_SEQR_BASE+0x5e)
+#define WCD9378_SA_DN_STAGE_LOC_7              (WCD9378_SEQR_BASE+0x5f)
+#define WCD9378_TX0_UP_T0                      (WCD9378_SEQR_BASE+0x60)
+#define WCD9378_TX0_UP_T1                      (WCD9378_SEQR_BASE+0x61)
+#define WCD9378_TX0_UP_T2                      (WCD9378_SEQR_BASE+0x62)
+#define WCD9378_TX0_UP_T3                      (WCD9378_SEQR_BASE+0x63)
+#define WCD9378_TX0_DN_T0                      (WCD9378_SEQR_BASE+0x64)
+#define WCD9378_TX0_DN_T1                      (WCD9378_SEQR_BASE+0x65)
+#define WCD9378_TX0_DN_T2                      (WCD9378_SEQR_BASE+0x66)
+#define WCD9378_TX0_DN_T3                      (WCD9378_SEQR_BASE+0x67)
+#define WCD9378_TX0_UP_STAGE_LOC_0             (WCD9378_SEQR_BASE+0x68)
+#define WCD9378_TX0_UP_STAGE_LOC_1             (WCD9378_SEQR_BASE+0x69)
+#define WCD9378_TX0_UP_STAGE_LOC_2             (WCD9378_SEQR_BASE+0x6a)
+#define WCD9378_TX0_UP_STAGE_LOC_3             (WCD9378_SEQR_BASE+0x6b)
+#define WCD9378_TX0_DN_STAGE_LOC_0             (WCD9378_SEQR_BASE+0x6c)
+#define WCD9378_TX0_DN_STAGE_LOC_1             (WCD9378_SEQR_BASE+0x6d)
+#define WCD9378_TX0_DN_STAGE_LOC_2             (WCD9378_SEQR_BASE+0x6e)
+#define WCD9378_TX0_DN_STAGE_LOC_3             (WCD9378_SEQR_BASE+0x6f)
+#define WCD9378_TX1_UP_T0                      (WCD9378_SEQR_BASE+0x70)
+#define WCD9378_TX1_UP_T1                      (WCD9378_SEQR_BASE+0x71)
+#define WCD9378_TX1_UP_T2                      (WCD9378_SEQR_BASE+0x72)
+#define WCD9378_TX1_UP_T3                      (WCD9378_SEQR_BASE+0x73)
+#define WCD9378_TX1_DN_T0                      (WCD9378_SEQR_BASE+0x74)
+#define WCD9378_TX1_DN_T1                      (WCD9378_SEQR_BASE+0x75)
+#define WCD9378_TX1_DN_T2                      (WCD9378_SEQR_BASE+0x76)
+#define WCD9378_TX1_DN_T3                      (WCD9378_SEQR_BASE+0x77)
+#define WCD9378_TX1_UP_STAGE_LOC_0             (WCD9378_SEQR_BASE+0x78)
+#define WCD9378_TX1_UP_STAGE_LOC_1             (WCD9378_SEQR_BASE+0x79)
+#define WCD9378_TX1_UP_STAGE_LOC_2             (WCD9378_SEQR_BASE+0x7a)
+#define WCD9378_TX1_UP_STAGE_LOC_3             (WCD9378_SEQR_BASE+0x7b)
+#define WCD9378_TX1_DN_STAGE_LOC_0             (WCD9378_SEQR_BASE+0x7c)
+#define WCD9378_TX1_DN_STAGE_LOC_1             (WCD9378_SEQR_BASE+0x7d)
+#define WCD9378_TX1_DN_STAGE_LOC_2             (WCD9378_SEQR_BASE+0x7e)
+#define WCD9378_TX1_DN_STAGE_LOC_3             (WCD9378_SEQR_BASE+0x7f)
+#define WCD9378_TX2_UP_T0                      (WCD9378_SEQR_BASE+0x80)
+#define WCD9378_TX2_UP_T1                      (WCD9378_SEQR_BASE+0x81)
+#define WCD9378_TX2_UP_T2                      (WCD9378_SEQR_BASE+0x82)
+#define WCD9378_TX2_UP_T3                      (WCD9378_SEQR_BASE+0x83)
+#define WCD9378_TX2_DN_T0                      (WCD9378_SEQR_BASE+0x84)
+#define WCD9378_TX2_DN_T1                      (WCD9378_SEQR_BASE+0x85)
+#define WCD9378_TX2_DN_T2                      (WCD9378_SEQR_BASE+0x86)
+#define WCD9378_TX2_DN_T3                      (WCD9378_SEQR_BASE+0x87)
+#define WCD9378_TX2_UP_STAGE_LOC_0             (WCD9378_SEQR_BASE+0x88)
+#define WCD9378_TX2_UP_STAGE_LOC_1             (WCD9378_SEQR_BASE+0x89)
+#define WCD9378_TX2_UP_STAGE_LOC_2             (WCD9378_SEQR_BASE+0x8a)
+#define WCD9378_TX2_UP_STAGE_LOC_3             (WCD9378_SEQR_BASE+0x8b)
+#define WCD9378_TX2_DN_STAGE_LOC_0             (WCD9378_SEQR_BASE+0x8c)
+#define WCD9378_TX2_DN_STAGE_LOC_1             (WCD9378_SEQR_BASE+0x8d)
+#define WCD9378_TX2_DN_STAGE_LOC_2             (WCD9378_SEQR_BASE+0x8e)
+#define WCD9378_TX2_DN_STAGE_LOC_3             (WCD9378_SEQR_BASE+0x8f)
+#define WCD9378_SEQ_HPH_STAT                   (WCD9378_SEQR_BASE+0x90)
+#define WCD9378_SEQ_SA_STAT                    (WCD9378_SEQR_BASE+0x91)
+#define WCD9378_SEQ_TX0_STAT                   (WCD9378_SEQR_BASE+0x92)
+#define WCD9378_SEQ_TX1_STAT                   (WCD9378_SEQR_BASE+0x93)
+#define WCD9378_SEQ_TX2_STAT                   (WCD9378_SEQR_BASE+0x94)
+#define WCD9378_MICB_REMAP_TABLE_VAL_0         (WCD9378_SEQR_BASE+0xa0)
+#define WCD9378_MICB_REMAP_TABLE_VAL_1         (WCD9378_SEQR_BASE+0xa1)
+#define WCD9378_MICB_REMAP_TABLE_VAL_2         (WCD9378_SEQR_BASE+0xa2)
+#define WCD9378_MICB_REMAP_TABLE_VAL_3         (WCD9378_SEQR_BASE+0xa3)
+#define WCD9378_MICB_REMAP_TABLE_VAL_4         (WCD9378_SEQR_BASE+0xa4)
+#define WCD9378_MICB_REMAP_TABLE_VAL_5         (WCD9378_SEQR_BASE+0xa5)
+#define WCD9378_MICB_REMAP_TABLE_VAL_6         (WCD9378_SEQR_BASE+0xa6)
+#define WCD9378_MICB_REMAP_TABLE_VAL_7         (WCD9378_SEQR_BASE+0xa7)
+#define WCD9378_MICB_REMAP_TABLE_VAL_8         (WCD9378_SEQR_BASE+0xa8)
+#define WCD9378_MICB_REMAP_TABLE_VAL_9         (WCD9378_SEQR_BASE+0xa9)
+#define WCD9378_MICB_REMAP_TABLE_VAL_10        (WCD9378_SEQR_BASE+0xaa)
+#define WCD9378_MICB_REMAP_TABLE_VAL_11        (WCD9378_SEQR_BASE+0xab)
+#define WCD9378_MICB_REMAP_TABLE_VAL_12        (WCD9378_SEQR_BASE+0xac)
+#define WCD9378_MICB_REMAP_TABLE_VAL_13        (WCD9378_SEQR_BASE+0xad)
+#define WCD9378_MICB_REMAP_TABLE_VAL_14        (WCD9378_SEQR_BASE+0xae)
+#define WCD9378_MICB_REMAP_TABLE_VAL_15        (WCD9378_SEQR_BASE+0xaf)
+#define WCD9378_SM0_MB_SEL                     (WCD9378_SEQR_BASE+0xb0)
+#define WCD9378_SM1_MB_SEL                     (WCD9378_SEQR_BASE+0xb1)
+#define WCD9378_SM2_MB_SEL                     (WCD9378_SEQR_BASE+0xb2)
+#define WCD9378_MB_PULLUP_EN                   (WCD9378_SEQR_BASE+0xb3)
+#define WCD9378_BYP_EN_CTL0                    (WCD9378_SEQR_BASE+0xc0)
+#define WCD9378_BYP_EN_CTL1                    (WCD9378_SEQR_BASE+0xc1)
+#define WCD9378_BYP_EN_CTL2                    (WCD9378_SEQR_BASE+0xc2)
+#define WCD9378_SEQ_OVRRIDE_CTL0               (WCD9378_SEQR_BASE+0xc3)
+#define WCD9378_SEQ_OVRRIDE_CTL1               (WCD9378_SEQR_BASE+0xc4)
+#define WCD9378_SEQ_OVRRIDE_CTL2               (WCD9378_SEQR_BASE+0xc5)
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL0           (WCD9378_SEQR_BASE+0xc7)
+#define WCD9378_HPH_SEQ_OVRRIDE_CTL1           (WCD9378_SEQR_BASE+0xc8)
+#define WCD9378_SA_SEQ_OVRRIDE_CTL             (WCD9378_SEQR_BASE+0xc9)
+#define WCD9378_TX0_SEQ_OVRRIDE_CTL            (WCD9378_SEQR_BASE+0xca)
+#define WCD9378_TX1_SEQ_OVRRIDE_CTL            (WCD9378_SEQR_BASE+0xcb)
+#define WCD9378_TX2_SEQ_OVRRIDE_CTL            (WCD9378_SEQR_BASE+0xcc)
+#define WCD9378_FORCE_CTL                      (WCD9378_SEQR_BASE+0xcd)
+
+#define WCD9378_MBHC_BASE                      (WCD9378_BASE+0x180601)
+#define WCD9378_DEVICE_DET                     (WCD9378_MBHC_BASE+0x01)
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0  (WCD9378_MBHC_BASE+0x10)
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0  (WCD9378_MBHC_BASE+0x11)
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x12)
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0 (WCD9378_MBHC_BASE+0x13)
+#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x14)
+#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0  (WCD9378_MBHC_BASE+0x15)
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1  (WCD9378_MBHC_BASE+0x20)
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1  (WCD9378_MBHC_BASE+0x21)
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x22)
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1 (WCD9378_MBHC_BASE+0x23)
+#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x24)
+#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1  (WCD9378_MBHC_BASE+0x25)
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2  (WCD9378_MBHC_BASE+0x30)
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2  (WCD9378_MBHC_BASE+0x31)
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x32)
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2 (WCD9378_MBHC_BASE+0x33)
+#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x34)
+#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2  (WCD9378_MBHC_BASE+0x35)
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3  (WCD9378_MBHC_BASE+0x40)
+#define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3  (WCD9378_MBHC_BASE+0x41)
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x42)
+#define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3 (WCD9378_MBHC_BASE+0x43)
+#define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x44)
+#define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3  (WCD9378_MBHC_BASE+0x45)
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0  (WCD9378_MBHC_BASE+0x50)
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0  (WCD9378_MBHC_BASE+0x51)
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x52)
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0 (WCD9378_MBHC_BASE+0x53)
+#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x54)
+#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0  (WCD9378_MBHC_BASE+0x55)
+#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0   (WCD9378_MBHC_BASE+0x56)
+#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x57)
+#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x58)
+#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0      (WCD9378_MBHC_BASE+0x59)
+#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0  (WCD9378_MBHC_BASE+0x5b)
+#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0       (WCD9378_MBHC_BASE+0x5c)
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1  (WCD9378_MBHC_BASE+0x60)
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1  (WCD9378_MBHC_BASE+0x61)
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x62)
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1 (WCD9378_MBHC_BASE+0x63)
+#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x64)
+#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1  (WCD9378_MBHC_BASE+0x65)
+#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1   (WCD9378_MBHC_BASE+0x66)
+#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x67)
+#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x68)
+#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1      (WCD9378_MBHC_BASE+0x69)
+#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1  (WCD9378_MBHC_BASE+0x6b)
+#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1       (WCD9378_MBHC_BASE+0x6c)
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2  (WCD9378_MBHC_BASE+0x70)
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2  (WCD9378_MBHC_BASE+0x71)
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x72)
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2 (WCD9378_MBHC_BASE+0x73)
+#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x74)
+#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2  (WCD9378_MBHC_BASE+0x75)
+#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2   (WCD9378_MBHC_BASE+0x76)
+#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x77)
+#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x78)
+#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2      (WCD9378_MBHC_BASE+0x79)
+#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2  (WCD9378_MBHC_BASE+0x7b)
+#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2       (WCD9378_MBHC_BASE+0x7c)
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3  (WCD9378_MBHC_BASE+0x80)
+#define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3  (WCD9378_MBHC_BASE+0x81)
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x82)
+#define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3 (WCD9378_MBHC_BASE+0x83)
+#define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x84)
+#define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3  (WCD9378_MBHC_BASE+0x85)
+#define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3   (WCD9378_MBHC_BASE+0x86)
+#define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x87)
+#define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x88)
+#define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3      (WCD9378_MBHC_BASE+0x89)
+#define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3  (WCD9378_MBHC_BASE+0x8b)
+#define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3       (WCD9378_MBHC_BASE+0x8c)
+#define WCD9378_SDCA_MESSAGE_GATE              (WCD9378_MBHC_BASE+0x8d)
+#define WCD9378_MBHC_DATA_IN_EDGE              (WCD9378_MBHC_BASE+0x90)
+#define WCD9378_MBHC_RESET                     (WCD9378_MBHC_BASE+0x91)
+#define WCD9378_MBHC_DEBUG                     (WCD9378_MBHC_BASE+0x92)
+#define WCD9378_MBHC_DEBUG_UMP_0               (WCD9378_MBHC_BASE+0x93)
+#define WCD9378_MBHC_DEBUG_UMP_1               (WCD9378_MBHC_BASE+0x94)
+#define WCD9378_MBHC_DEBUG_UMP_2               (WCD9378_MBHC_BASE+0x95)
+
+#define WCD9378_HID_BASE                       (WCD9378_BASE+0x400001)
+#define WCD9378_HID_FUNC_EXT_ID_0              (WCD9378_HID_BASE+0x48)
+#define WCD9378_HID_FUNC_EXT_ID_1              (WCD9378_HID_BASE+0x49)
+#define WCD9378_HID_FUNC_EXT_VER               (WCD9378_HID_BASE+0x50)
+#define WCD9378_HID_FUNC_STAT                  (WCD9378_HID_BASE+0x80000)
+#define WCD9378_HID_CUR_OWNER                  (WCD9378_HID_BASE+0x80080)
+#define WCD9378_HID_MSG_OFFSET                 (WCD9378_HID_BASE+0x80090)
+#define WCD9378_HID_MSG_LENGTH                 (WCD9378_HID_BASE+0x80098)
+#define WCD9378_HID_DEV_MANU_ID_0              (WCD9378_HID_BASE+0x100060)
+#define WCD9378_HID_DEV_MANU_ID_1              (WCD9378_HID_BASE+0x100061)
+#define WCD9378_HID_DEV_PART_ID_0              (WCD9378_HID_BASE+0x100068)
+#define WCD9378_HID_DEV_PART_ID_1              (WCD9378_HID_BASE+0x100069)
+#define WCD9378_HID_DEV_VER                    (WCD9378_HID_BASE+0x100070)
+
+#define WCD9378_SMP_AMP_BASE                   (WCD9378_BASE+0x800001)
+#define WCD9378_SMP_AMP_FUNC_EXT_ID_0          (WCD9378_SMP_AMP_BASE+0x48)
+#define WCD9378_SMP_AMP_FUNC_EXT_ID_1          (WCD9378_SMP_AMP_BASE+0x49)
+#define WCD9378_SMP_AMP_FUNC_EXT_VER           (WCD9378_SMP_AMP_BASE+0x50)
+#define WCD9378_XU22_BYP                       (WCD9378_SMP_AMP_BASE+0x188)
+#define WCD9378_PDE22_REQ_PS                   (WCD9378_SMP_AMP_BASE+0x208)
+#define WCD9378_FU23_MUTE                      (WCD9378_SMP_AMP_BASE+0x388)
+#define WCD9378_PDE23_REQ_PS                   (WCD9378_SMP_AMP_BASE+0x408)
+#define WCD9378_SMP_AMP_FUNC_STAT              (WCD9378_SMP_AMP_BASE+0x80000)
+#define WCD9378_FUNC_ACT                       (WCD9378_SMP_AMP_BASE+0x80008)
+#define WCD9378_PDE22_ACT_PS                   (WCD9378_SMP_AMP_BASE+0x80200)
+#define WCD9378_SAPU29_PROT_MODE               (WCD9378_SMP_AMP_BASE+0x80280)
+#define WCD9378_SAPU29_PROT_STAT               (WCD9378_SMP_AMP_BASE+0x80288)
+#define WCD9378_PDE23_ACT_PS                   (WCD9378_SMP_AMP_BASE+0x80400)
+#define WCD9378_SMP_AMP_DEV_MANU_ID_0          (WCD9378_SMP_AMP_BASE+0x100060)
+#define WCD9378_SMP_AMP_DEV_MANU_ID_1          (WCD9378_SMP_AMP_BASE+0x100061)
+#define WCD9378_SMP_AMP_DEV_PART_ID_0          (WCD9378_SMP_AMP_BASE+0x100068)
+#define WCD9378_SMP_AMP_DEV_PART_ID_1          (WCD9378_SMP_AMP_BASE+0x100069)
+#define WCD9378_SMP_AMP_DEV_VER                (WCD9378_SMP_AMP_BASE+0x100070)
+
+#define WCD9378_SMP_JACK_BASE                  (WCD9378_BASE+0xc00001)
+#define WCD9378_CMT_GRP_MASK                   (WCD9378_SMP_JACK_BASE+0x08)
+#define WCD9378_SMP_JACK_FUNC_EXT_ID_0         (WCD9378_SMP_JACK_BASE+0x48)
+#define WCD9378_SMP_JACK_FUNC_EXT_ID_1         (WCD9378_SMP_JACK_BASE+0x49)
+#define WCD9378_SMP_JACK_FUNC_EXT_VER          (WCD9378_SMP_JACK_BASE+0x50)
+#define WCD9378_IT41_USAGE                     (WCD9378_SMP_JACK_BASE+0xa0)
+#define WCD9378_XU42_BYP                       (WCD9378_SMP_JACK_BASE+0x208)
+#define WCD9378_PDE42_REQ_PS                   (WCD9378_SMP_JACK_BASE+0x288)
+#define WCD9378_FU42_MUTE_CH1                  (WCD9378_SMP_JACK_BASE+0x309)
+#define WCD9378_FU42_MUTE_CH2                  (WCD9378_SMP_JACK_BASE+0x30a)
+#define WCD9378_FU42_CH_VOL_CH1                (WCD9378_SMP_JACK_BASE+0x311)
+#define WCD9378_FU42_CH_VOL_CH2                (WCD9378_SMP_JACK_BASE+0x312)
+#define WCD9378_SU43_SELECTOR                  (WCD9378_SMP_JACK_BASE+0x388)
+#define WCD9378_SU45_SELECTOR                  (WCD9378_SMP_JACK_BASE+0x408)
+#define WCD9378_PDE47_REQ_PS                   (WCD9378_SMP_JACK_BASE+0x488)
+#define WCD9378_GE35_SEL_MODE                  (WCD9378_SMP_JACK_BASE+0x608)
+#define WCD9378_GE35_DET_MODE                  (WCD9378_SMP_JACK_BASE+0x610)
+#define WCD9378_IT31_MICB                      (WCD9378_SMP_JACK_BASE+0x798)
+#define WCD9378_IT31_USAGE                     (WCD9378_SMP_JACK_BASE+0x7a0)
+#define WCD9378_PDE34_REQ_PS                   (WCD9378_SMP_JACK_BASE+0x808)
+#define WCD9378_SU45_TX_SELECTOR               (WCD9378_SMP_JACK_BASE+0x908)
+#define WCD9378_XU36_BYP                       (WCD9378_SMP_JACK_BASE+0x988)
+#define WCD9378_PDE36_REQ_PS                   (WCD9378_SMP_JACK_BASE+0xa08)
+#define WCD9378_OT36_USAGE                     (WCD9378_SMP_JACK_BASE+0xb20)
+#define WCD9378_SMP_JACK_FUNC_STAT             (WCD9378_SMP_JACK_BASE+0x80000)
+#define WCD9378_SMP_JACK_FUNC_ACT              (WCD9378_SMP_JACK_BASE+0x80008)
+#define WCD9378_PDE42_ACT_PS                   (WCD9378_SMP_JACK_BASE+0x80280)
+#define WCD9378_PDE47_ACT_PS                   (WCD9378_SMP_JACK_BASE+0x80480)
+#define WCD9378_PDE34_ACT_PS                   (WCD9378_SMP_JACK_BASE+0x80800)
+#define WCD9378_PDE36_ACT_PS                   (WCD9378_SMP_JACK_BASE+0x80a00)
+#define WCD9378_SMP_JACK_DEV_MANU_ID_0         (WCD9378_SMP_JACK_BASE+0x100060)
+#define WCD9378_SMP_JACK_DEV_MANU_ID_1         (WCD9378_SMP_JACK_BASE+0x100061)
+#define WCD9378_SMP_JACK_DEV_PART_ID_0         (WCD9378_SMP_JACK_BASE+0x100068)
+#define WCD9378_SMP_JACK_DEV_PART_ID_1         (WCD9378_SMP_JACK_BASE+0x100069)
+#define WCD9378_SMP_JACK_DEV_VER               (WCD9378_SMP_JACK_BASE+0x100070)
+
+#define WCD9378_SMP_MIC_CTRL0_BASE             (WCD9378_BASE+0x1000001)
+#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0    (WCD9378_SMP_MIC_CTRL0_BASE+0x48)
+#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1    (WCD9378_SMP_MIC_CTRL0_BASE+0x49)
+#define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER     (WCD9378_SMP_MIC_CTRL0_BASE+0x50)
+#define WCD9378_IT11_MICB                      (WCD9378_SMP_MIC_CTRL0_BASE+0x98)
+#define WCD9378_IT11_USAGE                     (WCD9378_SMP_MIC_CTRL0_BASE+0xa0)
+#define WCD9378_PDE11_REQ_PS                   (WCD9378_SMP_MIC_CTRL0_BASE+0x108)
+#define WCD9378_OT10_USAGE                     (WCD9378_SMP_MIC_CTRL0_BASE+0x3a0)
+#define WCD9378_SMP_MIC_CTRL0_FUNC_STAT        (WCD9378_SMP_MIC_CTRL0_BASE+0x80000)
+#define WCD9378_SMP_MIC_CTRL0_FUNC_ACT         (WCD9378_SMP_MIC_CTRL0_BASE+0x80008)
+#define WCD9378_PDE11_ACT_PS                   (WCD9378_SMP_MIC_CTRL0_BASE+0x80100)
+#define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0    (WCD9378_SMP_MIC_CTRL0_BASE+0x100060)
+#define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1    (WCD9378_SMP_MIC_CTRL0_BASE+0x100061)
+#define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0    (WCD9378_SMP_MIC_CTRL0_BASE+0x100068)
+#define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1    (WCD9378_SMP_MIC_CTRL0_BASE+0x100069)
+#define WCD9378_SMP_MIC_CTRL0_DEV_VER          (WCD9378_SMP_MIC_CTRL0_BASE+0x100070)
+
+#define WCD9378_SMP_MIC_CTRL1_BASE             (WCD9378_BASE+0x1400001)
+#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0    (WCD9378_SMP_MIC_CTRL1_BASE+0x48)
+#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1    (WCD9378_SMP_MIC_CTRL1_BASE+0x49)
+#define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER     (WCD9378_SMP_MIC_CTRL1_BASE+0x50)
+#define WCD9378_SMP_MIC_CTRL1_IT11_MICB        (WCD9378_SMP_MIC_CTRL1_BASE+0x98)
+#define WCD9378_SMP_MIC_CTRL1_IT11_USAGE       (WCD9378_SMP_MIC_CTRL1_BASE+0xa0)
+#define WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS     (WCD9378_SMP_MIC_CTRL1_BASE+0x108)
+#define WCD9378_SMP_MIC_CTRL1_OT10_USAGE       (WCD9378_SMP_MIC_CTRL1_BASE+0x3a0)
+#define WCD9378_SMP_MIC_CTRL1_FUNC_STAT        (WCD9378_SMP_MIC_CTRL1_BASE+0x80000)
+#define WCD9378_SMP_MIC_CTRL1_FUNC_ACT         (WCD9378_SMP_MIC_CTRL1_BASE+0x80008)
+#define WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS     (WCD9378_SMP_MIC_CTRL1_BASE+0x80100)
+#define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0    (WCD9378_SMP_MIC_CTRL1_BASE+0x100060)
+#define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1    (WCD9378_SMP_MIC_CTRL1_BASE+0x100061)
+#define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0    (WCD9378_SMP_MIC_CTRL1_BASE+0x100068)
+#define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1    (WCD9378_SMP_MIC_CTRL1_BASE+0x100069)
+#define WCD9378_SMP_MIC_CTRL1_DEV_VER          (WCD9378_SMP_MIC_CTRL1_BASE+0x100070)
+
+#define WCD9378_SMP_MIC_CTRL2_BASE             (WCD9378_BASE+0x1800001)
+#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0    (WCD9378_SMP_MIC_CTRL2_BASE+0x48)
+#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1    (WCD9378_SMP_MIC_CTRL2_BASE+0x49)
+#define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER     (WCD9378_SMP_MIC_CTRL2_BASE+0x50)
+#define WCD9378_SMP_MIC_CTRL2_IT11_MICB        (WCD9378_SMP_MIC_CTRL2_BASE+0x98)
+#define WCD9378_SMP_MIC_CTRL2_IT11_USAGE       (WCD9378_SMP_MIC_CTRL2_BASE+0xa0)
+#define WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS     (WCD9378_SMP_MIC_CTRL2_BASE+0x108)
+#define WCD9378_SMP_MIC_CTRL2_OT10_USAGE       (WCD9378_SMP_MIC_CTRL2_BASE+0x3a0)
+#define WCD9378_SMP_MIC_CTRL2_FUNC_STAT        (WCD9378_SMP_MIC_CTRL2_BASE+0x80000)
+#define WCD9378_SMP_MIC_CTRL2_FUNC_ACT         (WCD9378_SMP_MIC_CTRL2_BASE+0x80008)
+#define WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS     (WCD9378_SMP_MIC_CTRL2_BASE+0x80100)
+#define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0    (WCD9378_SMP_MIC_CTRL2_BASE+0x100060)
+#define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1    (WCD9378_SMP_MIC_CTRL2_BASE+0x100061)
+#define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0    (WCD9378_SMP_MIC_CTRL2_BASE+0x100068)
+#define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1    (WCD9378_SMP_MIC_CTRL2_BASE+0x100069)
+#define WCD9378_SMP_MIC_CTRL2_DEV_VER          (WCD9378_SMP_MIC_CTRL2_BASE+0x100070)
+
+#define WCD9378_HID_MEM_BASE                   (WCD9378_BASE+0x4000001)
+#define WCD9378_REPORT_ID                      (WCD9378_HID_MEM_BASE+0x01)
+#define WCD9378_MESSAGE0                       (WCD9378_HID_MEM_BASE+0x02)
+#define WCD9378_MESSAGE1                       (WCD9378_HID_MEM_BASE+0x03)
+#define WCD9378_MESSAGE2                       (WCD9378_HID_MEM_BASE+0x04)
+
+#define WCD9378_NUM_REGISTERS                  (WCD9378_SMP_MIC_CTRL2_DEV_VER - WCD9378_BASE + 1)
+#define WCD9378_MAX_REGISTER                   (WCD9378_MESSAGE2 + 1)
+
+#define WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT                          0x03
+#define WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT                          0x00
+#define WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT                          0x00
+#define WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT                         0x03
+#define WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT                         0x02
+
+#define SWRS_SCP_BASE_CLK_BASE                 (0x004d)
+#define SWRS_SCP_BUSCLOCK_SCALE_BANK0          (0x0062)
+#define SWRS_SCP_BUSCLOCK_SCALE_BANK1          (0x0072)
+
+#define SWRS_SCP_SDCA_INTMASK_1                (0x0000005c)
+#define SWRS_SCP_SDCA_INTMASK_2                (0x0000005d)
+#define SWRS_SCP_SDCA_INTMASK_3                (0x0000005e)
+
+#define SWRS_SCP_SDCA_INTSTAT_1                (0x00000058)
+#define SWRS_SCP_SDCA_INTSTAT_2                (0x00000059)
+#define SWRS_SCP_SDCA_INTSTAT_3                (0x0000005a)
+
+#define SWRS_SCP_SDCA_INTRTYPE_1               (0x000000f4)
+#define SWRS_SCP_SDCA_INTRTYPE_2               (0x000000f8)
+#define SWRS_SCP_SDCA_INTRTYPE_3               (0x000000fc)
+
+
+#endif /* WCD9378_REGISTERS_H */

asoc/codecs/wcd9378/wcd9378-regmap.c

@@ -0,0 +1,939 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd9378-registers.h"
+
+extern const u8 wcd9378_reg_access[WCD9378_NUM_REGISTERS];
+
+static struct reg_default wcd9378_defaults[] = {
+	{SWRS_SCP_SDCA_INTSTAT_1,                0x00},
+	{SWRS_SCP_SDCA_INTSTAT_2,                0x00},
+	{SWRS_SCP_SDCA_INTSTAT_2,                0x00},
+	{SWRS_SCP_SDCA_INTMASK_1,                0x00},
+	{SWRS_SCP_SDCA_INTMASK_2,                0x00},
+	{SWRS_SCP_SDCA_INTMASK_3,                0x00},
+	{SWRS_SCP_SDCA_INTRTYPE_1,               0x00},
+	{SWRS_SCP_SDCA_INTRTYPE_2,               0x00},
+	{SWRS_SCP_SDCA_INTRTYPE_3,               0x00},
+	{WCD9378_FUNC_EXT_ID_0,                  0x00},
+	{WCD9378_FUNC_EXT_ID_1,                  0x00},
+	{WCD9378_FUNC_EXT_VER,                   0x00},
+	{WCD9378_FUNC_STAT,                      0x67},
+	{WCD9378_DEV_MANU_ID_0,                  0x17},
+	{WCD9378_DEV_MANU_ID_1,                  0x02},
+	{WCD9378_DEV_PART_ID_0,                  0x10},
+	{WCD9378_DEV_PART_ID_1,                  0x01},
+	{WCD9378_DEV_VER,                        0x10},
+	{WCD9378_ANA_PAGE,                       0x00},
+	{WCD9378_ANA_BIAS,                       0x00},
+	{WCD9378_ANA_RX_SUPPLIES,                0x00},
+	{WCD9378_ANA_HPH,                        0x0c},
+	{WCD9378_ANA_EAR,                        0x00},
+	{WCD9378_ANA_EAR_COMPANDER_CTL,          0x02},
+	{WCD9378_ANA_TX_CH1,                     0x20},
+	{WCD9378_ANA_TX_CH2,                     0x00},
+	{WCD9378_ANA_TX_CH3,                     0x20},
+	{WCD9378_ANA_TX_CH3_HPF,                 0x00},
+	{WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC,   0x00},
+	{WCD9378_ANA_MICB3_DSP_EN_LOGIC,         0x00},
+	{WCD9378_ANA_MBHC_MECH,                  0x39},
+	{WCD9378_ANA_MBHC_ELECT,                 0x08},
+	{WCD9378_ANA_MBHC_ZDET,                  0x00},
+	{WCD9378_ANA_MBHC_RESULT_1,              0x00},
+	{WCD9378_ANA_MBHC_RESULT_2,              0x00},
+	{WCD9378_ANA_MBHC_RESULT_3,              0x00},
+	{WCD9378_ANA_MBHC_BTN0,                  0x00},
+	{WCD9378_ANA_MBHC_BTN1,                  0x10},
+	{WCD9378_ANA_MBHC_BTN2,                  0x20},
+	{WCD9378_ANA_MBHC_BTN3,                  0x30},
+	{WCD9378_ANA_MBHC_BTN4,                  0x40},
+	{WCD9378_ANA_MBHC_BTN5,                  0x50},
+	{WCD9378_ANA_MBHC_BTN6,                  0x60},
+	{WCD9378_ANA_MBHC_BTN7,                  0x70},
+	{WCD9378_ANA_MICB1,                      0x10},
+	{WCD9378_ANA_MICB2,                      0x10},
+	{WCD9378_ANA_MICB2_RAMP,                 0x00},
+	{WCD9378_ANA_MICB3,                      0x00},
+	{WCD9378_BIAS_CTL,                       0x2a},
+	{WCD9378_BIAS_VBG_FINE_ADJ,              0x55},
+	{WCD9378_LDOL_VDDCX_ADJUST,              0x01},
+	{WCD9378_LDOL_DISABLE_LDOL,              0x00},
+	{WCD9378_MBHC_CTL_CLK,                   0x00},
+	{WCD9378_MBHC_CTL_ANA,                   0x00},
+	{WCD9378_MBHC_CTL_SPARE_1,               0x02},
+	{WCD9378_MBHC_CTL_SPARE_2,               0x00},
+	{WCD9378_MBHC_CTL_BCS,                   0x00},
+	{WCD9378_MBHC_MOISTURE_DET_FSM_STATUS,   0x00},
+	{WCD9378_MBHC_TEST_CTL,                  0x00},
+	{WCD9378_LDOH_MODE,                      0x2b},
+	{WCD9378_LDOH_BIAS,                      0x68},
+	{WCD9378_LDOH_STB_LOADS,                 0x00},
+	{WCD9378_LDOH_SLOWRAMP,                  0x50},
+	{WCD9378_MICB1_TEST_CTL_1,               0x1a},
+	{WCD9378_MICB1_TEST_CTL_2,               0x00},
+	{WCD9378_MICB1_TEST_CTL_3,               0xa4},
+	{WCD9378_MICB2_TEST_CTL_1,               0x1a},
+	{WCD9378_MICB2_TEST_CTL_2,               0x00},
+	{WCD9378_MICB2_TEST_CTL_3,               0x24},
+	{WCD9378_MICB3_TEST_CTL_1,               0x9a},
+	{WCD9378_MICB3_TEST_CTL_2,               0x80},
+	{WCD9378_MICB3_TEST_CTL_3,               0x24},
+	{WCD9378_TX_COM_ADC_VCM,                 0x39},
+	{WCD9378_TX_COM_BIAS_ATEST,              0xe0},
+	{WCD9378_TX_COM_SPARE1,                  0x00},
+	{WCD9378_TX_COM_SPARE2,                  0x00},
+	{WCD9378_TX_COM_TXFE_DIV_CTL,            0x22},
+	{WCD9378_TX_COM_TXFE_DIV_START,          0x00},
+	{WCD9378_TX_COM_SPARE3,                  0x00},
+	{WCD9378_TX_COM_SPARE4,                  0x00},
+	{WCD9378_TX_1_2_TEST_EN,                 0xcc},
+	{WCD9378_TX_1_2_ADC_IB,                  0xe9},
+	{WCD9378_TX_1_2_ATEST_REFCTL,            0x0b},
+	{WCD9378_TX_1_2_TEST_CTL,                0x38},
+	{WCD9378_TX_1_2_TEST_BLK_EN1,            0xff},
+	{WCD9378_TX_1_2_TXFE1_CLKDIV,            0x00},
+	{WCD9378_TX_1_2_SAR2_ERR,                0x00},
+	{WCD9378_TX_1_2_SAR1_ERR,                0x00},
+	{WCD9378_TX_3_TEST_EN,                   0xcc},
+	{WCD9378_TX_3_ADC_IB,                    0xe9},
+	{WCD9378_TX_3_ATEST_REFCTL,              0x0b},
+	{WCD9378_TX_3_TEST_CTL,                  0x38},
+	{WCD9378_TX_3_TEST_BLK_EN3,              0xff},
+	{WCD9378_TX_3_TXFE3_CLKDIV,              0x00},
+	{WCD9378_TX_3_SAR4_ERR,                  0x00},
+	{WCD9378_TX_3_SAR3_ERR,                  0x00},
+	{WCD9378_TX_3_TEST_BLK_EN2,              0xfb},
+	{WCD9378_TX_3_TXFE2_CLKDIV,              0x00},
+	{WCD9378_TX_3_SPARE1,                    0x00},
+	{WCD9378_TX_3_TEST_BLK_EN4,              0xfb},
+	{WCD9378_TX_3_SPARE2,                    0x00},
+	{WCD9378_TX_3_SPARE3,                    0x00},
+	{WCD9378_RX_AUX_SW_CTL,                  0x00},
+	{WCD9378_RX_PA_AUX_IN_CONN,              0x00},
+	{WCD9378_RX_TIMER_DIV,                   0x32},
+	{WCD9378_RX_OCP_CTL,                     0x1f},
+	{WCD9378_RX_OCP_COUNT,                   0x77},
+	{WCD9378_RX_BIAS_EAR_DAC,                0xa0},
+	{WCD9378_RX_BIAS_EAR_AMP,                0xaa},
+	{WCD9378_RX_BIAS_HPH_LDO,                0xa9},
+	{WCD9378_RX_BIAS_HPH_PA,                 0xaa},
+	{WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2,      0x8a},
+	{WCD9378_RX_BIAS_HPH_RDAC_LDO,           0x88},
+	{WCD9378_RX_BIAS_HPH_CNP1,               0x82},
+	{WCD9378_RX_BIAS_HPH_LOWPOWER,           0x82},
+	{WCD9378_RX_BIAS_AUX_DAC,                0xa0},
+	{WCD9378_RX_BIAS_AUX_AMP,                0xaa},
+	{WCD9378_RX_SPARE_1,                     0x50},
+	{WCD9378_RX_SPARE_2,                     0x00},
+	{WCD9378_RX_SPARE_3,                     0x08},
+	{WCD9378_RX_SPARE_4,                     0x44},
+	{WCD9378_RX_SPARE_5,                     0x40},
+	{WCD9378_RX_SPARE_6,                     0xaa},
+	{WCD9378_RX_SPARE_7,                     0x14},
+	{WCD9378_HPH_L_STATUS,                   0x04},
+	{WCD9378_HPH_R_STATUS,                   0x04},
+	{WCD9378_HPH_CNP_EN,                     0x80},
+	{WCD9378_HPH_CNP_WG_CTL,                 0x9a},
+	{WCD9378_HPH_CNP_WG_TIME,                0x14},
+	{WCD9378_HPH_OCP_CTL,                    0x28},
+	{WCD9378_HPH_AUTO_CHOP,                  0x16},
+	{WCD9378_HPH_CHOP_CTL,                   0x83},
+	{WCD9378_HPH_PA_CTL1,                    0x46},
+	{WCD9378_HPH_PA_CTL2,                    0x50},
+	{WCD9378_HPH_L_EN,                       0x80},
+	{WCD9378_HPH_L_TEST,                     0xe0},
+	{WCD9378_HPH_L_ATEST,                    0x50},
+	{WCD9378_HPH_R_EN,                       0x80},
+	{WCD9378_HPH_R_TEST,                     0xe0},
+	{WCD9378_HPH_R_ATEST,                    0x54},
+	{WCD9378_HPH_RDAC_CLK_CTL1,              0x99},
+	{WCD9378_HPH_RDAC_CLK_CTL2,              0x9b},
+	{WCD9378_HPH_RDAC_LDO_CTL,               0x33},
+	{WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL,       0x00},
+	{WCD9378_HPH_REFBUFF_UHQA_CTL,           0xa8},
+	{WCD9378_HPH_REFBUFF_LP_CTL,             0x0e},
+	{WCD9378_HPH_L_DAC_CTL,                  0x20},
+	{WCD9378_HPH_R_DAC_CTL,                  0x20},
+	{WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
+	{WCD9378_HPH_SURGE_HPHLR_SURGE_EN,       0x19},
+	{WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1,    0xa0},
+	{WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS,   0x00},
+	{WCD9378_EAR_EAR_EN_REG,                 0x22},
+	{WCD9378_EAR_EAR_PA_CON,                 0x44},
+	{WCD9378_EAR_EAR_SP_CON,                 0xdb},
+	{WCD9378_EAR_EAR_DAC_CON,                0x80},
+	{WCD9378_EAR_EAR_CNP_FSM_CON,            0xb2},
+	{WCD9378_EAR_TEST_CTL,                   0x00},
+	{WCD9378_EAR_STATUS_REG_1,               0x00},
+	{WCD9378_EAR_STATUS_REG_2,               0x00},
+	{WCD9378_ANA_NEW_PAGE,                   0x00},
+	{WCD9378_HPH_NEW_ANA_HPH2,               0x00},
+	{WCD9378_HPH_NEW_ANA_HPH3,               0x00},
+	{WCD9378_SLEEP_CTL,                      0x16},
+	{WCD9378_SLEEP_WATCHDOG_CTL,             0x00},
+	{WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL,   0x00},
+	{WCD9378_MBHC_NEW_CTL_1,                 0x0e},
+	{WCD9378_MBHC_NEW_CTL_2,                 0x05},
+	{WCD9378_MBHC_NEW_PLUG_DETECT_CTL,       0xe9},
+	{WCD9378_MBHC_NEW_ZDET_ANA_CTL,          0x0f},
+	{WCD9378_MBHC_NEW_ZDET_RAMP_CTL,         0x00},
+	{WCD9378_MBHC_NEW_FSM_STATUS,            0x00},
+	{WCD9378_MBHC_NEW_ADC_RESULT,            0x00},
+	{WCD9378_AUX_AUXPA,                      0x00},
+	{WCD9378_DIE_CRACK_DIE_CRK_DET_EN,       0x00},
+	{WCD9378_DIE_CRACK_DIE_CRK_DET_OUT,      0x00},
+	{WCD9378_TX_NEW_TX_CH12_MUX,             0x11},
+	{WCD9378_TX_NEW_TX_CH34_MUX,             0x23},
+	{WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,      0x40},
+	{WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,     0x81},
+	{WCD9378_HPH_NEW_INT_RDAC_VREF_CTL,      0x10},
+	{WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL,  0x00},
+	{WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,     0x81},
+	{WCD9378_HPH_NEW_INT_PA_MISC1,           0x22},
+	{WCD9378_HPH_NEW_INT_PA_MISC2,           0x00},
+	{WCD9378_HPH_NEW_INT_PA_RDAC_MISC,       0x01},
+	{WCD9378_HPH_NEW_INT_HPH_TIMER1,         0xfe},
+	{WCD9378_HPH_NEW_INT_HPH_TIMER2,         0x02},
+	{WCD9378_HPH_NEW_INT_HPH_TIMER3,         0x4e},
+	{WCD9378_HPH_NEW_INT_HPH_TIMER4,         0x54},
+	{WCD9378_HPH_NEW_INT_PA_RDAC_MISC2,      0x00},
+	{WCD9378_HPH_NEW_INT_PA_RDAC_MISC3,      0x00},
+	{WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
+	{WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP,   0x01},
+	{WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP,     0x11},
+	{WCD9378_CP_CLASSG_CP_CTRL_0,            0x00},
+	{WCD9378_CP_CLASSG_CP_CTRL_1,            0x00},
+	{WCD9378_CP_CLASSG_CP_CTRL_2,            0x23},
+	{WCD9378_CP_CLASSG_CP_CTRL_3,            0x03},
+	{WCD9378_CP_CLASSG_CP_CTRL_4,            0x00},
+	{WCD9378_CP_CLASSG_CP_CTRL_5,            0x0a},
+	{WCD9378_CP_CLASSG_CP_CTRL_6,            0x00},
+	{WCD9378_CP_CLASSG_CP_CTRL_7,            0x00},
+	{WCD9378_CP_VNEGDAC_CTRL_0,              0x23},
+	{WCD9378_CP_VNEGDAC_CTRL_1,              0x00},
+	{WCD9378_CP_VNEGDAC_CTRL_2,              0x00},
+	{WCD9378_CP_VNEGDAC_CTRL_3,              0x00},
+	{WCD9378_CP_CP_DTOP_CTRL_0,              0x00},
+	{WCD9378_CP_CP_DTOP_CTRL_1,              0x1b},
+	{WCD9378_CP_CP_DTOP_CTRL_2,              0x1b},
+	{WCD9378_CP_CP_DTOP_CTRL_3,              0x1b},
+	{WCD9378_CP_CP_DTOP_CTRL_4,              0x1b},
+	{WCD9378_CP_CP_DTOP_CTRL_5,              0x1b},
+	{WCD9378_CP_CP_DTOP_CTRL_6,              0x1b},
+	{WCD9378_CP_CP_DTOP_CTRL_7,              0x03},
+	{WCD9378_CP_CP_DTOP_CTRL_8,              0x33},
+	{WCD9378_CP_CP_DTOP_CTRL_9,              0x63},
+	{WCD9378_CP_CP_DTOP_CTRL_10,             0x1b},
+	{WCD9378_CP_CP_DTOP_CTRL_11,             0x03},
+	{WCD9378_CP_CP_DTOP_CTRL_12,             0x1b},
+	{WCD9378_CP_CP_DTOP_CTRL_13,             0x00},
+	{WCD9378_CP_CP_DTOP_CTRL_14,             0x00},
+	{WCD9378_CP_CP_DTOP_CTRL_15,             0xff},
+	{WCD9378_CP_CP_DTOP_CTRL_16,             0x00},
+	{WCD9378_CP_CP_DTOP_CTRL_17,             0x06},
+	{WCD9378_CP_CP_DTOP_CTRL_18,             0x00},
+	{WCD9378_CP_CP_DTOP_CTRL_19,             0x00},
+	{WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
+	{WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
+	{WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT,  0x00},
+	{WCD9378_MBHC_NEW_INT_SPARE_2,           0x00},
+	{WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON,    0xa8},
+	{WCD9378_EAR_INT_NEW_CNP_VCM_CON1,       0x42},
+	{WCD9378_EAR_INT_NEW_CNP_VCM_CON2,       0x22},
+	{WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS,   0x00},
+	{WCD9378_AUX_INT_EN_REG,                 0x00},
+	{WCD9378_AUX_INT_PA_CTRL,                0x06},
+	{WCD9378_AUX_INT_SP_CTRL,                0xd2},
+	{WCD9378_AUX_INT_DAC_CTRL,               0x80},
+	{WCD9378_AUX_INT_CLK_CTRL,               0x50},
+	{WCD9378_AUX_INT_TEST_CTRL,              0x00},
+	{WCD9378_AUX_INT_STATUS_REG,             0x00},
+	{WCD9378_AUX_INT_MISC,                   0x00},
+	{WCD9378_SLEEP_INT_WATCHDOG_CTL_1,       0x0a},
+	{WCD9378_SLEEP_INT_WATCHDOG_CTL_2,       0x0a},
+	{WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
+	{WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
+	{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xff},
+	{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7f},
+	{WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3f},
+	{WCD9378_TX_COM_NEW_INT_SPARE1,          0x1f},
+	{WCD9378_TX_COM_NEW_INT_SPARE2,          0x0f},
+	{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2,   0xd7},
+	{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1,   0xc8},
+	{WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0,   0xc6},
+	{WCD9378_TX_COM_NEW_INT_SPARE3,          0x95},
+	{WCD9378_TX_COM_NEW_INT_SPARE4,          0x6a},
+	{WCD9378_TX_COM_NEW_INT_SPARE5,          0x05},
+	{WCD9378_TX_COM_NEW_INT_SPARE6,          0xa5},
+	{WCD9378_TX_COM_NEW_INT_SPARE7,          0x13},
+	{WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
+	{WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0, 0x42},
+	{WCD9378_TX_COM_NEW_INT_TXADC_INT_L2,    0xff},
+	{WCD9378_TX_COM_NEW_INT_TXADC_INT_L1,    0x64},
+	{WCD9378_TX_COM_NEW_INT_TXADC_INT_L0,    0x64},
+	{WCD9378_TX_COM_NEW_INT_SPARE8,          0x77},
+	{WCD9378_TAMBORA_PAGE,                   0x00},
+	{WCD9378_CHIP_ID0,                       0x00},
+	{WCD9378_CHIP_ID1,                       0x00},
+	{WCD9378_CHIP_ID2,                       0x10},
+	{WCD9378_CHIP_ID3,                       0x01},
+	{WCD9378_SWR_TX_CLK_RATE,                0x00},
+	{WCD9378_CDC_RST_CTL,                    0x03},
+	{WCD9378_TOP_CLK_CFG,                    0x00},
+	{WCD9378_CDC_ANA_CLK_CTL,                0x00},
+	{WCD9378_CDC_DIG_CLK_CTL,                0x70},
+	{WCD9378_SWR_RST_EN,                     0x1f},
+	{WCD9378_CDC_PATH_MODE,                  0x00},
+	{WCD9378_CDC_RX_RST,                     0x00},
+	{WCD9378_CDC_RX0_CTL,                    0xfc},
+	{WCD9378_CDC_RX1_CTL,                    0xfc},
+	{WCD9378_CDC_RX2_CTL,                    0xfc},
+	{WCD9378_CDC_TX_ANA_MODE_0_1,            0x00},
+	{WCD9378_CDC_TX_ANA_MODE_2_3,            0x00},
+	{WCD9378_CDC_COMP_CTL_0,                 0x00},
+	{WCD9378_CDC_ANA_TX_CLK_CTL,             0x0e},
+	{WCD9378_CDC_HPH_DSM_A1_0,               0x00},
+	{WCD9378_CDC_HPH_DSM_A1_1,               0x01},
+	{WCD9378_CDC_HPH_DSM_A2_0,               0x63},
+	{WCD9378_CDC_HPH_DSM_A2_1,               0x04},
+	{WCD9378_CDC_HPH_DSM_A3_0,               0xac},
+	{WCD9378_CDC_HPH_DSM_A3_1,               0x04},
+	{WCD9378_CDC_HPH_DSM_A4_0,               0x1a},
+	{WCD9378_CDC_HPH_DSM_A4_1,               0x03},
+	{WCD9378_CDC_HPH_DSM_A5_0,               0xbc},
+	{WCD9378_CDC_HPH_DSM_A5_1,               0x02},
+	{WCD9378_CDC_HPH_DSM_A6_0,               0xc7},
+	{WCD9378_CDC_HPH_DSM_A7_0,               0xf8},
+	{WCD9378_CDC_HPH_DSM_C_0,                0x47},
+	{WCD9378_CDC_HPH_DSM_C_1,                0x43},
+	{WCD9378_CDC_HPH_DSM_C_2,                0xb1},
+	{WCD9378_CDC_HPH_DSM_C_3,                0x17},
+	{WCD9378_CDC_HPH_DSM_R1,                 0x4d},
+	{WCD9378_CDC_HPH_DSM_R2,                 0x29},
+	{WCD9378_CDC_HPH_DSM_R3,                 0x34},
+	{WCD9378_CDC_HPH_DSM_R4,                 0x59},
+	{WCD9378_CDC_HPH_DSM_R5,                 0x66},
+	{WCD9378_CDC_HPH_DSM_R6,                 0x87},
+	{WCD9378_CDC_HPH_DSM_R7,                 0x64},
+	{WCD9378_CDC_AUX_DSM_A1_0,               0x00},
+	{WCD9378_CDC_AUX_DSM_A1_1,               0x01},
+	{WCD9378_CDC_AUX_DSM_A2_0,               0x96},
+	{WCD9378_CDC_AUX_DSM_A2_1,               0x09},
+	{WCD9378_CDC_AUX_DSM_A3_0,               0xab},
+	{WCD9378_CDC_AUX_DSM_A3_1,               0x05},
+	{WCD9378_CDC_AUX_DSM_A4_0,               0x1c},
+	{WCD9378_CDC_AUX_DSM_A4_1,               0x02},
+	{WCD9378_CDC_AUX_DSM_A5_0,               0x17},
+	{WCD9378_CDC_AUX_DSM_A5_1,               0x02},
+	{WCD9378_CDC_AUX_DSM_A6_0,               0xaa},
+	{WCD9378_CDC_AUX_DSM_A7_0,               0xe3},
+	{WCD9378_CDC_AUX_DSM_C_0,                0x69},
+	{WCD9378_CDC_AUX_DSM_C_1,                0x54},
+	{WCD9378_CDC_AUX_DSM_C_2,                0x02},
+	{WCD9378_CDC_AUX_DSM_C_3,                0x15},
+	{WCD9378_CDC_AUX_DSM_R1,                 0xa4},
+	{WCD9378_CDC_AUX_DSM_R2,                 0xb5},
+	{WCD9378_CDC_AUX_DSM_R3,                 0x86},
+	{WCD9378_CDC_AUX_DSM_R4,                 0x85},
+	{WCD9378_CDC_AUX_DSM_R5,                 0xaa},
+	{WCD9378_CDC_AUX_DSM_R6,                 0xe2},
+	{WCD9378_CDC_AUX_DSM_R7,                 0x62},
+	{WCD9378_CDC_HPH_GAIN_RX_0,              0x55},
+	{WCD9378_CDC_HPH_GAIN_RX_1,              0xa9},
+	{WCD9378_CDC_HPH_GAIN_DSD_0,             0x3d},
+	{WCD9378_CDC_HPH_GAIN_DSD_1,             0x2e},
+	{WCD9378_CDC_HPH_GAIN_DSD_2,             0x01},
+	{WCD9378_CDC_AUX_GAIN_DSD_0,             0x00},
+	{WCD9378_CDC_AUX_GAIN_DSD_1,             0xfc},
+	{WCD9378_CDC_AUX_GAIN_DSD_2,             0x01},
+	{WCD9378_CDC_HPH_GAIN_CTL,               0x00},
+	{WCD9378_CDC_AUX_GAIN_CTL,               0x00},
+	{WCD9378_CDC_PATH_CTL,                   0x00},
+	{WCD9378_CDC_SWR_CLG,                    0x00},
+	{WCD9378_SWR_CLG_BYP,                    0x00},
+	{WCD9378_CDC_TX0_CTL,                    0x68},
+	{WCD9378_CDC_TX1_CTL,                    0x68},
+	{WCD9378_CDC_TX2_CTL,                    0x68},
+	{WCD9378_CDC_TX_RST,                     0x00},
+	{WCD9378_CDC_REQ_CTL,                    0x01},
+	{WCD9378_CDC_RST,                        0x00},
+	{WCD9378_CDC_AMIC_CTL,                   0x07},
+	{WCD9378_CDC_DMIC_CTL,                   0x04},
+	{WCD9378_CDC_DMIC1_CTL,                  0x01},
+	{WCD9378_CDC_DMIC2_CTL,                  0x01},
+	{WCD9378_CDC_DMIC3_CTL,                  0x01},
+	{WCD9378_EFUSE_PRG_CTL,                  0x00},
+	{WCD9378_EFUSE_CTL,                      0x2b},
+	{WCD9378_CDC_DMIC_RATE_1_2,              0x11},
+	{WCD9378_CDC_DMIC_RATE_3_4,              0x01},
+	{WCD9378_PDM_WD_EN_OVRD,                 0x00},
+	{WCD9378_PDM_WD_CTL0,                    0x0f},
+	{WCD9378_PDM_WD_CTL1,                    0x0f},
+	{WCD9378_PDM_WD_CTL2,                    0x01},
+	{WCD9378_RAMP_CTL,                       0x07},
+	{WCD9378_ACT_DET_CTL,                    0x00},
+	{WCD9378_ACT_DET_HOOKUP0,                0x00},
+	{WCD9378_ACT_DET_HOOKUP1,                0x07},
+	{WCD9378_ACT_DET_HOOKUP2,                0x00},
+	{WCD9378_ACT_DET_DLY_BUF_EN,             0x1f},
+	{WCD9378_INTR_MODE,                      0x00},
+	{WCD9378_INTR_STATUS_0,                  0x00},
+	{WCD9378_INTR_STATUS_1,                  0x00},
+	{WCD9378_INTR_STATUS_2,                  0x00},
+	{WCD9378_INTR_STATUS_3,                  0x00},
+	{WCD9378_INTR_MASK_0,                    0xff},
+	{WCD9378_INTR_MASK_1,                    0xff},
+	{WCD9378_INTR_MASK_2,                    0x3f},
+	{WCD9378_INTR_MASK_3,                    0x00},
+	{WCD9378_INTR_SET_0,                     0x00},
+	{WCD9378_INTR_SET_1,                     0x00},
+	{WCD9378_INTR_SET_2,                     0x00},
+	{WCD9378_INTR_SET_3,                     0x00},
+	{WCD9378_INTR_TEST_0,                    0x00},
+	{WCD9378_INTR_TEST_1,                    0x00},
+	{WCD9378_INTR_TEST_2,                    0x00},
+	{WCD9378_INTR_TEST_3,                    0x3e},
+	{WCD9378_TX_MODE_DBG_EN,                 0x00},
+	{WCD9378_TX_MODE_DBG_0_1,                0x00},
+	{WCD9378_TX_MODE_DBG_2_3,                0x00},
+	{WCD9378_LB_IN_SEL_CTL,                  0x00},
+	{WCD9378_LOOP_BACK_MODE,                 0x00},
+	{WCD9378_SWR_DAC_TEST,                   0x00},
+	{WCD9378_SWR_HM_TEST_RX_0,               0x40},
+	{WCD9378_SWR_HM_TEST_TX_0,               0x40},
+	{WCD9378_SWR_HM_TEST_RX_1,               0x00},
+	{WCD9378_SWR_HM_TEST_TX_1,               0x00},
+	{WCD9378_SWR_HM_TEST_0,                  0x00},
+	{WCD9378_PAD_CTL_SWR_0,                  0x8f},
+	{WCD9378_PAD_CTL_SWR_1,                  0x06},
+	{WCD9378_I2C_CTL,                        0x00},
+	{WCD9378_LEGACY_SW_MODE,                 0x00},
+	{WCD9378_EFUSE_TEST_CTL_0,               0x00},
+	{WCD9378_EFUSE_TEST_CTL_1,               0x00},
+	{WCD9378_EFUSE_T_DATA_0,                 0x00},
+	{WCD9378_PAD_CTL_PDM_RX0,                0xf1},
+	{WCD9378_PAD_CTL_PDM_RX1,                0xf1},
+	{WCD9378_PAD_CTL_PDM_TX0,                0xf1},
+	{WCD9378_PAD_CTL_PDM_TX1,                0xf1},
+	{WCD9378_PAD_INP_DIS_0,                  0x2a},
+	{WCD9378_DRIVE_STRENGTH_0,               0x00},
+	{WCD9378_DRIVE_STRENGTH_1,               0x00},
+	{WCD9378_RX_DATA_EDGE_CTL,               0x1c},
+	{WCD9378_TX_DATA_EDGE_CTL,               0x10},
+	{WCD9378_GPIO_MODE,                      0x00},
+	{WCD9378_PIN_CTL_OE,                     0x00},
+	{WCD9378_PIN_CTL_DATA_0,                 0x00},
+	{WCD9378_PIN_STATUS_0,                   0x00},
+	{WCD9378_DIG_DEBUG_CTL,                  0x00},
+	{WCD9378_DIG_DEBUG_EN,                   0x00},
+	{WCD9378_ANA_CSR_DBG_ADD,                0x00},
+	{WCD9378_ANA_CSR_DBG_CTL,                0x48},
+	{WCD9378_SSP_DBG,                        0x00},
+	{WCD9378_MODE_STATUS_0,                  0x00},
+	{WCD9378_MODE_STATUS_1,                  0x00},
+	{WCD9378_SPARE_0,                        0x00},
+	{WCD9378_SPARE_1,                        0x00},
+	{WCD9378_SPARE_2,                        0x00},
+	{WCD9378_EFUSE_REG_0,                    0x00},
+	{WCD9378_EFUSE_REG_1,                    0xff},
+	{WCD9378_EFUSE_REG_2,                    0xff},
+	{WCD9378_EFUSE_REG_3,                    0xff},
+	{WCD9378_EFUSE_REG_4,                    0xff},
+	{WCD9378_EFUSE_REG_5,                    0xff},
+	{WCD9378_EFUSE_REG_6,                    0xff},
+	{WCD9378_EFUSE_REG_7,                    0xff},
+	{WCD9378_EFUSE_REG_8,                    0xff},
+	{WCD9378_EFUSE_REG_9,                    0xff},
+	{WCD9378_EFUSE_REG_10,                   0xff},
+	{WCD9378_EFUSE_REG_11,                   0xff},
+	{WCD9378_EFUSE_REG_12,                   0xff},
+	{WCD9378_EFUSE_REG_13,                   0xff},
+	{WCD9378_EFUSE_REG_14,                   0xff},
+	{WCD9378_EFUSE_REG_15,                   0xff},
+	{WCD9378_EFUSE_REG_16,                   0xff},
+	{WCD9378_EFUSE_REG_17,                   0xff},
+	{WCD9378_EFUSE_REG_18,                   0xff},
+	{WCD9378_EFUSE_REG_19,                   0xff},
+	{WCD9378_EFUSE_REG_20,                   0x0e},
+	{WCD9378_EFUSE_REG_21,                   0x00},
+	{WCD9378_EFUSE_REG_22,                   0x00},
+	{WCD9378_EFUSE_REG_23,                   0xf6},
+	{WCD9378_EFUSE_REG_24,                   0x17},
+	{WCD9378_EFUSE_REG_25,                   0x00},
+	{WCD9378_EFUSE_REG_26,                   0x00},
+	{WCD9378_EFUSE_REG_27,                   0x00},
+	{WCD9378_EFUSE_REG_28,                   0x00},
+	{WCD9378_EFUSE_REG_29,                   0x00},
+	{WCD9378_EFUSE_REG_30,                   0x09},
+	{WCD9378_EFUSE_REG_31,                   0xf6},
+	{WCD9378_TX_REQ_FB_CTL_2,                0x11},
+	{WCD9378_TX_REQ_FB_CTL_3,                0x00},
+	{WCD9378_TX_REQ_FB_CTL_4,                0x00},
+	{WCD9378_DEM_BYPASS_DATA0,               0x55},
+	{WCD9378_DEM_BYPASS_DATA1,               0x55},
+	{WCD9378_DEM_BYPASS_DATA2,               0x55},
+	{WCD9378_DEM_BYPASS_DATA3,               0x01},
+	{WCD9378_RX0_PCM_RAMP_STEP,              0x05},
+	{WCD9378_RX0_DSD_RAMP_STEP,              0x0e},
+	{WCD9378_RX1_PCM_RAMP_STEP,              0x05},
+	{WCD9378_RX1_DSD_RAMP_STEP,              0x0e},
+	{WCD9378_RX2_RAMP_STEP,                  0x0e},
+	{WCD9378_PLATFORM_CTL,                   0x01},
+	{WCD9378_CLK_DIV_CFG,                    0x03},
+	{WCD9378_DRE_DLY_VAL,                    0x88},
+	{WCD9378_SYS_USAGE_CTRL,                 0x00},
+	{WCD9378_SURGE_CTL,                      0x00},
+	{WCD9378_SEQ_CTL,                        0x00},
+	{WCD9378_HPH_UP_T0,                      0x02},
+	{WCD9378_HPH_UP_T1,                      0x02},
+	{WCD9378_HPH_UP_T2,                      0x02},
+	{WCD9378_HPH_UP_T3,                      0x02},
+	{WCD9378_HPH_UP_T4,                      0x02},
+	{WCD9378_HPH_UP_T5,                      0x03},
+	{WCD9378_HPH_UP_T6,                      0x02},
+	{WCD9378_HPH_UP_T7,                      0x06},
+	{WCD9378_HPH_UP_T8,                      0x02},
+	{WCD9378_HPH_UP_T9,                      0x02},
+	{WCD9378_HPH_UP_T10,                     0x00},
+	{WCD9378_HPH_DN_T0,                      0x05},
+	{WCD9378_HPH_DN_T1,                      0x06},
+	{WCD9378_HPH_DN_T2,                      0x02},
+	{WCD9378_HPH_DN_T3,                      0x02},
+	{WCD9378_HPH_DN_T4,                      0x02},
+	{WCD9378_HPH_DN_T5,                      0x02},
+	{WCD9378_HPH_DN_T6,                      0x02},
+	{WCD9378_HPH_DN_T7,                      0x02},
+	{WCD9378_HPH_DN_T8,                      0x02},
+	{WCD9378_HPH_DN_T9,                      0x02},
+	{WCD9378_HPH_DN_T10,                     0x02},
+	{WCD9378_HPH_UP_STAGE_LOC_0,             0x00},
+	{WCD9378_HPH_UP_STAGE_LOC_1,             0x01},
+	{WCD9378_HPH_UP_STAGE_LOC_2,             0x02},
+	{WCD9378_HPH_UP_STAGE_LOC_3,             0x03},
+	{WCD9378_HPH_UP_STAGE_LOC_4,             0x04},
+	{WCD9378_HPH_UP_STAGE_LOC_5,             0x05},
+	{WCD9378_HPH_UP_STAGE_LOC_6,             0x06},
+	{WCD9378_HPH_UP_STAGE_LOC_7,             0x07},
+	{WCD9378_HPH_UP_STAGE_LOC_8,             0x08},
+	{WCD9378_HPH_UP_STAGE_LOC_9,             0x09},
+	{WCD9378_HPH_UP_STAGE_LOC_10,            0x0a},
+	{WCD9378_HPH_DN_STAGE_LOC_0,             0x08},
+	{WCD9378_HPH_DN_STAGE_LOC_1,             0x09},
+	{WCD9378_HPH_DN_STAGE_LOC_2,             0x06},
+	{WCD9378_HPH_DN_STAGE_LOC_3,             0x05},
+	{WCD9378_HPH_DN_STAGE_LOC_4,             0x04},
+	{WCD9378_HPH_DN_STAGE_LOC_5,             0x03},
+	{WCD9378_HPH_DN_STAGE_LOC_6,             0x07},
+	{WCD9378_HPH_DN_STAGE_LOC_7,             0x01},
+	{WCD9378_HPH_DN_STAGE_LOC_8,             0x02},
+	{WCD9378_HPH_DN_STAGE_LOC_9,             0x0a},
+	{WCD9378_HPH_DN_STAGE_LOC_10,            0x00},
+	{WCD9378_SA_UP_T0,                       0x02},
+	{WCD9378_SA_UP_T1,                       0x02},
+	{WCD9378_SA_UP_T2,                       0x02},
+	{WCD9378_SA_UP_T3,                       0x02},
+	{WCD9378_SA_UP_T4,                       0x02},
+	{WCD9378_SA_UP_T5,                       0x06},
+	{WCD9378_SA_UP_T6,                       0x02},
+	{WCD9378_SA_UP_T7,                       0x00},
+	{WCD9378_SA_DN_T0,                       0x05},
+	{WCD9378_SA_DN_T1,                       0x06},
+	{WCD9378_SA_DN_T2,                       0x02},
+	{WCD9378_SA_DN_T3,                       0x02},
+	{WCD9378_SA_DN_T4,                       0x02},
+	{WCD9378_SA_DN_T5,                       0x03},
+	{WCD9378_SA_DN_T6,                       0x02},
+	{WCD9378_SA_DN_T7,                       0x06},
+	{WCD9378_SA_UP_STAGE_LOC_0,              0x00},
+	{WCD9378_SA_UP_STAGE_LOC_1,              0x01},
+	{WCD9378_SA_UP_STAGE_LOC_2,              0x02},
+	{WCD9378_SA_UP_STAGE_LOC_3,              0x03},
+	{WCD9378_SA_UP_STAGE_LOC_4,              0x04},
+	{WCD9378_SA_UP_STAGE_LOC_5,              0x05},
+	{WCD9378_SA_UP_STAGE_LOC_6,              0x06},
+	{WCD9378_SA_UP_STAGE_LOC_7,              0x07},
+	{WCD9378_SA_DN_STAGE_LOC_0,              0x05},
+	{WCD9378_SA_DN_STAGE_LOC_1,              0x06},
+	{WCD9378_SA_DN_STAGE_LOC_2,              0x04},
+	{WCD9378_SA_DN_STAGE_LOC_3,              0x03},
+	{WCD9378_SA_DN_STAGE_LOC_4,              0x02},
+	{WCD9378_SA_DN_STAGE_LOC_5,              0x01},
+	{WCD9378_SA_DN_STAGE_LOC_6,              0x07},
+	{WCD9378_SA_DN_STAGE_LOC_7,              0x00},
+	{WCD9378_TX0_UP_T0,                      0x02},
+	{WCD9378_TX0_UP_T1,                      0x02},
+	{WCD9378_TX0_UP_T2,                      0x02},
+	{WCD9378_TX0_UP_T3,                      0x00},
+	{WCD9378_TX0_DN_T0,                      0x02},
+	{WCD9378_TX0_DN_T1,                      0x02},
+	{WCD9378_TX0_DN_T2,                      0x02},
+	{WCD9378_TX0_DN_T3,                      0x00},
+	{WCD9378_TX0_UP_STAGE_LOC_0,             0x00},
+	{WCD9378_TX0_UP_STAGE_LOC_1,             0x01},
+	{WCD9378_TX0_UP_STAGE_LOC_2,             0x02},
+	{WCD9378_TX0_UP_STAGE_LOC_3,             0x03},
+	{WCD9378_TX0_DN_STAGE_LOC_0,             0x02},
+	{WCD9378_TX0_DN_STAGE_LOC_1,             0x00},
+	{WCD9378_TX0_DN_STAGE_LOC_2,             0x01},
+	{WCD9378_TX0_DN_STAGE_LOC_3,             0x03},
+	{WCD9378_TX1_UP_T0,                      0x02},
+	{WCD9378_TX1_UP_T1,                      0x02},
+	{WCD9378_TX1_UP_T2,                      0x02},
+	{WCD9378_TX1_UP_T3,                      0x00},
+	{WCD9378_TX1_DN_T0,                      0x02},
+	{WCD9378_TX1_DN_T1,                      0x02},
+	{WCD9378_TX1_DN_T2,                      0x02},
+	{WCD9378_TX1_DN_T3,                      0x00},
+	{WCD9378_TX1_UP_STAGE_LOC_0,             0x00},
+	{WCD9378_TX1_UP_STAGE_LOC_1,             0x01},
+	{WCD9378_TX1_UP_STAGE_LOC_2,             0x02},
+	{WCD9378_TX1_UP_STAGE_LOC_3,             0x03},
+	{WCD9378_TX1_DN_STAGE_LOC_0,             0x02},
+	{WCD9378_TX1_DN_STAGE_LOC_1,             0x00},
+	{WCD9378_TX1_DN_STAGE_LOC_2,             0x01},
+	{WCD9378_TX1_DN_STAGE_LOC_3,             0x03},
+	{WCD9378_TX2_UP_T0,                      0x02},
+	{WCD9378_TX2_UP_T1,                      0x02},
+	{WCD9378_TX2_UP_T2,                      0x02},
+	{WCD9378_TX2_UP_T3,                      0x00},
+	{WCD9378_TX2_DN_T0,                      0x02},
+	{WCD9378_TX2_DN_T1,                      0x02},
+	{WCD9378_TX2_DN_T2,                      0x02},
+	{WCD9378_TX2_DN_T3,                      0x00},
+	{WCD9378_TX2_UP_STAGE_LOC_0,             0x00},
+	{WCD9378_TX2_UP_STAGE_LOC_1,             0x01},
+	{WCD9378_TX2_UP_STAGE_LOC_2,             0x02},
+	{WCD9378_TX2_UP_STAGE_LOC_3,             0x03},
+	{WCD9378_TX2_DN_STAGE_LOC_0,             0x02},
+	{WCD9378_TX2_DN_STAGE_LOC_1,             0x00},
+	{WCD9378_TX2_DN_STAGE_LOC_2,             0x01},
+	{WCD9378_TX2_DN_STAGE_LOC_3,             0x03},
+	{WCD9378_SEQ_HPH_STAT,                   0x00},
+	{WCD9378_SEQ_SA_STAT,                    0x00},
+	{WCD9378_SEQ_TX0_STAT,                   0x00},
+	{WCD9378_SEQ_TX1_STAT,                   0x00},
+	{WCD9378_SEQ_TX2_STAT,                   0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_0,         0x18},
+	{WCD9378_MICB_REMAP_TABLE_VAL_1,         0x22},
+	{WCD9378_MICB_REMAP_TABLE_VAL_2,         0x24},
+	{WCD9378_MICB_REMAP_TABLE_VAL_3,         0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_4,         0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_5,         0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_6,         0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_7,         0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_8,         0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_9,         0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_10,        0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_11,        0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_12,        0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_13,        0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_14,        0x00},
+	{WCD9378_MICB_REMAP_TABLE_VAL_15,        0x00},
+	{WCD9378_SM0_MB_SEL,                     0x00},
+	{WCD9378_SM1_MB_SEL,                     0x00},
+	{WCD9378_SM2_MB_SEL,                     0x00},
+	{WCD9378_MB_PULLUP_EN,                   0x00},
+	{WCD9378_BYP_EN_CTL0,                    0x00},
+	{WCD9378_BYP_EN_CTL1,                    0x00},
+	{WCD9378_BYP_EN_CTL2,                    0x00},
+	{WCD9378_SEQ_OVRRIDE_CTL0,               0x00},
+	{WCD9378_SEQ_OVRRIDE_CTL1,               0x00},
+	{WCD9378_SEQ_OVRRIDE_CTL2,               0x00},
+	{WCD9378_HPH_SEQ_OVRRIDE_CTL0,           0x00},
+	{WCD9378_HPH_SEQ_OVRRIDE_CTL1,           0x00},
+	{WCD9378_SA_SEQ_OVRRIDE_CTL,             0x00},
+	{WCD9378_TX0_SEQ_OVRRIDE_CTL,            0x00},
+	{WCD9378_TX1_SEQ_OVRRIDE_CTL,            0x00},
+	{WCD9378_TX2_SEQ_OVRRIDE_CTL,            0x00},
+	{WCD9378_FORCE_CTL,                      0x00},
+	{WCD9378_DEVICE_DET,                     0x03},
+	{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0, 0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0, 0x01},
+	{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0, 0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1, 0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1, 0x01},
+	{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1, 0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2, 0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2, 0x01},
+	{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2, 0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3,  0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3, 0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3, 0x01},
+	{WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3, 0x00},
+	{WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0, 0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0, 0x01},
+	{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0, 0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0,  0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0,   0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0, 0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0, 0x00},
+	{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0,      0x00},
+	{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0,  0x00},
+	{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0,       0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1, 0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1, 0x01},
+	{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1, 0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1,  0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1,   0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1, 0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1, 0x00},
+	{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1,      0x00},
+	{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1,  0x00},
+	{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1,       0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2, 0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2, 0x01},
+	{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2, 0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2,  0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2,   0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2, 0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2, 0x00},
+	{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2,      0x00},
+	{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2,  0x00},
+	{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2,       0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3,  0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3, 0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3, 0x01},
+	{WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3, 0x00},
+	{WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3,  0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3,   0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3, 0x00},
+	{WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3, 0x00},
+	{WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3,      0x00},
+	{WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3,  0x00},
+	{WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3,       0x00},
+	{WCD9378_SDCA_MESSAGE_GATE,              0x00},
+	{WCD9378_MBHC_DATA_IN_EDGE,              0x00},
+	{WCD9378_MBHC_RESET,                     0x00},
+	{WCD9378_MBHC_DEBUG,                     0x00},
+	{WCD9378_MBHC_DEBUG_UMP_0,               0x00},
+	{WCD9378_MBHC_DEBUG_UMP_1,               0x00},
+	{WCD9378_MBHC_DEBUG_UMP_2,               0x00},
+	{WCD9378_HID_FUNC_EXT_ID_0,              0x00},
+	{WCD9378_HID_FUNC_EXT_ID_1,              0x00},
+	{WCD9378_HID_FUNC_EXT_VER,               0x00},
+	{WCD9378_HID_FUNC_STAT,                  0x67},
+	{WCD9378_HID_CUR_OWNER,                  0x01},
+	{WCD9378_HID_MSG_OFFSET,                 0x44000001},
+	{WCD9378_HID_MSG_LENGTH,                 0x04},
+	{WCD9378_HID_DEV_MANU_ID_0,              0x17},
+	{WCD9378_HID_DEV_MANU_ID_1,              0x02},
+	{WCD9378_HID_DEV_PART_ID_0,              0x10},
+	{WCD9378_HID_DEV_PART_ID_1,              0x01},
+	{WCD9378_HID_DEV_VER,                    0x10},
+	{WCD9378_SMP_AMP_FUNC_EXT_ID_0,          0x00},
+	{WCD9378_SMP_AMP_FUNC_EXT_ID_1,          0x00},
+	{WCD9378_SMP_AMP_FUNC_EXT_VER,           0x00},
+	{WCD9378_XU22_BYP,                       0x01},
+	{WCD9378_PDE22_REQ_PS,                   0x03},
+	{WCD9378_FU23_MUTE,                      0x01},
+	{WCD9378_PDE23_REQ_PS,                   0x03},
+	{WCD9378_SMP_AMP_FUNC_STAT,              0x67},
+	{WCD9378_FUNC_ACT,                       0x00},
+	{WCD9378_PDE22_ACT_PS,                   0x03},
+	{WCD9378_SAPU29_PROT_MODE,               0x00},
+	{WCD9378_SAPU29_PROT_STAT,               0x00},
+	{WCD9378_PDE23_ACT_PS,                   0x03},
+	{WCD9378_SMP_AMP_DEV_MANU_ID_0,          0x17},
+	{WCD9378_SMP_AMP_DEV_MANU_ID_1,          0x02},
+	{WCD9378_SMP_AMP_DEV_PART_ID_0,          0x10},
+	{WCD9378_SMP_AMP_DEV_PART_ID_1,          0x01},
+	{WCD9378_SMP_AMP_DEV_VER,                0x10},
+	{WCD9378_CMT_GRP_MASK,                   0x00},
+	{WCD9378_SMP_JACK_FUNC_EXT_ID_0,         0x00},
+	{WCD9378_SMP_JACK_FUNC_EXT_ID_1,         0x00},
+	{WCD9378_SMP_JACK_FUNC_EXT_VER,          0x00},
+	{WCD9378_IT41_USAGE,                     0x03},
+	{WCD9378_XU42_BYP,                       0x01},
+	{WCD9378_PDE42_REQ_PS,                   0x03},
+	{WCD9378_FU42_MUTE_CH1,                  0x01},
+	{WCD9378_FU42_MUTE_CH2,                  0x01},
+	{WCD9378_FU42_CH_VOL_CH1,                0xe200},
+	{WCD9378_FU42_CH_VOL_CH2,                0xe200},
+	{WCD9378_SU43_SELECTOR,                  0x01},
+	{WCD9378_SU45_SELECTOR,                  0x01},
+	{WCD9378_PDE47_REQ_PS,                   0x03},
+	{WCD9378_GE35_SEL_MODE,                  0x00},
+	{WCD9378_GE35_DET_MODE,                  0x00},
+	{WCD9378_IT31_MICB,                      0x00},
+	{WCD9378_IT31_USAGE,                     0x03},
+	{WCD9378_PDE34_REQ_PS,                   0x03},
+	{WCD9378_SU45_TX_SELECTOR,               0x01},
+	{WCD9378_XU36_BYP,                       0x01},
+	{WCD9378_PDE36_REQ_PS,                   0x03},
+	{WCD9378_OT36_USAGE,                     0x03},
+	{WCD9378_SMP_JACK_FUNC_STAT,             0x67},
+	{WCD9378_SMP_JACK_FUNC_ACT,              0x00},
+	{WCD9378_PDE42_ACT_PS,                   0x03},
+	{WCD9378_PDE47_ACT_PS,                   0x03},
+	{WCD9378_PDE34_ACT_PS,                   0x03},
+	{WCD9378_PDE36_ACT_PS,                   0x03},
+	{WCD9378_SMP_JACK_DEV_MANU_ID_0,         0x17},
+	{WCD9378_SMP_JACK_DEV_MANU_ID_1,         0x02},
+	{WCD9378_SMP_JACK_DEV_PART_ID_0,         0x10},
+	{WCD9378_SMP_JACK_DEV_PART_ID_1,         0x01},
+	{WCD9378_SMP_JACK_DEV_VER,               0x10},
+	{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0,    0x00},
+	{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1,    0x00},
+	{WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER,     0x00},
+	{WCD9378_IT11_MICB,                      0x00},
+	{WCD9378_IT11_USAGE,                     0x03},
+	{WCD9378_PDE11_REQ_PS,                   0x03},
+	{WCD9378_OT10_USAGE,                     0x03},
+	{WCD9378_SMP_MIC_CTRL0_FUNC_STAT,        0x67},
+	{WCD9378_SMP_MIC_CTRL0_FUNC_ACT,         0x00},
+	{WCD9378_PDE11_ACT_PS,                   0x03},
+	{WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0,    0x17},
+	{WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1,    0x02},
+	{WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0,    0x10},
+	{WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1,    0x01},
+	{WCD9378_SMP_MIC_CTRL0_DEV_VER,          0x10},
+	{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0,    0x00},
+	{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1,    0x00},
+	{WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER,     0x00},
+	{WCD9378_SMP_MIC_CTRL1_IT11_MICB,        0x00},
+	{WCD9378_SMP_MIC_CTRL1_IT11_USAGE,       0x03},
+	{WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,     0x03},
+	{WCD9378_SMP_MIC_CTRL1_OT10_USAGE,       0x03},
+	{WCD9378_SMP_MIC_CTRL1_FUNC_STAT,        0x67},
+	{WCD9378_SMP_MIC_CTRL1_FUNC_ACT,         0x00},
+	{WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS,     0x03},
+	{WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0,    0x17},
+	{WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1,    0x02},
+	{WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0,    0x10},
+	{WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1,    0x01},
+	{WCD9378_SMP_MIC_CTRL1_DEV_VER,          0x10},
+	{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0,    0x00},
+	{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1,    0x00},
+	{WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER,     0x00},
+	{WCD9378_SMP_MIC_CTRL2_IT11_MICB,        0x00},
+	{WCD9378_SMP_MIC_CTRL2_IT11_USAGE,       0x03},
+	{WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,     0x03},
+	{WCD9378_SMP_MIC_CTRL2_OT10_USAGE,       0x03},
+	{WCD9378_SMP_MIC_CTRL2_FUNC_STAT,        0x67},
+	{WCD9378_SMP_MIC_CTRL2_FUNC_ACT,         0x00},
+	{WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS,     0x03},
+	{WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0,    0x17},
+	{WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1,    0x02},
+	{WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0,    0x10},
+	{WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1,    0x01},
+	{WCD9378_SMP_MIC_CTRL2_DEV_VER,          0x10},
+	{WCD9378_REPORT_ID,                      0x01},
+	{WCD9378_MESSAGE0,                       0x00},
+	{WCD9378_MESSAGE1,                       0x00},
+	{WCD9378_MESSAGE2,                       0x00},
+};
+
+static bool wcd9378_readable_register(struct device *dev, unsigned int reg)
+{
+	if (reg <= WCD9378_BASE) {
+		switch (reg) {
+		case SWRS_SCP_SDCA_INTSTAT_1:
+		case SWRS_SCP_SDCA_INTSTAT_2:
+		case SWRS_SCP_SDCA_INTSTAT_3:
+		case SWRS_SCP_SDCA_INTMASK_1:
+		case SWRS_SCP_SDCA_INTMASK_2:
+		case SWRS_SCP_SDCA_INTMASK_3:
+		case SWRS_SCP_SDCA_INTRTYPE_1:
+		case SWRS_SCP_SDCA_INTRTYPE_2:
+		case SWRS_SCP_SDCA_INTRTYPE_3:
+			break;
+		default:
+			return false;
+		}
+	}
+
+	if (wcd9378_reg_access[WCD9378_REG(reg)] & RD_REG)
+		return true;
+	else
+		return false;
+}
+
+static bool wcd9378_writeable_register(struct device *dev, unsigned int reg)
+{
+	if (reg <= WCD9378_BASE) {
+		switch (reg) {
+		case SWRS_SCP_SDCA_INTSTAT_1:
+		case SWRS_SCP_SDCA_INTSTAT_2:
+		case SWRS_SCP_SDCA_INTSTAT_3:
+		case SWRS_SCP_SDCA_INTMASK_1:
+		case SWRS_SCP_SDCA_INTMASK_2:
+		case SWRS_SCP_SDCA_INTMASK_3:
+		case SWRS_SCP_SDCA_INTRTYPE_1:
+		case SWRS_SCP_SDCA_INTRTYPE_2:
+		case SWRS_SCP_SDCA_INTRTYPE_3:
+			break;
+		default:
+			return false;
+		}
+	}
+
+	if (wcd9378_reg_access[WCD9378_REG(reg)] & WR_REG)
+		return true;
+	else
+		return false;
+}
+
+static bool wcd9378_volatile_register(struct device *dev, unsigned int reg)
+{
+
+	if (reg <= WCD9378_BASE) {
+		switch (reg) {
+		case SWRS_SCP_SDCA_INTSTAT_1:
+		case SWRS_SCP_SDCA_INTSTAT_2:
+		case SWRS_SCP_SDCA_INTSTAT_3:
+		case SWRS_SCP_SDCA_INTMASK_1:
+		case SWRS_SCP_SDCA_INTMASK_2:
+		case SWRS_SCP_SDCA_INTMASK_3:
+		case SWRS_SCP_SDCA_INTRTYPE_1:
+		case SWRS_SCP_SDCA_INTRTYPE_2:
+		case SWRS_SCP_SDCA_INTRTYPE_3:
+			return true;
+		default:
+			return false;
+		}
+	}
+
+	if ((wcd9378_reg_access[WCD9378_REG(reg)] & RD_REG) &&
+		!(wcd9378_reg_access[WCD9378_REG(reg)] & WR_REG))
+		return true;
+	else
+		return false;
+}
+
+struct regmap_config wcd9378_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 8,
+	.cache_type = REGCACHE_RBTREE,
+	.reg_defaults = wcd9378_defaults,
+	.num_reg_defaults = ARRAY_SIZE(wcd9378_defaults),
+	.max_register = WCD9378_MAX_REGISTER,
+	.volatile_reg = wcd9378_volatile_register,
+	.readable_reg = wcd9378_readable_register,
+	.writeable_reg = wcd9378_writeable_register,
+	.reg_format_endian = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian = REGMAP_ENDIAN_NATIVE,
+	.can_multi_write = true,
+	.use_single_read = true,
+};

asoc/codecs/wcd9378/wcd9378-slave.c

@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/component.h>
+#include <soc/soundwire.h>
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+
+#define SWR_SLV_MAX_REG_ADDR    0x2009
+#define SWR_SLV_START_REG_ADDR  0x40
+#define SWR_SLV_MAX_BUF_LEN     20
+#define BYTES_PER_LINE          12
+#define SWR_SLV_RD_BUF_LEN      8
+#define SWR_SLV_WR_BUF_LEN      32
+#define SWR_SLV_MAX_DEVICES     2
+#endif /* CONFIG_DEBUG_FS */
+
+#define SWR_MAX_RETRY    5
+
+struct wcd9378_slave_priv {
+	struct swr_device *swr_slave;
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *debugfs_wcd9378_dent;
+	struct dentry *debugfs_peek;
+	struct dentry *debugfs_poke;
+	struct dentry *debugfs_reg_dump;
+	unsigned int read_data;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_FS
+static int get_parameters(char *buf, u32 *param1, int num_of_par)
+{
+	char *token = NULL;
+	int base = 0, cnt = 0;
+
+	token = strsep(&buf, " ");
+	for (cnt = 0; cnt < num_of_par; cnt++) {
+		if (token) {
+			if ((token[1] == 'x') || (token[1] == 'X'))
+				base = 16;
+			else
+				base = 10;
+
+			if (kstrtou32(token, base, &param1[cnt]) != 0)
+				return -EINVAL;
+
+			token = strsep(&buf, " ");
+		} else {
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+static bool is_swr_slv_reg_readable(int reg)
+{
+	int ret = true;
+
+	if (((reg > 0x46) && (reg < 0x4A)) ||
+	    ((reg > 0x4A) && (reg < 0x50)) ||
+	    ((reg > 0x55) && (reg < 0xD0)) ||
+	    ((reg > 0xD0) && (reg < 0xE0)) ||
+	    ((reg > 0xE0) && (reg < 0xF0)) ||
+	    ((reg > 0xF0) && (reg < 0x100)) ||
+	    ((reg > 0x105) && (reg < 0x120)) ||
+	    ((reg > 0x205) && (reg < 0x220)) ||
+	    ((reg > 0x305) && (reg < 0x320)) ||
+	    ((reg > 0x405) && (reg < 0x420)) ||
+	    ((reg > 0x128) && (reg < 0x130)) ||
+	    ((reg > 0x228) && (reg < 0x230)) ||
+	    ((reg > 0x328) && (reg < 0x330)) ||
+	    ((reg > 0x428) && (reg < 0x430)) ||
+	    ((reg > 0x138) && (reg < 0x205)) ||
+	    ((reg > 0x238) && (reg < 0x305)) ||
+	    ((reg > 0x338) && (reg < 0x405)) ||
+	    ((reg > 0x438) && (reg < 0x2000)))
+		ret = false;
+
+	return ret;
+}
+
+static ssize_t wcd9378_swrslave_reg_show(struct swr_device *pdev,
+					char __user *ubuf,
+					size_t count, loff_t *ppos)
+{
+	int i, reg_val, len;
+	ssize_t total = 0;
+	char tmp_buf[SWR_SLV_MAX_BUF_LEN];
+
+	if (!ubuf || !ppos)
+		return 0;
+
+	for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
+		i <= SWR_SLV_MAX_REG_ADDR; i++) {
+		if (!is_swr_slv_reg_readable(i))
+			continue;
+		swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
+		len = scnprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
+			       (reg_val & 0xFF));
+		if (((total + len) >= count - 1) || (len < 0))
+			break;
+		if (copy_to_user((ubuf + total), tmp_buf, len)) {
+			pr_err("%s: fail to copy reg dump\n", __func__);
+			total = -EFAULT;
+			goto copy_err;
+		}
+		total += len;
+		*ppos += len;
+	}
+
+copy_err:
+	*ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
+	return total;
+}
+
+static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
+				size_t count, loff_t *ppos)
+{
+	struct swr_device *pdev;
+
+	if (!count || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	return wcd9378_swrslave_reg_show(pdev, ubuf, count, ppos);
+}
+
+static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
+				size_t count, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_RD_BUF_LEN];
+	struct swr_device *pdev = NULL;
+	struct wcd9378_slave_priv *wcd9378_slave = NULL;
+
+	if (!count || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	wcd9378_slave = swr_get_dev_data(pdev);
+	if (!wcd9378_slave)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	snprintf(lbuf, sizeof(lbuf), "0x%x\n",
+			(wcd9378_slave->read_data & 0xFF));
+
+	return simple_read_from_buffer(ubuf, count, ppos, lbuf,
+					       strnlen(lbuf, 7));
+}
+
+static ssize_t codec_debug_peek_write(struct file *file,
+	const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_WR_BUF_LEN];
+	int rc = 0;
+	u32 param[5];
+	struct swr_device *pdev = NULL;
+	struct wcd9378_slave_priv *wcd9378_slave = NULL;
+
+	if (!cnt || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	wcd9378_slave = swr_get_dev_data(pdev);
+	if (!wcd9378_slave)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	if (cnt > sizeof(lbuf) - 1)
+		return -EINVAL;
+
+	rc = copy_from_user(lbuf, ubuf, cnt);
+	if (rc)
+		return -EFAULT;
+
+	lbuf[cnt] = '\0';
+	rc = get_parameters(lbuf, param, 1);
+	if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
+		return -EINVAL;
+	swr_read(pdev, pdev->dev_num, param[0], &wcd9378_slave->read_data, 1);
+	if (rc == 0)
+		rc = cnt;
+	else
+		pr_err("%s: rc = %d\n", __func__, rc);
+
+	return rc;
+}
+
+static ssize_t codec_debug_write(struct file *file,
+	const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_WR_BUF_LEN];
+	int rc = 0;
+	u32 param[5];
+	struct swr_device *pdev;
+
+	if (!file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	if (cnt > sizeof(lbuf) - 1)
+		return -EINVAL;
+
+	rc = copy_from_user(lbuf, ubuf, cnt);
+	if (rc)
+		return -EFAULT;
+
+	lbuf[cnt] = '\0';
+	rc = get_parameters(lbuf, param, 2);
+	if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
+		(param[1] <= 0xFF) && (rc == 0)))
+		return -EINVAL;
+	swr_write(pdev, pdev->dev_num, param[0], &param[1]);
+	if (rc == 0)
+		rc = cnt;
+	else
+		pr_err("%s: rc = %d\n", __func__, rc);
+
+	return rc;
+}
+
+static const struct file_operations codec_debug_write_ops = {
+	.open = simple_open,
+	.write = codec_debug_write,
+};
+
+static const struct file_operations codec_debug_read_ops = {
+	.open = simple_open,
+	.read = codec_debug_read,
+	.write = codec_debug_peek_write,
+};
+
+static const struct file_operations codec_debug_dump_ops = {
+	.open = simple_open,
+	.read = codec_debug_dump,
+};
+#endif
+
+static int wcd9378_slave_bind(struct device *dev,
+				struct device *master, void *data)
+{
+	int ret = 0;
+	uint8_t devnum = 0;
+	struct swr_device *pdev = to_swr_device(dev);
+	int retry = SWR_MAX_RETRY;
+
+	if (!pdev) {
+		pr_err("%s: invalid swr device handle\n", __func__);
+		return -EINVAL;
+	}
+
+	do {
+		/* Add delay for soundwire enumeration */
+		usleep_range(100, 110);
+		ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
+	} while (ret && --retry);
+
+	if (ret) {
+		dev_dbg(&pdev->dev,
+			"%s get devnum %d for dev addr %llx failed\n",
+			__func__, devnum, pdev->addr);
+		ret = -EPROBE_DEFER;
+		return ret;
+	}
+	pdev->dev_num = devnum;
+
+	return ret;
+}
+
+static void wcd9378_slave_unbind(struct device *dev,
+				struct device *master, void *data)
+{
+	struct wcd9378_slave_priv *wcd9378_slave = NULL;
+	struct swr_device *pdev = to_swr_device(dev);
+
+	wcd9378_slave = swr_get_dev_data(pdev);
+	if (!wcd9378_slave) {
+		dev_err(&pdev->dev, "%s: wcd9378_slave is NULL\n", __func__);
+		return;
+	}
+}
+
+static const struct swr_device_id wcd9378_swr_id[] = {
+	{"wcd9378-slave", 0},
+	{}
+};
+
+static const struct of_device_id wcd9378_swr_dt_match[] = {
+	{
+		.compatible = "qcom,wcd9378-slave",
+	},
+	{}
+};
+
+static const struct component_ops wcd9378_slave_comp_ops = {
+	.bind   = wcd9378_slave_bind,
+	.unbind = wcd9378_slave_unbind,
+};
+
+static int wcd9378_swr_probe(struct swr_device *pdev)
+{
+	struct wcd9378_slave_priv *wcd9378_slave = NULL;
+
+	wcd9378_slave = devm_kzalloc(&pdev->dev,
+				sizeof(struct wcd9378_slave_priv), GFP_KERNEL);
+	if (!wcd9378_slave)
+		return -ENOMEM;
+
+	swr_set_dev_data(pdev, wcd9378_slave);
+
+	wcd9378_slave->swr_slave = pdev;
+
+#ifdef CONFIG_DEBUG_FS
+	if (!wcd9378_slave->debugfs_wcd9378_dent) {
+		wcd9378_slave->debugfs_wcd9378_dent = debugfs_create_dir(
+						dev_name(&pdev->dev), 0);
+		if (!IS_ERR(wcd9378_slave->debugfs_wcd9378_dent)) {
+			wcd9378_slave->debugfs_peek =
+					debugfs_create_file("swrslave_peek",
+					S_IFREG | 0444,
+					wcd9378_slave->debugfs_wcd9378_dent,
+					(void *) pdev,
+					&codec_debug_read_ops);
+
+			wcd9378_slave->debugfs_poke =
+					debugfs_create_file("swrslave_poke",
+					S_IFREG | 0444,
+					wcd9378_slave->debugfs_wcd9378_dent,
+					(void *) pdev,
+					&codec_debug_write_ops);
+
+			wcd9378_slave->debugfs_reg_dump =
+					debugfs_create_file(
+					"swrslave_reg_dump",
+					S_IFREG | 0444,
+					wcd9378_slave->debugfs_wcd9378_dent,
+					(void *) pdev,
+					&codec_debug_dump_ops);
+		}
+	}
+#endif
+
+	return component_add(&pdev->dev, &wcd9378_slave_comp_ops);
+}
+
+static int wcd9378_swr_remove(struct swr_device *pdev)
+{
+#ifdef CONFIG_DEBUG_FS
+	struct wcd9378_slave_priv *wcd9378_slave = swr_get_dev_data(pdev);
+
+	if (wcd9378_slave) {
+		debugfs_remove_recursive(wcd9378_slave->debugfs_wcd9378_dent);
+		wcd9378_slave->debugfs_wcd9378_dent = NULL;
+	}
+#endif
+	component_del(&pdev->dev, &wcd9378_slave_comp_ops);
+	swr_set_dev_data(pdev, NULL);
+	swr_remove_device(pdev);
+
+	return 0;
+}
+
+static struct swr_driver wcd9378_slave_driver = {
+	.driver = {
+		.name = "wcd9378-slave",
+		.owner = THIS_MODULE,
+		.of_match_table = wcd9378_swr_dt_match,
+	},
+	.probe = wcd9378_swr_probe,
+	.remove = wcd9378_swr_remove,
+	.id_table = wcd9378_swr_id,
+};
+
+static int __init wcd9378_slave_init(void)
+{
+	return swr_driver_register(&wcd9378_slave_driver);
+}
+
+static void __exit wcd9378_slave_exit(void)
+{
+	swr_driver_unregister(&wcd9378_slave_driver);
+}
+
+module_init(wcd9378_slave_init);
+module_exit(wcd9378_slave_exit);
+
+MODULE_DESCRIPTION("WCD9378 Swr Slave driver");
+MODULE_LICENSE("GPL");

asoc/codecs/wcd9378/wcd9378-tables.c

@@ -0,0 +1,845 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd9378-registers.h"
+
+const u8 wcd9378_reg_access[] = {
+	[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_1)]                = RD_WR_REG,
+	[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_2)]                = RD_WR_REG,
+	[WCD9378_REG(SWRS_SCP_SDCA_INTSTAT_3)]                = RD_WR_REG,
+	[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_1)]                = RD_WR_REG,
+	[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_2)]                = RD_WR_REG,
+	[WCD9378_REG(SWRS_SCP_SDCA_INTMASK_3)]                = RD_WR_REG,
+	[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_1)]               = RD_WR_REG,
+	[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_2)]               = RD_WR_REG,
+	[WCD9378_REG(SWRS_SCP_SDCA_INTRTYPE_3)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FUNC_EXT_ID_0)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_FUNC_EXT_ID_1)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_FUNC_EXT_VER)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_FUNC_STAT)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DEV_MANU_ID_0)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_DEV_MANU_ID_1)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_DEV_PART_ID_0)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_DEV_PART_ID_1)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_DEV_VER)]                        = RD_REG,
+	[WCD9378_REG(WCD9378_ANA_PAGE)]                         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_BIAS)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_RX_SUPPLIES)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_HPH)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_EAR)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_EAR_COMPANDER_CTL)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_TX_CH1)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_TX_CH2)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_TX_CH3)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_TX_CH3_HPF)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MICB3_DSP_EN_LOGIC)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_MECH)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_ELECT)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_ZDET)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_1)]              = RD_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_2)]              = RD_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_RESULT_3)]              = RD_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_BTN0)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_BTN1)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_BTN2)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_BTN3)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_BTN4)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_BTN5)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_BTN6)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MBHC_BTN7)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MICB1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MICB2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MICB2_RAMP)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_MICB3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_BIAS_CTL)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_BIAS_VBG_FINE_ADJ)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LDOL_VDDCX_ADJUST)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LDOL_DISABLE_LDOL)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_CTL_CLK)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_CTL_ANA)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_CTL_SPARE_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_CTL_SPARE_2)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_CTL_BCS)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_MOISTURE_DET_FSM_STATUS)]   = RD_REG,
+	[WCD9378_REG(WCD9378_MBHC_TEST_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LDOH_MODE)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LDOH_BIAS)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LDOH_STB_LOADS)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LDOH_SLOWRAMP)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB1_TEST_CTL_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB1_TEST_CTL_2)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB1_TEST_CTL_3)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB2_TEST_CTL_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB2_TEST_CTL_2)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB2_TEST_CTL_3)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB3_TEST_CTL_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB3_TEST_CTL_2)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB3_TEST_CTL_3)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_ADC_VCM)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_BIAS_ATEST)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_SPARE1)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_SPARE2)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_TXFE_DIV_CTL)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_TXFE_DIV_START)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_SPARE3)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_SPARE4)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_1_2_TEST_EN)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_1_2_ADC_IB)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_1_2_ATEST_REFCTL)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_1_2_TEST_CTL)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_1_2_TEST_BLK_EN1)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_1_2_TXFE1_CLKDIV)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_1_2_SAR2_ERR)]                = RD_REG,
+	[WCD9378_REG(WCD9378_TX_1_2_SAR1_ERR)]                = RD_REG,
+	[WCD9378_REG(WCD9378_TX_3_TEST_EN)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_ADC_IB)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_ATEST_REFCTL)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_TEST_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN3)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_TXFE3_CLKDIV)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_SAR4_ERR)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_TX_3_SAR3_ERR)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN2)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_TXFE2_CLKDIV)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_SPARE1)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_TEST_BLK_EN4)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_SPARE2)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_3_SPARE3)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_AUX_SW_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_PA_AUX_IN_CONN)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_TIMER_DIV)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_OCP_CTL)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_OCP_COUNT)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_EAR_DAC)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_EAR_AMP)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_HPH_LDO)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_HPH_PA)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_HPH_RDAC_LDO)]           = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_HPH_CNP1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_HPH_LOWPOWER)]           = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_AUX_DAC)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_BIAS_AUX_AMP)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_SPARE_1)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_SPARE_2)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_SPARE_3)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_SPARE_4)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_SPARE_5)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_SPARE_6)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_SPARE_7)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_L_STATUS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_HPH_R_STATUS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_HPH_CNP_EN)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_CNP_WG_CTL)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_CNP_WG_TIME)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_OCP_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_AUTO_CHOP)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_CHOP_CTL)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_PA_CTL1)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_PA_CTL2)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_L_EN)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_L_TEST)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_L_ATEST)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_R_EN)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_R_TEST)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_R_ATEST)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_RDAC_CLK_CTL1)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_RDAC_CLK_CTL2)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_RDAC_LDO_CTL)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_REFBUFF_UHQA_CTL)]           = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_REFBUFF_LP_CTL)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_L_DAC_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_R_DAC_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_EN)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1)]    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS)]   = RD_REG,
+	[WCD9378_REG(WCD9378_EAR_EAR_EN_REG)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_EAR_PA_CON)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_EAR_SP_CON)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_EAR_DAC_CON)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_EAR_CNP_FSM_CON)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_TEST_CTL)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_STATUS_REG_1)]               = RD_REG,
+	[WCD9378_REG(WCD9378_EAR_STATUS_REG_2)]               = RD_REG,
+	[WCD9378_REG(WCD9378_ANA_NEW_PAGE)]                         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_ANA_HPH2)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_ANA_HPH3)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SLEEP_CTL)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SLEEP_WATCHDOG_CTL)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_CTL_1)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_CTL_2)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_PLUG_DETECT_CTL)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_ZDET_ANA_CTL)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_ZDET_RAMP_CTL)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_FSM_STATUS)]            = RD_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_ADC_RESULT)]            = RD_REG,
+	[WCD9378_REG(WCD9378_AUX_AUXPA)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DIE_CRACK_DIE_CRK_DET_EN)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DIE_CRACK_DIE_CRK_DET_OUT)]      = RD_REG,
+	[WCD9378_REG(WCD9378_TX_NEW_TX_CH12_MUX)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_NEW_TX_CH34_MUX)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L)]     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_VREF_CTL)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R)]     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_MISC1)]           = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_MISC2)]           = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER1)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER2)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER3)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_HPH_TIMER4)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC2)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_NEW_INT_PA_RDAC_MISC3)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP)]     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_0)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_1)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_2)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_3)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_4)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_5)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_6)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CLASSG_CP_CTRL_7)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_0)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_1)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_2)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_VNEGDAC_CTRL_3)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_0)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_1)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_2)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_3)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_4)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_5)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_6)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_7)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_8)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_9)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_10)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_11)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_12)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_13)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_14)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_15)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_16)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_17)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_18)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CP_CP_DTOP_CTRL_19)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_NEW_INT_SPARE_2)]           = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON)]    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_INT_NEW_CNP_VCM_CON1)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_INT_NEW_CNP_VCM_CON2)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_AUX_INT_EN_REG)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_AUX_INT_PA_CTRL)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_AUX_INT_SP_CTRL)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_AUX_INT_DAC_CTRL)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_AUX_INT_CLK_CTRL)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_AUX_INT_TEST_CTRL)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_AUX_INT_STATUS_REG)]             = RD_REG,
+	[WCD9378_REG(WCD9378_AUX_INT_MISC)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SLEEP_INT_WATCHDOG_CTL_1)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SLEEP_INT_WATCHDOG_CTL_2)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE1)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE2)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE3)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE4)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE5)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE6)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE7)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L2)]    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L1)]    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_TXADC_INT_L0)]    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_COM_NEW_INT_SPARE8)]          = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TAMBORA_PAGE)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CHIP_ID0)]                       = RD_REG,
+	[WCD9378_REG(WCD9378_CHIP_ID1)]                       = RD_REG,
+	[WCD9378_REG(WCD9378_CHIP_ID2)]                       = RD_REG,
+	[WCD9378_REG(WCD9378_CHIP_ID3)]                       = RD_REG,
+	[WCD9378_REG(WCD9378_SWR_TX_CLK_RATE)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_RST_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TOP_CLK_CFG)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_ANA_CLK_CTL)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_DIG_CLK_CTL)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SWR_RST_EN)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_PATH_MODE)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_RX_RST)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_RX0_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_RX1_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_RX2_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_TX_ANA_MODE_0_1)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_TX_ANA_MODE_2_3)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_COMP_CTL_0)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_ANA_TX_CLK_CTL)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A1_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A1_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A2_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A2_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A3_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A3_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A4_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A4_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A5_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A5_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A6_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_A7_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_0)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_1)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_2)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_C_3)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_R1)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_R2)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_R3)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_R4)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_R5)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_R6)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_DSM_R7)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A1_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A1_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A2_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A2_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A3_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A3_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A4_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A4_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A5_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A5_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A6_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_A7_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_0)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_1)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_2)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_C_3)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_R1)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_R2)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_R3)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_R4)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_R5)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_R6)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_DSM_R7)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_GAIN_RX_0)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_GAIN_RX_1)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_GAIN_DSD_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_GAIN_DSD_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_HPH_GAIN_CTL)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AUX_GAIN_CTL)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_PATH_CTL)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_SWR_CLG)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SWR_CLG_BYP)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_TX0_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_TX1_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_TX2_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_TX_RST)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_REQ_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_RST)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_AMIC_CTL)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_DMIC_CTL)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_DMIC1_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_DMIC2_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_DMIC3_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EFUSE_PRG_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EFUSE_CTL)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_DMIC_RATE_1_2)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CDC_DMIC_RATE_3_4)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDM_WD_EN_OVRD)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDM_WD_CTL0)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDM_WD_CTL1)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDM_WD_CTL2)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RAMP_CTL)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ACT_DET_CTL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ACT_DET_HOOKUP0)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ACT_DET_HOOKUP1)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ACT_DET_HOOKUP2)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ACT_DET_DLY_BUF_EN)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_MODE)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_STATUS_0)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_STATUS_1)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_STATUS_2)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_STATUS_3)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_MASK_0)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_MASK_1)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_MASK_2)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_MASK_3)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_SET_0)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_SET_1)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_SET_2)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_SET_3)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_TEST_0)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_TEST_1)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_TEST_2)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_INTR_TEST_3)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_MODE_DBG_EN)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_MODE_DBG_0_1)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_MODE_DBG_2_3)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LB_IN_SEL_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LOOP_BACK_MODE)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SWR_DAC_TEST)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SWR_HM_TEST_RX_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SWR_HM_TEST_TX_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SWR_HM_TEST_RX_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SWR_HM_TEST_TX_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SWR_HM_TEST_0)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_PAD_CTL_SWR_0)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PAD_CTL_SWR_1)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_I2C_CTL)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_LEGACY_SW_MODE)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EFUSE_TEST_CTL_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EFUSE_TEST_CTL_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EFUSE_T_DATA_0)]                 = RD_REG,
+	[WCD9378_REG(WCD9378_PAD_CTL_PDM_RX0)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PAD_CTL_PDM_RX1)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PAD_CTL_PDM_TX0)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PAD_CTL_PDM_TX1)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PAD_INP_DIS_0)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DRIVE_STRENGTH_0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DRIVE_STRENGTH_1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX_DATA_EDGE_CTL)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_DATA_EDGE_CTL)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_GPIO_MODE)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PIN_CTL_OE)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PIN_CTL_DATA_0)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PIN_STATUS_0)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_DIG_DEBUG_CTL)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DIG_DEBUG_EN)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_CSR_DBG_ADD)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_ANA_CSR_DBG_CTL)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SSP_DBG)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MODE_STATUS_0)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_MODE_STATUS_1)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_SPARE_0)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SPARE_1)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SPARE_2)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_0)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_1)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_2)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_3)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_4)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_5)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_6)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_7)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_8)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_9)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_10)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_11)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_12)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_13)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_14)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_15)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_16)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_17)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_18)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_19)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_20)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_21)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_22)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_23)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_24)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_25)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_26)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_27)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_28)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_29)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_30)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_EFUSE_REG_31)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_2)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_3)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX_REQ_FB_CTL_4)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DEM_BYPASS_DATA0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DEM_BYPASS_DATA1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DEM_BYPASS_DATA2)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DEM_BYPASS_DATA3)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX0_PCM_RAMP_STEP)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX0_DSD_RAMP_STEP)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX1_PCM_RAMP_STEP)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX1_DSD_RAMP_STEP)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_RX2_RAMP_STEP)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PLATFORM_CTL)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_CLK_DIV_CFG)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DRE_DLY_VAL)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SYS_USAGE_CTRL)]                 = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SURGE_CTL)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SEQ_CTL)]                        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T0)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T4)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T5)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T6)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T7)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T8)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T9)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_T10)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T0)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T4)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T5)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T6)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T7)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T8)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T9)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_T10)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_3)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_4)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_5)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_6)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_7)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_8)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_9)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_UP_STAGE_LOC_10)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_3)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_4)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_5)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_6)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_7)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_8)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_9)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_DN_STAGE_LOC_10)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_T0)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_T1)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_T2)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_T3)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_T4)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_T5)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_T6)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_T7)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_T0)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_T1)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_T2)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_T3)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_T4)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_T5)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_T6)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_T7)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_0)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_1)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_2)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_3)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_4)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_5)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_6)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_UP_STAGE_LOC_7)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_0)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_1)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_2)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_3)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_4)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_5)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_6)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_DN_STAGE_LOC_7)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_UP_T0)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_UP_T1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_UP_T2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_UP_T3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_DN_T0)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_DN_T1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_DN_T2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_DN_T3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_UP_STAGE_LOC_3)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_DN_STAGE_LOC_3)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_UP_T0)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_UP_T1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_UP_T2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_UP_T3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_DN_T0)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_DN_T1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_DN_T2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_DN_T3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_UP_STAGE_LOC_3)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_DN_STAGE_LOC_3)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_UP_T0)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_UP_T1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_UP_T2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_UP_T3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_DN_T0)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_DN_T1)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_DN_T2)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_DN_T3)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_UP_STAGE_LOC_3)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_0)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_1)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_2)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_DN_STAGE_LOC_3)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SEQ_HPH_STAT)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_SEQ_SA_STAT)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_SEQ_TX0_STAT)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_SEQ_TX1_STAT)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_SEQ_TX2_STAT)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_0)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_1)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_2)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_3)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_4)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_5)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_6)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_7)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_8)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_9)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_10)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_11)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_12)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_13)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_14)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MICB_REMAP_TABLE_VAL_15)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SM0_MB_SEL)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SM1_MB_SEL)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SM2_MB_SEL)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MB_PULLUP_EN)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_BYP_EN_CTL0)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_BYP_EN_CTL1)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_BYP_EN_CTL2)]                    = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL0)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL1)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SEQ_OVRRIDE_CTL2)]               = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_SEQ_OVRRIDE_CTL0)]           = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HPH_SEQ_OVRRIDE_CTL1)]           = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SA_SEQ_OVRRIDE_CTL)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX0_SEQ_OVRRIDE_CTL)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX1_SEQ_OVRRIDE_CTL)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TX2_SEQ_OVRRIDE_CTL)]            = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FORCE_CTL)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_DEVICE_DET)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3)]   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3)] = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3)]      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3)]  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SDCA_MESSAGE_GATE)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_DATA_IN_EDGE)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_RESET)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_DEBUG)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_0)]               = RD_REG,
+	[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_1)]               = RD_REG,
+	[WCD9378_REG(WCD9378_MBHC_DEBUG_UMP_2)]               = RD_REG,
+	[WCD9378_REG(WCD9378_HID_FUNC_EXT_ID_0)]              = RD_REG,
+	[WCD9378_REG(WCD9378_HID_FUNC_EXT_ID_1)]              = RD_REG,
+	[WCD9378_REG(WCD9378_HID_FUNC_EXT_VER)]               = RD_REG,
+	[WCD9378_REG(WCD9378_HID_FUNC_STAT)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HID_CUR_OWNER)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_HID_MSG_OFFSET)]                 = RD_REG,
+	[WCD9378_REG(WCD9378_HID_MSG_LENGTH)]                 = RD_REG,
+	[WCD9378_REG(WCD9378_HID_DEV_MANU_ID_0)]              = RD_REG,
+	[WCD9378_REG(WCD9378_HID_DEV_MANU_ID_1)]              = RD_REG,
+	[WCD9378_REG(WCD9378_HID_DEV_PART_ID_0)]              = RD_REG,
+	[WCD9378_REG(WCD9378_HID_DEV_PART_ID_1)]              = RD_REG,
+	[WCD9378_REG(WCD9378_HID_DEV_VER)]                    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_ID_0)]          = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_ID_1)]          = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_FUNC_EXT_VER)]           = RD_REG,
+	[WCD9378_REG(WCD9378_XU22_BYP)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE22_REQ_PS)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU23_MUTE)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE23_REQ_PS)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_FUNC_STAT)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FUNC_ACT)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE22_ACT_PS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_SAPU29_PROT_MODE)]               = RD_REG,
+	[WCD9378_REG(WCD9378_SAPU29_PROT_STAT)]               = RD_REG,
+	[WCD9378_REG(WCD9378_PDE23_ACT_PS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_DEV_MANU_ID_0)]          = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_DEV_MANU_ID_1)]          = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_DEV_PART_ID_0)]          = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_DEV_PART_ID_1)]          = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_AMP_DEV_VER)]                = RD_REG,
+	[WCD9378_REG(WCD9378_CMT_GRP_MASK)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_ID_0)]         = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_ID_1)]         = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_FUNC_EXT_VER)]          = RD_REG,
+	[WCD9378_REG(WCD9378_IT41_USAGE)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_XU42_BYP)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE42_REQ_PS)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_MUTE_CH1)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_MUTE_CH2)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_CH_VOL_CH1)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_FU42_CH_VOL_CH2)]                = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SU43_SELECTOR)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_SU45_SELECTOR)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_PDE47_REQ_PS)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_GE35_SEL_MODE)]                  = RD_WR_REG,
+	[WCD9378_REG(WCD9378_GE35_DET_MODE)]                  = RD_REG,
+	[WCD9378_REG(WCD9378_IT31_MICB)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_IT31_USAGE)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE34_REQ_PS)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SU45_TX_SELECTOR)]               = RD_REG,
+	[WCD9378_REG(WCD9378_XU36_BYP)]                       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE36_REQ_PS)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_OT36_USAGE)]                     = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_FUNC_STAT)]             = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_FUNC_ACT)]              = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE42_ACT_PS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_PDE47_ACT_PS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_PDE34_ACT_PS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_PDE36_ACT_PS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_DEV_MANU_ID_0)]         = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_DEV_MANU_ID_1)]         = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_DEV_PART_ID_0)]         = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_DEV_PART_ID_1)]         = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_JACK_DEV_VER)]               = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER)]     = RD_REG,
+	[WCD9378_REG(WCD9378_IT11_MICB)]                      = RD_WR_REG,
+	[WCD9378_REG(WCD9378_IT11_USAGE)]                     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE11_REQ_PS)]                   = RD_WR_REG,
+	[WCD9378_REG(WCD9378_OT10_USAGE)]                     = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_STAT)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_FUNC_ACT)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_PDE11_ACT_PS)]                   = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL0_DEV_VER)]          = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER)]     = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_IT11_MICB)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_IT11_USAGE)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS)]     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_OT10_USAGE)]       = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_STAT)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_FUNC_ACT)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS)]     = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL1_DEV_VER)]          = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER)]     = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_IT11_MICB)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_IT11_USAGE)]       = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS)]     = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_OT10_USAGE)]       = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_STAT)]        = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_FUNC_ACT)]         = RD_WR_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS)]     = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1)]    = RD_REG,
+	[WCD9378_REG(WCD9378_SMP_MIC_CTRL2_DEV_VER)]          = RD_REG,
+	[WCD9378_REG(WCD9378_REPORT_ID)]                      = RD_REG,
+	[WCD9378_REG(WCD9378_MESSAGE0)]                       = RD_REG,
+	[WCD9378_REG(WCD9378_MESSAGE1)]                       = RD_REG,
+	[WCD9378_REG(WCD9378_MESSAGE2)]                       = RD_REG,
+};
+

asoc/codecs/wcd9378/wcd9378.c

@@ -0,0 +1,4566 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include <soc/soundwire.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <asoc/msm-cdc-pinctrl.h>
+#include <asoc/msm-cdc-supply.h>
+#include <bindings/audio-codec-port-types.h>
+#include <linux/qti-regmap-debugfs.h>
+
+#include "wcd9378-reg-masks.h"
+#include "wcd9378.h"
+#include "internal.h"
+#include "asoc/bolero-slave-internal.h"
+
+#define NUM_SWRS_DT_PARAMS 5
+
+#define WCD9378_MOBILE_MODE 0x01
+
+#define WCD9378_VERSION_1_0 1
+#define WCD9378_VERSION_ENTRY_SIZE 32
+#define EAR_RX_PATH_RX0 1
+#define AUX_RX_PATH_RX1 1
+
+#define SWR_BASECLK_19P2MHZ      (0x01)
+#define SWR_BASECLK_24P576MHZ    (0x03)
+#define SWR_BASECLK_22P5792MHZ   (0x04)
+
+#define SWR_CLKSCALE_DIV2        (0x02)
+
+#define ADC_MODE_VAL_HIFI     0x01
+#define ADC_MODE_VAL_NORMAL   0x03
+#define ADC_MODE_VAL_LP       0x05
+
+#define PWR_LEVEL_LOHIFI_VAL  0x00
+#define PWR_LEVEL_LP_VAL      0x01
+#define PWR_LEVEL_HIFI_VAL    0x02
+#define PWR_LEVEL_ULP_VAL     0x03
+
+#define WCD9378_MBQ_ENABLE_MASK   0x2000
+
+#define MICB_USAGE_VAL_DISABLE    0x00
+#define MICB_USAGE_VAL_PULL_DOWN    0x01
+#define MICB_USAGE_VAL_1P2V    0x02
+#define MICB_USAGE_VAL_1P8VORPULLUP    0x03
+#define MICB_USAGE_VAL_2P5V    0x04
+#define MICB_USAGE_VAL_2P75V    0x05
+
+#define MICB_USAGE_VAL_2P2V    0xF0
+#define MICB_USAGE_VAL_2P7V    0xF1
+#define MICB_USAGE_VAL_2P8V    0xF2
+
+#define MICB_USAGE_VAL_MICB1_TABLE_VAL    0xF3
+#define MICB_USAGE_VAL_MICB2_TABLE_VAL    0xF4
+#define MICB_USAGE_VAL_MICB3_TABLE_VAL    0xF5
+
+#define MICB_NUM_MAX     3
+
+#define NUM_ATTEMPTS 20
+
+#define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
+			SNDRV_PCM_RATE_384000)
+/* Fractional Rates */
+#define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
+				SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
+
+#define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+		SNDRV_PCM_FMTBIT_S24_LE |\
+		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+#define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
+{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+		 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+	.tlv.p = (tlv_array), \
+	.info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
+	.put = wcd9378_ear_pa_put_gain, \
+	.private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
+
+#define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
+{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+	.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+		 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+	.tlv.p = (tlv_array), \
+	.info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
+	.put = wcd9378_aux_pa_put_gain, \
+	.private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
+
+
+enum {
+	CODEC_TX = 0,
+	CODEC_RX,
+};
+
+enum {
+	RX2_HP_MODE,
+	RX2_NORMAL_MODE,
+};
+
+enum {
+	WCD_ADC1 = 0,
+	WCD_ADC2,
+	WCD_ADC3,
+	WCD_ADC4,
+	ALLOW_BUCK_DISABLE,
+	HPH_COMP_DELAY,
+	HPH_PA_DELAY,
+	AMIC2_BCS_ENABLE,
+	WCD_SUPPLIES_LPM_MODE,
+	WCD_ADC1_MODE,
+	WCD_ADC2_MODE,
+	WCD_ADC3_MODE,
+	WCD_ADC4_MODE,
+	WCD_AUX_EN,
+	WCD_EAR_EN,
+};
+
+
+enum {
+	NOSJ_SA_STEREO_3SM = 0,
+	SJ_SA_AUX_2SM,
+	NOSJ_SA_STEREO_3SM_1HDR,
+	SJ_SA_AUX_2SM_1HDR,
+	NOSJ_SA_EAR_3SM,
+	SJ_SA_EAR_2SM,
+	NOSJ_SA_EAR_3SM_1HDR,
+	SJ_SA_EAR_2SM_1HDR,
+	SJ_1HDR_SA_AUX_1SM,
+	SJ_1HDR_SA_EAR_1SM,
+	SJ_SA_STEREO_2SM,
+	SJ_NOMIC_SA_EAR_3SM,
+	SJ_NOMIC_SA_AUX_3SM,
+	WCD_SYS_USAGE_MAX,
+};
+
+
+enum {
+	NO_MICB_USED,
+	MICB1,
+	MICB2,
+	MICB3,
+	MICB_NUM,
+};
+
+enum {
+	ADC_MODE_INVALID = 0,
+	ADC_MODE_HIFI,
+	ADC_MODE_NORMAL,
+	ADC_MODE_LP,
+	ADC_MODE_ULP1,
+	ADC_MODE_ULP2,
+};
+
+static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
+static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(aux_pa_gain, 600, -600);
+static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
+
+static int wcd9378_reset(struct device *dev);
+static int wcd9378_reset_low(struct device *dev);
+static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable);
+
+static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
+	REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
+	REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
+	REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
+	REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
+	REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
+	REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
+	REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
+	REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
+	REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
+	REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
+	REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
+	REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
+	REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
+	REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
+	REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
+	REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
+	REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
+	REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
+	REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
+	REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
+};
+
+static int wcd9378_handle_post_irq(void *data)
+{
+	struct wcd9378_priv *wcd9378 = data;
+	u32 sts1 = 0, sts2 = 0, sts3 = 0;
+
+	regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
+	regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
+	regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
+
+	wcd9378->tx_swr_dev->slave_irq_pending =
+			((sts1 || sts2 || !sts3) ? true : false);
+
+	pr_debug("%s: sts1: 0x%0x, sts2: 0x%0x, sts3: 0x%0x\n", __func__, sts1, sts2, sts3);
+
+	return IRQ_HANDLED;
+}
+
+static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
+	.name = "wcd9378",
+	.irqs = wcd9378_regmap_irqs,
+	.num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
+	.num_regs = 3,
+	.status_base = SWRS_SCP_SDCA_INTSTAT_1,
+	.unmask_base = SWRS_SCP_SDCA_INTMASK_1,
+	.type_base = SWRS_SCP_SDCA_INTRTYPE_1,
+	.ack_base = SWRS_SCP_SDCA_INTSTAT_1,
+	.use_ack = 1,
+	.runtime_pm = false,
+	.handle_post_irq = wcd9378_handle_post_irq,
+	.irq_drv_data = NULL,
+};
+
+static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
+{
+	int ret = 0;
+	int bank = 0;
+
+	ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
+	if (ret)
+		return -EINVAL;
+
+	return ((bank & 0x40) ? 1 : 0);
+}
+
+static int wcd9378_init_reg(struct snd_soc_component *component)
+{
+	/*0.9 Volts*/
+	snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
+			WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
+	/*BG_EN ENABLE*/
+	snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
+			WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
+	usleep_range(1000, 1010);
+	/*LDOL_BG_SEL SLEEP_BG*/
+	snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
+			WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
+	usleep_range(1000, 1010);
+
+	/*Start up analog master bias. Sequence cannot change*/
+	/*VBG_FINE_ADJ 0.005 Volts*/
+	snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
+			WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
+
+	/*ANALOG_BIAS_EN ENABLE*/
+	snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
+			WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
+	/*PRECHRG_EN ENABLE*/
+	snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
+			WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
+	usleep_range(10000, 10010);
+	/*PRECHRG_EN DISABLE*/
+	snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
+			WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
+	/*End Analog Master Bias enable*/
+
+	/*SEQ_BYPASS ENABLE*/
+	snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
+			WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
+	/*TIME_OUT_SEL_PCM 160_CYCLES*/
+	snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
+			WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
+	/*TIME_OUT_SEL_PCM 160_CYCLES*/
+	snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
+			WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
+	/*IBIAS_LDO_DRIVER 5e-06*/
+	snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
+			WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
+	/*IBIAS_LDO_DRIVER 5e-06*/
+	snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
+			WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
+
+	/*SHORT_PROT_EN ENABLE*/
+	snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
+			WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
+
+	/*OCP FSM EN*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
+			WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
+	/*SCD OP EN*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
+			WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
+	/*OCP DET EN*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_L_TEST,
+			WCD9378_HPH_L_TEST_OCP_DET_EN_MASK, 0x01);
+	/*OCP DET EN*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_R_TEST,
+			WCD9378_HPH_R_TEST_OCP_DET_EN_MASK, 0x01);
+
+	/*HD2_RES_DIV_CTL_L 82.77*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
+			WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
+	/*HD2_RES_DIV_CTL_R 82.77*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
+			WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
+	/*OPAMP_CHOP_CLK_EN DISABLE*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
+			WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
+	/*RDAC_GAINCTL 0.55*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
+			WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
+	/*HPH_UP_T0: 0.002*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
+			WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
+	/*HPH_UP_T9: 0.002*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
+			WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
+	/*HPH_DN_T0: 0.007*/
+	snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
+			WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
+
+	return 0;
+}
+
+static int wcd9378_set_port_params(struct snd_soc_component *component,
+			u8 slv_prt_type, u8 *port_id, u8 *num_ch,
+			u8 *ch_mask, u32 *ch_rate,
+			u8 *port_type, u8 path)
+{
+	int i, j;
+	u8 num_ports = 0;
+	struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	switch (path) {
+	case CODEC_RX:
+		map = &wcd9378->rx_port_mapping;
+		num_ports = wcd9378->num_rx_ports;
+		break;
+	case CODEC_TX:
+		map = &wcd9378->tx_port_mapping;
+		num_ports = wcd9378->num_tx_ports;
+		break;
+	default:
+		dev_err(component->dev, "%s Invalid path selected %u\n",
+					__func__, path);
+		return -EINVAL;
+	}
+
+	for (i = 0; i <= num_ports; i++) {
+		for (j = 0; j < MAX_CH_PER_PORT; j++) {
+			if ((*map)[i][j].slave_port_type == slv_prt_type)
+				goto found;
+		}
+	}
+found:
+	if (i > num_ports || j == MAX_CH_PER_PORT) {
+		dev_err(component->dev, "%s Failed to find slave port for type %u\n",
+						__func__, slv_prt_type);
+		return -EINVAL;
+	}
+	*port_id = i;
+	*num_ch = (*map)[i][j].num_ch;
+	*ch_mask = (*map)[i][j].ch_mask;
+	*ch_rate = (*map)[i][j].ch_rate;
+	*port_type = (*map)[i][j].master_port_type;
+
+	return 0;
+}
+
+static int wcd9378_parse_port_params(struct device *dev,
+			char *prop, u8 path)
+{
+	u32 *dt_array, map_size, max_uc;
+	int ret = 0;
+	u32 cnt = 0;
+	u32 i, j;
+	struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
+	struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
+
+	switch (path) {
+	case CODEC_TX:
+		map = &wcd9378->tx_port_params;
+		map_uc = &wcd9378->swr_tx_port_params;
+		break;
+	default:
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+
+	if (!of_find_property(dev->of_node, prop,
+				&map_size)) {
+		dev_err(dev, "missing port mapping prop %s\n", prop);
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+
+	max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
+
+	if (max_uc != SWR_UC_MAX) {
+		dev_err(dev, "%s: port params not provided for all usecases\n",
+			__func__);
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+	dt_array = kzalloc(map_size, GFP_KERNEL);
+
+	if (!dt_array) {
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+	ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
+				SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
+	if (ret) {
+		dev_err(dev, "%s: Failed to read  port mapping from prop %s\n",
+					__func__, prop);
+		goto err_pdata_fail;
+	}
+
+	for (i = 0; i < max_uc; i++) {
+		for (j = 0; j < SWR_NUM_PORTS; j++) {
+			cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
+			(*map)[i][j].offset1 = dt_array[cnt];
+			(*map)[i][j].lane_ctrl = dt_array[cnt + 1];
+		}
+		(*map_uc)[i].pp = &(*map)[i][0];
+	}
+	kfree(dt_array);
+	return 0;
+
+err_pdata_fail:
+	kfree(dt_array);
+err_alloc:
+err_port_map:
+	return ret;
+}
+
+static int wcd9378_parse_port_mapping(struct device *dev,
+			char *prop, u8 path)
+{
+	u32 *dt_array, map_size, map_length;
+	u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
+	u32 slave_port_type, master_port_type;
+	u32 i, ch_iter = 0;
+	int ret = 0;
+	u8 *num_ports = NULL;
+	struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
+
+	switch (path) {
+	case CODEC_RX:
+		map = &wcd9378->rx_port_mapping;
+		num_ports = &wcd9378->num_rx_ports;
+		break;
+	case CODEC_TX:
+		map = &wcd9378->tx_port_mapping;
+		num_ports = &wcd9378->num_tx_ports;
+		break;
+	default:
+		dev_err(dev, "%s Invalid path selected %u\n",
+			      __func__, path);
+		return -EINVAL;
+	}
+
+	if (!of_find_property(dev->of_node, prop,
+				&map_size)) {
+		dev_err(dev, "missing port mapping prop %s\n", prop);
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+
+	map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
+
+	dt_array = kzalloc(map_size, GFP_KERNEL);
+
+	if (!dt_array) {
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+	ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
+				NUM_SWRS_DT_PARAMS * map_length);
+	if (ret) {
+		dev_err(dev, "%s: Failed to read  port mapping from prop %s\n",
+					__func__, prop);
+		goto err_pdata_fail;
+	}
+
+	for (i = 0; i < map_length; i++) {
+		port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
+		slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
+		ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
+		ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
+		master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
+
+		if (port_num != old_port_num)
+			ch_iter = 0;
+
+		(*map)[port_num][ch_iter].slave_port_type = slave_port_type;
+		(*map)[port_num][ch_iter].ch_mask = ch_mask;
+		(*map)[port_num][ch_iter].master_port_type = master_port_type;
+		(*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
+		(*map)[port_num][ch_iter++].ch_rate = ch_rate;
+		old_port_num = port_num;
+	}
+	*num_ports = port_num;
+	kfree(dt_array);
+	return 0;
+
+err_pdata_fail:
+	kfree(dt_array);
+err_alloc:
+err_port_map:
+	return ret;
+}
+
+static int wcd9378_tx_connect_port(struct snd_soc_component *component,
+					u8 slv_port_type, int clk_rate,
+					u8 enable)
+{
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	u8 port_id, num_ch, ch_mask;
+	u8 ch_type = 0;
+	u32 ch_rate;
+	int slave_ch_idx;
+	u8 num_port = 1;
+	int ret = 0;
+
+	ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
+				&num_ch, &ch_mask, &ch_rate,
+				&ch_type, CODEC_TX);
+	if (ret)
+		return ret;
+
+	if (clk_rate)
+		ch_rate = clk_rate;
+
+	slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
+	if (slave_ch_idx != -EINVAL)
+		ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
+
+	dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
+		__func__, slave_ch_idx, ch_type);
+
+	if (enable)
+		ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
+					num_port, &ch_mask, &ch_rate,
+					 &num_ch, &ch_type);
+	else
+		ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
+					num_port, &ch_mask, &ch_type);
+	return ret;
+
+}
+
+static int wcd9378_rx_connect_port(struct snd_soc_component *component,
+					u8 slv_port_type, u8 enable)
+{
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	u8 port_id, num_ch, ch_mask, port_type;
+	u32 ch_rate;
+	u8 num_port = 1;
+	int ret = 0;
+
+	ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
+				&num_ch, &ch_mask, &ch_rate,
+				&port_type, CODEC_RX);
+
+	if (ret)
+		return ret;
+
+	if (enable)
+		ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
+					num_port, &ch_mask, &ch_rate,
+					&num_ch, &port_type);
+	else
+		ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
+					num_port, &ch_mask, &port_type);
+	return ret;
+}
+
+
+static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
+			       struct snd_kcontrol *kcontrol,
+			       int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int mode = wcd9378->hph_mode;
+	int ret = 0;
+	int bank = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
+		mode == CLS_H_HIFI || mode == CLS_H_LP) {
+		wcd9378_rx_connect_port(component, CLSH,
+				SND_SOC_DAPM_EVENT_ON(event));
+	}
+	if (SND_SOC_DAPM_EVENT_OFF(event)) {
+		bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
+			wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, false);
+
+		ret = swr_slvdev_datapath_control(
+				wcd9378->rx_swr_dev,
+				wcd9378->rx_swr_dev->dev_num,
+				false);
+		wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, false);
+	}
+	return ret;
+}
+
+static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
+				     struct snd_kcontrol *kcontrol,
+				     int event)
+{
+	struct snd_soc_component *component =
+				snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	u32 dmic_clk_reg, dmic_clk_en_reg;
+	s32 *dmic_clk_cnt;
+	u8 dmic_ctl_shift = 0;
+	u8 dmic_clk_shift = 0;
+	u8 dmic_clk_mask = 0;
+	u32 dmic2_left_en = 0;
+	int ret = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (w->shift) {
+	case 0:
+	case 1:
+		dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
+		dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
+		dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
+		dmic_clk_mask = 0x0F;
+		dmic_clk_shift = 0x00;
+		dmic_ctl_shift = 0x00;
+		break;
+	case 2:
+		dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
+		fallthrough;
+	case 3:
+		dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
+		dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
+		dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
+		dmic_clk_mask = 0xF0;
+		dmic_clk_shift = 0x04;
+		dmic_ctl_shift = 0x01;
+		break;
+	case 4:
+	case 5:
+		dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
+		dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
+		dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
+		dmic_clk_mask = 0x0F;
+		dmic_clk_shift = 0x00;
+		dmic_ctl_shift = 0x02;
+		break;
+	default:
+		dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
+			__func__);
+		return -EINVAL;
+	};
+	dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
+			__func__, event,  (w->shift + 1), *dmic_clk_cnt);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_component_update_bits(component,
+				WCD9378_CDC_AMIC_CTL,
+				(0x01 << dmic_ctl_shift), 0x00);
+		/* 250us sleep as per HW requirement */
+		usleep_range(250, 260);
+		if (dmic2_left_en)
+			snd_soc_component_update_bits(component,
+				dmic2_left_en, 0x80, 0x80);
+		/* Setting DMIC clock rate to 2.4MHz */
+		snd_soc_component_update_bits(component,
+					dmic_clk_reg, dmic_clk_mask,
+					(0x03 << dmic_clk_shift));
+		snd_soc_component_update_bits(component,
+					dmic_clk_en_reg, 0x08, 0x08);
+		/* enable clock scaling */
+		snd_soc_component_update_bits(component,
+				WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
+		ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
+				wcd9378->tx_swr_dev->dev_num,
+				true);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
+				false);
+		snd_soc_component_update_bits(component,
+				WCD9378_CDC_AMIC_CTL,
+				(0x01 << dmic_ctl_shift),
+				(0x01 << dmic_ctl_shift));
+		if (dmic2_left_en)
+			snd_soc_component_update_bits(component,
+				dmic2_left_en, 0x80, 0x00);
+		snd_soc_component_update_bits(component,
+					dmic_clk_en_reg, 0x08, 0x00);
+		break;
+	};
+	return ret;
+}
+
+/*
+ * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
+ * @micb_mv: micbias in mv
+ *
+ * return register value converted
+ */
+int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
+{
+	/* min micbias voltage is 1V and maximum is 2.85V */
+	if (micb_mv < 1000 || micb_mv > 2850) {
+		pr_err("%s: unsupported micbias voltage\n", __func__);
+		return -EINVAL;
+	}
+
+	return (micb_mv - 1000) / 50;
+}
+EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
+
+/*
+ * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
+ * @component: handle to snd_soc_component *
+ * @req_volt: micbias voltage to be set
+ * @micb_num: micbias to be set, e.g. micbias1 or micbias2
+ *
+ * return 0 if adjustment is success or error code in case of failure
+ */
+static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
+				u32 micb_mv, int micb_num)
+{
+	int vcout_ctl;
+
+	switch (micb_mv) {
+	case 2200:
+		return MICB_USAGE_VAL_2P2V;
+	case 2700:
+		return MICB_USAGE_VAL_2P7V;
+	case 2800:
+		return MICB_USAGE_VAL_2P8V;
+	default:
+		vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
+		if (micb_num == MIC_BIAS_1) {
+			snd_soc_component_update_bits(component,
+				WCD9378_MICB_REMAP_TABLE_VAL_3,
+				WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
+				vcout_ctl);
+			return MICB_USAGE_VAL_MICB1_TABLE_VAL;
+		} else if (micb_num == MIC_BIAS_2) {
+			snd_soc_component_update_bits(component,
+				WCD9378_MICB_REMAP_TABLE_VAL_4,
+				WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
+				vcout_ctl);
+			return MICB_USAGE_VAL_MICB2_TABLE_VAL;
+		} else if (micb_num == MIC_BIAS_3) {
+			snd_soc_component_update_bits(component,
+				WCD9378_MICB_REMAP_TABLE_VAL_5,
+				WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
+				vcout_ctl);
+			return MICB_USAGE_VAL_MICB3_TABLE_VAL;
+		}
+	}
+
+	return 0;
+}
+
+static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
+				u32 micb_mv, int micb_num)
+{
+	switch (micb_mv) {
+	case 0:
+		return MICB_USAGE_VAL_PULL_DOWN;
+	case 1200:
+		return MICB_USAGE_VAL_1P2V;
+	case 1800:
+		return MICB_USAGE_VAL_1P8VORPULLUP;
+	case 2500:
+		return MICB_USAGE_VAL_2P5V;
+	case 2750:
+		return MICB_USAGE_VAL_2P75V;
+	default:
+		return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
+	}
+
+	return MICB_USAGE_VAL_DISABLE;
+}
+
+int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
+				   int req_volt, int micb_num)
+{
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+	int micb_usage = 0, micb_mask = 0, req_vout_ctl;
+	int sm_num = 0;
+	struct wcd9378_pdata *pdata = NULL;
+
+	pdata = dev_get_platdata(wcd9378->dev);
+
+	if (wcd9378 == NULL) {
+		dev_err(component->dev,
+			"%s: wcd9378 private data is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	for (sm_num = 0; sm_num < SIM_MIC_NUM; sm_num++)
+		if (wcd9378->micb_sel[sm_num] == micb_num)
+			break;
+
+	if ((sm_num == SIM_MIC_NUM) && (micb_num != MIC_BIAS_2)) {
+		pr_err("%s: cannot find the simple mic function which connect to micbias_%d\n",
+		__func__, micb_num);
+		return -EINVAL;
+	}
+
+
+	switch (sm_num) {
+	case SIM_MIC0:
+		micb_usage = WCD9378_IT11_USAGE;
+		micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
+		break;
+	case SIM_MIC1:
+		micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
+		micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
+		break;
+	case SIM_MIC2:
+		micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
+		micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
+		break;
+	default:
+		if (micb_num == MIC_BIAS_2) {
+			micb_usage = WCD9378_IT31_MICB;
+			micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
+		}
+		break;
+	}
+
+	mutex_lock(&wcd9378->micb_lock);
+
+	req_vout_ctl =
+		wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
+
+	snd_soc_component_update_bits(component,
+			micb_usage, micb_mask, req_vout_ctl);
+
+	mutex_unlock(&wcd9378->micb_lock);
+	return 0;
+
+
+}
+EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
+
+void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
+					    bool bcs_disable)
+{
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	if (wcd9378->update_wcd_event) {
+		if (bcs_disable)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
+		else
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
+	}
+}
+
+static int wcd9378_get_clk_rate(int mode)
+{
+	int rate;
+
+	switch (mode) {
+	case ADC_MODE_LP:
+		rate = SWR_CLK_RATE_4P8MHZ;
+		break;
+	case ADC_MODE_INVALID:
+	case ADC_MODE_NORMAL:
+	case ADC_MODE_HIFI:
+	default:
+		rate = SWR_CLK_RATE_9P6MHZ;
+		break;
+	}
+
+	pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
+	return rate;
+}
+
+static int wcd9378_set_swr_clk_rate(struct snd_soc_component *component,
+					int rate, int bank)
+{
+	u8 mask = (bank ? 0xF0 : 0x0F);
+	u8 val = 0;
+
+	switch (rate) {
+	case SWR_CLK_RATE_2P4MHZ:
+		val = (bank ? 0x30 : 0x03);
+		break;
+	case SWR_CLK_RATE_4P8MHZ:
+		val = (bank ? 0x10 : 0x01);
+		break;
+	case SWR_CLK_RATE_9P6MHZ:
+	default:
+		val = 0x00;
+		break;
+	}
+	dev_dbg(component->dev,
+		"%s: rate: 0x%0x\n", __func__, val);
+
+	snd_soc_component_update_bits(component, WCD9378_SWR_TX_CLK_RATE,
+				      mask, val);
+
+	return 0;
+}
+
+static void wcd9378_micb_usage_value_write(struct snd_soc_component *component,
+					unsigned char tx_path)
+{
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+	int micb_num;
+
+	switch (tx_path) {
+	case ADC1:
+		micb_num = (snd_soc_component_read(component,
+					WCD9378_SM0_MB_SEL) &
+					WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK);
+		break;
+	case ADC2:
+		micb_num = (snd_soc_component_read(component,
+					WCD9378_SM1_MB_SEL) &
+					WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK);
+		break;
+	case ADC3:
+		micb_num = (snd_soc_component_read(component,
+					WCD9378_SM2_MB_SEL) &
+					WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK);
+		break;
+	default:
+		pr_err("%s: unsupport tx path\n", __func__);
+		return;
+	}
+
+	if (!wcd9378->va_amic_en)
+		wcd9378_micbias_control(component, micb_num,
+			MICB_ENABLE, true);
+	else
+		wcd9378_micbias_control(component, micb_num,
+			MICB_PULLUP_ENABLE, true);
+}
+
+static int wcd9378_get_adc_mode_val(int mode)
+{
+	int ret = 0;
+
+	switch (mode) {
+	case ADC_MODE_INVALID:
+	case ADC_MODE_NORMAL:
+		ret = ADC_MODE_VAL_NORMAL;
+		break;
+	case ADC_MODE_HIFI:
+		ret = ADC_MODE_VAL_HIFI;
+		break;
+	case ADC_MODE_LP:
+		ret = ADC_MODE_VAL_LP;
+		break;
+	default:
+		ret = -EINVAL;
+		pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
+		break;
+	}
+	return ret;
+}
+
+static void wcd9378_micb_sel_set(struct snd_soc_component *component,
+		unsigned char micb_num)
+{
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+
+	switch (micb_num) {
+	case 0:
+		snd_soc_component_update_bits(component, WCD9378_SM0_MB_SEL,
+			WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK, wcd9378->micb_sel[0]);
+		break;
+	case 1:
+		snd_soc_component_update_bits(component, WCD9378_SM1_MB_SEL,
+			WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK, wcd9378->micb_sel[1]);
+		break;
+	case 2:
+		snd_soc_component_update_bits(component, WCD9378_SM2_MB_SEL,
+			WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK, wcd9378->micb_sel[2]);
+		break;
+	default:
+		break;
+	}
+
+}
+
+static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
+			       struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 =
+				snd_soc_component_get_drvdata(component);
+	int mode_val = 0, bank = 0, ret = 0, rate = 0;
+	int act_ps = 0;
+
+	bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
+		wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
+
+	dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
+		w->name, w->shift, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd9378_micb_sel_set(component, w->shift - ADC1);
+		mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
+		if (mode_val < 0) {
+			dev_dbg(component->dev,
+				"%s: invalid mode, setting to normal mode\n",
+				__func__);
+			mode_val = ADC_MODE_VAL_NORMAL;
+		}
+
+		rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
+
+		if (w->shift == ADC2 && !((snd_soc_component_read(component,
+				WCD9378_TX_NEW_TX_CH12_MUX) &
+				WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
+			if (!wcd9378->bcs_dis) {
+				dev_err(component->dev, "%s: mbhc connect port enter\n", __func__);
+				wcd9378_tx_connect_port(component, MBHC,
+					SWR_CLK_RATE_4P8MHZ, true);
+				set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
+			}
+		}
+
+		set_bit(w->shift - ADC1, &wcd9378->status_mask);
+		wcd9378_tx_connect_port(component, w->shift, rate,
+				true);
+
+		switch (w->shift) {
+		case ADC1:
+			dev_dbg(component->dev, "%s ADC1 enter\n", __func__);
+			/*SMP MIC0 MICB_USAGE SET*/
+			wcd9378_micb_usage_value_write(component, ADC1);
+
+			/*SMP MIC0 IT11 USAGE SET*/
+			snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
+						WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
+
+			/*Hold TXFE in Initialization During Startup*/
+			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
+						WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
+
+			/*Power up TX0 sequencer*/
+			snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
+					WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
+
+			break;
+		case ADC2:
+			switch (wcd9378->sys_usage) {
+			case SJ_SA_AUX_2SM:
+			case SJ_SA_AUX_2SM_1HDR:
+			case SJ_SA_EAR_2SM:
+			case SJ_SA_EAR_2SM_1HDR:
+			case SJ_1HDR_SA_AUX_1SM:
+			case SJ_1HDR_SA_EAR_1SM:
+			case SJ_NOMIC_SA_EAR_3SM:
+			case SJ_NOMIC_SA_AUX_3SM:
+				dev_dbg(component->dev, "%s SJ ADC2 enter\n", __func__);
+				/*SMP JACK IT31 MICB SET*/
+				wcd9378_micbias_control(component, MIC_BIAS_2,
+					MICB_ENABLE, true);
+
+				/*SMP JACK IT31 USAGE SET*/
+				snd_soc_component_update_bits(component,
+						WCD9378_IT31_USAGE,
+						WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
+				/*Power up TX1 sequencer*/
+				snd_soc_component_update_bits(component,
+						WCD9378_PDE34_REQ_PS,
+						WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
+				break;
+			case NOSJ_SA_STEREO_3SM:
+			case NOSJ_SA_STEREO_3SM_1HDR:
+			case NOSJ_SA_EAR_3SM:
+			case NOSJ_SA_EAR_3SM_1HDR:
+				dev_dbg(component->dev, "%s SM1 ADC2 enter\n", __func__);
+				/*SMP MIC1 MICB_USAGE SET*/
+				wcd9378_micb_usage_value_write(component, ADC2);
+
+				/*SMP MIC1 IT11 USAGE SET*/
+				snd_soc_component_update_bits(component,
+						WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
+						WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
+						mode_val);
+
+				/*Hold TXFE in Initialization During Startup*/
+				snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
+						WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
+
+				/*Power up TX1 sequencer*/
+				snd_soc_component_update_bits(component,
+					WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
+					WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
+					0x00);
+				break;
+			}
+			break;
+		case ADC3:
+			/*SMP MIC2 MICB_USAGE SET*/
+			wcd9378_micb_usage_value_write(component, ADC3);
+
+			/*SMP MIC2 IT11 USAGE SET*/
+			snd_soc_component_update_bits(component,
+						WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
+						WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
+						mode_val);
+
+			/*Hold TXFE in Initialization During Startup*/
+			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
+						WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
+
+			/*Power up TX2 sequencer*/
+			snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
+					WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
+			break;
+		default:
+			break;
+		}
+		/*default delay 800us*/
+		usleep_range(800, 810);
+		/****ADC START*****/
+		wcd9378_set_swr_clk_rate(component, rate, bank);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
+
+		ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
+				wcd9378->tx_swr_dev->dev_num,
+				true);
+
+		/* Copy clk settings to active bank */
+		wcd9378_set_swr_clk_rate(component, rate, !bank);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
+		/****ADC END*****/
+
+		switch (w->shift) {
+		case ADC1:
+			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
+						WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
+			break;
+		case ADC2:
+			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
+						WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
+			break;
+		case ADC3:
+			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
+						WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
+			break;
+		};
+
+		if (w->shift == ADC1) {
+			act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
+			if (act_ps)
+				pr_err("%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
+						__func__, act_ps);
+			else
+				pr_err("%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
+						__func__, act_ps);
+		}
+
+		if (w->shift == ADC2) {
+			act_ps = snd_soc_component_read(component,
+						WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
+			if (act_ps)
+				pr_err("%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
+						__func__, act_ps);
+			else
+				pr_err("%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
+						__func__, act_ps);
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/****ADC START****/
+		wcd9378_tx_connect_port(component, w->shift, 0, false);
+		if (w->shift == ADC2 &&
+			test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
+			wcd9378_tx_connect_port(component, MBHC, 0,
+					false);
+			clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
+		}
+
+		/****ADC END****/
+
+		switch (w->shift) {
+		case ADC1:
+			/*Normal TXFE Startup*/
+			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
+					WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
+
+			/*tear down TX0 sequencer*/
+			snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
+					WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
+
+			break;
+		case ADC2:
+			/*tear down TX1 sequencer*/
+			snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
+					WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
+
+			/*Normal TXFE Startup*/
+			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
+					WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
+
+			/*tear down TX1 sequencer*/
+			snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
+					WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
+			break;
+		case ADC3:
+			/*Normal TXFE Startup*/
+			snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
+					WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
+
+			/*tear down TX2 sequencer*/
+			snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
+					WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
+			break;
+		default:
+			break;
+		}
+		/*default delay 800us*/
+		usleep_range(800, 810);
+
+		rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
+
+		wcd9378_set_swr_clk_rate(component, rate, bank);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
+
+		ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
+				wcd9378->tx_swr_dev->dev_num,
+				false);
+		wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
+
+		wcd9378_set_swr_clk_rate(component, rate, !bank);
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
+				    struct snd_kcontrol *kcontrol,
+				    int event)
+{
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int ret = 0;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd9378_tx_connect_port(component, w->shift,
+					SWR_CLK_RATE_2P4MHZ, true);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
+				wcd9378->tx_swr_dev->dev_num,
+				false);
+		break;
+	};
+
+	return ret;
+}
+
+/*
+ * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
+ * @component: handle to snd_soc_component *
+ *
+ * return wcd9378_mbhc handle or error code in case of failure
+ */
+struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378;
+
+	if (!component) {
+		pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
+		return NULL;
+	}
+	wcd9378 = snd_soc_component_get_drvdata(component);
+
+	if (!wcd9378) {
+		pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
+		return NULL;
+	}
+
+	return wcd9378->mbhc;
+}
+EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
+
+static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		/*HPHL ENABLE*/
+		snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
+			WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
+		wcd9378_rx_connect_port(component, HPH_L, true);
+
+		if (wcd9378->comp1_enable) {
+			snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
+				WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
+			wcd9378_rx_connect_port(component, COMP_L, true);
+		}
+
+		if (wcd9378->update_wcd_event)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10));
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (wcd9378->update_wcd_event)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10 | 0x1));
+
+		if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
+			wcd9378->update_wcd_event(wcd9378->handle,
+					SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
+					(WCD_RX1 << 0x10));
+		/*HPHL DISABLE*/
+		snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
+			WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
+		wcd9378_rx_connect_port(component, HPH_L, false);
+
+		if (wcd9378->comp1_enable) {
+			snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
+				WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
+			wcd9378_rx_connect_port(component, COMP_R, false);
+		}
+		break;
+	default:
+		break;
+	};
+
+	return 0;
+
+}
+
+static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		/*HPHR ENABLE*/
+		snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
+				WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
+		wcd9378_rx_connect_port(component, HPH_R, true);
+
+		if (wcd9378->comp2_enable) {
+			snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
+				WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
+			wcd9378_rx_connect_port(component, COMP_R, true);
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/*HPHR DISABLE*/
+		snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
+			WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
+		wcd9378_rx_connect_port(component, HPH_R, false);
+
+		if (wcd9378->comp2_enable) {
+			snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
+				WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
+			wcd9378_rx_connect_port(component, COMP_R, false);
+		}
+		break;
+	default:
+		break;
+	};
+
+	return 0;
+
+}
+
+static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int ret;
+	int bank = 0;
+	int act_ps = 0;
+
+	bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
+		wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (wcd9378->update_wcd_event)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10 | 0x01));
+		wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
+
+		ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
+					wcd9378->rx_swr_dev->dev_num,
+					true);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
+		if (wcd9378->update_wcd_event)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10));
+
+		act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
+		if (act_ps)
+			pr_err("%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
+							__func__, act_ps);
+		else
+			pr_err("%s: hph sequencer power on successful, act_ps: 0x%0x\n",
+							__func__, act_ps);
+
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (wcd9378->update_wcd_event)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10 | 0x1));
+
+		if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
+			wcd9378->update_wcd_event(wcd9378->handle,
+					SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
+					(WCD_RX1 << 0x10));
+
+		if (!wcd9378->comp1_enable)
+			/*PA delay is 24250us*/
+			usleep_range(24300, 24310);
+		else
+			/*COMP delay is 11250us*/
+			usleep_range(11300, 11310);
+
+		blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
+					WCD_EVENT_POST_HPHL_PA_OFF,
+					&wcd9378->mbhc->wcd_mbhc);
+
+		break;
+	default:
+		break;
+	};
+
+	return 0;
+}
+
+static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int ret;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (wcd9378->update_wcd_event)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX2 << 0x10 | 0x1));
+		ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
+				    wcd9378->rx_swr_dev->dev_num,
+				    true);
+		if (wcd9378->update_wcd_event)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX2 << 0x10));
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (wcd9378->update_wcd_event)
+			wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX2 << 0x10 | 0x1));
+
+		if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
+			wcd9378->update_wcd_event(wcd9378->handle,
+					SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
+					(WCD_RX2 << 0x10));
+
+		if (!wcd9378->comp2_enable)
+			/*PA delay is 24250us*/
+			usleep_range(24300, 24310);
+		else
+			/*COMP delay is 11250us*/
+			usleep_range(11300, 11310);
+
+		blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
+					WCD_EVENT_POST_HPHR_PA_OFF,
+					&wcd9378->mbhc->wcd_mbhc);
+
+		break;
+	default:
+		break;
+	};
+
+	return 0;
+
+}
+
+static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_component *component =
+				snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int ret = 0;
+	int bank = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
+		wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
+
+		ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
+			    wcd9378->rx_swr_dev->dev_num,
+			    true);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
+
+		wcd9378->aux_rx_path =
+			(snd_soc_component_read(
+				component, WCD9378_CDC_HPH_GAIN_CTL) &
+					WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK) >> 0x03;
+
+		if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
+			if (wcd9378->update_wcd_event)
+				wcd9378->update_wcd_event(wcd9378->handle,
+							SLV_BOLERO_EVT_RX_MUTE,
+							(WCD_RX2 << 0x10));
+
+		} else {
+			if (wcd9378->update_wcd_event)
+				wcd9378->update_wcd_event(wcd9378->handle,
+							SLV_BOLERO_EVT_RX_MUTE,
+							(WCD_RX3 << 0x10));
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
+			if (wcd9378->update_wcd_event)
+				wcd9378->update_wcd_event(wcd9378->handle,
+							SLV_BOLERO_EVT_RX_MUTE,
+							(WCD_RX2 << 0x10 | 0x1));
+		} else {
+			if (wcd9378->update_wcd_event)
+				wcd9378->update_wcd_event(wcd9378->handle,
+							SLV_BOLERO_EVT_RX_MUTE,
+							(WCD_RX3 << 0x10 | 0x1));
+		}
+		break;
+	};
+	return ret;
+}
+
+static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int ret = 0, bank = 0;
+	int act_ps = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
+		wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
+
+		ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
+				wcd9378->rx_swr_dev->dev_num,
+				true);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
+
+		wcd9378->ear_rx_path =
+			(snd_soc_component_read(
+				component, WCD9378_CDC_HPH_GAIN_CTL) &
+					WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK) >> 0x02;
+
+		if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
+			if (wcd9378->update_wcd_event)
+				wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10));
+		} else {
+			if (wcd9378->update_wcd_event)
+				wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX3 << 0x10));
+		}
+
+		act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
+		if (act_ps)
+			pr_err("%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
+							__func__, act_ps);
+		else
+			pr_err("%s: sa sequencer power on successful, act_ps: 0x%0x\n",
+							__func__, act_ps);
+
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
+			if (wcd9378->update_wcd_event)
+				wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10 | 0x1));
+		} else {
+			if (wcd9378->update_wcd_event)
+				wcd9378->update_wcd_event(wcd9378->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX3 << 0x10 | 0x1));
+		}
+		break;
+	};
+	return ret;
+}
+
+static int wcd9378_get_hph_pwr_level(int hph_mode)
+{
+	switch (hph_mode) {
+	case CLS_H_LOHIFI:
+	case CLS_AB_LOHIFI:
+		return PWR_LEVEL_LOHIFI_VAL;
+	case CLS_H_LP:
+	case CLS_AB_LP:
+		return PWR_LEVEL_LP_VAL;
+	case CLS_H_HIFI:
+	case CLS_AB_HIFI:
+		return PWR_LEVEL_HIFI_VAL;
+	case CLS_H_ULP:
+	case CLS_AB:
+	case CLS_H_NORMAL:
+	default:
+		return PWR_LEVEL_ULP_VAL;
+	}
+
+	return PWR_LEVEL_ULP_VAL;
+}
+
+static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 =
+				snd_soc_component_get_drvdata(component);
+
+	if ((!wcd9378->comp1_enable) &&
+			(!wcd9378->comp2_enable)) {
+		dev_err(component->dev, "%s hph gainis 0x%0xd\n", __func__, wcd9378->hph_gain);
+		snd_soc_component_update_bits(component,
+				(WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
+				WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
+				wcd9378->hph_gain >> 8);
+		snd_soc_component_update_bits(component,
+				WCD9378_FU42_CH_VOL_CH1,
+				WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
+				wcd9378->hph_gain & 0x00ff);
+
+		snd_soc_component_update_bits(component,
+				(WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
+				WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
+				wcd9378->hph_gain >> 8);
+		snd_soc_component_update_bits(component,
+				WCD9378_FU42_CH_VOL_CH2,
+				WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
+				wcd9378->hph_gain & 0x00ff);
+	}
+}
+
+static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable)
+{
+	u16 clk_scale_reg = 0;
+	u8 clk_rst = 0x00, scale_rst = 0x00;
+	struct wcd9378_priv *wcd9378 = NULL;
+	struct swr_device *swr_dev = NULL;
+
+	wcd9378 = dev_get_drvdata(dev);
+	if (!wcd9378)
+		return -EINVAL;
+
+	if (path == RX_PATH)
+		swr_dev = wcd9378->rx_swr_dev;
+	else
+		swr_dev = wcd9378->tx_swr_dev;
+
+	clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
+				SWRS_SCP_BUSCLOCK_SCALE_BANK0);
+
+	if (enable) {
+		pr_debug("%s: bank: %d	base_clk: 0x%0x, clk_scale_reg: 0x%0x, swr_clk_scale: 0x%0x\n",
+				__func__, bank, wcd9378->swr_base_clk,
+				clk_scale_reg, wcd9378->swr_clk_scale);
+
+		swr_write(swr_dev, swr_dev->dev_num,
+				SWRS_SCP_BASE_CLK_BASE, &wcd9378->swr_base_clk);
+		swr_write(swr_dev, swr_dev->dev_num,
+				clk_scale_reg, &wcd9378->swr_clk_scale);
+	} else {
+		swr_write(swr_dev, swr_dev->dev_num,
+				SWRS_SCP_BASE_CLK_BASE, &clk_rst);
+		swr_write(swr_dev, swr_dev->dev_num,
+				clk_scale_reg, &scale_rst);
+	}
+
+	return 0;
+}
+
+static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
+				struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_component *component =
+				snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 =
+				snd_soc_component_get_drvdata(component);
+	int power_level;
+	struct swr_device *swr_dev = wcd9378->tx_swr_dev;
+	u8 scp_commit_val = 0x2;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
+			snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
+				WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
+
+			snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
+				WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
+		}
+
+		if ((wcd9378->hph_mode == CLS_AB) ||
+			(wcd9378->hph_mode == CLS_AB_HIFI) ||
+				(wcd9378->hph_mode == CLS_AB_LP) ||
+					(wcd9378->hph_mode == CLS_AB_LOHIFI))
+			snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
+				WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
+
+		/*GET HPH_MODE*/
+		power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
+
+		/*SET HPH_MODE*/
+		snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
+				WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
+
+		/*TURN ON HPH SEQUENCER*/
+		snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
+				WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
+
+		/*TBD: SET SDCA GAIN, NEED CHECK THE LOGIC*/
+		wcd9378_hph_set_channel_volume(component);
+
+		if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
+			/*PA delay is 22400us*/
+			usleep_range(22500, 22510);
+		else
+			/*COMP delay is 9400us*/
+			usleep_range(9500, 9510);
+
+		/*RX0 unmute*/
+		snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
+				WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
+
+		/*RX1 unmute*/
+		snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
+				WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
+
+		swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/*RX0 mute*/
+		snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
+				WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
+		/*RX1 mute*/
+		snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
+				WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
+
+		/*TEAR DOWN HPH SEQUENCER*/
+		snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
+				WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
+
+		break;
+	default:
+		break;
+	};
+
+	return 0;
+}
+
+static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int ear_rx0 = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	ear_rx0 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
+				WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		/*CHECK IF EAR CONNET TO RX2*/
+		if (!ear_rx0) {
+			pr_debug("%s: ear rx2 enter\n", __func__);
+			/*FORCE CLASS_AB EN*/
+			snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
+				WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
+
+			snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
+				WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
+
+			/*RX2 ENABLE*/
+			snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
+					WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
+
+			if (wcd9378->rx2_clk_mode)
+				snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
+					WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
+
+			wcd9378_rx_connect_port(component, LO, true);
+		} else {
+			pr_debug("%s: ear rx0 enter\n", __func__);
+			if (wcd9378->comp1_enable) {
+				snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
+					WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
+				wcd9378_rx_connect_port(component, COMP_L, true);
+			}
+
+			wcd9378_rx_connect_port(component, HPH_L, true);
+		}
+
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (ear_rx0) {
+			/*RX0 DISABLE*/
+			snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
+				WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
+			wcd9378_rx_connect_port(component, HPH_L, false);
+
+			if (wcd9378->comp1_enable) {
+				snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
+					WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
+				wcd9378_rx_connect_port(component, COMP_L, false);
+			}
+		} else {
+			/*RX1 DISABLE*/
+			snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
+					WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
+
+			wcd9378_rx_connect_port(component, LO, false);
+		}
+
+		break;
+	};
+	return 0;
+
+}
+
+static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int aux_rx1 = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	aux_rx1 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
+				WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (aux_rx1) {
+			wcd9378_rx_connect_port(component, HPH_R, true);
+		} else {
+			/*RX2 ENABLE*/
+			snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
+					WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
+
+			if (wcd9378->rx2_clk_mode)
+				snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
+					WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
+
+			wcd9378_rx_connect_port(component, LO, true);
+		}
+
+		set_bit(WCD_AUX_EN, &wcd9378->status_mask);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (aux_rx1) {
+			wcd9378_rx_connect_port(component, HPH_R, false);
+		} else {
+			snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
+					WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
+			wcd9378_rx_connect_port(component, LO, true);
+		}
+
+		clear_bit(WCD_AUX_EN, &wcd9378->status_mask);
+		break;
+	};
+	return 0;
+
+}
+
+static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
+				struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		/*TURN ON AMP SEQUENCER*/
+		snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
+				WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
+		/*default delay 8550us*/
+		usleep_range(8600, 8610);
+
+		/*FU23 UNMUTE*/
+		snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
+				WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
+
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/*FU23 MUTE*/
+		snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
+				WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
+
+		/*TEAR DOWN AMP SEQUENCER*/
+		snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
+				WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
+		/*default delay 1530us*/
+		usleep_range(15400, 15410);
+		break;
+	default:
+		break;
+	};
+
+	return 0;
+}
+
+int wcd9378_micbias_control(struct snd_soc_component *component,
+				int micb_num, int req, bool is_dapm)
+{
+
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+	struct wcd9378_pdata *pdata =
+			dev_get_platdata(wcd9378->dev);
+	struct wcd9378_micbias_setting *mb = &pdata->micbias;
+	int micb_index = micb_num - 1;
+	int pre_off_event = 0, post_off_event = 0;
+	int post_on_event = 0, post_dapm_off = 0;
+	int post_dapm_on = 0;
+	int ret = 0, sm_num = 0;
+	int micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
+	int pull_up_mask = 0, pull_up_en = 0;
+
+	dev_dbg(component->dev, "%s: enter, micb_num: %d, req: %d\n",
+			__func__, micb_num, req);
+
+	if ((micb_index < 0) || (micb_index > WCD9378_MAX_MICBIAS)) {
+		dev_err(component->dev,
+			"%s: Invalid micbias index, micb_index:%d\n",
+			__func__, micb_index);
+		return -EINVAL;
+	}
+
+	if (wcd9378 == NULL) {
+		dev_err(component->dev,
+			"%s: wcd9378 private data is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	for (sm_num = 0; sm_num < SIM_MIC_NUM; sm_num++)
+		if (wcd9378->micb_sel[sm_num] == micb_num)
+			break;
+
+	if ((sm_num == SIM_MIC_NUM) && (micb_num != MIC_BIAS_2)) {
+		pr_err("%s: cannot find the simple mic function which connect to micbias_%d\n",
+		__func__, micb_num);
+		return -EINVAL;
+	}
+
+	dev_err(component->dev, "%s: function num: %d\n",
+			__func__, sm_num);
+
+	switch (sm_num) {
+	case SIM_MIC0:
+		micb_usage = WCD9378_IT11_MICB;
+		micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
+		break;
+	case SIM_MIC1:
+		micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
+		micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
+		break;
+	case SIM_MIC2:
+		micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
+		micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
+		break;
+	default:
+		dev_err(component->dev, "%s: switch default enter: %d\n",
+				__func__, sm_num);
+		if (micb_num == MIC_BIAS_2) {
+			micb_usage = WCD9378_IT31_MICB;
+			micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
+		}
+		break;
+	}
+
+	dev_err(component->dev, "%s: sm_num: %d\n",
+			__func__, sm_num);
+
+	switch (micb_num) {
+	case MIC_BIAS_1:
+		pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
+		pull_up_en = 0x01;
+		micb_usage_val = mb->micb1_usage_val;
+		break;
+	case MIC_BIAS_2:
+		pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
+		pull_up_en = 0x02;
+		micb_usage_val = mb->micb2_usage_val;
+		pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
+		post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
+		post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
+		post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
+		post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
+		break;
+	case MIC_BIAS_3:
+		pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
+		pull_up_en = 0x04;
+		micb_usage_val = mb->micb3_usage_val;
+		break;
+	default:
+		dev_err(component->dev, "%s: Invalid micbias number: %d\n",
+			__func__, micb_num);
+		return -EINVAL;
+	}
+
+	mutex_lock(&wcd9378->micb_lock);
+
+	switch (req) {
+	case MICB_PULLUP_ENABLE:
+		if (!wcd9378->dev_up) {
+			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
+				__func__, req);
+			ret = -ENODEV;
+			goto done;
+		}
+		wcd9378->pullup_ref[micb_index]++;
+		if ((wcd9378->pullup_ref[micb_index] == 1) &&
+			(wcd9378->micb_ref[micb_index] == 0)) {
+			snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
+						pull_up_mask, pull_up_en);
+			snd_soc_component_update_bits(component,
+						micb_usage, micb_mask, 0x03);
+		}
+		break;
+	case MICB_PULLUP_DISABLE:
+		if (wcd9378->pullup_ref[micb_index] > 0)
+			wcd9378->pullup_ref[micb_index]--;
+		if (!wcd9378->dev_up) {
+			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
+				__func__, req);
+			ret = -ENODEV;
+			goto done;
+		}
+		if ((wcd9378->pullup_ref[micb_index] == 0) &&
+			    (wcd9378->micb_ref[micb_index] == 0))
+			snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
+		break;
+	case MICB_ENABLE:
+		dev_dbg(component->dev, "%s: micbias enable enter\n",
+			__func__);
+		if (!wcd9378->dev_up) {
+			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
+				__func__, req);
+			ret = -ENODEV;
+			goto done;
+		}
+		wcd9378->micb_ref[micb_index]++;
+		if (wcd9378->micb_ref[micb_index] == 1) {
+			dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
+			__func__, micb_usage, micb_usage_val);
+			snd_soc_component_update_bits(component,
+					micb_usage, micb_mask, micb_usage_val);
+
+			if (post_on_event)
+				blocking_notifier_call_chain(
+						&wcd9378->mbhc->notifier,
+						post_on_event,
+						&wcd9378->mbhc->wcd_mbhc);
+		}
+		if (is_dapm && post_dapm_on && wcd9378->mbhc)
+			blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
+						     post_dapm_on,
+						     &wcd9378->mbhc->wcd_mbhc);
+		break;
+	case MICB_DISABLE:
+		if (wcd9378->micb_ref[micb_index] > 0)
+			wcd9378->micb_ref[micb_index]--;
+		if (!wcd9378->dev_up) {
+			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
+				__func__, req);
+			ret = -ENODEV;
+			goto done;
+		}
+		if ((wcd9378->micb_ref[micb_index] == 0) &&
+			(wcd9378->pullup_ref[micb_index] > 0)) {
+			/*PULL UP?*/
+			snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
+						pull_up_mask, pull_up_en);
+			snd_soc_component_update_bits(component, micb_usage,
+						micb_mask, 0x03);
+		} else if ((wcd9378->micb_ref[micb_index] == 0) &&
+			 (wcd9378->pullup_ref[micb_index] == 0)) {
+			if (pre_off_event && wcd9378->mbhc)
+				blocking_notifier_call_chain(
+						&wcd9378->mbhc->notifier,
+						pre_off_event,
+						&wcd9378->mbhc->wcd_mbhc);
+			snd_soc_component_update_bits(component, micb_usage,
+							micb_mask, 0x00);
+
+			if (post_off_event && wcd9378->mbhc)
+				blocking_notifier_call_chain(
+						&wcd9378->mbhc->notifier,
+						post_off_event,
+						&wcd9378->mbhc->wcd_mbhc);
+		}
+		if (is_dapm && post_dapm_off && wcd9378->mbhc)
+			blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
+						post_dapm_off,
+						&wcd9378->mbhc->wcd_mbhc);
+
+		break;
+	default:
+		dev_err(component->dev, "%s: Invalid req event: %d\n",
+			__func__, req);
+		return -EINVAL;
+	}
+
+	dev_dbg(component->dev,
+		"%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
+		__func__, micb_num, wcd9378->micb_ref[micb_index],
+		wcd9378->pullup_ref[micb_index]);
+
+done:
+	mutex_unlock(&wcd9378->micb_lock);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
+
+static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
+{
+	int ret = 0;
+	uint8_t devnum = 0;
+	int num_retry = NUM_ATTEMPTS;
+
+	do {
+		/* retry after 4ms */
+		usleep_range(4000, 4010);
+		ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
+	} while (ret && --num_retry);
+
+	if (ret)
+		dev_err(&swr_dev->dev,
+			"%s get devnum %d for dev addr %llx failed\n",
+			__func__, devnum, swr_dev->addr);
+
+	swr_dev->dev_num = devnum;
+	return 0;
+}
+
+static bool get_usbc_hs_status(struct snd_soc_component *component,
+			struct wcd_mbhc_config *mbhc_cfg)
+{
+	if (mbhc_cfg->enable_usbc_analog) {
+		if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
+			& 0x20))
+			return true;
+	}
+	return false;
+}
+
+int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
+					struct notifier_block *nblock,
+					bool enable)
+{
+	struct wcd9378_priv *wcd9378_priv = NULL;
+
+	if (component == NULL) {
+		pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd9378_priv = snd_soc_component_get_drvdata(component);
+	wcd9378_priv->notify_swr_dmic = enable;
+	if (enable)
+		return blocking_notifier_chain_register(&wcd9378_priv->notifier,
+							nblock);
+	else
+		return blocking_notifier_chain_unregister(
+				&wcd9378_priv->notifier, nblock);
+}
+EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
+
+/*TBD: NEED TO CHECK AND UPDATE*/
+static int wcd9378_event_notify(struct notifier_block *block,
+				unsigned long val,
+				void *data)
+{
+	u16 event = (val & 0xffff);
+	int ret = 0;
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
+	struct snd_soc_component *component = wcd9378->component;
+	struct wcd_mbhc *mbhc;
+	int rx_clk_type;
+
+	switch (event) {
+	case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
+		if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
+			snd_soc_component_update_bits(component,
+					WCD9378_ANA_TX_CH2, 0x40, 0x00);
+			set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
+			clear_bit(WCD_ADC1, &wcd9378->status_mask);
+		}
+		if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
+			snd_soc_component_update_bits(component,
+					WCD9378_ANA_TX_CH2, 0x20, 0x00);
+			set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
+			clear_bit(WCD_ADC2, &wcd9378->status_mask);
+		}
+		if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
+			snd_soc_component_update_bits(component,
+					WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
+			set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
+			clear_bit(WCD_ADC3, &wcd9378->status_mask);
+		}
+		break;
+	case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
+		snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
+					0xC0, 0x00);
+		snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
+					0x80, 0x00);
+		snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
+					0x80, 0x00);
+		break;
+	case BOLERO_SLV_EVT_SSR_DOWN:
+		wcd9378->dev_up = false;
+		if (wcd9378->notify_swr_dmic)
+			blocking_notifier_call_chain(&wcd9378->notifier,
+						WCD9378_EVT_SSR_DOWN,
+						NULL);
+		wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
+		mbhc = &wcd9378->mbhc->wcd_mbhc;
+		wcd9378->usbc_hs_status = get_usbc_hs_status(component,
+						mbhc->mbhc_cfg);
+		wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
+		wcd9378_reset_low(wcd9378->dev);
+		break;
+	case BOLERO_SLV_EVT_SSR_UP:
+		wcd9378_reset(wcd9378->dev);
+		/* allow reset to take effect */
+		usleep_range(10000, 10010);
+
+		wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
+		wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
+
+		wcd9378_init_reg(component);
+		regcache_mark_dirty(wcd9378->regmap);
+		regcache_sync(wcd9378->regmap);
+		/* Initialize MBHC module */
+		mbhc = &wcd9378->mbhc->wcd_mbhc;
+		ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
+		if (ret) {
+			dev_err(component->dev, "%s: mbhc initialization failed\n",
+				__func__);
+		} else {
+			wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
+		}
+		wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
+		wcd9378->dev_up = true;
+		if (wcd9378->notify_swr_dmic)
+			blocking_notifier_call_chain(&wcd9378->notifier,
+						WCD9378_EVT_SSR_UP,
+						NULL);
+		if (wcd9378->usbc_hs_status)
+			mdelay(500);
+		break;
+	case BOLERO_SLV_EVT_CLK_NOTIFY:
+		snd_soc_component_update_bits(component,
+				WCD9378_TOP_CLK_CFG, 0x06,
+				((val >> 0x10) << 0x01));
+
+		rx_clk_type = (val >> 0x10);
+
+		switch (rx_clk_type) {
+		case RX_CLK_12P288MHZ:
+			wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
+			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			break;
+		case RX_CLK_11P2896MHZ:
+			wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
+			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			break;
+		default:
+			wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
+			wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
+			break;
+		}
+		dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
+				__func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
+
+		break;
+	default:
+		dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
+		break;
+	}
+	return 0;
+}
+
+static int wcd9378_wakeup(void *handle, bool enable)
+{
+	struct wcd9378_priv *priv;
+	int ret = 0;
+
+	if (!handle) {
+		pr_err("%s: NULL handle\n", __func__);
+		return -EINVAL;
+	}
+	priv = (struct wcd9378_priv *)handle;
+	if (!priv->tx_swr_dev) {
+		pr_err("%s: tx swr dev is NULL\n", __func__);
+		return -EINVAL;
+	}
+	mutex_lock(&priv->wakeup_lock);
+	if (enable)
+		ret = swr_device_wakeup_vote(priv->tx_swr_dev);
+	else
+		ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
+	mutex_unlock(&priv->wakeup_lock);
+
+	return ret;
+}
+
+static inline int wcd9378_tx_path_get(const char *wname,
+				      unsigned int *path_num)
+{
+	int ret = 0;
+	char *widget_name = NULL;
+	char *w_name = NULL;
+	char *path_num_char = NULL;
+	char *path_name = NULL;
+
+	widget_name = kstrndup(wname, 9, GFP_KERNEL);
+	if (!widget_name)
+		return -EINVAL;
+
+	w_name = widget_name;
+
+	path_name = strsep(&widget_name, " ");
+	if (!path_name) {
+		pr_err("%s: Invalid widget name = %s\n",
+			__func__, widget_name);
+		ret = -EINVAL;
+		goto err;
+	}
+	path_num_char = strpbrk(path_name, "0123");
+	if (!path_num_char) {
+		pr_err("%s: tx path index not found\n",
+			__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	ret = kstrtouint(path_num_char, 10, path_num);
+	if (ret < 0)
+		pr_err("%s: Invalid tx path = %s\n",
+			__func__, w_name);
+
+err:
+	kfree(w_name);
+	return ret;
+}
+
+static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = NULL;
+	int ret = 0;
+	unsigned int path = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+
+	if (!wcd9378)
+		return -EINVAL;
+
+	ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
+	if (ret < 0)
+		return ret;
+
+	ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
+
+	return 0;
+}
+
+static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = NULL;
+	u32 mode_val;
+	unsigned int path = 0;
+	int ret = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd9378  = snd_soc_component_get_drvdata(component);
+
+	if (!wcd9378)
+		return -EINVAL;
+
+	ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
+	if (ret)
+		return ret;
+
+	mode_val = ucontrol->value.enumerated.item[0];
+
+	dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
+
+	wcd9378->tx_mode[path] = mode_val;
+
+	return 0;
+}
+
+static int wcd9378_sys_usage_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	u32 sys_usage_val = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	sys_usage_val = (snd_soc_component_read(component, WCD9378_SYS_USAGE_CTRL) &
+				WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK);
+
+	ucontrol->value.integer.value[0] = sys_usage_val;
+	return 0;
+}
+
+static int wcd9378_sys_usage_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = NULL;
+	u32 sys_usage_val = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd9378  = snd_soc_component_get_drvdata(component);
+	if (!wcd9378)
+		return -EINVAL;
+
+	sys_usage_val = ucontrol->value.enumerated.item[0];
+	if (sys_usage_val >= WCD_SYS_USAGE_MAX) {
+		dev_err(component->dev, "%s: unsupport sys_usage_val: %d\n",
+			__func__, sys_usage_val);
+		return -EINVAL;
+	}
+
+	snd_soc_component_update_bits(component,
+			WCD9378_SYS_USAGE_CTRL,
+			WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
+			sys_usage_val);
+
+	wcd9378->sys_usage = sys_usage_val;
+	dev_dbg(component->dev, "%s: sys_usage_val: %d\n", __func__, wcd9378->sys_usage);
+
+	return 0;
+}
+
+static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	u32 loopback_mode = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
+				WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
+
+	ucontrol->value.integer.value[0] = loopback_mode;
+	return 0;
+}
+
+static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	u32 loopback_mode = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	loopback_mode = ucontrol->value.enumerated.item[0];
+
+	snd_soc_component_update_bits(component,
+			WCD9378_LOOP_BACK_MODE,
+			WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
+			loopback_mode);
+
+	dev_dbg(component->dev, "%s: loopback_mode: %d\n",
+			__func__, loopback_mode);
+	return 0;
+}
+
+static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	u32 aux_dsm_in = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
+				WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
+
+	ucontrol->value.integer.value[0] = aux_dsm_in;
+	return 0;
+}
+
+static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	u32 aux_dsm_in = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	aux_dsm_in = ucontrol->value.enumerated.item[0];
+
+	snd_soc_component_update_bits(component,
+			WCD9378_LB_IN_SEL_CTL,
+			WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
+			aux_dsm_in);
+
+	dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
+			__func__, aux_dsm_in);
+	return 0;
+}
+
+static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	u32 hph_dsm_in = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
+				WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
+
+	ucontrol->value.integer.value[0] = hph_dsm_in;
+	return 0;
+}
+
+static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	u32 hph_dsm_in = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	hph_dsm_in = ucontrol->value.enumerated.item[0];
+
+	snd_soc_component_update_bits(component,
+			WCD9378_LB_IN_SEL_CTL,
+			WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
+			hph_dsm_in);
+
+	dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
+			__func__, hph_dsm_in);
+	return 0;
+}
+
+static inline int wcd9378_simple_mic_num_get(const char *wname,
+				      unsigned int *sm_num)
+{
+	int ret = 0;
+	char *widget_name = NULL;
+	char *w_name = NULL;
+	char *sm_num_char = NULL;
+	char *sm_name = NULL;
+
+	widget_name = kstrndup(wname, 9, GFP_KERNEL);
+	if (!widget_name)
+		return -EINVAL;
+
+	w_name = widget_name;
+
+	sm_name = strsep(&widget_name, " ");
+	if (!sm_name) {
+		pr_err("%s: Invalid widget name = %s\n",
+			__func__, widget_name);
+		ret = -EINVAL;
+		goto err;
+	}
+	sm_num_char = strpbrk(sm_name, "0123");
+	if (!sm_num_char) {
+		pr_err("%s: simple mic index not found\n",
+			__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	ret = kstrtouint(sm_num_char, 10, sm_num);
+	if (ret < 0)
+		pr_err("%s: Invalid micb num = %s\n",
+			__func__, w_name);
+
+err:
+	kfree(w_name);
+	return ret;
+}
+
+static int wcd9378_mb_sel_get(struct snd_kcontrol *kcontrol,
+			       struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = NULL;
+	int ret = 0;
+	unsigned int sm_num = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+
+	if (!wcd9378)
+		return -EINVAL;
+
+	ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
+	if (ret < 0)
+		return ret;
+
+	ucontrol->value.integer.value[0] = wcd9378->micb_sel[sm_num];
+
+	return 0;
+
+}
+
+static int wcd9378_mb_sel_put(struct snd_kcontrol *kcontrol,
+			       struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = NULL;
+	u32 mode_val;
+	unsigned int sm_num = 0;
+	int ret = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd9378  = snd_soc_component_get_drvdata(component);
+
+	if (!wcd9378)
+		return -EINVAL;
+
+	ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
+	if (ret)
+		return ret;
+
+	mode_val = ucontrol->value.enumerated.item[0];
+
+	dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
+
+	wcd9378->micb_sel[sm_num] = mode_val;
+
+	return 0;
+}
+
+/*TBD: NEED CHECK THE LOGIC*/
+static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	u16 offset = ucontrol->value.enumerated.item[0];
+	u32 temp = 0;
+
+	temp = 0x00 - offset * 0x180;
+
+	wcd9378->hph_gain = (u16)(temp & 0xffff);
+
+	dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
+	return 0;
+}
+
+static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	u32 temp = 0;
+	u16 offset =  0;
+
+	temp = 0 - wcd9378->hph_gain;
+
+	offset = (u16)(temp & 0xffff);
+
+	offset /= 0x180;
+	ucontrol->value.enumerated.item[0] = offset;
+
+	dev_dbg(component->dev, "%s： offset is 0x%0x\n", __func__, offset);
+	return 0;
+}
+
+
+static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+
+	if (ucontrol->value.enumerated.item[0])
+		wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
+	else
+		wcd9378->rx2_clk_mode = RX2_HP_MODE;
+	return 1;
+}
+
+static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
+
+	return 0;
+}
+
+static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
+		return 0;
+
+	wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
+
+	return 1;
+}
+
+/* wcd9378_codec_get_dev_num - returns swr device number
+ * @component: Codec instance
+ *
+ * Return: swr device number on success or negative error
+ * code on failure.
+ */
+int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+	if (!wcd9378 || !wcd9378->rx_swr_dev) {
+		pr_err("%s: wcd9378 component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	return wcd9378->rx_swr_dev->dev_num;
+}
+EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
+
+static int wcd9378_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 =
+				snd_soc_component_get_drvdata(component);
+
+	if (wcd9378->comp1_enable) {
+		dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
+		return -EINVAL;
+	}
+
+	snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
+				      WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
+				      ucontrol->value.integer.value[0]);
+
+	return 1;
+}
+
+static int wcd9378_aux_pa_put_gain(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 =
+				snd_soc_component_get_drvdata(component);
+
+	if (wcd9378->comp1_enable) {
+		dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
+		return -EINVAL;
+	}
+
+	snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
+				      WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
+				      ucontrol->value.integer.value[0]);
+
+	return 1;
+}
+
+static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	bool hphr;
+	struct soc_multi_mixer_control *mc;
+
+	mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
+	hphr = mc->shift;
+
+	ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
+						wcd9378->comp1_enable;
+	return 0;
+}
+
+static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+	int value = ucontrol->value.integer.value[0];
+	bool hphr;
+	struct soc_multi_mixer_control *mc;
+
+	mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
+	hphr = mc->shift;
+	if (hphr)
+		wcd9378->comp2_enable = value;
+	else
+		wcd9378->comp1_enable = value;
+
+	dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
+
+	return 0;
+}
+
+static int wcd9378_get_va_amic_switch(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = wcd9378->va_amic_en;
+
+	return 0;
+}
+
+static int wcd9378_set_va_amic_switch(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+	int value = ucontrol->value.integer.value[0];
+
+	wcd9378->va_amic_en = value;
+
+	return 0;
+}
+
+static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
+					 struct snd_kcontrol *kcontrol,
+					 int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	struct wcd9378_pdata *pdata = NULL;
+	int ret = 0;
+
+	pdata = dev_get_platdata(wcd9378->dev);
+
+	if (!pdata) {
+		dev_err(component->dev, "%s: pdata is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
+					wcd9378->supplies,
+					pdata->regulator,
+					pdata->num_supplies,
+					"cdc-vdd-buck"))
+		return 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
+			dev_dbg(component->dev,
+				"%s: buck already in enabled state\n",
+				__func__);
+			clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
+			return 0;
+		}
+		ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
+						wcd9378->supplies,
+						pdata->regulator,
+						pdata->num_supplies,
+						"cdc-vdd-buck");
+		if (ret == -EINVAL) {
+			dev_err(component->dev, "%s: vdd buck is not enabled\n",
+				__func__);
+			return ret;
+		}
+		clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
+		/*
+		 * 200us sleep is required after LDO is enabled as per
+		 * HW requirement
+		 */
+		usleep_range(200, 250);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
+		break;
+	}
+	return 0;
+}
+
+const char * const tx_master_ch_text[] = {
+	"ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
+	"SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
+	"SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
+	"SWRM_PCM_IN",
+};
+
+const struct soc_enum tx_master_ch_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
+					tx_master_ch_text);
+
+static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
+{
+	u8 ch_type = 0;
+
+	if (strnstr(wname, "ADC1", sizeof("ADC1")))
+		ch_type = ADC1;
+	else if (strnstr(wname, "ADC2", sizeof("ADC2")))
+		ch_type = ADC2;
+	else if (strnstr(wname, "ADC3", sizeof("ADC3")))
+		ch_type = ADC3;
+	else if (strnstr(wname, "ADC4", sizeof("ADC4")))
+		ch_type = ADC4;
+	else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
+		ch_type = DMIC0;
+	else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
+		ch_type = DMIC1;
+	else if (strnstr(wname, "MBHC", sizeof("MBHC")))
+		ch_type = MBHC;
+	else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
+		ch_type = DMIC2;
+	else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
+		ch_type = DMIC3;
+	else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
+		ch_type = DMIC4;
+	else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
+		ch_type = DMIC5;
+	else
+		pr_err("%s: port name: %s is not listed\n", __func__, wname);
+
+	if (ch_type)
+		*ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
+	else
+		*ch_idx = -EINVAL;
+}
+
+static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = NULL;
+	int slave_ch_idx = -EINVAL;
+
+	if (component == NULL)
+		return -EINVAL;
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+	if (wcd9378 == NULL)
+		return -EINVAL;
+
+	wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
+	if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
+		return -EINVAL;
+
+	ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
+			wcd9378->tx_master_ch_map[slave_ch_idx]);
+
+	return 0;
+}
+
+static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = NULL;
+	int slave_ch_idx = -EINVAL, idx = 0;
+
+	if (component == NULL)
+		return -EINVAL;
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+	if (wcd9378 == NULL)
+		return -EINVAL;
+
+	wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
+
+	if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
+		return -EINVAL;
+
+	dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
+	dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
+			__func__, ucontrol->value.enumerated.item[0]);
+
+	idx = ucontrol->value.enumerated.item[0];
+	if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
+		return -EINVAL;
+
+	wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
+	return 0;
+}
+
+static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
+
+	return 0;
+}
+
+static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	wcd9378->bcs_dis = ucontrol->value.integer.value[0];
+
+	return 0;
+}
+
+static const char * const sys_usage_text[] = {
+	"NOSJ_SA_STEREO_3SM", "SJ_SA_AUX_2SM", "NOSJ_SA_STEREO_3SM_1HDR",
+	"SJ_SA_AUX_2SM_1HDR", "NOSJ_SA_EAR_3SM", "SJ_SA_EAR_2SM", "NOSJ_SA_EAR_3SM_1HDR",
+	"SJ_SA_EAR_2SM_1HDR", "SJ_1HDR_SA_AUX_1SM", "SJ_1HDR_SA_EAR_1SM",
+	"SJ_SA_STEREO_2SM", "SJ_NOMIC_SA_EAR_3SM", "SJ_NOMIC_SA_AUX_3SM",
+};
+
+static const struct soc_enum sys_usage_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sys_usage_text),
+			    sys_usage_text);
+
+static const char * const loopback_mode_text[] = {
+	"NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
+};
+
+static const struct soc_enum loopback_mode_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
+			    loopback_mode_text);
+
+static const char * const aux_dsm_text[] = {
+	"TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
+};
+
+static const struct soc_enum aux_dsm_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
+			    aux_dsm_text);
+
+static const char * const hph_dsm_text[] = {
+	"HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
+};
+
+static const struct soc_enum hph_dsm_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
+			    hph_dsm_text);
+
+static const char * const tx_mode_mux_text[] = {
+	"ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
+};
+
+static const struct soc_enum tx_mode_mux_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
+			    tx_mode_mux_text);
+
+static const char * const micb_sel_text[] = {
+	"NO_MICB", "MICB1", "MICB2", "MICB3",
+};
+
+static const struct soc_enum sm_micb_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micb_sel_text),
+			    micb_sel_text);
+
+static const char * const rx2_mode_text[] = {
+	"HP", "NORMAL",
+};
+
+static const struct soc_enum rx2_mode_enum =
+		SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
+				    rx2_mode_text);
+
+static const char * const rx_hph_mode_mux_text[] = {
+	"CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
+	"CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
+};
+
+static const struct soc_enum rx_hph_mode_mux_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
+			    rx_hph_mode_mux_text);
+
+static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
+	SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
+		wcd9378_get_compander, wcd9378_set_compander),
+	SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
+		wcd9378_get_compander, wcd9378_set_compander),
+	SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
+		wcd9378_bcs_get, wcd9378_bcs_put),
+
+	SOC_SINGLE_EXT("VA_AMIC_MIXER Switch", SND_SOC_NOPM, 0, 1, 0,
+		wcd9378_get_va_amic_switch, wcd9378_set_va_amic_switch),
+
+	SOC_ENUM_EXT("SYS_USAGE Mode", sys_usage_enum,
+		     wcd9378_sys_usage_get, wcd9378_sys_usage_put),
+
+	SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
+		     wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
+	SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
+		     wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
+	SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
+		     wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
+
+	SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
+		     wcd9378_tx_mode_get, wcd9378_tx_mode_put),
+	SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
+		     wcd9378_tx_mode_get, wcd9378_tx_mode_put),
+	SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
+		     wcd9378_tx_mode_get, wcd9378_tx_mode_put),
+
+	SOC_ENUM_EXT("SM0 MICB SEL", sm_micb_enum,
+		     wcd9378_mb_sel_get, wcd9378_mb_sel_put),
+	SOC_ENUM_EXT("SM1 MICB SEL", sm_micb_enum,
+		     wcd9378_mb_sel_get, wcd9378_mb_sel_put),
+	SOC_ENUM_EXT("SM2 MICB SEL", sm_micb_enum,
+		     wcd9378_mb_sel_get, wcd9378_mb_sel_put),
+
+	SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
+		       NULL, wcd9378_rx2_mode_put),
+	SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
+		     wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
+	SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
+		       wcd9378_hph_get_gain, wcd9378_hph_put_gain),
+	WCD9378_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD9378_ANA_EAR_COMPANDER_CTL,
+		       2, 0x10, 0, ear_pa_gain),
+	WCD9378_AUX_PA_GAIN_TLV("AUX_PA Volume", WCD9378_AUX_INT_MISC,
+		       0, 0x8, 0, aux_pa_gain),
+
+	SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
+			analog_gain),
+	SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
+			analog_gain),
+	SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
+			analog_gain),
+
+	SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
+			wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
+};
+
+static const struct snd_kcontrol_new dmic1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic2_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic3_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic4_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic5_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic6_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const char * const adc1_mux_text[] = {
+	"CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
+};
+
+static const char * const adc2_mux_text[] = {
+	"CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
+};
+
+static const char * const adc3_mux_text[] = {
+	"CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC2", "CH3_AMIC3", "CH3_AMIC4"
+};
+
+static const char * const ear_mux_text[] = {
+	"RX2", "RX0"
+};
+
+static const char * const aux_mux_text[] = {
+	"RX2", "RX1"
+};
+
+static const struct soc_enum adc1_enum =
+		SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
+				WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
+				ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
+
+static const struct soc_enum adc2_enum =
+		SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
+				WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
+				ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
+
+static const struct soc_enum adc3_enum =
+		SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
+				WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
+				ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
+
+static const struct soc_enum ear_enum =
+		SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
+				WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT,
+				ARRAY_SIZE(ear_mux_text), ear_mux_text);
+
+static const struct soc_enum aux_enum =
+		SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
+				WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT,
+				ARRAY_SIZE(aux_mux_text), aux_mux_text);
+
+static const struct snd_kcontrol_new tx_adc1_mux =
+	SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
+
+static const struct snd_kcontrol_new tx_adc2_mux =
+	SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
+
+static const struct snd_kcontrol_new tx_adc3_mux =
+	SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
+
+static const struct snd_kcontrol_new ear_mux =
+	SOC_DAPM_ENUM("EAR Mux", ear_enum);
+
+static const struct snd_kcontrol_new aux_mux =
+	SOC_DAPM_ENUM("AUX Mux", aux_enum);
+
+static const struct snd_kcontrol_new dac1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dac2_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new ear_mixer_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new aux_mixer_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new hphl_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new hphr_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new rx0_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new rx1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
+
+	/*input widgets*/
+	SND_SOC_DAPM_INPUT("AMIC1"),
+	SND_SOC_DAPM_INPUT("AMIC2"),
+	SND_SOC_DAPM_INPUT("AMIC3"),
+	SND_SOC_DAPM_INPUT("AMIC4"),
+
+	SND_SOC_DAPM_INPUT("IN1_HPHL"),
+	SND_SOC_DAPM_INPUT("IN2_HPHR"),
+	SND_SOC_DAPM_INPUT("IN3_AUX"),
+
+	/*tx widgets*/
+	SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
+				NULL, 0, wcd9378_tx_sequencer_enable,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
+				NULL, 0, wcd9378_tx_sequencer_enable,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
+				NULL, 0, wcd9378_tx_sequencer_enable,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
+				&tx_adc1_mux),
+	SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
+				&tx_adc2_mux),
+	SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
+				&tx_adc3_mux),
+
+	SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
+				wcd9378_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
+				wcd9378_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
+				wcd9378_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
+				wcd9378_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
+				wcd9378_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
+				wcd9378_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	/*rx widgets*/
+	SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
+			   wcd9378_codec_hphl_dac_event,
+			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
+			   wcd9378_codec_hphr_dac_event,
+			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd9378_hph_sequencer_enable,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd9378_codec_enable_hphl_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd9378_codec_enable_hphr_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
+				NULL, 0, wcd9378_sa_sequencer_enable,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
+				wcd9378_codec_ear_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
+				wcd9378_codec_aux_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd9378_codec_enable_ear_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd9378_codec_enable_aux_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
+				wcd9378_codec_enable_vdd_buck,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
+				wcd9378_enable_clsh,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
+				0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
+				wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
+				0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
+				wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
+				0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
+				wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
+				0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
+				wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
+				0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
+				wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
+				0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
+				wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+
+	/* rx mixer widgets*/
+	SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
+	SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
+	SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
+			ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
+	SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
+			aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
+	SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
+			dac1_switch, ARRAY_SIZE(dac1_switch)),
+	SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
+			dac2_switch, ARRAY_SIZE(dac2_switch)),
+	SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
+			hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
+	SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
+			hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
+
+	/*output widgets tx*/
+	SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
+
+	/*output widgets rx*/
+	SND_SOC_DAPM_OUTPUT("EAR"),
+	SND_SOC_DAPM_OUTPUT("AUX"),
+	SND_SOC_DAPM_OUTPUT("HPHL"),
+	SND_SOC_DAPM_OUTPUT("HPHR"),
+};
+
+static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
+/*ADC-1 (channel-1)*/
+	{"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
+	{"TX0 SEQUENCER", NULL, "ADC1 MUX"},
+	{"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
+	{"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
+	{"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
+	{"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
+
+/*ADC-2 (channel-2)*/
+	{"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
+	{"TX1 SEQUENCER", NULL, "ADC2 MUX"},
+	{"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
+	{"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
+	{"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
+	{"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
+
+/*ADC-3 (channel-3)*/
+	{"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
+	{"TX2 SEQUENCER", NULL, "ADC3 MUX"},
+	{"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
+	{"ADC3 MUX", "CH3_AMIC2", "AMIC2"},
+	{"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
+	{"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
+
+	{"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
+	{"DMIC1_MIXER", "Switch", "DMIC1"},
+
+	{"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
+	{"DMIC2_MIXER", "Switch", "DMIC2"},
+
+	{"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
+	{"DMIC3_MIXER", "Switch", "DMIC3"},
+
+	{"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
+	{"DMIC4_MIXER", "Switch", "DMIC4"},
+
+	{"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
+	{"DMIC5_MIXER", "Switch", "DMIC5"},
+
+	{"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
+	{"DMIC6_MIXER", "Switch", "DMIC6"},
+
+/*Headphone playback*/
+	{"IN1_HPHL", NULL, "VDD_BUCK"},
+	{"IN1_HPHL", NULL, "CLS_H_PORT"},
+	{"HPH SEQUENCER", NULL, "IN1_HPHL"},
+	{"RDAC1", NULL, "HPH SEQUENCER"},
+	{"HPHL_RDAC", "Switch", "RDAC1"},
+	{"HPHL PGA", NULL, "HPHL_RDAC"},
+	{"HPHL", NULL, "HPHL PGA"},
+
+	{"IN2_HPHR", NULL, "VDD_BUCK"},
+	{"IN2_HPHR", NULL, "CLS_H_PORT"},
+	{"HPH SEQUENCER", NULL, "IN2_HPHR"},
+	{"RDAC2", NULL, "HPH SEQUENCER"},
+	{"HPHR_RDAC", "Switch", "RDAC2"},
+	{"HPHR PGA", NULL, "HPHR_RDAC"},
+	{"HPHR", NULL, "HPHR PGA"},
+
+/*Amplier playback*/
+	{"IN3_AUX", NULL, "VDD_BUCK"},
+	{"IN3_AUX", NULL, "CLS_H_PORT"},
+	{"EAR_MUX", "RX0", "IN1_HPHL"},
+	{"EAR_MUX", "RX2", "IN3_AUX"},
+	{"DAC1", "Switch", "EAR_MUX"},
+	{"EAR_RDAC", NULL, "DAC1"},
+	{"SA SEQUENCER", NULL, "EAR_RDAC"},
+	{"EAR_MIXER", "Switch", "SA SEQUENCER"},
+	{"EAR PGA", NULL, "EAR_MIXER"},
+	{"EAR", NULL, "EAR PGA"},
+
+	{"AUX_MUX", "RX1", "IN2_HPHR"},
+	{"AUX_MUX", "RX2", "IN3_AUX"},
+	{"DAC2", "Switch", "AUX_MUX"},
+	{"AUX_RDAC", NULL, "DAC2"},
+	{"SA SEQUENCER", NULL, "AUX_RDAC"},
+	{"AUX_MIXER", "Switch", "SA SEQUENCER",},
+	{"AUX PGA", NULL, "AUX_MIXER"},
+	{"AUX", NULL, "AUX PGA"},
+};
+
+static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
+				   void *file_private_data,
+				   struct file *file,
+				   char __user *buf, size_t count,
+				   loff_t pos)
+{
+	struct wcd9378_priv *priv;
+	char buffer[WCD9378_VERSION_ENTRY_SIZE];
+	int len = 0;
+
+	priv = (struct wcd9378_priv *) entry->private_data;
+	if (!priv) {
+		pr_err("%s: wcd9378 priv is null\n", __func__);
+		return -EINVAL;
+	}
+
+	switch (priv->version) {
+	case WCD9378_VERSION_1_0:
+		len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
+		break;
+	default:
+		len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
+	}
+
+	return simple_read_from_buffer(buf, count, &pos, buffer, len);
+}
+
+static struct snd_info_entry_ops wcd9378_info_ops = {
+	.read = wcd9378_version_read,
+};
+
+/*
+ * wcd9378_info_create_codec_entry - creates wcd9378 module
+ * @codec_root: The parent directory
+ * @component: component instance
+ *
+ * Creates wcd9378 module, version entry under the given
+ * parent directory.
+ *
+ * Return: 0 on success or negative error code on failure.
+ */
+int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
+				   struct snd_soc_component *component)
+{
+	struct snd_info_entry *version_entry;
+	struct wcd9378_priv *priv;
+	struct snd_soc_card *card;
+
+	if (!codec_root || !component)
+		return -EINVAL;
+
+	priv = snd_soc_component_get_drvdata(component);
+	if (priv->entry) {
+		dev_dbg(priv->dev,
+			"%s:wcd9378 module already created\n", __func__);
+		return 0;
+	}
+	card = component->card;
+
+	priv->entry = snd_info_create_module_entry(codec_root->module,
+					     "wcd9378", codec_root);
+	if (!priv->entry) {
+		dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
+			__func__);
+		return -ENOMEM;
+	}
+	priv->entry->mode = S_IFDIR | 0555;
+	if (snd_info_register(priv->entry) < 0) {
+		snd_info_free_entry(priv->entry);
+		return -ENOMEM;
+	}
+
+	version_entry = snd_info_create_card_entry(card->snd_card,
+						   "version",
+						   priv->entry);
+	if (!version_entry) {
+		dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
+			__func__);
+		snd_info_free_entry(priv->entry);
+		return -ENOMEM;
+	}
+
+	version_entry->private_data = priv;
+	version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
+	version_entry->content = SNDRV_INFO_CONTENT_DATA;
+	version_entry->c.ops = &wcd9378_info_ops;
+
+	if (snd_info_register(version_entry) < 0) {
+		snd_info_free_entry(version_entry);
+		snd_info_free_entry(priv->entry);
+		return -ENOMEM;
+	}
+	priv->version_entry = version_entry;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
+
+static void wcd9378_class_load(struct snd_soc_component *component)
+{
+	/*SMP AMP CLASS LOADING*/
+	snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
+			WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
+	usleep_range(20000, 20010);
+
+	snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
+			WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
+
+	/*SMP JACK CLASS LOADING*/
+	snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
+			WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
+	usleep_range(30000, 30010);
+
+	snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
+			WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
+
+	snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
+			WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
+
+	/*SMP MIC0 CLASS LOADING*/
+	snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
+			WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
+	usleep_range(5000, 5010);
+
+	snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
+			WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
+
+	/*SMP MIC1 CLASS LOADING*/
+	snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
+			WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
+	usleep_range(5000, 5010);
+
+	snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
+			WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
+
+	/*SMP MIC2 CLASS LOADING*/
+	snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
+			WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
+	usleep_range(5000, 5010);
+
+	snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
+			WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
+}
+
+static int wcd9378_sys_usage_set(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	int ret = 0;
+
+	ret = of_property_read_u32(wcd9378->dev->of_node, "qcom,wcd-sys-usage",
+			&wcd9378->sys_usage);
+	if (ret) {
+		dev_dbg(component->dev, "%s:sys_usage read failed, use default\n",
+			__func__);
+		wcd9378->sys_usage = NOSJ_SA_STEREO_3SM;
+	} else {
+		if (wcd9378->sys_usage >= WCD_SYS_USAGE_MAX) {
+			dev_err(component->dev, "%s: invalid sys-usage, pls check\n", __func__);
+			return -EINVAL;
+		}
+	}
+
+	snd_soc_component_update_bits(component,
+			WCD9378_SYS_USAGE_CTRL,
+			WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
+			wcd9378->sys_usage);
+
+	return 0;
+
+}
+
+static void wcd9378_micb_value_convert(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+	struct wcd9378_pdata *pdata =
+			dev_get_platdata(wcd9378->dev);
+	struct wcd9378_micbias_setting *mb = &pdata->micbias;
+
+	mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
+						mb->micb1_mv, MIC_BIAS_1);
+
+	mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
+						mb->micb2_mv, MIC_BIAS_2);
+
+	mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
+						mb->micb3_mv, MIC_BIAS_3);
+
+	pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
+			mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
+}
+
+static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 =
+			snd_soc_component_get_drvdata(component);
+
+	if (snd_soc_component_read(component,
+			WCD9378_EFUSE_REG_29)
+			& WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
+		if (((snd_soc_component_read(component,
+				WCD9378_EFUSE_REG_29) &
+				WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
+			return true;
+		else
+			return false;
+	} else {
+		if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
+				& WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
+			return true;
+		else
+			return false;
+	}
+
+	return 0;
+}
+
+static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+	struct snd_soc_dapm_context *dapm =
+			snd_soc_component_get_dapm(component);
+	int ret = -EINVAL;
+
+	wcd9378 = snd_soc_component_get_drvdata(component);
+	if (!wcd9378)
+		return -EINVAL;
+
+	wcd9378->component = component;
+	snd_soc_component_init_regmap(component, wcd9378->regmap);
+
+	devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
+
+	ret = wcd9378_wcd_mode_check(component);
+	if (!ret) {
+		dev_err(component->dev, "wcd mode check failed\n");
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
+	if (ret) {
+		pr_err("%s: mbhc initialization failed\n", __func__);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	dev_dbg(component->dev, "%s: mbhc init done\n", __func__);
+
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
+	snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
+	snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
+	snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
+	snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
+	snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
+	snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
+	snd_soc_dapm_ignore_suspend(dapm, "EAR");
+	snd_soc_dapm_ignore_suspend(dapm, "AUX");
+	snd_soc_dapm_ignore_suspend(dapm, "HPHL");
+	snd_soc_dapm_ignore_suspend(dapm, "HPHR");
+	snd_soc_dapm_sync(dapm);
+
+	wcd_cls_h_init(&wcd9378->clsh_info);
+
+	wcd9378_init_reg(component);
+
+	wcd9378_sys_usage_set(component);
+
+	wcd9378_class_load(component);
+
+	wcd9378_micb_value_convert(component);
+
+	wcd9378->version = WCD9378_VERSION_1_0;
+       /* Register event notifier */
+	wcd9378->nblock.notifier_call = wcd9378_event_notify;
+	if (wcd9378->register_notifier) {
+		ret = wcd9378->register_notifier(wcd9378->handle,
+						&wcd9378->nblock,
+						true);
+		if (ret) {
+			dev_err(component->dev,
+				"%s: Failed to register notifier %d\n",
+				__func__, ret);
+			return ret;
+		}
+	}
+exit:
+	return ret;
+}
+
+static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	if (!wcd9378) {
+		dev_err(component->dev, "%s: wcd9378 is already NULL\n",
+			__func__);
+		return;
+	}
+	if (wcd9378->register_notifier)
+		wcd9378->register_notifier(wcd9378->handle,
+						&wcd9378->nblock,
+						false);
+}
+
+static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	if (!wcd9378)
+		return 0;
+	wcd9378->dapm_bias_off = true;
+	return 0;
+}
+
+static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
+{
+	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
+
+	if (!wcd9378)
+		return 0;
+	wcd9378->dapm_bias_off = false;
+	return 0;
+}
+
+static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
+	.name = WCD9378_DRV_NAME,
+	.probe = wcd9378_soc_codec_probe,
+	.remove = wcd9378_soc_codec_remove,
+	.controls = wcd9378_snd_controls,
+	.num_controls = ARRAY_SIZE(wcd9378_snd_controls),
+	.dapm_widgets = wcd9378_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
+	.dapm_routes = wcd9378_audio_map,
+	.num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
+	.suspend =  wcd9378_soc_codec_suspend,
+	.resume = wcd9378_soc_codec_resume,
+};
+
+static int wcd9378_reset(struct device *dev)
+{
+	struct wcd9378_priv *wcd9378 = NULL;
+	int rc = 0;
+	int value = 0;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd9378 = dev_get_drvdata(dev);
+	if (!wcd9378)
+		return -EINVAL;
+
+	if (!wcd9378->rst_np) {
+		dev_err(dev, "%s: reset gpio device node not specified\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
+	if (value > 0)
+		return 0;
+
+	rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
+	if (rc) {
+		dev_err(dev, "%s: wcd sleep state request fail!\n",
+				__func__);
+		return rc;
+	}
+	/* 20us sleep required after pulling the reset gpio to LOW */
+	usleep_range(20, 30);
+
+	rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
+	if (rc) {
+		dev_err(dev, "%s: wcd active state request fail!\n",
+				__func__);
+		return rc;
+	}
+	/* 20us sleep required after pulling the reset gpio to HIGH */
+	usleep_range(20, 30);
+
+	return rc;
+}
+
+static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
+					u32 *val)
+{
+	int rc = 0;
+
+	rc = of_property_read_u32(dev->of_node, name, val);
+	if (rc)
+		dev_err(dev, "%s: Looking up %s property in node %s failed\n",
+			__func__, name, dev->of_node->full_name);
+
+	return rc;
+}
+
+static void wcd9378_dt_parse_micbias_info(struct device *dev,
+					struct wcd9378_micbias_setting *mb)
+{
+	u32 prop_val = 0;
+	int rc = 0;
+
+	/* MB1 */
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
+				    NULL)) {
+		rc = wcd9378_read_of_property_u32(dev,
+						  "qcom,cdc-micbias1-mv",
+						  &prop_val);
+		if (!rc)
+			mb->micb1_mv = prop_val;
+	} else {
+		dev_info(dev, "%s: Micbias1 DT property not found\n",
+			__func__);
+	}
+
+	/* MB2 */
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
+				    NULL)) {
+		rc = wcd9378_read_of_property_u32(dev,
+						  "qcom,cdc-micbias2-mv",
+						  &prop_val);
+		if (!rc)
+			mb->micb2_mv = prop_val;
+	} else {
+		dev_info(dev, "%s: Micbias2 DT property not found\n",
+			__func__);
+	}
+
+	/* MB3 */
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
+				    NULL)) {
+		rc = wcd9378_read_of_property_u32(dev,
+						  "qcom,cdc-micbias3-mv",
+						  &prop_val);
+		if (!rc)
+			mb->micb3_mv = prop_val;
+	} else {
+		dev_info(dev, "%s: Micbias3 DT property not found\n",
+			__func__);
+	}
+}
+
+static int wcd9378_reset_low(struct device *dev)
+{
+	struct wcd9378_priv *wcd9378 = NULL;
+	int rc = 0;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd9378 = dev_get_drvdata(dev);
+	if (!wcd9378)
+		return -EINVAL;
+
+	if (!wcd9378->rst_np) {
+		dev_err(dev, "%s: reset gpio device node not specified\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
+	if (rc) {
+		dev_err(dev, "%s: wcd sleep state request fail!\n",
+				__func__);
+		return rc;
+	}
+	/* 20us sleep required after pulling the reset gpio to LOW */
+	usleep_range(20, 30);
+
+	return rc;
+}
+
+struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
+{
+	struct wcd9378_pdata *pdata = NULL;
+
+	pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
+				GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	pdata->rst_np = of_parse_phandle(dev->of_node,
+			"qcom,wcd-rst-gpio-node", 0);
+
+	if (!pdata->rst_np) {
+		dev_err(dev, "%s: Looking up %s property in node %s failed\n",
+				__func__, "qcom,wcd-rst-gpio-node",
+				dev->of_node->full_name);
+		return NULL;
+	}
+
+	/* Parse power supplies */
+	msm_cdc_get_power_supplies(dev, &pdata->regulator,
+				   &pdata->num_supplies);
+	if (!pdata->regulator || (pdata->num_supplies <= 0)) {
+		dev_err(dev, "%s: no power supplies defined for codec\n",
+			__func__);
+		return NULL;
+	}
+
+	pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
+	pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
+
+	wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
+
+	return pdata;
+}
+
+static struct snd_soc_dai_driver wcd9378_dai[] = {
+	{
+		.name = "wcd9378_cdc",
+		.playback = {
+			.stream_name = "WCD9378_AIF Playback",
+			.rates = WCD9378_RATES | WCD9378_FRAC_RATES,
+			.formats = WCD9378_FORMATS,
+			.rate_max = 384000,
+			.rate_min = 8000,
+			.channels_min = 1,
+			.channels_max = 4,
+		},
+		.capture = {
+			.stream_name = "WCD9378_AIF Capture",
+			.rates = WCD9378_RATES | WCD9378_FRAC_RATES,
+			.formats = WCD9378_FORMATS,
+			.rate_max = 384000,
+			.rate_min = 8000,
+			.channels_min = 1,
+			.channels_max = 4,
+		},
+	},
+};
+
+static int wcd9378_bind(struct device *dev)
+{
+	int ret = 0;
+	struct wcd9378_pdata *pdata = dev_get_platdata(dev);
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
+
+	/*
+	 * Add 5msec delay to provide sufficient time for
+	 * soundwire auto enumeration of slave devices as
+	 * per HW requirement.
+	 */
+	usleep_range(5000, 5010);
+
+	ret = component_bind_all(dev, wcd9378);
+	if (ret) {
+		dev_err(dev, "%s: Slave bind failed, ret = %d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
+	if (!wcd9378->rx_swr_dev) {
+		dev_err(dev, "%s: Could not find RX swr slave device\n",
+			 __func__);
+		ret = -ENODEV;
+		goto err;
+	}
+	wcd9378->rx_swr_dev->paging_support = true;
+
+	wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
+	if (!wcd9378->tx_swr_dev) {
+		dev_err(dev, "%s: Could not find TX swr slave device\n",
+			__func__);
+		ret = -ENODEV;
+		goto err;
+	}
+	wcd9378->tx_swr_dev->paging_support = true;
+
+	swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
+			     wcd9378->swr_tx_port_params);
+
+	wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
+					       &wcd9378_regmap_config);
+	if (!wcd9378->regmap) {
+		dev_err(dev, "%s: Regmap init failed\n",
+				__func__);
+		goto err;
+	}
+
+	regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
+	regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
+	regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
+
+	wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
+	wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
+	wcd9378->irq_info.codec_name = "WCD9378";
+	wcd9378->irq_info.regmap = wcd9378->regmap;
+	wcd9378->irq_info.dev = dev;
+	ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
+	if (ret) {
+		dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
+			__func__, ret);
+		goto err;
+	}
+
+	dev_err(wcd9378->dev, "%s: wcd irq init done\n",
+			__func__);
+	wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
+
+	ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
+					wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
+	if (ret) {
+		dev_err(dev, "%s: Codec registration failed\n",
+				__func__);
+		goto err_irq;
+	}
+	wcd9378->dev_up = true;
+
+	return ret;
+err_irq:
+	wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
+err:
+	component_unbind_all(dev, wcd9378);
+	return ret;
+}
+
+static void wcd9378_unbind(struct device *dev)
+{
+	struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
+
+	wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
+	snd_soc_unregister_component(dev);
+	component_unbind_all(dev, wcd9378);
+}
+
+static const struct of_device_id wcd9378_dt_match[] = {
+	{ .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
+	{}
+};
+
+static const struct component_master_ops wcd9378_comp_ops = {
+	.bind   = wcd9378_bind,
+	.unbind = wcd9378_unbind,
+};
+
+static int wcd9378_compare_of(struct device *dev, void *data)
+{
+	return dev->of_node == data;
+}
+
+static void wcd9378_release_of(struct device *dev, void *data)
+{
+	of_node_put(data);
+}
+
+static int wcd9378_add_slave_components(struct device *dev,
+				struct component_match **matchptr)
+{
+	struct device_node *np, *rx_node, *tx_node;
+
+	np = dev->of_node;
+
+	rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
+	if (!rx_node) {
+		dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
+		return -ENODEV;
+	}
+	of_node_get(rx_node);
+	component_match_add_release(dev, matchptr,
+			wcd9378_release_of,
+			wcd9378_compare_of,
+			rx_node);
+
+	tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
+	if (!tx_node) {
+		dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
+			return -ENODEV;
+	}
+	of_node_get(tx_node);
+	component_match_add_release(dev, matchptr,
+			wcd9378_release_of,
+			wcd9378_compare_of,
+			tx_node);
+	return 0;
+}
+
+static int wcd9378_probe(struct platform_device *pdev)
+{
+	struct component_match *match = NULL;
+	struct wcd9378_priv *wcd9378 = NULL;
+	struct wcd9378_pdata *pdata = NULL;
+	struct wcd_ctrl_platform_data *plat_data = NULL;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
+				GFP_KERNEL);
+	if (!wcd9378)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, wcd9378);
+	wcd9378->dev = dev;
+
+	pdata = wcd9378_populate_dt_data(dev);
+	if (!pdata) {
+		dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
+		return -EINVAL;
+	}
+	dev->platform_data = pdata;
+
+	wcd9378->rst_np = pdata->rst_np;
+	ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
+				    pdata->regulator, pdata->num_supplies);
+	if (!wcd9378->supplies) {
+		dev_err(dev, "%s: Cannot init wcd supplies\n",
+			__func__);
+		return ret;
+	}
+
+	plat_data = dev_get_platdata(dev->parent);
+	if (!plat_data) {
+		dev_err(dev, "%s: platform data from parent is NULL\n",
+			__func__);
+		return -EINVAL;
+	}
+	wcd9378->handle = (void *)plat_data->handle;
+	if (!wcd9378->handle) {
+		dev_err(dev, "%s: handle is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd9378->update_wcd_event = plat_data->update_wcd_event;
+	if (!wcd9378->update_wcd_event) {
+		dev_err(dev, "%s: update_wcd_event api is null!\n",
+			__func__);
+		return -EINVAL;
+	}
+	wcd9378->register_notifier = plat_data->register_notifier;
+	if (!wcd9378->register_notifier) {
+		dev_err(dev, "%s: register_notifier api is null!\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
+			&wcd9378->wcd_mode);
+	if (ret) {
+		dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
+			__func__);
+		wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
+	}
+
+	ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
+					     pdata->regulator,
+					     pdata->num_supplies);
+	if (ret) {
+		dev_err(dev, "%s: wcd static supply enable failed!\n",
+			__func__);
+		return ret;
+	}
+
+	ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
+					CODEC_RX);
+	ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
+					CODEC_TX);
+
+	if (ret) {
+		dev_err(dev, "Failed to read port mapping\n");
+		goto err;
+	}
+	ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
+					CODEC_TX);
+	if (ret) {
+		dev_err(dev, "Failed to read port params\n");
+		goto err;
+	}
+
+	mutex_init(&wcd9378->wakeup_lock);
+	mutex_init(&wcd9378->micb_lock);
+	ret = wcd9378_add_slave_components(dev, &match);
+	if (ret)
+		goto err_lock_init;
+
+	wcd9378_reset(dev);
+
+	wcd9378->wakeup = wcd9378_wakeup;
+
+	return component_master_add_with_match(dev,
+					&wcd9378_comp_ops, match);
+
+err_lock_init:
+	mutex_destroy(&wcd9378->micb_lock);
+	mutex_destroy(&wcd9378->wakeup_lock);
+err:
+	return ret;
+}
+
+static int wcd9378_remove(struct platform_device *pdev)
+{
+	struct wcd9378_priv *wcd9378 = NULL;
+
+	wcd9378 = platform_get_drvdata(pdev);
+	component_master_del(&pdev->dev, &wcd9378_comp_ops);
+	mutex_destroy(&wcd9378->micb_lock);
+	mutex_destroy(&wcd9378->wakeup_lock);
+	dev_set_drvdata(&pdev->dev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int wcd9378_suspend(struct device *dev)
+{
+	struct wcd9378_priv *wcd9378 = NULL;
+	int ret = 0;
+	struct wcd9378_pdata *pdata = NULL;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd9378 = dev_get_drvdata(dev);
+	if (!wcd9378)
+		return -EINVAL;
+
+	pdata = dev_get_platdata(wcd9378->dev);
+
+	if (!pdata) {
+		dev_err(dev, "%s: pdata is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
+		ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
+						wcd9378->supplies,
+						pdata->regulator,
+						pdata->num_supplies,
+						"cdc-vdd-buck");
+		if (ret == -EINVAL) {
+			dev_err(dev, "%s: vdd buck is not disabled\n",
+				__func__);
+			return 0;
+		}
+		clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
+	}
+	if (wcd9378->dapm_bias_off) {
+		msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
+					      wcd9378->supplies,
+					      pdata->regulator,
+					      pdata->num_supplies,
+					      true);
+		set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
+	}
+	return 0;
+}
+
+static int wcd9378_resume(struct device *dev)
+{
+	struct wcd9378_priv *wcd9378 = NULL;
+	struct wcd9378_pdata *pdata = NULL;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd9378 = dev_get_drvdata(dev);
+	if (!wcd9378)
+		return -EINVAL;
+
+	pdata = dev_get_platdata(wcd9378->dev);
+
+	if (!pdata) {
+		dev_err(dev, "%s: pdata is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
+		msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
+					      wcd9378->supplies,
+					      pdata->regulator,
+					      pdata->num_supplies,
+					      false);
+		clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops wcd9378_dev_pm_ops = {
+	.suspend_late = wcd9378_suspend,
+	.resume_early = wcd9378_resume,
+};
+#endif
+
+static struct platform_driver wcd9378_codec_driver = {
+	.probe = wcd9378_probe,
+	.remove = wcd9378_remove,
+	.driver = {
+		.name = "wcd9378_codec",
+		.of_match_table = of_match_ptr(wcd9378_dt_match),
+#ifdef CONFIG_PM_SLEEP
+		.pm = &wcd9378_dev_pm_ops,
+#endif
+		.suppress_bind_attrs = true,
+	},
+};
+
+module_platform_driver(wcd9378_codec_driver);
+MODULE_DESCRIPTION("WCD9378 Codec driver");
+MODULE_LICENSE("GPL");

asoc/codecs/wcd9378/wcd9378.h

@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _WCD9378_H
+#define _WCD9378_H
+
+#include <bindings/audio-codec-port-types.h>
+#include <sound/info.h>
+#include <linux/component.h>
+
+#define WCD9378_MAX_SLAVE_CH_TYPES 13
+#define ZERO 0
+#define WCD9378_DRV_NAME "wcd9378_codec"
+
+/* from WCD to SWR DMIC events */
+enum {
+	WCD9378_EVT_SSR_DOWN,
+	WCD9378_EVT_SSR_UP,
+};
+
+struct wcd9378_swr_slave_ch_map {
+	u8 ch_type;
+	u8 index;
+};
+
+static const struct wcd9378_swr_slave_ch_map wcd9378_swr_slv_tx_ch_idx[] = {
+	{ADC1, 0},
+	{ADC2, 1},
+	{ADC3, 2},
+	{ADC4, 3},
+	{DMIC0, 4},
+	{DMIC1, 5},
+	{MBHC, 6},
+	{DMIC2, 6},
+	{DMIC3, 7},
+	{DMIC4, 8},
+	{DMIC5, 9},
+	{DMIC6, 10},
+	{DMIC7, 11},
+};
+
+static int wcd9378_swr_master_ch_map[] = {
+	ZERO,
+	SWRM_TX1_CH1,
+	SWRM_TX1_CH2,
+	SWRM_TX1_CH3,
+	SWRM_TX1_CH4,
+	SWRM_TX2_CH1,
+	SWRM_TX2_CH2,
+	SWRM_TX2_CH3,
+	SWRM_TX2_CH4,
+	SWRM_TX3_CH1,
+	SWRM_TX3_CH2,
+	SWRM_TX3_CH3,
+	SWRM_TX3_CH4,
+	SWRM_TX_PCM_IN,
+};
+
+#if IS_ENABLED(CONFIG_SND_SOC_WCD9378)
+int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
+				struct snd_soc_component *component);
+
+int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *wcd9378,
+					struct notifier_block *nblock,
+					bool enable);
+
+int wcd9378_codec_get_dev_num(struct snd_soc_component *component);
+
+static inline int wcd9378_slave_get_master_ch_val(int ch)
+{
+	int i;
+
+	for (i = 0; i < WCD9378_MAX_SLAVE_CH_TYPES; i++)
+		if (ch == wcd9378_swr_master_ch_map[i])
+			return i;
+	return 0;
+}
+
+static inline int wcd9378_slave_get_master_ch(int idx)
+{
+	return wcd9378_swr_master_ch_map[idx];
+}
+
+static inline int wcd9378_slave_get_slave_ch_val(int ch)
+{
+	int i;
+
+	for (i = 0; i < WCD9378_MAX_SLAVE_CH_TYPES; i++)
+		if (ch == wcd9378_swr_slv_tx_ch_idx[i].ch_type)
+			return wcd9378_swr_slv_tx_ch_idx[i].index;
+
+	return -EINVAL;
+}
+#else
+static inline int wcd9378_info_create_codec_entry(
+					struct snd_info_entry *codec_root,
+					struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static inline int wcd9378_slave_get_master_ch_val(int ch)
+{
+	return 0;
+}
+static inline int wcd9378_slave_get_master_ch(int idx)
+{
+	return 0;
+}
+static inline int wcd9378_slave_get_slave_ch_val(int ch)
+{
+	return 0;
+}
+static int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
+{
+	return 0;
+}
+#endif /* CONFIG_SND_SOC_WCD9378 */
+#endif /* _WCD9378_H */
+