wcd9378-registers.h 61 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #ifndef WCD9378_REGISTERS_H
  6. #define WCD9378_REGISTERS_H
  7. enum {
  8. REG_NO_ACCESS,
  9. RD_REG,
  10. WR_REG,
  11. RD_WR_REG,
  12. };
  13. #define WCD9378_BASE 0x3fffffff
  14. #define WCD9378_REG(reg) (((reg & 0x0ff00000) >> 8) | (reg & 0xfff))
  15. #define WCD9378_FUNC0_BASE (WCD9378_BASE+0x01)
  16. #define WCD9378_FUNC_EXT_ID_0 (WCD9378_FUNC0_BASE+0x48)
  17. #define WCD9378_FUNC_EXT_ID_1 (WCD9378_FUNC0_BASE+0x49)
  18. #define WCD9378_FUNC_EXT_VER (WCD9378_FUNC0_BASE+0x50)
  19. #define WCD9378_FUNC_STAT (WCD9378_FUNC0_BASE+0x80000)
  20. #define WCD9378_DEV_MANU_ID_0 (WCD9378_FUNC0_BASE+0x100060)
  21. #define WCD9378_DEV_MANU_ID_1 (WCD9378_FUNC0_BASE+0x100061)
  22. #define WCD9378_DEV_PART_ID_0 (WCD9378_FUNC0_BASE+0x100068)
  23. #define WCD9378_DEV_PART_ID_1 (WCD9378_FUNC0_BASE+0x100069)
  24. #define WCD9378_DEV_VER (WCD9378_FUNC0_BASE+0x100070)
  25. #define WCD9378_A_BASE (WCD9378_BASE+0x180001)
  26. #define WCD9378_ANA_PAGE (WCD9378_A_BASE+0x00)
  27. #define WCD9378_ANA_BIAS (WCD9378_A_BASE+0x01)
  28. #define WCD9378_ANA_RX_SUPPLIES (WCD9378_A_BASE+0x08)
  29. #define WCD9378_ANA_HPH (WCD9378_A_BASE+0x09)
  30. #define WCD9378_ANA_EAR (WCD9378_A_BASE+0x0a)
  31. #define WCD9378_ANA_EAR_COMPANDER_CTL (WCD9378_A_BASE+0x0b)
  32. #define WCD9378_ANA_TX_CH1 (WCD9378_A_BASE+0x0e)
  33. #define WCD9378_ANA_TX_CH2 (WCD9378_A_BASE+0x0f)
  34. #define WCD9378_ANA_TX_CH3 (WCD9378_A_BASE+0x10)
  35. #define WCD9378_ANA_TX_CH3_HPF (WCD9378_A_BASE+0x11)
  36. #define WCD9378_ANA_MICB1_MICB2_DSP_EN_LOGIC (WCD9378_A_BASE+0x12)
  37. #define WCD9378_ANA_MICB3_DSP_EN_LOGIC (WCD9378_A_BASE+0x13)
  38. #define WCD9378_ANA_MBHC_MECH (WCD9378_A_BASE+0x14)
  39. #define WCD9378_ANA_MBHC_ELECT (WCD9378_A_BASE+0x15)
  40. #define WCD9378_ANA_MBHC_ZDET (WCD9378_A_BASE+0x16)
  41. #define WCD9378_ANA_MBHC_RESULT_1 (WCD9378_A_BASE+0x17)
  42. #define WCD9378_ANA_MBHC_RESULT_2 (WCD9378_A_BASE+0x18)
  43. #define WCD9378_ANA_MBHC_RESULT_3 (WCD9378_A_BASE+0x19)
  44. #define WCD9378_ANA_MBHC_BTN0 (WCD9378_A_BASE+0x1a)
  45. #define WCD9378_ANA_MBHC_BTN1 (WCD9378_A_BASE+0x1b)
  46. #define WCD9378_ANA_MBHC_BTN2 (WCD9378_A_BASE+0x1c)
  47. #define WCD9378_ANA_MBHC_BTN3 (WCD9378_A_BASE+0x1d)
  48. #define WCD9378_ANA_MBHC_BTN4 (WCD9378_A_BASE+0x1e)
  49. #define WCD9378_ANA_MBHC_BTN5 (WCD9378_A_BASE+0x1f)
  50. #define WCD9378_ANA_MBHC_BTN6 (WCD9378_A_BASE+0x20)
  51. #define WCD9378_ANA_MBHC_BTN7 (WCD9378_A_BASE+0x21)
  52. #define WCD9378_ANA_MICB1 (WCD9378_A_BASE+0x22)
  53. #define WCD9378_ANA_MICB2 (WCD9378_A_BASE+0x23)
  54. #define WCD9378_ANA_MICB2_RAMP (WCD9378_A_BASE+0x24)
  55. #define WCD9378_ANA_MICB3 (WCD9378_A_BASE+0x25)
  56. #define WCD9378_BIAS_CTL (WCD9378_A_BASE+0x28)
  57. #define WCD9378_BIAS_VBG_FINE_ADJ (WCD9378_A_BASE+0x29)
  58. #define WCD9378_LDOL_VDDCX_ADJUST (WCD9378_A_BASE+0x40)
  59. #define WCD9378_LDOL_DISABLE_LDOL (WCD9378_A_BASE+0x41)
  60. #define WCD9378_MBHC_CTL_CLK (WCD9378_A_BASE+0x56)
  61. #define WCD9378_MBHC_CTL_ANA (WCD9378_A_BASE+0x57)
  62. #define WCD9378_MBHC_CTL_SPARE_1 (WCD9378_A_BASE+0x58)
  63. #define WCD9378_MBHC_CTL_SPARE_2 (WCD9378_A_BASE+0x59)
  64. #define WCD9378_MBHC_CTL_BCS (WCD9378_A_BASE+0x5a)
  65. #define WCD9378_MBHC_MOISTURE_DET_FSM_STATUS (WCD9378_A_BASE+0x5b)
  66. #define WCD9378_MBHC_TEST_CTL (WCD9378_A_BASE+0x5c)
  67. #define WCD9378_LDOH_MODE (WCD9378_A_BASE+0x67)
  68. #define WCD9378_LDOH_BIAS (WCD9378_A_BASE+0x68)
  69. #define WCD9378_LDOH_STB_LOADS (WCD9378_A_BASE+0x69)
  70. #define WCD9378_LDOH_SLOWRAMP (WCD9378_A_BASE+0x6a)
  71. #define WCD9378_MICB1_TEST_CTL_1 (WCD9378_A_BASE+0x6b)
  72. #define WCD9378_MICB1_TEST_CTL_2 (WCD9378_A_BASE+0x6c)
  73. #define WCD9378_MICB1_TEST_CTL_3 (WCD9378_A_BASE+0x6d)
  74. #define WCD9378_MICB2_TEST_CTL_1 (WCD9378_A_BASE+0x6e)
  75. #define WCD9378_MICB2_TEST_CTL_2 (WCD9378_A_BASE+0x6f)
  76. #define WCD9378_MICB2_TEST_CTL_3 (WCD9378_A_BASE+0x70)
  77. #define WCD9378_MICB3_TEST_CTL_1 (WCD9378_A_BASE+0x71)
  78. #define WCD9378_MICB3_TEST_CTL_2 (WCD9378_A_BASE+0x72)
  79. #define WCD9378_MICB3_TEST_CTL_3 (WCD9378_A_BASE+0x73)
  80. #define WCD9378_TX_COM_ADC_VCM (WCD9378_A_BASE+0x77)
  81. #define WCD9378_TX_COM_BIAS_ATEST (WCD9378_A_BASE+0x78)
  82. #define WCD9378_TX_COM_SPARE1 (WCD9378_A_BASE+0x79)
  83. #define WCD9378_TX_COM_SPARE2 (WCD9378_A_BASE+0x7a)
  84. #define WCD9378_TX_COM_TXFE_DIV_CTL (WCD9378_A_BASE+0x7b)
  85. #define WCD9378_TX_COM_TXFE_DIV_START (WCD9378_A_BASE+0x7c)
  86. #define WCD9378_TX_COM_SPARE3 (WCD9378_A_BASE+0x7d)
  87. #define WCD9378_TX_COM_SPARE4 (WCD9378_A_BASE+0x7e)
  88. #define WCD9378_TX_1_2_TEST_EN (WCD9378_A_BASE+0x7f)
  89. #define WCD9378_TX_1_2_ADC_IB (WCD9378_A_BASE+0x80)
  90. #define WCD9378_TX_1_2_ATEST_REFCTL (WCD9378_A_BASE+0x81)
  91. #define WCD9378_TX_1_2_TEST_CTL (WCD9378_A_BASE+0x82)
  92. #define WCD9378_TX_1_2_TEST_BLK_EN1 (WCD9378_A_BASE+0x83)
  93. #define WCD9378_TX_1_2_TXFE1_CLKDIV (WCD9378_A_BASE+0x84)
  94. #define WCD9378_TX_1_2_SAR2_ERR (WCD9378_A_BASE+0x85)
  95. #define WCD9378_TX_1_2_SAR1_ERR (WCD9378_A_BASE+0x86)
  96. #define WCD9378_TX_3_TEST_EN (WCD9378_A_BASE+0x87)
  97. #define WCD9378_TX_3_ADC_IB (WCD9378_A_BASE+0x88)
  98. #define WCD9378_TX_3_ATEST_REFCTL (WCD9378_A_BASE+0x89)
  99. #define WCD9378_TX_3_TEST_CTL (WCD9378_A_BASE+0x8a)
  100. #define WCD9378_TX_3_TEST_BLK_EN3 (WCD9378_A_BASE+0x8b)
  101. #define WCD9378_TX_3_TXFE3_CLKDIV (WCD9378_A_BASE+0x8c)
  102. #define WCD9378_TX_3_SAR4_ERR (WCD9378_A_BASE+0x8d)
  103. #define WCD9378_TX_3_SAR3_ERR (WCD9378_A_BASE+0x8e)
  104. #define WCD9378_TX_3_TEST_BLK_EN2 (WCD9378_A_BASE+0x8f)
  105. #define WCD9378_TX_3_TXFE2_CLKDIV (WCD9378_A_BASE+0x90)
  106. #define WCD9378_TX_3_SPARE1 (WCD9378_A_BASE+0x91)
  107. #define WCD9378_TX_3_TEST_BLK_EN4 (WCD9378_A_BASE+0x92)
  108. #define WCD9378_TX_3_SPARE2 (WCD9378_A_BASE+0x93)
  109. #define WCD9378_TX_3_SPARE3 (WCD9378_A_BASE+0x94)
  110. #define WCD9378_RX_AUX_SW_CTL (WCD9378_A_BASE+0xb3)
  111. #define WCD9378_RX_PA_AUX_IN_CONN (WCD9378_A_BASE+0xb4)
  112. #define WCD9378_RX_TIMER_DIV (WCD9378_A_BASE+0xb5)
  113. #define WCD9378_RX_OCP_CTL (WCD9378_A_BASE+0xb6)
  114. #define WCD9378_RX_OCP_COUNT (WCD9378_A_BASE+0xb7)
  115. #define WCD9378_RX_BIAS_EAR_DAC (WCD9378_A_BASE+0xb8)
  116. #define WCD9378_RX_BIAS_EAR_AMP (WCD9378_A_BASE+0xb9)
  117. #define WCD9378_RX_BIAS_HPH_LDO (WCD9378_A_BASE+0xba)
  118. #define WCD9378_RX_BIAS_HPH_PA (WCD9378_A_BASE+0xbb)
  119. #define WCD9378_RX_BIAS_HPH_RDACBUFF_CNP2 (WCD9378_A_BASE+0xbc)
  120. #define WCD9378_RX_BIAS_HPH_RDAC_LDO (WCD9378_A_BASE+0xbd)
  121. #define WCD9378_RX_BIAS_HPH_CNP1 (WCD9378_A_BASE+0xbe)
  122. #define WCD9378_RX_BIAS_HPH_LOWPOWER (WCD9378_A_BASE+0xbf)
  123. #define WCD9378_RX_BIAS_AUX_DAC (WCD9378_A_BASE+0xc0)
  124. #define WCD9378_RX_BIAS_AUX_AMP (WCD9378_A_BASE+0xc1)
  125. #define WCD9378_RX_SPARE_1 (WCD9378_A_BASE+0xc2)
  126. #define WCD9378_RX_SPARE_2 (WCD9378_A_BASE+0xc3)
  127. #define WCD9378_RX_SPARE_3 (WCD9378_A_BASE+0xc4)
  128. #define WCD9378_RX_SPARE_4 (WCD9378_A_BASE+0xc5)
  129. #define WCD9378_RX_SPARE_5 (WCD9378_A_BASE+0xc6)
  130. #define WCD9378_RX_SPARE_6 (WCD9378_A_BASE+0xc7)
  131. #define WCD9378_RX_SPARE_7 (WCD9378_A_BASE+0xc8)
  132. #define WCD9378_HPH_L_STATUS (WCD9378_A_BASE+0xc9)
  133. #define WCD9378_HPH_R_STATUS (WCD9378_A_BASE+0xca)
  134. #define WCD9378_HPH_CNP_EN (WCD9378_A_BASE+0xcb)
  135. #define WCD9378_HPH_CNP_WG_CTL (WCD9378_A_BASE+0xcc)
  136. #define WCD9378_HPH_CNP_WG_TIME (WCD9378_A_BASE+0xcd)
  137. #define WCD9378_HPH_OCP_CTL (WCD9378_A_BASE+0xce)
  138. #define WCD9378_HPH_AUTO_CHOP (WCD9378_A_BASE+0xcf)
  139. #define WCD9378_HPH_CHOP_CTL (WCD9378_A_BASE+0xd0)
  140. #define WCD9378_HPH_PA_CTL1 (WCD9378_A_BASE+0xd1)
  141. #define WCD9378_HPH_PA_CTL2 (WCD9378_A_BASE+0xd2)
  142. #define WCD9378_HPH_L_EN (WCD9378_A_BASE+0xd3)
  143. #define WCD9378_HPH_L_TEST (WCD9378_A_BASE+0xd4)
  144. #define WCD9378_HPH_L_ATEST (WCD9378_A_BASE+0xd5)
  145. #define WCD9378_HPH_R_EN (WCD9378_A_BASE+0xd6)
  146. #define WCD9378_HPH_R_TEST (WCD9378_A_BASE+0xd7)
  147. #define WCD9378_HPH_R_ATEST (WCD9378_A_BASE+0xd8)
  148. #define WCD9378_HPH_RDAC_CLK_CTL1 (WCD9378_A_BASE+0xd9)
  149. #define WCD9378_HPH_RDAC_CLK_CTL2 (WCD9378_A_BASE+0xda)
  150. #define WCD9378_HPH_RDAC_LDO_CTL (WCD9378_A_BASE+0xdb)
  151. #define WCD9378_HPH_RDAC_CHOP_CLK_LP_CTL (WCD9378_A_BASE+0xdc)
  152. #define WCD9378_HPH_REFBUFF_UHQA_CTL (WCD9378_A_BASE+0xdd)
  153. #define WCD9378_HPH_REFBUFF_LP_CTL (WCD9378_A_BASE+0xde)
  154. #define WCD9378_HPH_L_DAC_CTL (WCD9378_A_BASE+0xdf)
  155. #define WCD9378_HPH_R_DAC_CTL (WCD9378_A_BASE+0xe0)
  156. #define WCD9378_HPH_SURGE_HPHLR_SURGE_COMP_SEL (WCD9378_A_BASE+0xe1)
  157. #define WCD9378_HPH_SURGE_HPHLR_SURGE_EN (WCD9378_A_BASE+0xe2)
  158. #define WCD9378_HPH_SURGE_HPHLR_SURGE_MISC1 (WCD9378_A_BASE+0xe3)
  159. #define WCD9378_HPH_SURGE_HPHLR_SURGE_STATUS (WCD9378_A_BASE+0xe4)
  160. #define WCD9378_EAR_EAR_EN_REG (WCD9378_A_BASE+0xe9)
  161. #define WCD9378_EAR_EAR_PA_CON (WCD9378_A_BASE+0xea)
  162. #define WCD9378_EAR_EAR_SP_CON (WCD9378_A_BASE+0xeb)
  163. #define WCD9378_EAR_EAR_DAC_CON (WCD9378_A_BASE+0xec)
  164. #define WCD9378_EAR_EAR_CNP_FSM_CON (WCD9378_A_BASE+0xed)
  165. #define WCD9378_EAR_TEST_CTL (WCD9378_A_BASE+0xee)
  166. #define WCD9378_EAR_STATUS_REG_1 (WCD9378_A_BASE+0xef)
  167. #define WCD9378_EAR_STATUS_REG_2 (WCD9378_A_BASE+0xf0)
  168. #define WCD9378_ANA_NEW_PAGE (WCD9378_A_BASE+0x100)
  169. #define WCD9378_HPH_NEW_ANA_HPH2 (WCD9378_A_BASE+0x101)
  170. #define WCD9378_HPH_NEW_ANA_HPH3 (WCD9378_A_BASE+0x102)
  171. #define WCD9378_SLEEP_CTL (WCD9378_A_BASE+0x103)
  172. #define WCD9378_SLEEP_WATCHDOG_CTL (WCD9378_A_BASE+0x104)
  173. #define WCD9378_MBHC_NEW_ELECT_REM_CLAMP_CTL (WCD9378_A_BASE+0x11f)
  174. #define WCD9378_MBHC_NEW_CTL_1 (WCD9378_A_BASE+0x120)
  175. #define WCD9378_MBHC_NEW_CTL_2 (WCD9378_A_BASE+0x121)
  176. #define WCD9378_MBHC_NEW_PLUG_DETECT_CTL (WCD9378_A_BASE+0x122)
  177. #define WCD9378_MBHC_NEW_ZDET_ANA_CTL (WCD9378_A_BASE+0x123)
  178. #define WCD9378_MBHC_NEW_ZDET_RAMP_CTL (WCD9378_A_BASE+0x124)
  179. #define WCD9378_MBHC_NEW_FSM_STATUS (WCD9378_A_BASE+0x125)
  180. #define WCD9378_MBHC_NEW_ADC_RESULT (WCD9378_A_BASE+0x126)
  181. #define WCD9378_AUX_AUXPA (WCD9378_A_BASE+0x128)
  182. #define WCD9378_DIE_CRACK_DIE_CRK_DET_EN (WCD9378_A_BASE+0x12c)
  183. #define WCD9378_DIE_CRACK_DIE_CRK_DET_OUT (WCD9378_A_BASE+0x12d)
  184. #define WCD9378_TX_NEW_TX_CH12_MUX (WCD9378_A_BASE+0x12e)
  185. #define WCD9378_TX_NEW_TX_CH34_MUX (WCD9378_A_BASE+0x12f)
  186. #define WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL (WCD9378_A_BASE+0x132)
  187. #define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L (WCD9378_A_BASE+0x133)
  188. #define WCD9378_HPH_NEW_INT_RDAC_VREF_CTL (WCD9378_A_BASE+0x134)
  189. #define WCD9378_HPH_NEW_INT_RDAC_OVERRIDE_CTL (WCD9378_A_BASE+0x135)
  190. #define WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R (WCD9378_A_BASE+0x136)
  191. #define WCD9378_HPH_NEW_INT_PA_MISC1 (WCD9378_A_BASE+0x137)
  192. #define WCD9378_HPH_NEW_INT_PA_MISC2 (WCD9378_A_BASE+0x138)
  193. #define WCD9378_HPH_NEW_INT_PA_RDAC_MISC (WCD9378_A_BASE+0x139)
  194. #define WCD9378_HPH_NEW_INT_HPH_TIMER1 (WCD9378_A_BASE+0x13a)
  195. #define WCD9378_HPH_NEW_INT_HPH_TIMER2 (WCD9378_A_BASE+0x13b)
  196. #define WCD9378_HPH_NEW_INT_HPH_TIMER3 (WCD9378_A_BASE+0x13c)
  197. #define WCD9378_HPH_NEW_INT_HPH_TIMER4 (WCD9378_A_BASE+0x13d)
  198. #define WCD9378_HPH_NEW_INT_PA_RDAC_MISC2 (WCD9378_A_BASE+0x13e)
  199. #define WCD9378_HPH_NEW_INT_PA_RDAC_MISC3 (WCD9378_A_BASE+0x13f)
  200. #define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (WCD9378_A_BASE+0x145)
  201. #define WCD9378_RX_NEW_INT_HPH_RDAC_BIAS_ULP (WCD9378_A_BASE+0x146)
  202. #define WCD9378_RX_NEW_INT_HPH_RDAC_LDO_LP (WCD9378_A_BASE+0x147)
  203. #define WCD9378_CP_CLASSG_CP_CTRL_0 (WCD9378_A_BASE+0x150)
  204. #define WCD9378_CP_CLASSG_CP_CTRL_1 (WCD9378_A_BASE+0x151)
  205. #define WCD9378_CP_CLASSG_CP_CTRL_2 (WCD9378_A_BASE+0x152)
  206. #define WCD9378_CP_CLASSG_CP_CTRL_3 (WCD9378_A_BASE+0x153)
  207. #define WCD9378_CP_CLASSG_CP_CTRL_4 (WCD9378_A_BASE+0x154)
  208. #define WCD9378_CP_CLASSG_CP_CTRL_5 (WCD9378_A_BASE+0x155)
  209. #define WCD9378_CP_CLASSG_CP_CTRL_6 (WCD9378_A_BASE+0x156)
  210. #define WCD9378_CP_CLASSG_CP_CTRL_7 (WCD9378_A_BASE+0x157)
  211. #define WCD9378_CP_VNEGDAC_CTRL_0 (WCD9378_A_BASE+0x158)
  212. #define WCD9378_CP_VNEGDAC_CTRL_1 (WCD9378_A_BASE+0x159)
  213. #define WCD9378_CP_VNEGDAC_CTRL_2 (WCD9378_A_BASE+0x15a)
  214. #define WCD9378_CP_VNEGDAC_CTRL_3 (WCD9378_A_BASE+0x15b)
  215. #define WCD9378_CP_CP_DTOP_CTRL_0 (WCD9378_A_BASE+0x15c)
  216. #define WCD9378_CP_CP_DTOP_CTRL_1 (WCD9378_A_BASE+0x15d)
  217. #define WCD9378_CP_CP_DTOP_CTRL_2 (WCD9378_A_BASE+0x15e)
  218. #define WCD9378_CP_CP_DTOP_CTRL_3 (WCD9378_A_BASE+0x15f)
  219. #define WCD9378_CP_CP_DTOP_CTRL_4 (WCD9378_A_BASE+0x160)
  220. #define WCD9378_CP_CP_DTOP_CTRL_5 (WCD9378_A_BASE+0x161)
  221. #define WCD9378_CP_CP_DTOP_CTRL_6 (WCD9378_A_BASE+0x162)
  222. #define WCD9378_CP_CP_DTOP_CTRL_7 (WCD9378_A_BASE+0x163)
  223. #define WCD9378_CP_CP_DTOP_CTRL_8 (WCD9378_A_BASE+0x164)
  224. #define WCD9378_CP_CP_DTOP_CTRL_9 (WCD9378_A_BASE+0x165)
  225. #define WCD9378_CP_CP_DTOP_CTRL_10 (WCD9378_A_BASE+0x166)
  226. #define WCD9378_CP_CP_DTOP_CTRL_11 (WCD9378_A_BASE+0x167)
  227. #define WCD9378_CP_CP_DTOP_CTRL_12 (WCD9378_A_BASE+0x168)
  228. #define WCD9378_CP_CP_DTOP_CTRL_13 (WCD9378_A_BASE+0x169)
  229. #define WCD9378_CP_CP_DTOP_CTRL_14 (WCD9378_A_BASE+0x16a)
  230. #define WCD9378_CP_CP_DTOP_CTRL_15 (WCD9378_A_BASE+0x16b)
  231. #define WCD9378_CP_CP_DTOP_CTRL_16 (WCD9378_A_BASE+0x16c)
  232. #define WCD9378_CP_CP_DTOP_CTRL_17 (WCD9378_A_BASE+0x16d)
  233. #define WCD9378_CP_CP_DTOP_CTRL_18 (WCD9378_A_BASE+0x16e)
  234. #define WCD9378_CP_CP_DTOP_CTRL_19 (WCD9378_A_BASE+0x16f)
  235. #define WCD9378_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (WCD9378_A_BASE+0x1af)
  236. #define WCD9378_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (WCD9378_A_BASE+0x1b0)
  237. #define WCD9378_MBHC_NEW_INT_MECH_DET_CURRENT (WCD9378_A_BASE+0x1b1)
  238. #define WCD9378_MBHC_NEW_INT_SPARE_2 (WCD9378_A_BASE+0x1b2)
  239. #define WCD9378_EAR_INT_NEW_EAR_CHOPPER_CON (WCD9378_A_BASE+0x1b7)
  240. #define WCD9378_EAR_INT_NEW_CNP_VCM_CON1 (WCD9378_A_BASE+0x1b8)
  241. #define WCD9378_EAR_INT_NEW_CNP_VCM_CON2 (WCD9378_A_BASE+0x1b9)
  242. #define WCD9378_EAR_INT_NEW_EAR_DYNAMIC_BIAS (WCD9378_A_BASE+0x1ba)
  243. #define WCD9378_AUX_INT_EN_REG (WCD9378_A_BASE+0x1bd)
  244. #define WCD9378_AUX_INT_PA_CTRL (WCD9378_A_BASE+0x1be)
  245. #define WCD9378_AUX_INT_SP_CTRL (WCD9378_A_BASE+0x1bf)
  246. #define WCD9378_AUX_INT_DAC_CTRL (WCD9378_A_BASE+0x1c0)
  247. #define WCD9378_AUX_INT_CLK_CTRL (WCD9378_A_BASE+0x1c1)
  248. #define WCD9378_AUX_INT_TEST_CTRL (WCD9378_A_BASE+0x1c2)
  249. #define WCD9378_AUX_INT_STATUS_REG (WCD9378_A_BASE+0x1c3)
  250. #define WCD9378_AUX_INT_MISC (WCD9378_A_BASE+0x1c4)
  251. #define WCD9378_SLEEP_INT_WATCHDOG_CTL_1 (WCD9378_A_BASE+0x1d0)
  252. #define WCD9378_SLEEP_INT_WATCHDOG_CTL_2 (WCD9378_A_BASE+0x1d1)
  253. #define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT1 (WCD9378_A_BASE+0x1d3)
  254. #define WCD9378_DIE_CRACK_INT_DIE_CRK_DET_INT2 (WCD9378_A_BASE+0x1d4)
  255. #define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L2 (WCD9378_A_BASE+0x1d5)
  256. #define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L1 (WCD9378_A_BASE+0x1d6)
  257. #define WCD9378_TX_COM_NEW_INT_TXFE_DIVSTOP_L0 (WCD9378_A_BASE+0x1d7)
  258. #define WCD9378_TX_COM_NEW_INT_SPARE1 (WCD9378_A_BASE+0x1d8)
  259. #define WCD9378_TX_COM_NEW_INT_SPARE2 (WCD9378_A_BASE+0x1d9)
  260. #define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L2 (WCD9378_A_BASE+0x1da)
  261. #define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L1 (WCD9378_A_BASE+0x1db)
  262. #define WCD9378_TX_COM_NEW_INT_TXFE_NINIT_L0 (WCD9378_A_BASE+0x1dc)
  263. #define WCD9378_TX_COM_NEW_INT_SPARE3 (WCD9378_A_BASE+0x1dd)
  264. #define WCD9378_TX_COM_NEW_INT_SPARE4 (WCD9378_A_BASE+0x1de)
  265. #define WCD9378_TX_COM_NEW_INT_SPARE5 (WCD9378_A_BASE+0x1df)
  266. #define WCD9378_TX_COM_NEW_INT_SPARE6 (WCD9378_A_BASE+0x1e0)
  267. #define WCD9378_TX_COM_NEW_INT_SPARE7 (WCD9378_A_BASE+0x1e1)
  268. #define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1 (WCD9378_A_BASE+0x1e2)
  269. #define WCD9378_TX_COM_NEW_INT_TXADC_SCBIAS_L0 (WCD9378_A_BASE+0x1e3)
  270. #define WCD9378_TX_COM_NEW_INT_TXADC_INT_L2 (WCD9378_A_BASE+0x1e4)
  271. #define WCD9378_TX_COM_NEW_INT_TXADC_INT_L1 (WCD9378_A_BASE+0x1e5)
  272. #define WCD9378_TX_COM_NEW_INT_TXADC_INT_L0 (WCD9378_A_BASE+0x1e6)
  273. #define WCD9378_TX_COM_NEW_INT_SPARE8 (WCD9378_A_BASE+0x1e7)
  274. #define WCD9378_TAMBORA_BASE (WCD9378_BASE+0x180401)
  275. #define WCD9378_TAMBORA_PAGE (WCD9378_TAMBORA_BASE+0x00)
  276. #define WCD9378_CHIP_ID0 (WCD9378_TAMBORA_BASE+0x01)
  277. #define WCD9378_CHIP_ID1 (WCD9378_TAMBORA_BASE+0x02)
  278. #define WCD9378_CHIP_ID2 (WCD9378_TAMBORA_BASE+0x03)
  279. #define WCD9378_CHIP_ID3 (WCD9378_TAMBORA_BASE+0x04)
  280. #define WCD9378_SWR_TX_CLK_RATE (WCD9378_TAMBORA_BASE+0x05)
  281. #define WCD9378_CDC_RST_CTL (WCD9378_TAMBORA_BASE+0x06)
  282. #define WCD9378_TOP_CLK_CFG (WCD9378_TAMBORA_BASE+0x07)
  283. #define WCD9378_CDC_ANA_CLK_CTL (WCD9378_TAMBORA_BASE+0x08)
  284. #define WCD9378_CDC_DIG_CLK_CTL (WCD9378_TAMBORA_BASE+0x09)
  285. #define WCD9378_SWR_RST_EN (WCD9378_TAMBORA_BASE+0x0a)
  286. #define WCD9378_CDC_PATH_MODE (WCD9378_TAMBORA_BASE+0x0b)
  287. #define WCD9378_CDC_RX_RST (WCD9378_TAMBORA_BASE+0x0c)
  288. #define WCD9378_CDC_RX0_CTL (WCD9378_TAMBORA_BASE+0x0d)
  289. #define WCD9378_CDC_RX1_CTL (WCD9378_TAMBORA_BASE+0x0e)
  290. #define WCD9378_CDC_RX2_CTL (WCD9378_TAMBORA_BASE+0x0f)
  291. #define WCD9378_CDC_TX_ANA_MODE_0_1 (WCD9378_TAMBORA_BASE+0x10)
  292. #define WCD9378_CDC_TX_ANA_MODE_2_3 (WCD9378_TAMBORA_BASE+0x11)
  293. #define WCD9378_CDC_COMP_CTL_0 (WCD9378_TAMBORA_BASE+0x14)
  294. #define WCD9378_CDC_ANA_TX_CLK_CTL (WCD9378_TAMBORA_BASE+0x17)
  295. #define WCD9378_CDC_HPH_DSM_A1_0 (WCD9378_TAMBORA_BASE+0x18)
  296. #define WCD9378_CDC_HPH_DSM_A1_1 (WCD9378_TAMBORA_BASE+0x19)
  297. #define WCD9378_CDC_HPH_DSM_A2_0 (WCD9378_TAMBORA_BASE+0x1a)
  298. #define WCD9378_CDC_HPH_DSM_A2_1 (WCD9378_TAMBORA_BASE+0x1b)
  299. #define WCD9378_CDC_HPH_DSM_A3_0 (WCD9378_TAMBORA_BASE+0x1c)
  300. #define WCD9378_CDC_HPH_DSM_A3_1 (WCD9378_TAMBORA_BASE+0x1d)
  301. #define WCD9378_CDC_HPH_DSM_A4_0 (WCD9378_TAMBORA_BASE+0x1e)
  302. #define WCD9378_CDC_HPH_DSM_A4_1 (WCD9378_TAMBORA_BASE+0x1f)
  303. #define WCD9378_CDC_HPH_DSM_A5_0 (WCD9378_TAMBORA_BASE+0x20)
  304. #define WCD9378_CDC_HPH_DSM_A5_1 (WCD9378_TAMBORA_BASE+0x21)
  305. #define WCD9378_CDC_HPH_DSM_A6_0 (WCD9378_TAMBORA_BASE+0x22)
  306. #define WCD9378_CDC_HPH_DSM_A7_0 (WCD9378_TAMBORA_BASE+0x23)
  307. #define WCD9378_CDC_HPH_DSM_C_0 (WCD9378_TAMBORA_BASE+0x24)
  308. #define WCD9378_CDC_HPH_DSM_C_1 (WCD9378_TAMBORA_BASE+0x25)
  309. #define WCD9378_CDC_HPH_DSM_C_2 (WCD9378_TAMBORA_BASE+0x26)
  310. #define WCD9378_CDC_HPH_DSM_C_3 (WCD9378_TAMBORA_BASE+0x27)
  311. #define WCD9378_CDC_HPH_DSM_R1 (WCD9378_TAMBORA_BASE+0x28)
  312. #define WCD9378_CDC_HPH_DSM_R2 (WCD9378_TAMBORA_BASE+0x29)
  313. #define WCD9378_CDC_HPH_DSM_R3 (WCD9378_TAMBORA_BASE+0x2a)
  314. #define WCD9378_CDC_HPH_DSM_R4 (WCD9378_TAMBORA_BASE+0x2b)
  315. #define WCD9378_CDC_HPH_DSM_R5 (WCD9378_TAMBORA_BASE+0x2c)
  316. #define WCD9378_CDC_HPH_DSM_R6 (WCD9378_TAMBORA_BASE+0x2d)
  317. #define WCD9378_CDC_HPH_DSM_R7 (WCD9378_TAMBORA_BASE+0x2e)
  318. #define WCD9378_CDC_AUX_DSM_A1_0 (WCD9378_TAMBORA_BASE+0x2f)
  319. #define WCD9378_CDC_AUX_DSM_A1_1 (WCD9378_TAMBORA_BASE+0x30)
  320. #define WCD9378_CDC_AUX_DSM_A2_0 (WCD9378_TAMBORA_BASE+0x31)
  321. #define WCD9378_CDC_AUX_DSM_A2_1 (WCD9378_TAMBORA_BASE+0x32)
  322. #define WCD9378_CDC_AUX_DSM_A3_0 (WCD9378_TAMBORA_BASE+0x33)
  323. #define WCD9378_CDC_AUX_DSM_A3_1 (WCD9378_TAMBORA_BASE+0x34)
  324. #define WCD9378_CDC_AUX_DSM_A4_0 (WCD9378_TAMBORA_BASE+0x35)
  325. #define WCD9378_CDC_AUX_DSM_A4_1 (WCD9378_TAMBORA_BASE+0x36)
  326. #define WCD9378_CDC_AUX_DSM_A5_0 (WCD9378_TAMBORA_BASE+0x37)
  327. #define WCD9378_CDC_AUX_DSM_A5_1 (WCD9378_TAMBORA_BASE+0x38)
  328. #define WCD9378_CDC_AUX_DSM_A6_0 (WCD9378_TAMBORA_BASE+0x39)
  329. #define WCD9378_CDC_AUX_DSM_A7_0 (WCD9378_TAMBORA_BASE+0x3a)
  330. #define WCD9378_CDC_AUX_DSM_C_0 (WCD9378_TAMBORA_BASE+0x3b)
  331. #define WCD9378_CDC_AUX_DSM_C_1 (WCD9378_TAMBORA_BASE+0x3c)
  332. #define WCD9378_CDC_AUX_DSM_C_2 (WCD9378_TAMBORA_BASE+0x3d)
  333. #define WCD9378_CDC_AUX_DSM_C_3 (WCD9378_TAMBORA_BASE+0x3e)
  334. #define WCD9378_CDC_AUX_DSM_R1 (WCD9378_TAMBORA_BASE+0x3f)
  335. #define WCD9378_CDC_AUX_DSM_R2 (WCD9378_TAMBORA_BASE+0x40)
  336. #define WCD9378_CDC_AUX_DSM_R3 (WCD9378_TAMBORA_BASE+0x41)
  337. #define WCD9378_CDC_AUX_DSM_R4 (WCD9378_TAMBORA_BASE+0x42)
  338. #define WCD9378_CDC_AUX_DSM_R5 (WCD9378_TAMBORA_BASE+0x43)
  339. #define WCD9378_CDC_AUX_DSM_R6 (WCD9378_TAMBORA_BASE+0x44)
  340. #define WCD9378_CDC_AUX_DSM_R7 (WCD9378_TAMBORA_BASE+0x45)
  341. #define WCD9378_CDC_HPH_GAIN_RX_0 (WCD9378_TAMBORA_BASE+0x46)
  342. #define WCD9378_CDC_HPH_GAIN_RX_1 (WCD9378_TAMBORA_BASE+0x47)
  343. #define WCD9378_CDC_HPH_GAIN_DSD_0 (WCD9378_TAMBORA_BASE+0x48)
  344. #define WCD9378_CDC_HPH_GAIN_DSD_1 (WCD9378_TAMBORA_BASE+0x49)
  345. #define WCD9378_CDC_HPH_GAIN_DSD_2 (WCD9378_TAMBORA_BASE+0x4a)
  346. #define WCD9378_CDC_AUX_GAIN_DSD_0 (WCD9378_TAMBORA_BASE+0x4b)
  347. #define WCD9378_CDC_AUX_GAIN_DSD_1 (WCD9378_TAMBORA_BASE+0x4c)
  348. #define WCD9378_CDC_AUX_GAIN_DSD_2 (WCD9378_TAMBORA_BASE+0x4d)
  349. #define WCD9378_CDC_HPH_GAIN_CTL (WCD9378_TAMBORA_BASE+0x4e)
  350. #define WCD9378_CDC_AUX_GAIN_CTL (WCD9378_TAMBORA_BASE+0x4f)
  351. #define WCD9378_CDC_PATH_CTL (WCD9378_TAMBORA_BASE+0x50)
  352. #define WCD9378_CDC_SWR_CLG (WCD9378_TAMBORA_BASE+0x51)
  353. #define WCD9378_SWR_CLG_BYP (WCD9378_TAMBORA_BASE+0x52)
  354. #define WCD9378_CDC_TX0_CTL (WCD9378_TAMBORA_BASE+0x53)
  355. #define WCD9378_CDC_TX1_CTL (WCD9378_TAMBORA_BASE+0x54)
  356. #define WCD9378_CDC_TX2_CTL (WCD9378_TAMBORA_BASE+0x55)
  357. #define WCD9378_CDC_TX_RST (WCD9378_TAMBORA_BASE+0x56)
  358. #define WCD9378_CDC_REQ_CTL (WCD9378_TAMBORA_BASE+0x57)
  359. #define WCD9378_CDC_RST (WCD9378_TAMBORA_BASE+0x58)
  360. #define WCD9378_CDC_AMIC_CTL (WCD9378_TAMBORA_BASE+0x5a)
  361. #define WCD9378_CDC_DMIC_CTL (WCD9378_TAMBORA_BASE+0x5b)
  362. #define WCD9378_CDC_DMIC1_CTL (WCD9378_TAMBORA_BASE+0x5c)
  363. #define WCD9378_CDC_DMIC2_CTL (WCD9378_TAMBORA_BASE+0x5d)
  364. #define WCD9378_CDC_DMIC3_CTL (WCD9378_TAMBORA_BASE+0x5e)
  365. #define WCD9378_EFUSE_PRG_CTL (WCD9378_TAMBORA_BASE+0x60)
  366. #define WCD9378_EFUSE_CTL (WCD9378_TAMBORA_BASE+0x61)
  367. #define WCD9378_CDC_DMIC_RATE_1_2 (WCD9378_TAMBORA_BASE+0x62)
  368. #define WCD9378_CDC_DMIC_RATE_3_4 (WCD9378_TAMBORA_BASE+0x63)
  369. #define WCD9378_PDM_WD_EN_OVRD (WCD9378_TAMBORA_BASE+0x64)
  370. #define WCD9378_PDM_WD_CTL0 (WCD9378_TAMBORA_BASE+0x65)
  371. #define WCD9378_PDM_WD_CTL1 (WCD9378_TAMBORA_BASE+0x66)
  372. #define WCD9378_PDM_WD_CTL2 (WCD9378_TAMBORA_BASE+0x67)
  373. #define WCD9378_RAMP_CTL (WCD9378_TAMBORA_BASE+0x68)
  374. #define WCD9378_ACT_DET_CTL (WCD9378_TAMBORA_BASE+0x69)
  375. #define WCD9378_ACT_DET_HOOKUP0 (WCD9378_TAMBORA_BASE+0x6a)
  376. #define WCD9378_ACT_DET_HOOKUP1 (WCD9378_TAMBORA_BASE+0x6b)
  377. #define WCD9378_ACT_DET_HOOKUP2 (WCD9378_TAMBORA_BASE+0x6c)
  378. #define WCD9378_ACT_DET_DLY_BUF_EN (WCD9378_TAMBORA_BASE+0x6d)
  379. #define WCD9378_INTR_MODE (WCD9378_TAMBORA_BASE+0x6e)
  380. #define WCD9378_INTR_STATUS_0 (WCD9378_TAMBORA_BASE+0x6f)
  381. #define WCD9378_INTR_STATUS_1 (WCD9378_TAMBORA_BASE+0x70)
  382. #define WCD9378_INTR_STATUS_2 (WCD9378_TAMBORA_BASE+0x71)
  383. #define WCD9378_INTR_STATUS_3 (WCD9378_TAMBORA_BASE+0x72)
  384. #define WCD9378_INTR_MASK_0 (WCD9378_TAMBORA_BASE+0x73)
  385. #define WCD9378_INTR_MASK_1 (WCD9378_TAMBORA_BASE+0x74)
  386. #define WCD9378_INTR_MASK_2 (WCD9378_TAMBORA_BASE+0x75)
  387. #define WCD9378_INTR_MASK_3 (WCD9378_TAMBORA_BASE+0x76)
  388. #define WCD9378_INTR_SET_0 (WCD9378_TAMBORA_BASE+0x77)
  389. #define WCD9378_INTR_SET_1 (WCD9378_TAMBORA_BASE+0x78)
  390. #define WCD9378_INTR_SET_2 (WCD9378_TAMBORA_BASE+0x79)
  391. #define WCD9378_INTR_SET_3 (WCD9378_TAMBORA_BASE+0x7a)
  392. #define WCD9378_INTR_TEST_0 (WCD9378_TAMBORA_BASE+0x7b)
  393. #define WCD9378_INTR_TEST_1 (WCD9378_TAMBORA_BASE+0x7c)
  394. #define WCD9378_INTR_TEST_2 (WCD9378_TAMBORA_BASE+0x7d)
  395. #define WCD9378_INTR_TEST_3 (WCD9378_TAMBORA_BASE+0x7e)
  396. #define WCD9378_TX_MODE_DBG_EN (WCD9378_TAMBORA_BASE+0x7f)
  397. #define WCD9378_TX_MODE_DBG_0_1 (WCD9378_TAMBORA_BASE+0x80)
  398. #define WCD9378_TX_MODE_DBG_2_3 (WCD9378_TAMBORA_BASE+0x81)
  399. #define WCD9378_LB_IN_SEL_CTL (WCD9378_TAMBORA_BASE+0x82)
  400. #define WCD9378_LOOP_BACK_MODE (WCD9378_TAMBORA_BASE+0x83)
  401. #define WCD9378_SWR_DAC_TEST (WCD9378_TAMBORA_BASE+0x84)
  402. #define WCD9378_SWR_HM_TEST_RX_0 (WCD9378_TAMBORA_BASE+0x85)
  403. #define WCD9378_SWR_HM_TEST_TX_0 (WCD9378_TAMBORA_BASE+0x86)
  404. #define WCD9378_SWR_HM_TEST_RX_1 (WCD9378_TAMBORA_BASE+0x87)
  405. #define WCD9378_SWR_HM_TEST_TX_1 (WCD9378_TAMBORA_BASE+0x88)
  406. #define WCD9378_SWR_HM_TEST_0 (WCD9378_TAMBORA_BASE+0x8a)
  407. #define WCD9378_PAD_CTL_SWR_0 (WCD9378_TAMBORA_BASE+0x8c)
  408. #define WCD9378_PAD_CTL_SWR_1 (WCD9378_TAMBORA_BASE+0x8d)
  409. #define WCD9378_I2C_CTL (WCD9378_TAMBORA_BASE+0x8e)
  410. #define WCD9378_LEGACY_SW_MODE (WCD9378_TAMBORA_BASE+0x8f)
  411. #define WCD9378_EFUSE_TEST_CTL_0 (WCD9378_TAMBORA_BASE+0x90)
  412. #define WCD9378_EFUSE_TEST_CTL_1 (WCD9378_TAMBORA_BASE+0x91)
  413. #define WCD9378_EFUSE_T_DATA_0 (WCD9378_TAMBORA_BASE+0x92)
  414. #define WCD9378_PAD_CTL_PDM_RX0 (WCD9378_TAMBORA_BASE+0x94)
  415. #define WCD9378_PAD_CTL_PDM_RX1 (WCD9378_TAMBORA_BASE+0x95)
  416. #define WCD9378_PAD_CTL_PDM_TX0 (WCD9378_TAMBORA_BASE+0x96)
  417. #define WCD9378_PAD_CTL_PDM_TX1 (WCD9378_TAMBORA_BASE+0x97)
  418. #define WCD9378_PAD_INP_DIS_0 (WCD9378_TAMBORA_BASE+0x99)
  419. #define WCD9378_DRIVE_STRENGTH_0 (WCD9378_TAMBORA_BASE+0x9b)
  420. #define WCD9378_DRIVE_STRENGTH_1 (WCD9378_TAMBORA_BASE+0x9c)
  421. #define WCD9378_RX_DATA_EDGE_CTL (WCD9378_TAMBORA_BASE+0x9e)
  422. #define WCD9378_TX_DATA_EDGE_CTL (WCD9378_TAMBORA_BASE+0x9f)
  423. #define WCD9378_GPIO_MODE (WCD9378_TAMBORA_BASE+0xa0)
  424. #define WCD9378_PIN_CTL_OE (WCD9378_TAMBORA_BASE+0xa1)
  425. #define WCD9378_PIN_CTL_DATA_0 (WCD9378_TAMBORA_BASE+0xa2)
  426. #define WCD9378_PIN_STATUS_0 (WCD9378_TAMBORA_BASE+0xa4)
  427. #define WCD9378_DIG_DEBUG_CTL (WCD9378_TAMBORA_BASE+0xa6)
  428. #define WCD9378_DIG_DEBUG_EN (WCD9378_TAMBORA_BASE+0xa7)
  429. #define WCD9378_ANA_CSR_DBG_ADD (WCD9378_TAMBORA_BASE+0xa8)
  430. #define WCD9378_ANA_CSR_DBG_CTL (WCD9378_TAMBORA_BASE+0xa9)
  431. #define WCD9378_SSP_DBG (WCD9378_TAMBORA_BASE+0xaa)
  432. #define WCD9378_MODE_STATUS_0 (WCD9378_TAMBORA_BASE+0xab)
  433. #define WCD9378_MODE_STATUS_1 (WCD9378_TAMBORA_BASE+0xac)
  434. #define WCD9378_SPARE_0 (WCD9378_TAMBORA_BASE+0xad)
  435. #define WCD9378_SPARE_1 (WCD9378_TAMBORA_BASE+0xae)
  436. #define WCD9378_SPARE_2 (WCD9378_TAMBORA_BASE+0xaf)
  437. #define WCD9378_EFUSE_REG_0 (WCD9378_TAMBORA_BASE+0xb0)
  438. #define WCD9378_EFUSE_REG_1 (WCD9378_TAMBORA_BASE+0xb1)
  439. #define WCD9378_EFUSE_REG_2 (WCD9378_TAMBORA_BASE+0xb2)
  440. #define WCD9378_EFUSE_REG_3 (WCD9378_TAMBORA_BASE+0xb3)
  441. #define WCD9378_EFUSE_REG_4 (WCD9378_TAMBORA_BASE+0xb4)
  442. #define WCD9378_EFUSE_REG_5 (WCD9378_TAMBORA_BASE+0xb5)
  443. #define WCD9378_EFUSE_REG_6 (WCD9378_TAMBORA_BASE+0xb6)
  444. #define WCD9378_EFUSE_REG_7 (WCD9378_TAMBORA_BASE+0xb7)
  445. #define WCD9378_EFUSE_REG_8 (WCD9378_TAMBORA_BASE+0xb8)
  446. #define WCD9378_EFUSE_REG_9 (WCD9378_TAMBORA_BASE+0xb9)
  447. #define WCD9378_EFUSE_REG_10 (WCD9378_TAMBORA_BASE+0xba)
  448. #define WCD9378_EFUSE_REG_11 (WCD9378_TAMBORA_BASE+0xbb)
  449. #define WCD9378_EFUSE_REG_12 (WCD9378_TAMBORA_BASE+0xbc)
  450. #define WCD9378_EFUSE_REG_13 (WCD9378_TAMBORA_BASE+0xbd)
  451. #define WCD9378_EFUSE_REG_14 (WCD9378_TAMBORA_BASE+0xbe)
  452. #define WCD9378_EFUSE_REG_15 (WCD9378_TAMBORA_BASE+0xbf)
  453. #define WCD9378_EFUSE_REG_16 (WCD9378_TAMBORA_BASE+0xc0)
  454. #define WCD9378_EFUSE_REG_17 (WCD9378_TAMBORA_BASE+0xc1)
  455. #define WCD9378_EFUSE_REG_18 (WCD9378_TAMBORA_BASE+0xc2)
  456. #define WCD9378_EFUSE_REG_19 (WCD9378_TAMBORA_BASE+0xc3)
  457. #define WCD9378_EFUSE_REG_20 (WCD9378_TAMBORA_BASE+0xc4)
  458. #define WCD9378_EFUSE_REG_21 (WCD9378_TAMBORA_BASE+0xc5)
  459. #define WCD9378_EFUSE_REG_22 (WCD9378_TAMBORA_BASE+0xc6)
  460. #define WCD9378_EFUSE_REG_23 (WCD9378_TAMBORA_BASE+0xc7)
  461. #define WCD9378_EFUSE_REG_24 (WCD9378_TAMBORA_BASE+0xc8)
  462. #define WCD9378_EFUSE_REG_25 (WCD9378_TAMBORA_BASE+0xc9)
  463. #define WCD9378_EFUSE_REG_26 (WCD9378_TAMBORA_BASE+0xca)
  464. #define WCD9378_EFUSE_REG_27 (WCD9378_TAMBORA_BASE+0xcb)
  465. #define WCD9378_EFUSE_REG_28 (WCD9378_TAMBORA_BASE+0xcc)
  466. #define WCD9378_EFUSE_REG_29 (WCD9378_TAMBORA_BASE+0xcd)
  467. #define WCD9378_EFUSE_REG_30 (WCD9378_TAMBORA_BASE+0xce)
  468. #define WCD9378_EFUSE_REG_31 (WCD9378_TAMBORA_BASE+0xcf)
  469. #define WCD9378_TX_REQ_FB_CTL_2 (WCD9378_TAMBORA_BASE+0xd2)
  470. #define WCD9378_TX_REQ_FB_CTL_3 (WCD9378_TAMBORA_BASE+0xd3)
  471. #define WCD9378_TX_REQ_FB_CTL_4 (WCD9378_TAMBORA_BASE+0xd4)
  472. #define WCD9378_DEM_BYPASS_DATA0 (WCD9378_TAMBORA_BASE+0xd5)
  473. #define WCD9378_DEM_BYPASS_DATA1 (WCD9378_TAMBORA_BASE+0xd6)
  474. #define WCD9378_DEM_BYPASS_DATA2 (WCD9378_TAMBORA_BASE+0xd7)
  475. #define WCD9378_DEM_BYPASS_DATA3 (WCD9378_TAMBORA_BASE+0xd8)
  476. #define WCD9378_RX0_PCM_RAMP_STEP (WCD9378_TAMBORA_BASE+0xd9)
  477. #define WCD9378_RX0_DSD_RAMP_STEP (WCD9378_TAMBORA_BASE+0xda)
  478. #define WCD9378_RX1_PCM_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdb)
  479. #define WCD9378_RX1_DSD_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdc)
  480. #define WCD9378_RX2_RAMP_STEP (WCD9378_TAMBORA_BASE+0xdd)
  481. #define WCD9378_PLATFORM_CTL (WCD9378_TAMBORA_BASE+0xf0)
  482. #define WCD9378_CLK_DIV_CFG (WCD9378_TAMBORA_BASE+0xf1)
  483. #define WCD9378_DRE_DLY_VAL (WCD9378_TAMBORA_BASE+0xf2)
  484. #define WCD9378_SEQR_BASE (WCD9378_BASE+0x180501)
  485. #define WCD9378_SYS_USAGE_CTRL (WCD9378_SEQR_BASE+0x01)
  486. #define WCD9378_SURGE_CTL (WCD9378_SEQR_BASE+0x02)
  487. #define WCD9378_SEQ_CTL (WCD9378_SEQR_BASE+0x03)
  488. #define WCD9378_HPH_UP_T0 (WCD9378_SEQR_BASE+0x10)
  489. #define WCD9378_HPH_UP_T1 (WCD9378_SEQR_BASE+0x11)
  490. #define WCD9378_HPH_UP_T2 (WCD9378_SEQR_BASE+0x12)
  491. #define WCD9378_HPH_UP_T3 (WCD9378_SEQR_BASE+0x13)
  492. #define WCD9378_HPH_UP_T4 (WCD9378_SEQR_BASE+0x14)
  493. #define WCD9378_HPH_UP_T5 (WCD9378_SEQR_BASE+0x15)
  494. #define WCD9378_HPH_UP_T6 (WCD9378_SEQR_BASE+0x16)
  495. #define WCD9378_HPH_UP_T7 (WCD9378_SEQR_BASE+0x17)
  496. #define WCD9378_HPH_UP_T8 (WCD9378_SEQR_BASE+0x18)
  497. #define WCD9378_HPH_UP_T9 (WCD9378_SEQR_BASE+0x19)
  498. #define WCD9378_HPH_UP_T10 (WCD9378_SEQR_BASE+0x1a)
  499. #define WCD9378_HPH_DN_T0 (WCD9378_SEQR_BASE+0x1b)
  500. #define WCD9378_HPH_DN_T1 (WCD9378_SEQR_BASE+0x1c)
  501. #define WCD9378_HPH_DN_T2 (WCD9378_SEQR_BASE+0x1d)
  502. #define WCD9378_HPH_DN_T3 (WCD9378_SEQR_BASE+0x1e)
  503. #define WCD9378_HPH_DN_T4 (WCD9378_SEQR_BASE+0x1f)
  504. #define WCD9378_HPH_DN_T5 (WCD9378_SEQR_BASE+0x20)
  505. #define WCD9378_HPH_DN_T6 (WCD9378_SEQR_BASE+0x21)
  506. #define WCD9378_HPH_DN_T7 (WCD9378_SEQR_BASE+0x22)
  507. #define WCD9378_HPH_DN_T8 (WCD9378_SEQR_BASE+0x23)
  508. #define WCD9378_HPH_DN_T9 (WCD9378_SEQR_BASE+0x24)
  509. #define WCD9378_HPH_DN_T10 (WCD9378_SEQR_BASE+0x25)
  510. #define WCD9378_HPH_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x26)
  511. #define WCD9378_HPH_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x27)
  512. #define WCD9378_HPH_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x28)
  513. #define WCD9378_HPH_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x29)
  514. #define WCD9378_HPH_UP_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x2a)
  515. #define WCD9378_HPH_UP_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x2b)
  516. #define WCD9378_HPH_UP_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x2c)
  517. #define WCD9378_HPH_UP_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x2d)
  518. #define WCD9378_HPH_UP_STAGE_LOC_8 (WCD9378_SEQR_BASE+0x2e)
  519. #define WCD9378_HPH_UP_STAGE_LOC_9 (WCD9378_SEQR_BASE+0x2f)
  520. #define WCD9378_HPH_UP_STAGE_LOC_10 (WCD9378_SEQR_BASE+0x30)
  521. #define WCD9378_HPH_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x31)
  522. #define WCD9378_HPH_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x32)
  523. #define WCD9378_HPH_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x33)
  524. #define WCD9378_HPH_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x34)
  525. #define WCD9378_HPH_DN_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x35)
  526. #define WCD9378_HPH_DN_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x36)
  527. #define WCD9378_HPH_DN_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x37)
  528. #define WCD9378_HPH_DN_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x38)
  529. #define WCD9378_HPH_DN_STAGE_LOC_8 (WCD9378_SEQR_BASE+0x39)
  530. #define WCD9378_HPH_DN_STAGE_LOC_9 (WCD9378_SEQR_BASE+0x3a)
  531. #define WCD9378_HPH_DN_STAGE_LOC_10 (WCD9378_SEQR_BASE+0x3b)
  532. #define WCD9378_SA_UP_T0 (WCD9378_SEQR_BASE+0x40)
  533. #define WCD9378_SA_UP_T1 (WCD9378_SEQR_BASE+0x41)
  534. #define WCD9378_SA_UP_T2 (WCD9378_SEQR_BASE+0x42)
  535. #define WCD9378_SA_UP_T3 (WCD9378_SEQR_BASE+0x43)
  536. #define WCD9378_SA_UP_T4 (WCD9378_SEQR_BASE+0x44)
  537. #define WCD9378_SA_UP_T5 (WCD9378_SEQR_BASE+0x45)
  538. #define WCD9378_SA_UP_T6 (WCD9378_SEQR_BASE+0x46)
  539. #define WCD9378_SA_UP_T7 (WCD9378_SEQR_BASE+0x47)
  540. #define WCD9378_SA_DN_T0 (WCD9378_SEQR_BASE+0x48)
  541. #define WCD9378_SA_DN_T1 (WCD9378_SEQR_BASE+0x49)
  542. #define WCD9378_SA_DN_T2 (WCD9378_SEQR_BASE+0x4a)
  543. #define WCD9378_SA_DN_T3 (WCD9378_SEQR_BASE+0x4b)
  544. #define WCD9378_SA_DN_T4 (WCD9378_SEQR_BASE+0x4c)
  545. #define WCD9378_SA_DN_T5 (WCD9378_SEQR_BASE+0x4d)
  546. #define WCD9378_SA_DN_T6 (WCD9378_SEQR_BASE+0x4e)
  547. #define WCD9378_SA_DN_T7 (WCD9378_SEQR_BASE+0x4f)
  548. #define WCD9378_SA_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x50)
  549. #define WCD9378_SA_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x51)
  550. #define WCD9378_SA_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x52)
  551. #define WCD9378_SA_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x53)
  552. #define WCD9378_SA_UP_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x54)
  553. #define WCD9378_SA_UP_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x55)
  554. #define WCD9378_SA_UP_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x56)
  555. #define WCD9378_SA_UP_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x57)
  556. #define WCD9378_SA_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x58)
  557. #define WCD9378_SA_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x59)
  558. #define WCD9378_SA_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x5a)
  559. #define WCD9378_SA_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x5b)
  560. #define WCD9378_SA_DN_STAGE_LOC_4 (WCD9378_SEQR_BASE+0x5c)
  561. #define WCD9378_SA_DN_STAGE_LOC_5 (WCD9378_SEQR_BASE+0x5d)
  562. #define WCD9378_SA_DN_STAGE_LOC_6 (WCD9378_SEQR_BASE+0x5e)
  563. #define WCD9378_SA_DN_STAGE_LOC_7 (WCD9378_SEQR_BASE+0x5f)
  564. #define WCD9378_TX0_UP_T0 (WCD9378_SEQR_BASE+0x60)
  565. #define WCD9378_TX0_UP_T1 (WCD9378_SEQR_BASE+0x61)
  566. #define WCD9378_TX0_UP_T2 (WCD9378_SEQR_BASE+0x62)
  567. #define WCD9378_TX0_UP_T3 (WCD9378_SEQR_BASE+0x63)
  568. #define WCD9378_TX0_DN_T0 (WCD9378_SEQR_BASE+0x64)
  569. #define WCD9378_TX0_DN_T1 (WCD9378_SEQR_BASE+0x65)
  570. #define WCD9378_TX0_DN_T2 (WCD9378_SEQR_BASE+0x66)
  571. #define WCD9378_TX0_DN_T3 (WCD9378_SEQR_BASE+0x67)
  572. #define WCD9378_TX0_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x68)
  573. #define WCD9378_TX0_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x69)
  574. #define WCD9378_TX0_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x6a)
  575. #define WCD9378_TX0_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x6b)
  576. #define WCD9378_TX0_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x6c)
  577. #define WCD9378_TX0_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x6d)
  578. #define WCD9378_TX0_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x6e)
  579. #define WCD9378_TX0_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x6f)
  580. #define WCD9378_TX1_UP_T0 (WCD9378_SEQR_BASE+0x70)
  581. #define WCD9378_TX1_UP_T1 (WCD9378_SEQR_BASE+0x71)
  582. #define WCD9378_TX1_UP_T2 (WCD9378_SEQR_BASE+0x72)
  583. #define WCD9378_TX1_UP_T3 (WCD9378_SEQR_BASE+0x73)
  584. #define WCD9378_TX1_DN_T0 (WCD9378_SEQR_BASE+0x74)
  585. #define WCD9378_TX1_DN_T1 (WCD9378_SEQR_BASE+0x75)
  586. #define WCD9378_TX1_DN_T2 (WCD9378_SEQR_BASE+0x76)
  587. #define WCD9378_TX1_DN_T3 (WCD9378_SEQR_BASE+0x77)
  588. #define WCD9378_TX1_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x78)
  589. #define WCD9378_TX1_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x79)
  590. #define WCD9378_TX1_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x7a)
  591. #define WCD9378_TX1_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x7b)
  592. #define WCD9378_TX1_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x7c)
  593. #define WCD9378_TX1_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x7d)
  594. #define WCD9378_TX1_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x7e)
  595. #define WCD9378_TX1_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x7f)
  596. #define WCD9378_TX2_UP_T0 (WCD9378_SEQR_BASE+0x80)
  597. #define WCD9378_TX2_UP_T1 (WCD9378_SEQR_BASE+0x81)
  598. #define WCD9378_TX2_UP_T2 (WCD9378_SEQR_BASE+0x82)
  599. #define WCD9378_TX2_UP_T3 (WCD9378_SEQR_BASE+0x83)
  600. #define WCD9378_TX2_DN_T0 (WCD9378_SEQR_BASE+0x84)
  601. #define WCD9378_TX2_DN_T1 (WCD9378_SEQR_BASE+0x85)
  602. #define WCD9378_TX2_DN_T2 (WCD9378_SEQR_BASE+0x86)
  603. #define WCD9378_TX2_DN_T3 (WCD9378_SEQR_BASE+0x87)
  604. #define WCD9378_TX2_UP_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x88)
  605. #define WCD9378_TX2_UP_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x89)
  606. #define WCD9378_TX2_UP_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x8a)
  607. #define WCD9378_TX2_UP_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x8b)
  608. #define WCD9378_TX2_DN_STAGE_LOC_0 (WCD9378_SEQR_BASE+0x8c)
  609. #define WCD9378_TX2_DN_STAGE_LOC_1 (WCD9378_SEQR_BASE+0x8d)
  610. #define WCD9378_TX2_DN_STAGE_LOC_2 (WCD9378_SEQR_BASE+0x8e)
  611. #define WCD9378_TX2_DN_STAGE_LOC_3 (WCD9378_SEQR_BASE+0x8f)
  612. #define WCD9378_SEQ_HPH_STAT (WCD9378_SEQR_BASE+0x90)
  613. #define WCD9378_SEQ_SA_STAT (WCD9378_SEQR_BASE+0x91)
  614. #define WCD9378_SEQ_TX0_STAT (WCD9378_SEQR_BASE+0x92)
  615. #define WCD9378_SEQ_TX1_STAT (WCD9378_SEQR_BASE+0x93)
  616. #define WCD9378_SEQ_TX2_STAT (WCD9378_SEQR_BASE+0x94)
  617. #define WCD9378_MICB_REMAP_TABLE_VAL_0 (WCD9378_SEQR_BASE+0xa0)
  618. #define WCD9378_MICB_REMAP_TABLE_VAL_1 (WCD9378_SEQR_BASE+0xa1)
  619. #define WCD9378_MICB_REMAP_TABLE_VAL_2 (WCD9378_SEQR_BASE+0xa2)
  620. #define WCD9378_MICB_REMAP_TABLE_VAL_3 (WCD9378_SEQR_BASE+0xa3)
  621. #define WCD9378_MICB_REMAP_TABLE_VAL_4 (WCD9378_SEQR_BASE+0xa4)
  622. #define WCD9378_MICB_REMAP_TABLE_VAL_5 (WCD9378_SEQR_BASE+0xa5)
  623. #define WCD9378_MICB_REMAP_TABLE_VAL_6 (WCD9378_SEQR_BASE+0xa6)
  624. #define WCD9378_MICB_REMAP_TABLE_VAL_7 (WCD9378_SEQR_BASE+0xa7)
  625. #define WCD9378_MICB_REMAP_TABLE_VAL_8 (WCD9378_SEQR_BASE+0xa8)
  626. #define WCD9378_MICB_REMAP_TABLE_VAL_9 (WCD9378_SEQR_BASE+0xa9)
  627. #define WCD9378_MICB_REMAP_TABLE_VAL_10 (WCD9378_SEQR_BASE+0xaa)
  628. #define WCD9378_MICB_REMAP_TABLE_VAL_11 (WCD9378_SEQR_BASE+0xab)
  629. #define WCD9378_MICB_REMAP_TABLE_VAL_12 (WCD9378_SEQR_BASE+0xac)
  630. #define WCD9378_MICB_REMAP_TABLE_VAL_13 (WCD9378_SEQR_BASE+0xad)
  631. #define WCD9378_MICB_REMAP_TABLE_VAL_14 (WCD9378_SEQR_BASE+0xae)
  632. #define WCD9378_MICB_REMAP_TABLE_VAL_15 (WCD9378_SEQR_BASE+0xaf)
  633. #define WCD9378_SM0_MB_SEL (WCD9378_SEQR_BASE+0xb0)
  634. #define WCD9378_SM1_MB_SEL (WCD9378_SEQR_BASE+0xb1)
  635. #define WCD9378_SM2_MB_SEL (WCD9378_SEQR_BASE+0xb2)
  636. #define WCD9378_MB_PULLUP_EN (WCD9378_SEQR_BASE+0xb3)
  637. #define WCD9378_BYP_EN_CTL0 (WCD9378_SEQR_BASE+0xc0)
  638. #define WCD9378_BYP_EN_CTL1 (WCD9378_SEQR_BASE+0xc1)
  639. #define WCD9378_BYP_EN_CTL2 (WCD9378_SEQR_BASE+0xc2)
  640. #define WCD9378_SEQ_OVRRIDE_CTL0 (WCD9378_SEQR_BASE+0xc3)
  641. #define WCD9378_SEQ_OVRRIDE_CTL1 (WCD9378_SEQR_BASE+0xc4)
  642. #define WCD9378_SEQ_OVRRIDE_CTL2 (WCD9378_SEQR_BASE+0xc5)
  643. #define WCD9378_HPH_SEQ_OVRRIDE_CTL0 (WCD9378_SEQR_BASE+0xc7)
  644. #define WCD9378_HPH_SEQ_OVRRIDE_CTL1 (WCD9378_SEQR_BASE+0xc8)
  645. #define WCD9378_SA_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xc9)
  646. #define WCD9378_TX0_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xca)
  647. #define WCD9378_TX1_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xcb)
  648. #define WCD9378_TX2_SEQ_OVRRIDE_CTL (WCD9378_SEQR_BASE+0xcc)
  649. #define WCD9378_FORCE_CTL (WCD9378_SEQR_BASE+0xcd)
  650. #define WCD9378_MBHC_BASE (WCD9378_BASE+0x180601)
  651. #define WCD9378_DEVICE_DET (WCD9378_MBHC_BASE+0x01)
  652. #define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x10)
  653. #define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_0 (WCD9378_MBHC_BASE+0x11)
  654. #define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x12)
  655. #define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_0 (WCD9378_MBHC_BASE+0x13)
  656. #define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x14)
  657. #define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_0 (WCD9378_MBHC_BASE+0x15)
  658. #define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x20)
  659. #define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_1 (WCD9378_MBHC_BASE+0x21)
  660. #define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x22)
  661. #define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_1 (WCD9378_MBHC_BASE+0x23)
  662. #define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x24)
  663. #define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_1 (WCD9378_MBHC_BASE+0x25)
  664. #define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x30)
  665. #define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_2 (WCD9378_MBHC_BASE+0x31)
  666. #define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x32)
  667. #define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_2 (WCD9378_MBHC_BASE+0x33)
  668. #define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x34)
  669. #define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_2 (WCD9378_MBHC_BASE+0x35)
  670. #define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x40)
  671. #define WCD9378_TYPE0_WRAP_OSCNX_TPRESS_MAX_3 (WCD9378_MBHC_BASE+0x41)
  672. #define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x42)
  673. #define WCD9378_TYPE0_WRAP_OSCNX_TRELEASE_MAX_3 (WCD9378_MBHC_BASE+0x43)
  674. #define WCD9378_TYPE0_WRAP_OSCNX_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x44)
  675. #define WCD9378_TYPE0_WRAP_OSCNX_OUTPUT_SEL_3 (WCD9378_MBHC_BASE+0x45)
  676. #define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x50)
  677. #define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_0 (WCD9378_MBHC_BASE+0x51)
  678. #define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x52)
  679. #define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_0 (WCD9378_MBHC_BASE+0x53)
  680. #define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x54)
  681. #define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_0 (WCD9378_MBHC_BASE+0x55)
  682. #define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_0 (WCD9378_MBHC_BASE+0x56)
  683. #define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_0 (WCD9378_MBHC_BASE+0x57)
  684. #define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x58)
  685. #define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_0 (WCD9378_MBHC_BASE+0x59)
  686. #define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_0 (WCD9378_MBHC_BASE+0x5b)
  687. #define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_0 (WCD9378_MBHC_BASE+0x5c)
  688. #define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x60)
  689. #define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_1 (WCD9378_MBHC_BASE+0x61)
  690. #define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x62)
  691. #define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_1 (WCD9378_MBHC_BASE+0x63)
  692. #define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x64)
  693. #define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_1 (WCD9378_MBHC_BASE+0x65)
  694. #define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_1 (WCD9378_MBHC_BASE+0x66)
  695. #define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_1 (WCD9378_MBHC_BASE+0x67)
  696. #define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x68)
  697. #define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_1 (WCD9378_MBHC_BASE+0x69)
  698. #define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_1 (WCD9378_MBHC_BASE+0x6b)
  699. #define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_1 (WCD9378_MBHC_BASE+0x6c)
  700. #define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x70)
  701. #define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_2 (WCD9378_MBHC_BASE+0x71)
  702. #define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x72)
  703. #define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_2 (WCD9378_MBHC_BASE+0x73)
  704. #define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x74)
  705. #define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_2 (WCD9378_MBHC_BASE+0x75)
  706. #define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_2 (WCD9378_MBHC_BASE+0x76)
  707. #define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_2 (WCD9378_MBHC_BASE+0x77)
  708. #define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x78)
  709. #define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_2 (WCD9378_MBHC_BASE+0x79)
  710. #define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_2 (WCD9378_MBHC_BASE+0x7b)
  711. #define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_2 (WCD9378_MBHC_BASE+0x7c)
  712. #define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x80)
  713. #define WCD9378_TYPE1_WRAP_OSCNX_TPRESS_MAX_3 (WCD9378_MBHC_BASE+0x81)
  714. #define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x82)
  715. #define WCD9378_TYPE1_WRAP_OSCNX_TRELEASE_MAX_3 (WCD9378_MBHC_BASE+0x83)
  716. #define WCD9378_TYPE1_WRAP_OSCNX_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x84)
  717. #define WCD9378_TYPE1_WRAP_OSCNX_OUTPUT_SEL_3 (WCD9378_MBHC_BASE+0x85)
  718. #define WCD9378_TYPE1_WRAP_HOLD_TPRESS_MIN_3 (WCD9378_MBHC_BASE+0x86)
  719. #define WCD9378_TYPE1_WRAP_HOLD_TRELEASE_MIN_3 (WCD9378_MBHC_BASE+0x87)
  720. #define WCD9378_TYPE1_WRAP_HOLD_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x88)
  721. #define WCD9378_TYPE1_WRAP_RO_TDEBOUNCE_3 (WCD9378_MBHC_BASE+0x89)
  722. #define WCD9378_TYPE1_WRAP_RO_HDL_BT_ASSIGN_3 (WCD9378_MBHC_BASE+0x8b)
  723. #define WCD9378_TYPE1_WRAP_RTC_OOC_SEL_3 (WCD9378_MBHC_BASE+0x8c)
  724. #define WCD9378_SDCA_MESSAGE_GATE (WCD9378_MBHC_BASE+0x8d)
  725. #define WCD9378_MBHC_DATA_IN_EDGE (WCD9378_MBHC_BASE+0x90)
  726. #define WCD9378_MBHC_RESET (WCD9378_MBHC_BASE+0x91)
  727. #define WCD9378_MBHC_DEBUG (WCD9378_MBHC_BASE+0x92)
  728. #define WCD9378_MBHC_DEBUG_UMP_0 (WCD9378_MBHC_BASE+0x93)
  729. #define WCD9378_MBHC_DEBUG_UMP_1 (WCD9378_MBHC_BASE+0x94)
  730. #define WCD9378_MBHC_DEBUG_UMP_2 (WCD9378_MBHC_BASE+0x95)
  731. #define WCD9378_HID_BASE (WCD9378_BASE+0x400001)
  732. #define WCD9378_HID_FUNC_EXT_ID_0 (WCD9378_HID_BASE+0x48)
  733. #define WCD9378_HID_FUNC_EXT_ID_1 (WCD9378_HID_BASE+0x49)
  734. #define WCD9378_HID_FUNC_EXT_VER (WCD9378_HID_BASE+0x50)
  735. #define WCD9378_HID_FUNC_STAT (WCD9378_HID_BASE+0x80000)
  736. #define WCD9378_HID_CUR_OWNER (WCD9378_HID_BASE+0x80080)
  737. #define WCD9378_HID_MSG_OFFSET (WCD9378_HID_BASE+0x80090)
  738. #define WCD9378_HID_MSG_LENGTH (WCD9378_HID_BASE+0x80098)
  739. #define WCD9378_HID_DEV_MANU_ID_0 (WCD9378_HID_BASE+0x100060)
  740. #define WCD9378_HID_DEV_MANU_ID_1 (WCD9378_HID_BASE+0x100061)
  741. #define WCD9378_HID_DEV_PART_ID_0 (WCD9378_HID_BASE+0x100068)
  742. #define WCD9378_HID_DEV_PART_ID_1 (WCD9378_HID_BASE+0x100069)
  743. #define WCD9378_HID_DEV_VER (WCD9378_HID_BASE+0x100070)
  744. #define WCD9378_SMP_AMP_BASE (WCD9378_BASE+0x800001)
  745. #define WCD9378_SMP_AMP_FUNC_EXT_ID_0 (WCD9378_SMP_AMP_BASE+0x48)
  746. #define WCD9378_SMP_AMP_FUNC_EXT_ID_1 (WCD9378_SMP_AMP_BASE+0x49)
  747. #define WCD9378_SMP_AMP_FUNC_EXT_VER (WCD9378_SMP_AMP_BASE+0x50)
  748. #define WCD9378_XU22_BYP (WCD9378_SMP_AMP_BASE+0x188)
  749. #define WCD9378_PDE22_REQ_PS (WCD9378_SMP_AMP_BASE+0x208)
  750. #define WCD9378_FU23_MUTE (WCD9378_SMP_AMP_BASE+0x388)
  751. #define WCD9378_PDE23_REQ_PS (WCD9378_SMP_AMP_BASE+0x408)
  752. #define WCD9378_SMP_AMP_FUNC_STAT (WCD9378_SMP_AMP_BASE+0x80000)
  753. #define WCD9378_FUNC_ACT (WCD9378_SMP_AMP_BASE+0x80008)
  754. #define WCD9378_PDE22_ACT_PS (WCD9378_SMP_AMP_BASE+0x80200)
  755. #define WCD9378_SAPU29_PROT_MODE (WCD9378_SMP_AMP_BASE+0x80280)
  756. #define WCD9378_SAPU29_PROT_STAT (WCD9378_SMP_AMP_BASE+0x80288)
  757. #define WCD9378_PDE23_ACT_PS (WCD9378_SMP_AMP_BASE+0x80400)
  758. #define WCD9378_SMP_AMP_DEV_MANU_ID_0 (WCD9378_SMP_AMP_BASE+0x100060)
  759. #define WCD9378_SMP_AMP_DEV_MANU_ID_1 (WCD9378_SMP_AMP_BASE+0x100061)
  760. #define WCD9378_SMP_AMP_DEV_PART_ID_0 (WCD9378_SMP_AMP_BASE+0x100068)
  761. #define WCD9378_SMP_AMP_DEV_PART_ID_1 (WCD9378_SMP_AMP_BASE+0x100069)
  762. #define WCD9378_SMP_AMP_DEV_VER (WCD9378_SMP_AMP_BASE+0x100070)
  763. #define WCD9378_SMP_JACK_BASE (WCD9378_BASE+0xc00001)
  764. #define WCD9378_CMT_GRP_MASK (WCD9378_SMP_JACK_BASE+0x08)
  765. #define WCD9378_SMP_JACK_FUNC_EXT_ID_0 (WCD9378_SMP_JACK_BASE+0x48)
  766. #define WCD9378_SMP_JACK_FUNC_EXT_ID_1 (WCD9378_SMP_JACK_BASE+0x49)
  767. #define WCD9378_SMP_JACK_FUNC_EXT_VER (WCD9378_SMP_JACK_BASE+0x50)
  768. #define WCD9378_IT41_USAGE (WCD9378_SMP_JACK_BASE+0xa0)
  769. #define WCD9378_XU42_BYP (WCD9378_SMP_JACK_BASE+0x208)
  770. #define WCD9378_PDE42_REQ_PS (WCD9378_SMP_JACK_BASE+0x288)
  771. #define WCD9378_FU42_MUTE_CH1 (WCD9378_SMP_JACK_BASE+0x309)
  772. #define WCD9378_FU42_MUTE_CH2 (WCD9378_SMP_JACK_BASE+0x30a)
  773. #define WCD9378_FU42_CH_VOL_CH1 (WCD9378_SMP_JACK_BASE+0x311)
  774. #define WCD9378_FU42_CH_VOL_CH2 (WCD9378_SMP_JACK_BASE+0x312)
  775. #define WCD9378_SU43_SELECTOR (WCD9378_SMP_JACK_BASE+0x388)
  776. #define WCD9378_SU45_SELECTOR (WCD9378_SMP_JACK_BASE+0x408)
  777. #define WCD9378_PDE47_REQ_PS (WCD9378_SMP_JACK_BASE+0x488)
  778. #define WCD9378_GE35_SEL_MODE (WCD9378_SMP_JACK_BASE+0x608)
  779. #define WCD9378_GE35_DET_MODE (WCD9378_SMP_JACK_BASE+0x610)
  780. #define WCD9378_IT31_MICB (WCD9378_SMP_JACK_BASE+0x798)
  781. #define WCD9378_IT31_USAGE (WCD9378_SMP_JACK_BASE+0x7a0)
  782. #define WCD9378_PDE34_REQ_PS (WCD9378_SMP_JACK_BASE+0x808)
  783. #define WCD9378_SU45_TX_SELECTOR (WCD9378_SMP_JACK_BASE+0x908)
  784. #define WCD9378_XU36_BYP (WCD9378_SMP_JACK_BASE+0x988)
  785. #define WCD9378_PDE36_REQ_PS (WCD9378_SMP_JACK_BASE+0xa08)
  786. #define WCD9378_OT36_USAGE (WCD9378_SMP_JACK_BASE+0xb20)
  787. #define WCD9378_SMP_JACK_FUNC_STAT (WCD9378_SMP_JACK_BASE+0x80000)
  788. #define WCD9378_SMP_JACK_FUNC_ACT (WCD9378_SMP_JACK_BASE+0x80008)
  789. #define WCD9378_PDE42_ACT_PS (WCD9378_SMP_JACK_BASE+0x80280)
  790. #define WCD9378_PDE47_ACT_PS (WCD9378_SMP_JACK_BASE+0x80480)
  791. #define WCD9378_PDE34_ACT_PS (WCD9378_SMP_JACK_BASE+0x80800)
  792. #define WCD9378_PDE36_ACT_PS (WCD9378_SMP_JACK_BASE+0x80a00)
  793. #define WCD9378_SMP_JACK_DEV_MANU_ID_0 (WCD9378_SMP_JACK_BASE+0x100060)
  794. #define WCD9378_SMP_JACK_DEV_MANU_ID_1 (WCD9378_SMP_JACK_BASE+0x100061)
  795. #define WCD9378_SMP_JACK_DEV_PART_ID_0 (WCD9378_SMP_JACK_BASE+0x100068)
  796. #define WCD9378_SMP_JACK_DEV_PART_ID_1 (WCD9378_SMP_JACK_BASE+0x100069)
  797. #define WCD9378_SMP_JACK_DEV_VER (WCD9378_SMP_JACK_BASE+0x100070)
  798. #define WCD9378_SMP_MIC_CTRL0_BASE (WCD9378_BASE+0x1000001)
  799. #define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x48)
  800. #define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x49)
  801. #define WCD9378_SMP_MIC_CTRL0_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL0_BASE+0x50)
  802. #define WCD9378_IT11_MICB (WCD9378_SMP_MIC_CTRL0_BASE+0x98)
  803. #define WCD9378_IT11_USAGE (WCD9378_SMP_MIC_CTRL0_BASE+0xa0)
  804. #define WCD9378_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL0_BASE+0x108)
  805. #define WCD9378_OT10_USAGE (WCD9378_SMP_MIC_CTRL0_BASE+0x3a0)
  806. #define WCD9378_SMP_MIC_CTRL0_FUNC_STAT (WCD9378_SMP_MIC_CTRL0_BASE+0x80000)
  807. #define WCD9378_SMP_MIC_CTRL0_FUNC_ACT (WCD9378_SMP_MIC_CTRL0_BASE+0x80008)
  808. #define WCD9378_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL0_BASE+0x80100)
  809. #define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x100060)
  810. #define WCD9378_SMP_MIC_CTRL0_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x100061)
  811. #define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL0_BASE+0x100068)
  812. #define WCD9378_SMP_MIC_CTRL0_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL0_BASE+0x100069)
  813. #define WCD9378_SMP_MIC_CTRL0_DEV_VER (WCD9378_SMP_MIC_CTRL0_BASE+0x100070)
  814. #define WCD9378_SMP_MIC_CTRL1_BASE (WCD9378_BASE+0x1400001)
  815. #define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x48)
  816. #define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x49)
  817. #define WCD9378_SMP_MIC_CTRL1_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL1_BASE+0x50)
  818. #define WCD9378_SMP_MIC_CTRL1_IT11_MICB (WCD9378_SMP_MIC_CTRL1_BASE+0x98)
  819. #define WCD9378_SMP_MIC_CTRL1_IT11_USAGE (WCD9378_SMP_MIC_CTRL1_BASE+0xa0)
  820. #define WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL1_BASE+0x108)
  821. #define WCD9378_SMP_MIC_CTRL1_OT10_USAGE (WCD9378_SMP_MIC_CTRL1_BASE+0x3a0)
  822. #define WCD9378_SMP_MIC_CTRL1_FUNC_STAT (WCD9378_SMP_MIC_CTRL1_BASE+0x80000)
  823. #define WCD9378_SMP_MIC_CTRL1_FUNC_ACT (WCD9378_SMP_MIC_CTRL1_BASE+0x80008)
  824. #define WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL1_BASE+0x80100)
  825. #define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x100060)
  826. #define WCD9378_SMP_MIC_CTRL1_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x100061)
  827. #define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL1_BASE+0x100068)
  828. #define WCD9378_SMP_MIC_CTRL1_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL1_BASE+0x100069)
  829. #define WCD9378_SMP_MIC_CTRL1_DEV_VER (WCD9378_SMP_MIC_CTRL1_BASE+0x100070)
  830. #define WCD9378_SMP_MIC_CTRL2_BASE (WCD9378_BASE+0x1800001)
  831. #define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x48)
  832. #define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x49)
  833. #define WCD9378_SMP_MIC_CTRL2_FUNC_EXT_VER (WCD9378_SMP_MIC_CTRL2_BASE+0x50)
  834. #define WCD9378_SMP_MIC_CTRL2_IT11_MICB (WCD9378_SMP_MIC_CTRL2_BASE+0x98)
  835. #define WCD9378_SMP_MIC_CTRL2_IT11_USAGE (WCD9378_SMP_MIC_CTRL2_BASE+0xa0)
  836. #define WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS (WCD9378_SMP_MIC_CTRL2_BASE+0x108)
  837. #define WCD9378_SMP_MIC_CTRL2_OT10_USAGE (WCD9378_SMP_MIC_CTRL2_BASE+0x3a0)
  838. #define WCD9378_SMP_MIC_CTRL2_FUNC_STAT (WCD9378_SMP_MIC_CTRL2_BASE+0x80000)
  839. #define WCD9378_SMP_MIC_CTRL2_FUNC_ACT (WCD9378_SMP_MIC_CTRL2_BASE+0x80008)
  840. #define WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS (WCD9378_SMP_MIC_CTRL2_BASE+0x80100)
  841. #define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x100060)
  842. #define WCD9378_SMP_MIC_CTRL2_DEV_MANU_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x100061)
  843. #define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_0 (WCD9378_SMP_MIC_CTRL2_BASE+0x100068)
  844. #define WCD9378_SMP_MIC_CTRL2_DEV_PART_ID_1 (WCD9378_SMP_MIC_CTRL2_BASE+0x100069)
  845. #define WCD9378_SMP_MIC_CTRL2_DEV_VER (WCD9378_SMP_MIC_CTRL2_BASE+0x100070)
  846. #define WCD9378_HID_MEM_BASE (WCD9378_BASE+0x4000001)
  847. #define WCD9378_REPORT_ID (WCD9378_HID_MEM_BASE+0x01)
  848. #define WCD9378_MESSAGE0 (WCD9378_HID_MEM_BASE+0x02)
  849. #define WCD9378_MESSAGE1 (WCD9378_HID_MEM_BASE+0x03)
  850. #define WCD9378_MESSAGE2 (WCD9378_HID_MEM_BASE+0x04)
  851. #define WCD9378_NUM_REGISTERS (WCD9378_SMP_MIC_CTRL2_DEV_VER - WCD9378_BASE + 1)
  852. #define WCD9378_MAX_REGISTER (WCD9378_MESSAGE2 + 1)
  853. #define WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT 0x03
  854. #define WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT 0x00
  855. #define WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT 0x00
  856. #define WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT 0x03
  857. #define WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT 0x02
  858. #define SWRS_SCP_BASE_CLK_BASE (0x004d)
  859. #define SWRS_SCP_BUSCLOCK_SCALE_BANK0 (0x0062)
  860. #define SWRS_SCP_BUSCLOCK_SCALE_BANK1 (0x0072)
  861. #define SWRS_SCP_SDCA_INTMASK_1 (0x0000005c)
  862. #define SWRS_SCP_SDCA_INTMASK_2 (0x0000005d)
  863. #define SWRS_SCP_SDCA_INTMASK_3 (0x0000005e)
  864. #define SWRS_SCP_SDCA_INTSTAT_1 (0x00000058)
  865. #define SWRS_SCP_SDCA_INTSTAT_2 (0x00000059)
  866. #define SWRS_SCP_SDCA_INTSTAT_3 (0x0000005a)
  867. #define SWRS_SCP_SDCA_INTRTYPE_1 (0x000000f4)
  868. #define SWRS_SCP_SDCA_INTRTYPE_2 (0x000000f8)
  869. #define SWRS_SCP_SDCA_INTRTYPE_3 (0x000000fc)
  870. #endif /* WCD9378_REGISTERS_H */