wcd9378.c 125 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include <asoc/msm-cdc-supply.h>
  20. #include <bindings/audio-codec-port-types.h>
  21. #include <linux/qti-regmap-debugfs.h>
  22. #include "wcd9378-reg-masks.h"
  23. #include "wcd9378.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD9378_MOBILE_MODE 0x01
  28. #define WCD9378_VERSION_1_0 1
  29. #define WCD9378_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_RX0 1
  31. #define AUX_RX_PATH_RX1 1
  32. #define SWR_BASECLK_19P2MHZ (0x01)
  33. #define SWR_BASECLK_24P576MHZ (0x03)
  34. #define SWR_BASECLK_22P5792MHZ (0x04)
  35. #define SWR_CLKSCALE_DIV2 (0x02)
  36. #define ADC_MODE_VAL_HIFI 0x01
  37. #define ADC_MODE_VAL_NORMAL 0x03
  38. #define ADC_MODE_VAL_LP 0x05
  39. #define PWR_LEVEL_LOHIFI_VAL 0x00
  40. #define PWR_LEVEL_LP_VAL 0x01
  41. #define PWR_LEVEL_HIFI_VAL 0x02
  42. #define PWR_LEVEL_ULP_VAL 0x03
  43. #define WCD9378_MBQ_ENABLE_MASK 0x2000
  44. #define MICB_USAGE_VAL_DISABLE 0x00
  45. #define MICB_USAGE_VAL_PULL_DOWN 0x01
  46. #define MICB_USAGE_VAL_1P2V 0x02
  47. #define MICB_USAGE_VAL_1P8VORPULLUP 0x03
  48. #define MICB_USAGE_VAL_2P5V 0x04
  49. #define MICB_USAGE_VAL_2P75V 0x05
  50. #define MICB_USAGE_VAL_2P2V 0xF0
  51. #define MICB_USAGE_VAL_2P7V 0xF1
  52. #define MICB_USAGE_VAL_2P8V 0xF2
  53. #define MICB_USAGE_VAL_MICB1_TABLE_VAL 0xF3
  54. #define MICB_USAGE_VAL_MICB2_TABLE_VAL 0xF4
  55. #define MICB_USAGE_VAL_MICB3_TABLE_VAL 0xF5
  56. #define MICB_NUM_MAX 3
  57. #define NUM_ATTEMPTS 20
  58. #define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  59. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  60. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  61. SNDRV_PCM_RATE_384000)
  62. /* Fractional Rates */
  63. #define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  64. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  65. #define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  66. SNDRV_PCM_FMTBIT_S24_LE |\
  67. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  68. #define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  69. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  70. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  71. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  72. .tlv.p = (tlv_array), \
  73. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  74. .put = wcd9378_ear_pa_put_gain, \
  75. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  76. #define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  77. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  78. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  79. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  80. .tlv.p = (tlv_array), \
  81. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  82. .put = wcd9378_aux_pa_put_gain, \
  83. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  84. enum {
  85. CODEC_TX = 0,
  86. CODEC_RX,
  87. };
  88. enum {
  89. RX2_HP_MODE,
  90. RX2_NORMAL_MODE,
  91. };
  92. enum {
  93. WCD_ADC1 = 0,
  94. WCD_ADC2,
  95. WCD_ADC3,
  96. WCD_ADC4,
  97. ALLOW_BUCK_DISABLE,
  98. HPH_COMP_DELAY,
  99. HPH_PA_DELAY,
  100. AMIC2_BCS_ENABLE,
  101. WCD_SUPPLIES_LPM_MODE,
  102. WCD_ADC1_MODE,
  103. WCD_ADC2_MODE,
  104. WCD_ADC3_MODE,
  105. WCD_ADC4_MODE,
  106. WCD_AUX_EN,
  107. WCD_EAR_EN,
  108. };
  109. enum {
  110. NOSJ_SA_STEREO_3SM = 0,
  111. SJ_SA_AUX_2SM,
  112. NOSJ_SA_STEREO_3SM_1HDR,
  113. SJ_SA_AUX_2SM_1HDR,
  114. NOSJ_SA_EAR_3SM,
  115. SJ_SA_EAR_2SM,
  116. NOSJ_SA_EAR_3SM_1HDR,
  117. SJ_SA_EAR_2SM_1HDR,
  118. SJ_1HDR_SA_AUX_1SM,
  119. SJ_1HDR_SA_EAR_1SM,
  120. SJ_SA_STEREO_2SM,
  121. SJ_NOMIC_SA_EAR_3SM,
  122. SJ_NOMIC_SA_AUX_3SM,
  123. WCD_SYS_USAGE_MAX,
  124. };
  125. enum {
  126. NO_MICB_USED,
  127. MICB1,
  128. MICB2,
  129. MICB3,
  130. MICB_NUM,
  131. };
  132. enum {
  133. ADC_MODE_INVALID = 0,
  134. ADC_MODE_HIFI,
  135. ADC_MODE_NORMAL,
  136. ADC_MODE_LP,
  137. ADC_MODE_ULP1,
  138. ADC_MODE_ULP2,
  139. };
  140. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
  141. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(aux_pa_gain, 600, -600);
  142. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
  143. static int wcd9378_reset(struct device *dev);
  144. static int wcd9378_reset_low(struct device *dev);
  145. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable);
  146. static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
  147. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  148. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  149. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  150. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  151. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
  152. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
  153. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
  154. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
  155. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
  156. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
  157. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
  158. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
  159. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
  160. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  161. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  162. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  163. REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
  164. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  165. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  166. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  167. };
  168. static int wcd9378_handle_post_irq(void *data)
  169. {
  170. struct wcd9378_priv *wcd9378 = data;
  171. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  172. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
  173. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
  174. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
  175. wcd9378->tx_swr_dev->slave_irq_pending =
  176. ((sts1 || sts2 || !sts3) ? true : false);
  177. pr_debug("%s: sts1: 0x%0x, sts2: 0x%0x, sts3: 0x%0x\n", __func__, sts1, sts2, sts3);
  178. return IRQ_HANDLED;
  179. }
  180. static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
  181. .name = "wcd9378",
  182. .irqs = wcd9378_regmap_irqs,
  183. .num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
  184. .num_regs = 3,
  185. .status_base = SWRS_SCP_SDCA_INTSTAT_1,
  186. .unmask_base = SWRS_SCP_SDCA_INTMASK_1,
  187. .type_base = SWRS_SCP_SDCA_INTRTYPE_1,
  188. .ack_base = SWRS_SCP_SDCA_INTSTAT_1,
  189. .use_ack = 1,
  190. .runtime_pm = false,
  191. .handle_post_irq = wcd9378_handle_post_irq,
  192. .irq_drv_data = NULL,
  193. };
  194. static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  195. {
  196. int ret = 0;
  197. int bank = 0;
  198. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  199. if (ret)
  200. return -EINVAL;
  201. return ((bank & 0x40) ? 1 : 0);
  202. }
  203. static int wcd9378_init_reg(struct snd_soc_component *component)
  204. {
  205. /*0.9 Volts*/
  206. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  207. WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
  208. /*BG_EN ENABLE*/
  209. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  210. WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
  211. usleep_range(1000, 1010);
  212. /*LDOL_BG_SEL SLEEP_BG*/
  213. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  214. WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
  215. usleep_range(1000, 1010);
  216. /*Start up analog master bias. Sequence cannot change*/
  217. /*VBG_FINE_ADJ 0.005 Volts*/
  218. snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
  219. WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
  220. /*ANALOG_BIAS_EN ENABLE*/
  221. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  222. WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
  223. /*PRECHRG_EN ENABLE*/
  224. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  225. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
  226. usleep_range(10000, 10010);
  227. /*PRECHRG_EN DISABLE*/
  228. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  229. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
  230. /*End Analog Master Bias enable*/
  231. /*SEQ_BYPASS ENABLE*/
  232. snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
  233. WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
  234. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  235. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
  236. WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
  237. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  238. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
  239. WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
  240. /*IBIAS_LDO_DRIVER 5e-06*/
  241. snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
  242. WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  243. /*IBIAS_LDO_DRIVER 5e-06*/
  244. snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
  245. WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  246. /*SHORT_PROT_EN ENABLE*/
  247. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  248. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
  249. /*OCP FSM EN*/
  250. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  251. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  252. /*SCD OP EN*/
  253. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  254. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  255. /*OCP DET EN*/
  256. snd_soc_component_update_bits(component, WCD9378_HPH_L_TEST,
  257. WCD9378_HPH_L_TEST_OCP_DET_EN_MASK, 0x01);
  258. /*OCP DET EN*/
  259. snd_soc_component_update_bits(component, WCD9378_HPH_R_TEST,
  260. WCD9378_HPH_R_TEST_OCP_DET_EN_MASK, 0x01);
  261. /*HD2_RES_DIV_CTL_L 82.77*/
  262. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
  263. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
  264. /*HD2_RES_DIV_CTL_R 82.77*/
  265. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
  266. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
  267. /*OPAMP_CHOP_CLK_EN DISABLE*/
  268. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  269. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  270. /*RDAC_GAINCTL 0.55*/
  271. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
  272. WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
  273. /*HPH_UP_T0: 0.002*/
  274. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
  275. WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
  276. /*HPH_UP_T9: 0.002*/
  277. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
  278. WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
  279. /*HPH_DN_T0: 0.007*/
  280. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
  281. WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
  282. return 0;
  283. }
  284. static int wcd9378_set_port_params(struct snd_soc_component *component,
  285. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  286. u8 *ch_mask, u32 *ch_rate,
  287. u8 *port_type, u8 path)
  288. {
  289. int i, j;
  290. u8 num_ports = 0;
  291. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  292. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  293. switch (path) {
  294. case CODEC_RX:
  295. map = &wcd9378->rx_port_mapping;
  296. num_ports = wcd9378->num_rx_ports;
  297. break;
  298. case CODEC_TX:
  299. map = &wcd9378->tx_port_mapping;
  300. num_ports = wcd9378->num_tx_ports;
  301. break;
  302. default:
  303. dev_err(component->dev, "%s Invalid path selected %u\n",
  304. __func__, path);
  305. return -EINVAL;
  306. }
  307. for (i = 0; i <= num_ports; i++) {
  308. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  309. if ((*map)[i][j].slave_port_type == slv_prt_type)
  310. goto found;
  311. }
  312. }
  313. found:
  314. if (i > num_ports || j == MAX_CH_PER_PORT) {
  315. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  316. __func__, slv_prt_type);
  317. return -EINVAL;
  318. }
  319. *port_id = i;
  320. *num_ch = (*map)[i][j].num_ch;
  321. *ch_mask = (*map)[i][j].ch_mask;
  322. *ch_rate = (*map)[i][j].ch_rate;
  323. *port_type = (*map)[i][j].master_port_type;
  324. return 0;
  325. }
  326. static int wcd9378_parse_port_params(struct device *dev,
  327. char *prop, u8 path)
  328. {
  329. u32 *dt_array, map_size, max_uc;
  330. int ret = 0;
  331. u32 cnt = 0;
  332. u32 i, j;
  333. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  334. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  335. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  336. switch (path) {
  337. case CODEC_TX:
  338. map = &wcd9378->tx_port_params;
  339. map_uc = &wcd9378->swr_tx_port_params;
  340. break;
  341. default:
  342. ret = -EINVAL;
  343. goto err_port_map;
  344. }
  345. if (!of_find_property(dev->of_node, prop,
  346. &map_size)) {
  347. dev_err(dev, "missing port mapping prop %s\n", prop);
  348. ret = -EINVAL;
  349. goto err_port_map;
  350. }
  351. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  352. if (max_uc != SWR_UC_MAX) {
  353. dev_err(dev, "%s: port params not provided for all usecases\n",
  354. __func__);
  355. ret = -EINVAL;
  356. goto err_port_map;
  357. }
  358. dt_array = kzalloc(map_size, GFP_KERNEL);
  359. if (!dt_array) {
  360. ret = -ENOMEM;
  361. goto err_alloc;
  362. }
  363. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  364. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  365. if (ret) {
  366. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  367. __func__, prop);
  368. goto err_pdata_fail;
  369. }
  370. for (i = 0; i < max_uc; i++) {
  371. for (j = 0; j < SWR_NUM_PORTS; j++) {
  372. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  373. (*map)[i][j].offset1 = dt_array[cnt];
  374. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  375. }
  376. (*map_uc)[i].pp = &(*map)[i][0];
  377. }
  378. kfree(dt_array);
  379. return 0;
  380. err_pdata_fail:
  381. kfree(dt_array);
  382. err_alloc:
  383. err_port_map:
  384. return ret;
  385. }
  386. static int wcd9378_parse_port_mapping(struct device *dev,
  387. char *prop, u8 path)
  388. {
  389. u32 *dt_array, map_size, map_length;
  390. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  391. u32 slave_port_type, master_port_type;
  392. u32 i, ch_iter = 0;
  393. int ret = 0;
  394. u8 *num_ports = NULL;
  395. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  396. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  397. switch (path) {
  398. case CODEC_RX:
  399. map = &wcd9378->rx_port_mapping;
  400. num_ports = &wcd9378->num_rx_ports;
  401. break;
  402. case CODEC_TX:
  403. map = &wcd9378->tx_port_mapping;
  404. num_ports = &wcd9378->num_tx_ports;
  405. break;
  406. default:
  407. dev_err(dev, "%s Invalid path selected %u\n",
  408. __func__, path);
  409. return -EINVAL;
  410. }
  411. if (!of_find_property(dev->of_node, prop,
  412. &map_size)) {
  413. dev_err(dev, "missing port mapping prop %s\n", prop);
  414. ret = -EINVAL;
  415. goto err_port_map;
  416. }
  417. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  418. dt_array = kzalloc(map_size, GFP_KERNEL);
  419. if (!dt_array) {
  420. ret = -ENOMEM;
  421. goto err_alloc;
  422. }
  423. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  424. NUM_SWRS_DT_PARAMS * map_length);
  425. if (ret) {
  426. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  427. __func__, prop);
  428. goto err_pdata_fail;
  429. }
  430. for (i = 0; i < map_length; i++) {
  431. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  432. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  433. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  434. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  435. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  436. if (port_num != old_port_num)
  437. ch_iter = 0;
  438. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  439. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  440. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  441. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  442. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  443. old_port_num = port_num;
  444. }
  445. *num_ports = port_num;
  446. kfree(dt_array);
  447. return 0;
  448. err_pdata_fail:
  449. kfree(dt_array);
  450. err_alloc:
  451. err_port_map:
  452. return ret;
  453. }
  454. static int wcd9378_tx_connect_port(struct snd_soc_component *component,
  455. u8 slv_port_type, int clk_rate,
  456. u8 enable)
  457. {
  458. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  459. u8 port_id, num_ch, ch_mask;
  460. u8 ch_type = 0;
  461. u32 ch_rate;
  462. int slave_ch_idx;
  463. u8 num_port = 1;
  464. int ret = 0;
  465. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  466. &num_ch, &ch_mask, &ch_rate,
  467. &ch_type, CODEC_TX);
  468. if (ret)
  469. return ret;
  470. if (clk_rate)
  471. ch_rate = clk_rate;
  472. slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
  473. if (slave_ch_idx != -EINVAL)
  474. ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
  475. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  476. __func__, slave_ch_idx, ch_type);
  477. if (enable)
  478. ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
  479. num_port, &ch_mask, &ch_rate,
  480. &num_ch, &ch_type);
  481. else
  482. ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
  483. num_port, &ch_mask, &ch_type);
  484. return ret;
  485. }
  486. static int wcd9378_rx_connect_port(struct snd_soc_component *component,
  487. u8 slv_port_type, u8 enable)
  488. {
  489. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  490. u8 port_id, num_ch, ch_mask, port_type;
  491. u32 ch_rate;
  492. u8 num_port = 1;
  493. int ret = 0;
  494. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  495. &num_ch, &ch_mask, &ch_rate,
  496. &port_type, CODEC_RX);
  497. if (ret)
  498. return ret;
  499. if (enable)
  500. ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
  501. num_port, &ch_mask, &ch_rate,
  502. &num_ch, &port_type);
  503. else
  504. ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
  505. num_port, &ch_mask, &port_type);
  506. return ret;
  507. }
  508. static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
  509. struct snd_kcontrol *kcontrol,
  510. int event)
  511. {
  512. struct snd_soc_component *component =
  513. snd_soc_dapm_to_component(w->dapm);
  514. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  515. int mode = wcd9378->hph_mode;
  516. int ret = 0;
  517. int bank = 0;
  518. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  519. w->name, event);
  520. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  521. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  522. wcd9378_rx_connect_port(component, CLSH,
  523. SND_SOC_DAPM_EVENT_ON(event));
  524. }
  525. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  526. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  527. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  528. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, false);
  529. ret = swr_slvdev_datapath_control(
  530. wcd9378->rx_swr_dev,
  531. wcd9378->rx_swr_dev->dev_num,
  532. false);
  533. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, false);
  534. }
  535. return ret;
  536. }
  537. static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  538. struct snd_kcontrol *kcontrol,
  539. int event)
  540. {
  541. struct snd_soc_component *component =
  542. snd_soc_dapm_to_component(w->dapm);
  543. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  544. u32 dmic_clk_reg, dmic_clk_en_reg;
  545. s32 *dmic_clk_cnt;
  546. u8 dmic_ctl_shift = 0;
  547. u8 dmic_clk_shift = 0;
  548. u8 dmic_clk_mask = 0;
  549. u32 dmic2_left_en = 0;
  550. int ret = 0;
  551. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  552. w->name, event);
  553. switch (w->shift) {
  554. case 0:
  555. case 1:
  556. dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
  557. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  558. dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
  559. dmic_clk_mask = 0x0F;
  560. dmic_clk_shift = 0x00;
  561. dmic_ctl_shift = 0x00;
  562. break;
  563. case 2:
  564. dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
  565. fallthrough;
  566. case 3:
  567. dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
  568. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  569. dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
  570. dmic_clk_mask = 0xF0;
  571. dmic_clk_shift = 0x04;
  572. dmic_ctl_shift = 0x01;
  573. break;
  574. case 4:
  575. case 5:
  576. dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
  577. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
  578. dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
  579. dmic_clk_mask = 0x0F;
  580. dmic_clk_shift = 0x00;
  581. dmic_ctl_shift = 0x02;
  582. break;
  583. default:
  584. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  585. __func__);
  586. return -EINVAL;
  587. };
  588. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  589. __func__, event, (w->shift + 1), *dmic_clk_cnt);
  590. switch (event) {
  591. case SND_SOC_DAPM_PRE_PMU:
  592. snd_soc_component_update_bits(component,
  593. WCD9378_CDC_AMIC_CTL,
  594. (0x01 << dmic_ctl_shift), 0x00);
  595. /* 250us sleep as per HW requirement */
  596. usleep_range(250, 260);
  597. if (dmic2_left_en)
  598. snd_soc_component_update_bits(component,
  599. dmic2_left_en, 0x80, 0x80);
  600. /* Setting DMIC clock rate to 2.4MHz */
  601. snd_soc_component_update_bits(component,
  602. dmic_clk_reg, dmic_clk_mask,
  603. (0x03 << dmic_clk_shift));
  604. snd_soc_component_update_bits(component,
  605. dmic_clk_en_reg, 0x08, 0x08);
  606. /* enable clock scaling */
  607. snd_soc_component_update_bits(component,
  608. WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
  609. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  610. wcd9378->tx_swr_dev->dev_num,
  611. true);
  612. break;
  613. case SND_SOC_DAPM_POST_PMD:
  614. wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
  615. false);
  616. snd_soc_component_update_bits(component,
  617. WCD9378_CDC_AMIC_CTL,
  618. (0x01 << dmic_ctl_shift),
  619. (0x01 << dmic_ctl_shift));
  620. if (dmic2_left_en)
  621. snd_soc_component_update_bits(component,
  622. dmic2_left_en, 0x80, 0x00);
  623. snd_soc_component_update_bits(component,
  624. dmic_clk_en_reg, 0x08, 0x00);
  625. break;
  626. };
  627. return ret;
  628. }
  629. /*
  630. * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
  631. * @micb_mv: micbias in mv
  632. *
  633. * return register value converted
  634. */
  635. int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
  636. {
  637. /* min micbias voltage is 1V and maximum is 2.85V */
  638. if (micb_mv < 1000 || micb_mv > 2850) {
  639. pr_err("%s: unsupported micbias voltage\n", __func__);
  640. return -EINVAL;
  641. }
  642. return (micb_mv - 1000) / 50;
  643. }
  644. EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
  645. /*
  646. * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  647. * @component: handle to snd_soc_component *
  648. * @req_volt: micbias voltage to be set
  649. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  650. *
  651. * return 0 if adjustment is success or error code in case of failure
  652. */
  653. static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
  654. u32 micb_mv, int micb_num)
  655. {
  656. int vcout_ctl;
  657. switch (micb_mv) {
  658. case 2200:
  659. return MICB_USAGE_VAL_2P2V;
  660. case 2700:
  661. return MICB_USAGE_VAL_2P7V;
  662. case 2800:
  663. return MICB_USAGE_VAL_2P8V;
  664. default:
  665. vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
  666. if (micb_num == MIC_BIAS_1) {
  667. snd_soc_component_update_bits(component,
  668. WCD9378_MICB_REMAP_TABLE_VAL_3,
  669. WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
  670. vcout_ctl);
  671. return MICB_USAGE_VAL_MICB1_TABLE_VAL;
  672. } else if (micb_num == MIC_BIAS_2) {
  673. snd_soc_component_update_bits(component,
  674. WCD9378_MICB_REMAP_TABLE_VAL_4,
  675. WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
  676. vcout_ctl);
  677. return MICB_USAGE_VAL_MICB2_TABLE_VAL;
  678. } else if (micb_num == MIC_BIAS_3) {
  679. snd_soc_component_update_bits(component,
  680. WCD9378_MICB_REMAP_TABLE_VAL_5,
  681. WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
  682. vcout_ctl);
  683. return MICB_USAGE_VAL_MICB3_TABLE_VAL;
  684. }
  685. }
  686. return 0;
  687. }
  688. static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
  689. u32 micb_mv, int micb_num)
  690. {
  691. switch (micb_mv) {
  692. case 0:
  693. return MICB_USAGE_VAL_PULL_DOWN;
  694. case 1200:
  695. return MICB_USAGE_VAL_1P2V;
  696. case 1800:
  697. return MICB_USAGE_VAL_1P8VORPULLUP;
  698. case 2500:
  699. return MICB_USAGE_VAL_2P5V;
  700. case 2750:
  701. return MICB_USAGE_VAL_2P75V;
  702. default:
  703. return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
  704. }
  705. return MICB_USAGE_VAL_DISABLE;
  706. }
  707. int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  708. int req_volt, int micb_num)
  709. {
  710. struct wcd9378_priv *wcd9378 =
  711. snd_soc_component_get_drvdata(component);
  712. int micb_usage = 0, micb_mask = 0, req_vout_ctl;
  713. int sm_num = 0;
  714. struct wcd9378_pdata *pdata = NULL;
  715. pdata = dev_get_platdata(wcd9378->dev);
  716. if (wcd9378 == NULL) {
  717. dev_err(component->dev,
  718. "%s: wcd9378 private data is NULL\n", __func__);
  719. return -EINVAL;
  720. }
  721. for (sm_num = 0; sm_num < SIM_MIC_NUM; sm_num++)
  722. if (wcd9378->micb_sel[sm_num] == micb_num)
  723. break;
  724. if ((sm_num == SIM_MIC_NUM) && (micb_num != MIC_BIAS_2)) {
  725. pr_err("%s: cannot find the simple mic function which connect to micbias_%d\n",
  726. __func__, micb_num);
  727. return -EINVAL;
  728. }
  729. switch (sm_num) {
  730. case SIM_MIC0:
  731. micb_usage = WCD9378_IT11_USAGE;
  732. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  733. break;
  734. case SIM_MIC1:
  735. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  736. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  737. break;
  738. case SIM_MIC2:
  739. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  740. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  741. break;
  742. default:
  743. if (micb_num == MIC_BIAS_2) {
  744. micb_usage = WCD9378_IT31_MICB;
  745. micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
  746. }
  747. break;
  748. }
  749. mutex_lock(&wcd9378->micb_lock);
  750. req_vout_ctl =
  751. wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
  752. snd_soc_component_update_bits(component,
  753. micb_usage, micb_mask, req_vout_ctl);
  754. mutex_unlock(&wcd9378->micb_lock);
  755. return 0;
  756. }
  757. EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
  758. void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  759. bool bcs_disable)
  760. {
  761. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  762. if (wcd9378->update_wcd_event) {
  763. if (bcs_disable)
  764. wcd9378->update_wcd_event(wcd9378->handle,
  765. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  766. else
  767. wcd9378->update_wcd_event(wcd9378->handle,
  768. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  769. }
  770. }
  771. static int wcd9378_get_clk_rate(int mode)
  772. {
  773. int rate;
  774. switch (mode) {
  775. case ADC_MODE_LP:
  776. rate = SWR_CLK_RATE_4P8MHZ;
  777. break;
  778. case ADC_MODE_INVALID:
  779. case ADC_MODE_NORMAL:
  780. case ADC_MODE_HIFI:
  781. default:
  782. rate = SWR_CLK_RATE_9P6MHZ;
  783. break;
  784. }
  785. pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
  786. return rate;
  787. }
  788. static int wcd9378_set_swr_clk_rate(struct snd_soc_component *component,
  789. int rate, int bank)
  790. {
  791. u8 mask = (bank ? 0xF0 : 0x0F);
  792. u8 val = 0;
  793. switch (rate) {
  794. case SWR_CLK_RATE_2P4MHZ:
  795. val = (bank ? 0x30 : 0x03);
  796. break;
  797. case SWR_CLK_RATE_4P8MHZ:
  798. val = (bank ? 0x10 : 0x01);
  799. break;
  800. case SWR_CLK_RATE_9P6MHZ:
  801. default:
  802. val = 0x00;
  803. break;
  804. }
  805. dev_dbg(component->dev,
  806. "%s: rate: 0x%0x\n", __func__, val);
  807. snd_soc_component_update_bits(component, WCD9378_SWR_TX_CLK_RATE,
  808. mask, val);
  809. return 0;
  810. }
  811. static void wcd9378_micb_usage_value_write(struct snd_soc_component *component,
  812. unsigned char tx_path)
  813. {
  814. struct wcd9378_priv *wcd9378 =
  815. snd_soc_component_get_drvdata(component);
  816. int micb_num;
  817. switch (tx_path) {
  818. case ADC1:
  819. micb_num = (snd_soc_component_read(component,
  820. WCD9378_SM0_MB_SEL) &
  821. WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK);
  822. break;
  823. case ADC2:
  824. micb_num = (snd_soc_component_read(component,
  825. WCD9378_SM1_MB_SEL) &
  826. WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK);
  827. break;
  828. case ADC3:
  829. micb_num = (snd_soc_component_read(component,
  830. WCD9378_SM2_MB_SEL) &
  831. WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK);
  832. break;
  833. default:
  834. pr_err("%s: unsupport tx path\n", __func__);
  835. return;
  836. }
  837. if (!wcd9378->va_amic_en)
  838. wcd9378_micbias_control(component, micb_num,
  839. MICB_ENABLE, true);
  840. else
  841. wcd9378_micbias_control(component, micb_num,
  842. MICB_PULLUP_ENABLE, true);
  843. }
  844. static int wcd9378_get_adc_mode_val(int mode)
  845. {
  846. int ret = 0;
  847. switch (mode) {
  848. case ADC_MODE_INVALID:
  849. case ADC_MODE_NORMAL:
  850. ret = ADC_MODE_VAL_NORMAL;
  851. break;
  852. case ADC_MODE_HIFI:
  853. ret = ADC_MODE_VAL_HIFI;
  854. break;
  855. case ADC_MODE_LP:
  856. ret = ADC_MODE_VAL_LP;
  857. break;
  858. default:
  859. ret = -EINVAL;
  860. pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
  861. break;
  862. }
  863. return ret;
  864. }
  865. static void wcd9378_micb_sel_set(struct snd_soc_component *component,
  866. unsigned char micb_num)
  867. {
  868. struct wcd9378_priv *wcd9378 =
  869. snd_soc_component_get_drvdata(component);
  870. switch (micb_num) {
  871. case 0:
  872. snd_soc_component_update_bits(component, WCD9378_SM0_MB_SEL,
  873. WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK, wcd9378->micb_sel[0]);
  874. break;
  875. case 1:
  876. snd_soc_component_update_bits(component, WCD9378_SM1_MB_SEL,
  877. WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK, wcd9378->micb_sel[1]);
  878. break;
  879. case 2:
  880. snd_soc_component_update_bits(component, WCD9378_SM2_MB_SEL,
  881. WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK, wcd9378->micb_sel[2]);
  882. break;
  883. default:
  884. break;
  885. }
  886. }
  887. static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
  888. struct snd_kcontrol *kcontrol, int event)
  889. {
  890. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  891. struct wcd9378_priv *wcd9378 =
  892. snd_soc_component_get_drvdata(component);
  893. int mode_val = 0, bank = 0, ret = 0, rate = 0;
  894. int act_ps = 0;
  895. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
  896. wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
  897. dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
  898. w->name, w->shift, event);
  899. switch (event) {
  900. case SND_SOC_DAPM_PRE_PMU:
  901. wcd9378_micb_sel_set(component, w->shift - ADC1);
  902. mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
  903. if (mode_val < 0) {
  904. dev_dbg(component->dev,
  905. "%s: invalid mode, setting to normal mode\n",
  906. __func__);
  907. mode_val = ADC_MODE_VAL_NORMAL;
  908. }
  909. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  910. if (w->shift == ADC2 && !((snd_soc_component_read(component,
  911. WCD9378_TX_NEW_TX_CH12_MUX) &
  912. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
  913. if (!wcd9378->bcs_dis) {
  914. dev_err(component->dev, "%s: mbhc connect port enter\n", __func__);
  915. wcd9378_tx_connect_port(component, MBHC,
  916. SWR_CLK_RATE_4P8MHZ, true);
  917. set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  918. }
  919. }
  920. set_bit(w->shift - ADC1, &wcd9378->status_mask);
  921. wcd9378_tx_connect_port(component, w->shift, rate,
  922. true);
  923. switch (w->shift) {
  924. case ADC1:
  925. dev_dbg(component->dev, "%s ADC1 enter\n", __func__);
  926. /*SMP MIC0 MICB_USAGE SET*/
  927. wcd9378_micb_usage_value_write(component, ADC1);
  928. /*SMP MIC0 IT11 USAGE SET*/
  929. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  930. WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
  931. /*Hold TXFE in Initialization During Startup*/
  932. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  933. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
  934. /*Power up TX0 sequencer*/
  935. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  936. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  937. break;
  938. case ADC2:
  939. switch (wcd9378->sys_usage) {
  940. case SJ_SA_AUX_2SM:
  941. case SJ_SA_AUX_2SM_1HDR:
  942. case SJ_SA_EAR_2SM:
  943. case SJ_SA_EAR_2SM_1HDR:
  944. case SJ_1HDR_SA_AUX_1SM:
  945. case SJ_1HDR_SA_EAR_1SM:
  946. case SJ_NOMIC_SA_EAR_3SM:
  947. case SJ_NOMIC_SA_AUX_3SM:
  948. dev_dbg(component->dev, "%s SJ ADC2 enter\n", __func__);
  949. /*SMP JACK IT31 MICB SET*/
  950. wcd9378_micbias_control(component, MIC_BIAS_2,
  951. MICB_ENABLE, true);
  952. /*SMP JACK IT31 USAGE SET*/
  953. snd_soc_component_update_bits(component,
  954. WCD9378_IT31_USAGE,
  955. WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
  956. /*Power up TX1 sequencer*/
  957. snd_soc_component_update_bits(component,
  958. WCD9378_PDE34_REQ_PS,
  959. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
  960. break;
  961. case NOSJ_SA_STEREO_3SM:
  962. case NOSJ_SA_STEREO_3SM_1HDR:
  963. case NOSJ_SA_EAR_3SM:
  964. case NOSJ_SA_EAR_3SM_1HDR:
  965. dev_dbg(component->dev, "%s SM1 ADC2 enter\n", __func__);
  966. /*SMP MIC1 MICB_USAGE SET*/
  967. wcd9378_micb_usage_value_write(component, ADC2);
  968. /*SMP MIC1 IT11 USAGE SET*/
  969. snd_soc_component_update_bits(component,
  970. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  971. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  972. mode_val);
  973. /*Hold TXFE in Initialization During Startup*/
  974. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  975. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
  976. /*Power up TX1 sequencer*/
  977. snd_soc_component_update_bits(component,
  978. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  979. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  980. 0x00);
  981. break;
  982. }
  983. break;
  984. case ADC3:
  985. /*SMP MIC2 MICB_USAGE SET*/
  986. wcd9378_micb_usage_value_write(component, ADC3);
  987. /*SMP MIC2 IT11 USAGE SET*/
  988. snd_soc_component_update_bits(component,
  989. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  990. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  991. mode_val);
  992. /*Hold TXFE in Initialization During Startup*/
  993. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  994. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
  995. /*Power up TX2 sequencer*/
  996. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  997. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  998. break;
  999. default:
  1000. break;
  1001. }
  1002. /*default delay 800us*/
  1003. usleep_range(800, 810);
  1004. /****ADC START*****/
  1005. wcd9378_set_swr_clk_rate(component, rate, bank);
  1006. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
  1007. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1008. wcd9378->tx_swr_dev->dev_num,
  1009. true);
  1010. /* Copy clk settings to active bank */
  1011. wcd9378_set_swr_clk_rate(component, rate, !bank);
  1012. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
  1013. /****ADC END*****/
  1014. switch (w->shift) {
  1015. case ADC1:
  1016. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1017. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1018. break;
  1019. case ADC2:
  1020. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1021. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
  1022. break;
  1023. case ADC3:
  1024. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1025. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1026. break;
  1027. };
  1028. if (w->shift == ADC1) {
  1029. act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
  1030. if (act_ps)
  1031. pr_err("%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
  1032. __func__, act_ps);
  1033. else
  1034. pr_err("%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
  1035. __func__, act_ps);
  1036. }
  1037. if (w->shift == ADC2) {
  1038. act_ps = snd_soc_component_read(component,
  1039. WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
  1040. if (act_ps)
  1041. pr_err("%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
  1042. __func__, act_ps);
  1043. else
  1044. pr_err("%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
  1045. __func__, act_ps);
  1046. }
  1047. break;
  1048. case SND_SOC_DAPM_POST_PMD:
  1049. /****ADC START****/
  1050. wcd9378_tx_connect_port(component, w->shift, 0, false);
  1051. if (w->shift == ADC2 &&
  1052. test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
  1053. wcd9378_tx_connect_port(component, MBHC, 0,
  1054. false);
  1055. clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  1056. }
  1057. /****ADC END****/
  1058. switch (w->shift) {
  1059. case ADC1:
  1060. /*Normal TXFE Startup*/
  1061. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1062. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1063. /*tear down TX0 sequencer*/
  1064. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1065. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1066. break;
  1067. case ADC2:
  1068. /*tear down TX1 sequencer*/
  1069. snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
  1070. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
  1071. /*Normal TXFE Startup*/
  1072. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  1073. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  1074. /*tear down TX1 sequencer*/
  1075. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1076. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1077. break;
  1078. case ADC3:
  1079. /*Normal TXFE Startup*/
  1080. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  1081. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  1082. /*tear down TX2 sequencer*/
  1083. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  1084. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  1085. break;
  1086. default:
  1087. break;
  1088. }
  1089. /*default delay 800us*/
  1090. usleep_range(800, 810);
  1091. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  1092. wcd9378_set_swr_clk_rate(component, rate, bank);
  1093. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
  1094. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1095. wcd9378->tx_swr_dev->dev_num,
  1096. false);
  1097. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
  1098. wcd9378_set_swr_clk_rate(component, rate, !bank);
  1099. break;
  1100. default:
  1101. break;
  1102. }
  1103. return ret;
  1104. }
  1105. static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1106. struct snd_kcontrol *kcontrol,
  1107. int event)
  1108. {
  1109. struct snd_soc_component *component =
  1110. snd_soc_dapm_to_component(w->dapm);
  1111. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1112. int ret = 0;
  1113. switch (event) {
  1114. case SND_SOC_DAPM_PRE_PMU:
  1115. wcd9378_tx_connect_port(component, w->shift,
  1116. SWR_CLK_RATE_2P4MHZ, true);
  1117. break;
  1118. case SND_SOC_DAPM_POST_PMD:
  1119. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1120. wcd9378->tx_swr_dev->dev_num,
  1121. false);
  1122. break;
  1123. };
  1124. return ret;
  1125. }
  1126. /*
  1127. * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
  1128. * @component: handle to snd_soc_component *
  1129. *
  1130. * return wcd9378_mbhc handle or error code in case of failure
  1131. */
  1132. struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
  1133. {
  1134. struct wcd9378_priv *wcd9378;
  1135. if (!component) {
  1136. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  1137. return NULL;
  1138. }
  1139. wcd9378 = snd_soc_component_get_drvdata(component);
  1140. if (!wcd9378) {
  1141. pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
  1142. return NULL;
  1143. }
  1144. return wcd9378->mbhc;
  1145. }
  1146. EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
  1147. static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1148. struct snd_kcontrol *kcontrol,
  1149. int event)
  1150. {
  1151. struct snd_soc_component *component =
  1152. snd_soc_dapm_to_component(w->dapm);
  1153. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1154. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1155. w->name, event);
  1156. switch (event) {
  1157. case SND_SOC_DAPM_PRE_PMU:
  1158. /*HPHL ENABLE*/
  1159. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1160. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1161. wcd9378_rx_connect_port(component, HPH_L, true);
  1162. if (wcd9378->comp1_enable) {
  1163. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1164. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
  1165. wcd9378_rx_connect_port(component, COMP_L, true);
  1166. }
  1167. if (wcd9378->update_wcd_event)
  1168. wcd9378->update_wcd_event(wcd9378->handle,
  1169. SLV_BOLERO_EVT_RX_MUTE,
  1170. (WCD_RX1 << 0x10));
  1171. break;
  1172. case SND_SOC_DAPM_POST_PMD:
  1173. if (wcd9378->update_wcd_event)
  1174. wcd9378->update_wcd_event(wcd9378->handle,
  1175. SLV_BOLERO_EVT_RX_MUTE,
  1176. (WCD_RX1 << 0x10 | 0x1));
  1177. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1178. wcd9378->update_wcd_event(wcd9378->handle,
  1179. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1180. (WCD_RX1 << 0x10));
  1181. /*HPHL DISABLE*/
  1182. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1183. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1184. wcd9378_rx_connect_port(component, HPH_L, false);
  1185. if (wcd9378->comp1_enable) {
  1186. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1187. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
  1188. wcd9378_rx_connect_port(component, COMP_R, false);
  1189. }
  1190. break;
  1191. default:
  1192. break;
  1193. };
  1194. return 0;
  1195. }
  1196. static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1197. struct snd_kcontrol *kcontrol,
  1198. int event)
  1199. {
  1200. struct snd_soc_component *component =
  1201. snd_soc_dapm_to_component(w->dapm);
  1202. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1203. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1204. w->name, event);
  1205. switch (event) {
  1206. case SND_SOC_DAPM_PRE_PMU:
  1207. /*HPHR ENABLE*/
  1208. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1209. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1210. wcd9378_rx_connect_port(component, HPH_R, true);
  1211. if (wcd9378->comp2_enable) {
  1212. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1213. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
  1214. wcd9378_rx_connect_port(component, COMP_R, true);
  1215. }
  1216. break;
  1217. case SND_SOC_DAPM_POST_PMD:
  1218. /*HPHR DISABLE*/
  1219. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1220. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
  1221. wcd9378_rx_connect_port(component, HPH_R, false);
  1222. if (wcd9378->comp2_enable) {
  1223. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1224. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
  1225. wcd9378_rx_connect_port(component, COMP_R, false);
  1226. }
  1227. break;
  1228. default:
  1229. break;
  1230. };
  1231. return 0;
  1232. }
  1233. static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1234. struct snd_kcontrol *kcontrol,
  1235. int event)
  1236. {
  1237. struct snd_soc_component *component =
  1238. snd_soc_dapm_to_component(w->dapm);
  1239. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1240. int ret;
  1241. int bank = 0;
  1242. int act_ps = 0;
  1243. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1244. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1245. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1246. w->name, event);
  1247. switch (event) {
  1248. case SND_SOC_DAPM_PRE_PMU:
  1249. if (wcd9378->update_wcd_event)
  1250. wcd9378->update_wcd_event(wcd9378->handle,
  1251. SLV_BOLERO_EVT_RX_MUTE,
  1252. (WCD_RX1 << 0x10 | 0x01));
  1253. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1254. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1255. wcd9378->rx_swr_dev->dev_num,
  1256. true);
  1257. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1258. if (wcd9378->update_wcd_event)
  1259. wcd9378->update_wcd_event(wcd9378->handle,
  1260. SLV_BOLERO_EVT_RX_MUTE,
  1261. (WCD_RX1 << 0x10));
  1262. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1263. if (act_ps)
  1264. pr_err("%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1265. __func__, act_ps);
  1266. else
  1267. pr_err("%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1268. __func__, act_ps);
  1269. break;
  1270. case SND_SOC_DAPM_POST_PMD:
  1271. if (wcd9378->update_wcd_event)
  1272. wcd9378->update_wcd_event(wcd9378->handle,
  1273. SLV_BOLERO_EVT_RX_MUTE,
  1274. (WCD_RX1 << 0x10 | 0x1));
  1275. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1276. wcd9378->update_wcd_event(wcd9378->handle,
  1277. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1278. (WCD_RX1 << 0x10));
  1279. if (!wcd9378->comp1_enable)
  1280. /*PA delay is 24250us*/
  1281. usleep_range(24300, 24310);
  1282. else
  1283. /*COMP delay is 11250us*/
  1284. usleep_range(11300, 11310);
  1285. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1286. WCD_EVENT_POST_HPHL_PA_OFF,
  1287. &wcd9378->mbhc->wcd_mbhc);
  1288. break;
  1289. default:
  1290. break;
  1291. };
  1292. return 0;
  1293. }
  1294. static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1295. struct snd_kcontrol *kcontrol,
  1296. int event)
  1297. {
  1298. struct snd_soc_component *component =
  1299. snd_soc_dapm_to_component(w->dapm);
  1300. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1301. int ret;
  1302. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1303. w->name, event);
  1304. switch (event) {
  1305. case SND_SOC_DAPM_PRE_PMU:
  1306. if (wcd9378->update_wcd_event)
  1307. wcd9378->update_wcd_event(wcd9378->handle,
  1308. SLV_BOLERO_EVT_RX_MUTE,
  1309. (WCD_RX2 << 0x10 | 0x1));
  1310. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1311. wcd9378->rx_swr_dev->dev_num,
  1312. true);
  1313. if (wcd9378->update_wcd_event)
  1314. wcd9378->update_wcd_event(wcd9378->handle,
  1315. SLV_BOLERO_EVT_RX_MUTE,
  1316. (WCD_RX2 << 0x10));
  1317. break;
  1318. case SND_SOC_DAPM_POST_PMD:
  1319. if (wcd9378->update_wcd_event)
  1320. wcd9378->update_wcd_event(wcd9378->handle,
  1321. SLV_BOLERO_EVT_RX_MUTE,
  1322. (WCD_RX2 << 0x10 | 0x1));
  1323. if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
  1324. wcd9378->update_wcd_event(wcd9378->handle,
  1325. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1326. (WCD_RX2 << 0x10));
  1327. if (!wcd9378->comp2_enable)
  1328. /*PA delay is 24250us*/
  1329. usleep_range(24300, 24310);
  1330. else
  1331. /*COMP delay is 11250us*/
  1332. usleep_range(11300, 11310);
  1333. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1334. WCD_EVENT_POST_HPHR_PA_OFF,
  1335. &wcd9378->mbhc->wcd_mbhc);
  1336. break;
  1337. default:
  1338. break;
  1339. };
  1340. return 0;
  1341. }
  1342. static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1343. struct snd_kcontrol *kcontrol,
  1344. int event)
  1345. {
  1346. struct snd_soc_component *component =
  1347. snd_soc_dapm_to_component(w->dapm);
  1348. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1349. int ret = 0;
  1350. int bank = 0;
  1351. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1352. w->name, event);
  1353. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1354. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1355. switch (event) {
  1356. case SND_SOC_DAPM_PRE_PMU:
  1357. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1358. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1359. wcd9378->rx_swr_dev->dev_num,
  1360. true);
  1361. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1362. wcd9378->aux_rx_path =
  1363. (snd_soc_component_read(
  1364. component, WCD9378_CDC_HPH_GAIN_CTL) &
  1365. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK) >> 0x03;
  1366. if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
  1367. if (wcd9378->update_wcd_event)
  1368. wcd9378->update_wcd_event(wcd9378->handle,
  1369. SLV_BOLERO_EVT_RX_MUTE,
  1370. (WCD_RX2 << 0x10));
  1371. } else {
  1372. if (wcd9378->update_wcd_event)
  1373. wcd9378->update_wcd_event(wcd9378->handle,
  1374. SLV_BOLERO_EVT_RX_MUTE,
  1375. (WCD_RX3 << 0x10));
  1376. }
  1377. break;
  1378. case SND_SOC_DAPM_POST_PMD:
  1379. if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
  1380. if (wcd9378->update_wcd_event)
  1381. wcd9378->update_wcd_event(wcd9378->handle,
  1382. SLV_BOLERO_EVT_RX_MUTE,
  1383. (WCD_RX2 << 0x10 | 0x1));
  1384. } else {
  1385. if (wcd9378->update_wcd_event)
  1386. wcd9378->update_wcd_event(wcd9378->handle,
  1387. SLV_BOLERO_EVT_RX_MUTE,
  1388. (WCD_RX3 << 0x10 | 0x1));
  1389. }
  1390. break;
  1391. };
  1392. return ret;
  1393. }
  1394. static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1395. struct snd_kcontrol *kcontrol,
  1396. int event)
  1397. {
  1398. struct snd_soc_component *component =
  1399. snd_soc_dapm_to_component(w->dapm);
  1400. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1401. int ret = 0, bank = 0;
  1402. int act_ps = 0;
  1403. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1404. w->name, event);
  1405. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1406. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1407. switch (event) {
  1408. case SND_SOC_DAPM_PRE_PMU:
  1409. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1410. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1411. wcd9378->rx_swr_dev->dev_num,
  1412. true);
  1413. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1414. wcd9378->ear_rx_path =
  1415. (snd_soc_component_read(
  1416. component, WCD9378_CDC_HPH_GAIN_CTL) &
  1417. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK) >> 0x02;
  1418. if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
  1419. if (wcd9378->update_wcd_event)
  1420. wcd9378->update_wcd_event(wcd9378->handle,
  1421. SLV_BOLERO_EVT_RX_MUTE,
  1422. (WCD_RX1 << 0x10));
  1423. } else {
  1424. if (wcd9378->update_wcd_event)
  1425. wcd9378->update_wcd_event(wcd9378->handle,
  1426. SLV_BOLERO_EVT_RX_MUTE,
  1427. (WCD_RX3 << 0x10));
  1428. }
  1429. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1430. if (act_ps)
  1431. pr_err("%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1432. __func__, act_ps);
  1433. else
  1434. pr_err("%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1435. __func__, act_ps);
  1436. break;
  1437. case SND_SOC_DAPM_POST_PMD:
  1438. if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
  1439. if (wcd9378->update_wcd_event)
  1440. wcd9378->update_wcd_event(wcd9378->handle,
  1441. SLV_BOLERO_EVT_RX_MUTE,
  1442. (WCD_RX1 << 0x10 | 0x1));
  1443. } else {
  1444. if (wcd9378->update_wcd_event)
  1445. wcd9378->update_wcd_event(wcd9378->handle,
  1446. SLV_BOLERO_EVT_RX_MUTE,
  1447. (WCD_RX3 << 0x10 | 0x1));
  1448. }
  1449. break;
  1450. };
  1451. return ret;
  1452. }
  1453. static int wcd9378_get_hph_pwr_level(int hph_mode)
  1454. {
  1455. switch (hph_mode) {
  1456. case CLS_H_LOHIFI:
  1457. case CLS_AB_LOHIFI:
  1458. return PWR_LEVEL_LOHIFI_VAL;
  1459. case CLS_H_LP:
  1460. case CLS_AB_LP:
  1461. return PWR_LEVEL_LP_VAL;
  1462. case CLS_H_HIFI:
  1463. case CLS_AB_HIFI:
  1464. return PWR_LEVEL_HIFI_VAL;
  1465. case CLS_H_ULP:
  1466. case CLS_AB:
  1467. case CLS_H_NORMAL:
  1468. default:
  1469. return PWR_LEVEL_ULP_VAL;
  1470. }
  1471. return PWR_LEVEL_ULP_VAL;
  1472. }
  1473. static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
  1474. {
  1475. struct wcd9378_priv *wcd9378 =
  1476. snd_soc_component_get_drvdata(component);
  1477. if ((!wcd9378->comp1_enable) &&
  1478. (!wcd9378->comp2_enable)) {
  1479. dev_err(component->dev, "%s hph gainis 0x%0xd\n", __func__, wcd9378->hph_gain);
  1480. snd_soc_component_update_bits(component,
  1481. (WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
  1482. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1483. wcd9378->hph_gain >> 8);
  1484. snd_soc_component_update_bits(component,
  1485. WCD9378_FU42_CH_VOL_CH1,
  1486. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1487. wcd9378->hph_gain & 0x00ff);
  1488. snd_soc_component_update_bits(component,
  1489. (WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
  1490. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1491. wcd9378->hph_gain >> 8);
  1492. snd_soc_component_update_bits(component,
  1493. WCD9378_FU42_CH_VOL_CH2,
  1494. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1495. wcd9378->hph_gain & 0x00ff);
  1496. }
  1497. }
  1498. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable)
  1499. {
  1500. u16 clk_scale_reg = 0;
  1501. u8 clk_rst = 0x00, scale_rst = 0x00;
  1502. struct wcd9378_priv *wcd9378 = NULL;
  1503. struct swr_device *swr_dev = NULL;
  1504. wcd9378 = dev_get_drvdata(dev);
  1505. if (!wcd9378)
  1506. return -EINVAL;
  1507. if (path == RX_PATH)
  1508. swr_dev = wcd9378->rx_swr_dev;
  1509. else
  1510. swr_dev = wcd9378->tx_swr_dev;
  1511. clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  1512. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  1513. if (enable) {
  1514. pr_debug("%s: bank: %d base_clk: 0x%0x, clk_scale_reg: 0x%0x, swr_clk_scale: 0x%0x\n",
  1515. __func__, bank, wcd9378->swr_base_clk,
  1516. clk_scale_reg, wcd9378->swr_clk_scale);
  1517. swr_write(swr_dev, swr_dev->dev_num,
  1518. SWRS_SCP_BASE_CLK_BASE, &wcd9378->swr_base_clk);
  1519. swr_write(swr_dev, swr_dev->dev_num,
  1520. clk_scale_reg, &wcd9378->swr_clk_scale);
  1521. } else {
  1522. swr_write(swr_dev, swr_dev->dev_num,
  1523. SWRS_SCP_BASE_CLK_BASE, &clk_rst);
  1524. swr_write(swr_dev, swr_dev->dev_num,
  1525. clk_scale_reg, &scale_rst);
  1526. }
  1527. return 0;
  1528. }
  1529. static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
  1530. struct snd_kcontrol *kcontrol, int event)
  1531. {
  1532. struct snd_soc_component *component =
  1533. snd_soc_dapm_to_component(w->dapm);
  1534. struct wcd9378_priv *wcd9378 =
  1535. snd_soc_component_get_drvdata(component);
  1536. int power_level;
  1537. struct swr_device *swr_dev = wcd9378->tx_swr_dev;
  1538. u8 scp_commit_val = 0x2;
  1539. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1540. w->name, event);
  1541. switch (event) {
  1542. case SND_SOC_DAPM_PRE_PMU:
  1543. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
  1544. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
  1545. WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
  1546. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
  1547. WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
  1548. }
  1549. if ((wcd9378->hph_mode == CLS_AB) ||
  1550. (wcd9378->hph_mode == CLS_AB_HIFI) ||
  1551. (wcd9378->hph_mode == CLS_AB_LP) ||
  1552. (wcd9378->hph_mode == CLS_AB_LOHIFI))
  1553. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1554. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1555. /*GET HPH_MODE*/
  1556. power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
  1557. /*SET HPH_MODE*/
  1558. snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
  1559. WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
  1560. /*TURN ON HPH SEQUENCER*/
  1561. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1562. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
  1563. /*TBD: SET SDCA GAIN, NEED CHECK THE LOGIC*/
  1564. wcd9378_hph_set_channel_volume(component);
  1565. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
  1566. /*PA delay is 22400us*/
  1567. usleep_range(22500, 22510);
  1568. else
  1569. /*COMP delay is 9400us*/
  1570. usleep_range(9500, 9510);
  1571. /*RX0 unmute*/
  1572. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1573. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
  1574. /*RX1 unmute*/
  1575. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1576. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
  1577. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
  1578. break;
  1579. case SND_SOC_DAPM_POST_PMD:
  1580. /*RX0 mute*/
  1581. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1582. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
  1583. /*RX1 mute*/
  1584. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1585. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
  1586. /*TEAR DOWN HPH SEQUENCER*/
  1587. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1588. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
  1589. break;
  1590. default:
  1591. break;
  1592. };
  1593. return 0;
  1594. }
  1595. static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1596. struct snd_kcontrol *kcontrol,
  1597. int event)
  1598. {
  1599. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1600. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1601. int ear_rx0 = 0;
  1602. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1603. w->name, event);
  1604. ear_rx0 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
  1605. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK;
  1606. switch (event) {
  1607. case SND_SOC_DAPM_PRE_PMU:
  1608. /*CHECK IF EAR CONNET TO RX2*/
  1609. if (!ear_rx0) {
  1610. pr_debug("%s: ear rx2 enter\n", __func__);
  1611. /*FORCE CLASS_AB EN*/
  1612. snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
  1613. WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
  1614. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1615. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1616. /*RX2 ENABLE*/
  1617. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1618. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
  1619. if (wcd9378->rx2_clk_mode)
  1620. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1621. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1622. wcd9378_rx_connect_port(component, LO, true);
  1623. } else {
  1624. pr_debug("%s: ear rx0 enter\n", __func__);
  1625. if (wcd9378->comp1_enable) {
  1626. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1627. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
  1628. wcd9378_rx_connect_port(component, COMP_L, true);
  1629. }
  1630. wcd9378_rx_connect_port(component, HPH_L, true);
  1631. }
  1632. break;
  1633. case SND_SOC_DAPM_POST_PMD:
  1634. if (ear_rx0) {
  1635. /*RX0 DISABLE*/
  1636. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1637. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1638. wcd9378_rx_connect_port(component, HPH_L, false);
  1639. if (wcd9378->comp1_enable) {
  1640. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1641. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
  1642. wcd9378_rx_connect_port(component, COMP_L, false);
  1643. }
  1644. } else {
  1645. /*RX1 DISABLE*/
  1646. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1647. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
  1648. wcd9378_rx_connect_port(component, LO, false);
  1649. }
  1650. break;
  1651. };
  1652. return 0;
  1653. }
  1654. static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  1655. struct snd_kcontrol *kcontrol,
  1656. int event)
  1657. {
  1658. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1659. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1660. int aux_rx1 = 0;
  1661. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1662. w->name, event);
  1663. aux_rx1 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
  1664. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK;
  1665. switch (event) {
  1666. case SND_SOC_DAPM_PRE_PMU:
  1667. if (aux_rx1) {
  1668. wcd9378_rx_connect_port(component, HPH_R, true);
  1669. } else {
  1670. /*RX2 ENABLE*/
  1671. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1672. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
  1673. if (wcd9378->rx2_clk_mode)
  1674. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1675. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1676. wcd9378_rx_connect_port(component, LO, true);
  1677. }
  1678. set_bit(WCD_AUX_EN, &wcd9378->status_mask);
  1679. break;
  1680. case SND_SOC_DAPM_POST_PMD:
  1681. if (aux_rx1) {
  1682. wcd9378_rx_connect_port(component, HPH_R, false);
  1683. } else {
  1684. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1685. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
  1686. wcd9378_rx_connect_port(component, LO, true);
  1687. }
  1688. clear_bit(WCD_AUX_EN, &wcd9378->status_mask);
  1689. break;
  1690. };
  1691. return 0;
  1692. }
  1693. static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
  1694. struct snd_kcontrol *kcontrol, int event)
  1695. {
  1696. struct snd_soc_component *component =
  1697. snd_soc_dapm_to_component(w->dapm);
  1698. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1699. w->name, event);
  1700. switch (event) {
  1701. case SND_SOC_DAPM_PRE_PMU:
  1702. /*TURN ON AMP SEQUENCER*/
  1703. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1704. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
  1705. /*default delay 8550us*/
  1706. usleep_range(8600, 8610);
  1707. /*FU23 UNMUTE*/
  1708. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1709. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1710. break;
  1711. case SND_SOC_DAPM_POST_PMD:
  1712. /*FU23 MUTE*/
  1713. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1714. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
  1715. /*TEAR DOWN AMP SEQUENCER*/
  1716. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1717. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
  1718. /*default delay 1530us*/
  1719. usleep_range(15400, 15410);
  1720. break;
  1721. default:
  1722. break;
  1723. };
  1724. return 0;
  1725. }
  1726. int wcd9378_micbias_control(struct snd_soc_component *component,
  1727. int micb_num, int req, bool is_dapm)
  1728. {
  1729. struct wcd9378_priv *wcd9378 =
  1730. snd_soc_component_get_drvdata(component);
  1731. struct wcd9378_pdata *pdata =
  1732. dev_get_platdata(wcd9378->dev);
  1733. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  1734. int micb_index = micb_num - 1;
  1735. int pre_off_event = 0, post_off_event = 0;
  1736. int post_on_event = 0, post_dapm_off = 0;
  1737. int post_dapm_on = 0;
  1738. int ret = 0, sm_num = 0;
  1739. int micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
  1740. int pull_up_mask = 0, pull_up_en = 0;
  1741. dev_dbg(component->dev, "%s: enter, micb_num: %d, req: %d\n",
  1742. __func__, micb_num, req);
  1743. if ((micb_index < 0) || (micb_index > WCD9378_MAX_MICBIAS)) {
  1744. dev_err(component->dev,
  1745. "%s: Invalid micbias index, micb_index:%d\n",
  1746. __func__, micb_index);
  1747. return -EINVAL;
  1748. }
  1749. if (wcd9378 == NULL) {
  1750. dev_err(component->dev,
  1751. "%s: wcd9378 private data is NULL\n", __func__);
  1752. return -EINVAL;
  1753. }
  1754. for (sm_num = 0; sm_num < SIM_MIC_NUM; sm_num++)
  1755. if (wcd9378->micb_sel[sm_num] == micb_num)
  1756. break;
  1757. if ((sm_num == SIM_MIC_NUM) && (micb_num != MIC_BIAS_2)) {
  1758. pr_err("%s: cannot find the simple mic function which connect to micbias_%d\n",
  1759. __func__, micb_num);
  1760. return -EINVAL;
  1761. }
  1762. dev_err(component->dev, "%s: function num: %d\n",
  1763. __func__, sm_num);
  1764. switch (sm_num) {
  1765. case SIM_MIC0:
  1766. micb_usage = WCD9378_IT11_MICB;
  1767. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  1768. break;
  1769. case SIM_MIC1:
  1770. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  1771. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  1772. break;
  1773. case SIM_MIC2:
  1774. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  1775. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  1776. break;
  1777. default:
  1778. dev_err(component->dev, "%s: switch default enter: %d\n",
  1779. __func__, sm_num);
  1780. if (micb_num == MIC_BIAS_2) {
  1781. micb_usage = WCD9378_IT31_MICB;
  1782. micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
  1783. }
  1784. break;
  1785. }
  1786. dev_err(component->dev, "%s: sm_num: %d\n",
  1787. __func__, sm_num);
  1788. switch (micb_num) {
  1789. case MIC_BIAS_1:
  1790. pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
  1791. pull_up_en = 0x01;
  1792. micb_usage_val = mb->micb1_usage_val;
  1793. break;
  1794. case MIC_BIAS_2:
  1795. pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
  1796. pull_up_en = 0x02;
  1797. micb_usage_val = mb->micb2_usage_val;
  1798. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1799. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1800. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1801. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1802. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1803. break;
  1804. case MIC_BIAS_3:
  1805. pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
  1806. pull_up_en = 0x04;
  1807. micb_usage_val = mb->micb3_usage_val;
  1808. break;
  1809. default:
  1810. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1811. __func__, micb_num);
  1812. return -EINVAL;
  1813. }
  1814. mutex_lock(&wcd9378->micb_lock);
  1815. switch (req) {
  1816. case MICB_PULLUP_ENABLE:
  1817. if (!wcd9378->dev_up) {
  1818. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1819. __func__, req);
  1820. ret = -ENODEV;
  1821. goto done;
  1822. }
  1823. wcd9378->pullup_ref[micb_index]++;
  1824. if ((wcd9378->pullup_ref[micb_index] == 1) &&
  1825. (wcd9378->micb_ref[micb_index] == 0)) {
  1826. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1827. pull_up_mask, pull_up_en);
  1828. snd_soc_component_update_bits(component,
  1829. micb_usage, micb_mask, 0x03);
  1830. }
  1831. break;
  1832. case MICB_PULLUP_DISABLE:
  1833. if (wcd9378->pullup_ref[micb_index] > 0)
  1834. wcd9378->pullup_ref[micb_index]--;
  1835. if (!wcd9378->dev_up) {
  1836. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1837. __func__, req);
  1838. ret = -ENODEV;
  1839. goto done;
  1840. }
  1841. if ((wcd9378->pullup_ref[micb_index] == 0) &&
  1842. (wcd9378->micb_ref[micb_index] == 0))
  1843. snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
  1844. break;
  1845. case MICB_ENABLE:
  1846. dev_dbg(component->dev, "%s: micbias enable enter\n",
  1847. __func__);
  1848. if (!wcd9378->dev_up) {
  1849. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1850. __func__, req);
  1851. ret = -ENODEV;
  1852. goto done;
  1853. }
  1854. wcd9378->micb_ref[micb_index]++;
  1855. if (wcd9378->micb_ref[micb_index] == 1) {
  1856. dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
  1857. __func__, micb_usage, micb_usage_val);
  1858. snd_soc_component_update_bits(component,
  1859. micb_usage, micb_mask, micb_usage_val);
  1860. if (post_on_event)
  1861. blocking_notifier_call_chain(
  1862. &wcd9378->mbhc->notifier,
  1863. post_on_event,
  1864. &wcd9378->mbhc->wcd_mbhc);
  1865. }
  1866. if (is_dapm && post_dapm_on && wcd9378->mbhc)
  1867. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1868. post_dapm_on,
  1869. &wcd9378->mbhc->wcd_mbhc);
  1870. break;
  1871. case MICB_DISABLE:
  1872. if (wcd9378->micb_ref[micb_index] > 0)
  1873. wcd9378->micb_ref[micb_index]--;
  1874. if (!wcd9378->dev_up) {
  1875. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1876. __func__, req);
  1877. ret = -ENODEV;
  1878. goto done;
  1879. }
  1880. if ((wcd9378->micb_ref[micb_index] == 0) &&
  1881. (wcd9378->pullup_ref[micb_index] > 0)) {
  1882. /*PULL UP?*/
  1883. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1884. pull_up_mask, pull_up_en);
  1885. snd_soc_component_update_bits(component, micb_usage,
  1886. micb_mask, 0x03);
  1887. } else if ((wcd9378->micb_ref[micb_index] == 0) &&
  1888. (wcd9378->pullup_ref[micb_index] == 0)) {
  1889. if (pre_off_event && wcd9378->mbhc)
  1890. blocking_notifier_call_chain(
  1891. &wcd9378->mbhc->notifier,
  1892. pre_off_event,
  1893. &wcd9378->mbhc->wcd_mbhc);
  1894. snd_soc_component_update_bits(component, micb_usage,
  1895. micb_mask, 0x00);
  1896. if (post_off_event && wcd9378->mbhc)
  1897. blocking_notifier_call_chain(
  1898. &wcd9378->mbhc->notifier,
  1899. post_off_event,
  1900. &wcd9378->mbhc->wcd_mbhc);
  1901. }
  1902. if (is_dapm && post_dapm_off && wcd9378->mbhc)
  1903. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1904. post_dapm_off,
  1905. &wcd9378->mbhc->wcd_mbhc);
  1906. break;
  1907. default:
  1908. dev_err(component->dev, "%s: Invalid req event: %d\n",
  1909. __func__, req);
  1910. return -EINVAL;
  1911. }
  1912. dev_dbg(component->dev,
  1913. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1914. __func__, micb_num, wcd9378->micb_ref[micb_index],
  1915. wcd9378->pullup_ref[micb_index]);
  1916. done:
  1917. mutex_unlock(&wcd9378->micb_lock);
  1918. return ret;
  1919. }
  1920. EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
  1921. static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
  1922. {
  1923. int ret = 0;
  1924. uint8_t devnum = 0;
  1925. int num_retry = NUM_ATTEMPTS;
  1926. do {
  1927. /* retry after 4ms */
  1928. usleep_range(4000, 4010);
  1929. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1930. } while (ret && --num_retry);
  1931. if (ret)
  1932. dev_err(&swr_dev->dev,
  1933. "%s get devnum %d for dev addr %llx failed\n",
  1934. __func__, devnum, swr_dev->addr);
  1935. swr_dev->dev_num = devnum;
  1936. return 0;
  1937. }
  1938. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1939. struct wcd_mbhc_config *mbhc_cfg)
  1940. {
  1941. if (mbhc_cfg->enable_usbc_analog) {
  1942. if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
  1943. & 0x20))
  1944. return true;
  1945. }
  1946. return false;
  1947. }
  1948. int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
  1949. struct notifier_block *nblock,
  1950. bool enable)
  1951. {
  1952. struct wcd9378_priv *wcd9378_priv = NULL;
  1953. if (component == NULL) {
  1954. pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
  1955. return -EINVAL;
  1956. }
  1957. wcd9378_priv = snd_soc_component_get_drvdata(component);
  1958. wcd9378_priv->notify_swr_dmic = enable;
  1959. if (enable)
  1960. return blocking_notifier_chain_register(&wcd9378_priv->notifier,
  1961. nblock);
  1962. else
  1963. return blocking_notifier_chain_unregister(
  1964. &wcd9378_priv->notifier, nblock);
  1965. }
  1966. EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
  1967. /*TBD: NEED TO CHECK AND UPDATE*/
  1968. static int wcd9378_event_notify(struct notifier_block *block,
  1969. unsigned long val,
  1970. void *data)
  1971. {
  1972. u16 event = (val & 0xffff);
  1973. int ret = 0;
  1974. struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
  1975. struct snd_soc_component *component = wcd9378->component;
  1976. struct wcd_mbhc *mbhc;
  1977. int rx_clk_type;
  1978. switch (event) {
  1979. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1980. if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
  1981. snd_soc_component_update_bits(component,
  1982. WCD9378_ANA_TX_CH2, 0x40, 0x00);
  1983. set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
  1984. clear_bit(WCD_ADC1, &wcd9378->status_mask);
  1985. }
  1986. if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
  1987. snd_soc_component_update_bits(component,
  1988. WCD9378_ANA_TX_CH2, 0x20, 0x00);
  1989. set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
  1990. clear_bit(WCD_ADC2, &wcd9378->status_mask);
  1991. }
  1992. if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
  1993. snd_soc_component_update_bits(component,
  1994. WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
  1995. set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
  1996. clear_bit(WCD_ADC3, &wcd9378->status_mask);
  1997. }
  1998. break;
  1999. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2000. snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
  2001. 0xC0, 0x00);
  2002. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  2003. 0x80, 0x00);
  2004. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  2005. 0x80, 0x00);
  2006. break;
  2007. case BOLERO_SLV_EVT_SSR_DOWN:
  2008. wcd9378->dev_up = false;
  2009. if (wcd9378->notify_swr_dmic)
  2010. blocking_notifier_call_chain(&wcd9378->notifier,
  2011. WCD9378_EVT_SSR_DOWN,
  2012. NULL);
  2013. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
  2014. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2015. wcd9378->usbc_hs_status = get_usbc_hs_status(component,
  2016. mbhc->mbhc_cfg);
  2017. wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
  2018. wcd9378_reset_low(wcd9378->dev);
  2019. break;
  2020. case BOLERO_SLV_EVT_SSR_UP:
  2021. wcd9378_reset(wcd9378->dev);
  2022. /* allow reset to take effect */
  2023. usleep_range(10000, 10010);
  2024. wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
  2025. wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
  2026. wcd9378_init_reg(component);
  2027. regcache_mark_dirty(wcd9378->regmap);
  2028. regcache_sync(wcd9378->regmap);
  2029. /* Initialize MBHC module */
  2030. mbhc = &wcd9378->mbhc->wcd_mbhc;
  2031. ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
  2032. if (ret) {
  2033. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2034. __func__);
  2035. } else {
  2036. wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2037. }
  2038. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
  2039. wcd9378->dev_up = true;
  2040. if (wcd9378->notify_swr_dmic)
  2041. blocking_notifier_call_chain(&wcd9378->notifier,
  2042. WCD9378_EVT_SSR_UP,
  2043. NULL);
  2044. if (wcd9378->usbc_hs_status)
  2045. mdelay(500);
  2046. break;
  2047. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2048. snd_soc_component_update_bits(component,
  2049. WCD9378_TOP_CLK_CFG, 0x06,
  2050. ((val >> 0x10) << 0x01));
  2051. rx_clk_type = (val >> 0x10);
  2052. switch (rx_clk_type) {
  2053. case RX_CLK_12P288MHZ:
  2054. wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
  2055. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2056. break;
  2057. case RX_CLK_11P2896MHZ:
  2058. wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
  2059. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2060. break;
  2061. default:
  2062. wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
  2063. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2064. break;
  2065. }
  2066. dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
  2067. __func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
  2068. break;
  2069. default:
  2070. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2071. break;
  2072. }
  2073. return 0;
  2074. }
  2075. static int wcd9378_wakeup(void *handle, bool enable)
  2076. {
  2077. struct wcd9378_priv *priv;
  2078. int ret = 0;
  2079. if (!handle) {
  2080. pr_err("%s: NULL handle\n", __func__);
  2081. return -EINVAL;
  2082. }
  2083. priv = (struct wcd9378_priv *)handle;
  2084. if (!priv->tx_swr_dev) {
  2085. pr_err("%s: tx swr dev is NULL\n", __func__);
  2086. return -EINVAL;
  2087. }
  2088. mutex_lock(&priv->wakeup_lock);
  2089. if (enable)
  2090. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2091. else
  2092. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2093. mutex_unlock(&priv->wakeup_lock);
  2094. return ret;
  2095. }
  2096. static inline int wcd9378_tx_path_get(const char *wname,
  2097. unsigned int *path_num)
  2098. {
  2099. int ret = 0;
  2100. char *widget_name = NULL;
  2101. char *w_name = NULL;
  2102. char *path_num_char = NULL;
  2103. char *path_name = NULL;
  2104. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2105. if (!widget_name)
  2106. return -EINVAL;
  2107. w_name = widget_name;
  2108. path_name = strsep(&widget_name, " ");
  2109. if (!path_name) {
  2110. pr_err("%s: Invalid widget name = %s\n",
  2111. __func__, widget_name);
  2112. ret = -EINVAL;
  2113. goto err;
  2114. }
  2115. path_num_char = strpbrk(path_name, "0123");
  2116. if (!path_num_char) {
  2117. pr_err("%s: tx path index not found\n",
  2118. __func__);
  2119. ret = -EINVAL;
  2120. goto err;
  2121. }
  2122. ret = kstrtouint(path_num_char, 10, path_num);
  2123. if (ret < 0)
  2124. pr_err("%s: Invalid tx path = %s\n",
  2125. __func__, w_name);
  2126. err:
  2127. kfree(w_name);
  2128. return ret;
  2129. }
  2130. static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
  2131. struct snd_ctl_elem_value *ucontrol)
  2132. {
  2133. struct snd_soc_component *component =
  2134. snd_soc_kcontrol_component(kcontrol);
  2135. struct wcd9378_priv *wcd9378 = NULL;
  2136. int ret = 0;
  2137. unsigned int path = 0;
  2138. if (!component)
  2139. return -EINVAL;
  2140. wcd9378 = snd_soc_component_get_drvdata(component);
  2141. if (!wcd9378)
  2142. return -EINVAL;
  2143. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2144. if (ret < 0)
  2145. return ret;
  2146. ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
  2147. return 0;
  2148. }
  2149. static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
  2150. struct snd_ctl_elem_value *ucontrol)
  2151. {
  2152. struct snd_soc_component *component =
  2153. snd_soc_kcontrol_component(kcontrol);
  2154. struct wcd9378_priv *wcd9378 = NULL;
  2155. u32 mode_val;
  2156. unsigned int path = 0;
  2157. int ret = 0;
  2158. if (!component)
  2159. return -EINVAL;
  2160. wcd9378 = snd_soc_component_get_drvdata(component);
  2161. if (!wcd9378)
  2162. return -EINVAL;
  2163. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2164. if (ret)
  2165. return ret;
  2166. mode_val = ucontrol->value.enumerated.item[0];
  2167. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2168. wcd9378->tx_mode[path] = mode_val;
  2169. return 0;
  2170. }
  2171. static int wcd9378_sys_usage_get(struct snd_kcontrol *kcontrol,
  2172. struct snd_ctl_elem_value *ucontrol)
  2173. {
  2174. struct snd_soc_component *component =
  2175. snd_soc_kcontrol_component(kcontrol);
  2176. u32 sys_usage_val = 0;
  2177. if (!component)
  2178. return -EINVAL;
  2179. sys_usage_val = (snd_soc_component_read(component, WCD9378_SYS_USAGE_CTRL) &
  2180. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK);
  2181. ucontrol->value.integer.value[0] = sys_usage_val;
  2182. return 0;
  2183. }
  2184. static int wcd9378_sys_usage_put(struct snd_kcontrol *kcontrol,
  2185. struct snd_ctl_elem_value *ucontrol)
  2186. {
  2187. struct snd_soc_component *component =
  2188. snd_soc_kcontrol_component(kcontrol);
  2189. struct wcd9378_priv *wcd9378 = NULL;
  2190. u32 sys_usage_val = 0;
  2191. if (!component)
  2192. return -EINVAL;
  2193. wcd9378 = snd_soc_component_get_drvdata(component);
  2194. if (!wcd9378)
  2195. return -EINVAL;
  2196. sys_usage_val = ucontrol->value.enumerated.item[0];
  2197. if (sys_usage_val >= WCD_SYS_USAGE_MAX) {
  2198. dev_err(component->dev, "%s: unsupport sys_usage_val: %d\n",
  2199. __func__, sys_usage_val);
  2200. return -EINVAL;
  2201. }
  2202. snd_soc_component_update_bits(component,
  2203. WCD9378_SYS_USAGE_CTRL,
  2204. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  2205. sys_usage_val);
  2206. wcd9378->sys_usage = sys_usage_val;
  2207. dev_dbg(component->dev, "%s: sys_usage_val: %d\n", __func__, wcd9378->sys_usage);
  2208. return 0;
  2209. }
  2210. static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
  2211. struct snd_ctl_elem_value *ucontrol)
  2212. {
  2213. struct snd_soc_component *component =
  2214. snd_soc_kcontrol_component(kcontrol);
  2215. u32 loopback_mode = 0;
  2216. if (!component)
  2217. return -EINVAL;
  2218. loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
  2219. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
  2220. ucontrol->value.integer.value[0] = loopback_mode;
  2221. return 0;
  2222. }
  2223. static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
  2224. struct snd_ctl_elem_value *ucontrol)
  2225. {
  2226. struct snd_soc_component *component =
  2227. snd_soc_kcontrol_component(kcontrol);
  2228. u32 loopback_mode = 0;
  2229. if (!component)
  2230. return -EINVAL;
  2231. loopback_mode = ucontrol->value.enumerated.item[0];
  2232. snd_soc_component_update_bits(component,
  2233. WCD9378_LOOP_BACK_MODE,
  2234. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
  2235. loopback_mode);
  2236. dev_dbg(component->dev, "%s: loopback_mode: %d\n",
  2237. __func__, loopback_mode);
  2238. return 0;
  2239. }
  2240. static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
  2241. struct snd_ctl_elem_value *ucontrol)
  2242. {
  2243. struct snd_soc_component *component =
  2244. snd_soc_kcontrol_component(kcontrol);
  2245. u32 aux_dsm_in = 0;
  2246. if (!component)
  2247. return -EINVAL;
  2248. aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2249. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
  2250. ucontrol->value.integer.value[0] = aux_dsm_in;
  2251. return 0;
  2252. }
  2253. static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
  2254. struct snd_ctl_elem_value *ucontrol)
  2255. {
  2256. struct snd_soc_component *component =
  2257. snd_soc_kcontrol_component(kcontrol);
  2258. u32 aux_dsm_in = 0;
  2259. if (!component)
  2260. return -EINVAL;
  2261. aux_dsm_in = ucontrol->value.enumerated.item[0];
  2262. snd_soc_component_update_bits(component,
  2263. WCD9378_LB_IN_SEL_CTL,
  2264. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
  2265. aux_dsm_in);
  2266. dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
  2267. __func__, aux_dsm_in);
  2268. return 0;
  2269. }
  2270. static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
  2271. struct snd_ctl_elem_value *ucontrol)
  2272. {
  2273. struct snd_soc_component *component =
  2274. snd_soc_kcontrol_component(kcontrol);
  2275. u32 hph_dsm_in = 0;
  2276. if (!component)
  2277. return -EINVAL;
  2278. hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2279. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
  2280. ucontrol->value.integer.value[0] = hph_dsm_in;
  2281. return 0;
  2282. }
  2283. static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
  2284. struct snd_ctl_elem_value *ucontrol)
  2285. {
  2286. struct snd_soc_component *component =
  2287. snd_soc_kcontrol_component(kcontrol);
  2288. u32 hph_dsm_in = 0;
  2289. if (!component)
  2290. return -EINVAL;
  2291. hph_dsm_in = ucontrol->value.enumerated.item[0];
  2292. snd_soc_component_update_bits(component,
  2293. WCD9378_LB_IN_SEL_CTL,
  2294. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
  2295. hph_dsm_in);
  2296. dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
  2297. __func__, hph_dsm_in);
  2298. return 0;
  2299. }
  2300. static inline int wcd9378_simple_mic_num_get(const char *wname,
  2301. unsigned int *sm_num)
  2302. {
  2303. int ret = 0;
  2304. char *widget_name = NULL;
  2305. char *w_name = NULL;
  2306. char *sm_num_char = NULL;
  2307. char *sm_name = NULL;
  2308. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2309. if (!widget_name)
  2310. return -EINVAL;
  2311. w_name = widget_name;
  2312. sm_name = strsep(&widget_name, " ");
  2313. if (!sm_name) {
  2314. pr_err("%s: Invalid widget name = %s\n",
  2315. __func__, widget_name);
  2316. ret = -EINVAL;
  2317. goto err;
  2318. }
  2319. sm_num_char = strpbrk(sm_name, "0123");
  2320. if (!sm_num_char) {
  2321. pr_err("%s: simple mic index not found\n",
  2322. __func__);
  2323. ret = -EINVAL;
  2324. goto err;
  2325. }
  2326. ret = kstrtouint(sm_num_char, 10, sm_num);
  2327. if (ret < 0)
  2328. pr_err("%s: Invalid micb num = %s\n",
  2329. __func__, w_name);
  2330. err:
  2331. kfree(w_name);
  2332. return ret;
  2333. }
  2334. static int wcd9378_mb_sel_get(struct snd_kcontrol *kcontrol,
  2335. struct snd_ctl_elem_value *ucontrol)
  2336. {
  2337. struct snd_soc_component *component =
  2338. snd_soc_kcontrol_component(kcontrol);
  2339. struct wcd9378_priv *wcd9378 = NULL;
  2340. int ret = 0;
  2341. unsigned int sm_num = 0;
  2342. if (!component)
  2343. return -EINVAL;
  2344. wcd9378 = snd_soc_component_get_drvdata(component);
  2345. if (!wcd9378)
  2346. return -EINVAL;
  2347. ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
  2348. if (ret < 0)
  2349. return ret;
  2350. ucontrol->value.integer.value[0] = wcd9378->micb_sel[sm_num];
  2351. return 0;
  2352. }
  2353. static int wcd9378_mb_sel_put(struct snd_kcontrol *kcontrol,
  2354. struct snd_ctl_elem_value *ucontrol)
  2355. {
  2356. struct snd_soc_component *component =
  2357. snd_soc_kcontrol_component(kcontrol);
  2358. struct wcd9378_priv *wcd9378 = NULL;
  2359. u32 mode_val;
  2360. unsigned int sm_num = 0;
  2361. int ret = 0;
  2362. if (!component)
  2363. return -EINVAL;
  2364. wcd9378 = snd_soc_component_get_drvdata(component);
  2365. if (!wcd9378)
  2366. return -EINVAL;
  2367. ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
  2368. if (ret)
  2369. return ret;
  2370. mode_val = ucontrol->value.enumerated.item[0];
  2371. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2372. wcd9378->micb_sel[sm_num] = mode_val;
  2373. return 0;
  2374. }
  2375. /*TBD: NEED CHECK THE LOGIC*/
  2376. static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
  2377. struct snd_ctl_elem_value *ucontrol)
  2378. {
  2379. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2380. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2381. u16 offset = ucontrol->value.enumerated.item[0];
  2382. u32 temp = 0;
  2383. temp = 0x00 - offset * 0x180;
  2384. wcd9378->hph_gain = (u16)(temp & 0xffff);
  2385. dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
  2386. return 0;
  2387. }
  2388. static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
  2389. struct snd_ctl_elem_value *ucontrol)
  2390. {
  2391. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2392. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2393. u32 temp = 0;
  2394. u16 offset = 0;
  2395. temp = 0 - wcd9378->hph_gain;
  2396. offset = (u16)(temp & 0xffff);
  2397. offset /= 0x180;
  2398. ucontrol->value.enumerated.item[0] = offset;
  2399. dev_dbg(component->dev, "%s: offset is 0x%0x\n", __func__, offset);
  2400. return 0;
  2401. }
  2402. static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
  2403. struct snd_ctl_elem_value *ucontrol)
  2404. {
  2405. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2406. struct wcd9378_priv *wcd9378 =
  2407. snd_soc_component_get_drvdata(component);
  2408. if (ucontrol->value.enumerated.item[0])
  2409. wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
  2410. else
  2411. wcd9378->rx2_clk_mode = RX2_HP_MODE;
  2412. return 1;
  2413. }
  2414. static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2415. struct snd_ctl_elem_value *ucontrol)
  2416. {
  2417. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2418. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2419. ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
  2420. return 0;
  2421. }
  2422. static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2423. struct snd_ctl_elem_value *ucontrol)
  2424. {
  2425. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2426. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2427. if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
  2428. return 0;
  2429. wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
  2430. return 1;
  2431. }
  2432. /* wcd9378_codec_get_dev_num - returns swr device number
  2433. * @component: Codec instance
  2434. *
  2435. * Return: swr device number on success or negative error
  2436. * code on failure.
  2437. */
  2438. int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
  2439. {
  2440. struct wcd9378_priv *wcd9378;
  2441. if (!component)
  2442. return -EINVAL;
  2443. wcd9378 = snd_soc_component_get_drvdata(component);
  2444. if (!wcd9378 || !wcd9378->rx_swr_dev) {
  2445. pr_err("%s: wcd9378 component is NULL\n", __func__);
  2446. return -EINVAL;
  2447. }
  2448. return wcd9378->rx_swr_dev->dev_num;
  2449. }
  2450. EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
  2451. static int wcd9378_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
  2452. struct snd_ctl_elem_value *ucontrol)
  2453. {
  2454. struct snd_soc_component *component =
  2455. snd_soc_kcontrol_component(kcontrol);
  2456. struct wcd9378_priv *wcd9378 =
  2457. snd_soc_component_get_drvdata(component);
  2458. if (wcd9378->comp1_enable) {
  2459. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2460. return -EINVAL;
  2461. }
  2462. snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
  2463. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
  2464. ucontrol->value.integer.value[0]);
  2465. return 1;
  2466. }
  2467. static int wcd9378_aux_pa_put_gain(struct snd_kcontrol *kcontrol,
  2468. struct snd_ctl_elem_value *ucontrol)
  2469. {
  2470. struct snd_soc_component *component =
  2471. snd_soc_kcontrol_component(kcontrol);
  2472. struct wcd9378_priv *wcd9378 =
  2473. snd_soc_component_get_drvdata(component);
  2474. if (wcd9378->comp1_enable) {
  2475. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2476. return -EINVAL;
  2477. }
  2478. snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
  2479. WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
  2480. ucontrol->value.integer.value[0]);
  2481. return 1;
  2482. }
  2483. static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
  2484. struct snd_ctl_elem_value *ucontrol)
  2485. {
  2486. struct snd_soc_component *component =
  2487. snd_soc_kcontrol_component(kcontrol);
  2488. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2489. bool hphr;
  2490. struct soc_multi_mixer_control *mc;
  2491. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2492. hphr = mc->shift;
  2493. ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
  2494. wcd9378->comp1_enable;
  2495. return 0;
  2496. }
  2497. static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
  2498. struct snd_ctl_elem_value *ucontrol)
  2499. {
  2500. struct snd_soc_component *component =
  2501. snd_soc_kcontrol_component(kcontrol);
  2502. struct wcd9378_priv *wcd9378 =
  2503. snd_soc_component_get_drvdata(component);
  2504. int value = ucontrol->value.integer.value[0];
  2505. bool hphr;
  2506. struct soc_multi_mixer_control *mc;
  2507. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2508. hphr = mc->shift;
  2509. if (hphr)
  2510. wcd9378->comp2_enable = value;
  2511. else
  2512. wcd9378->comp1_enable = value;
  2513. dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
  2514. return 0;
  2515. }
  2516. static int wcd9378_get_va_amic_switch(struct snd_kcontrol *kcontrol,
  2517. struct snd_ctl_elem_value *ucontrol)
  2518. {
  2519. struct snd_soc_component *component =
  2520. snd_soc_kcontrol_component(kcontrol);
  2521. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2522. ucontrol->value.integer.value[0] = wcd9378->va_amic_en;
  2523. return 0;
  2524. }
  2525. static int wcd9378_set_va_amic_switch(struct snd_kcontrol *kcontrol,
  2526. struct snd_ctl_elem_value *ucontrol)
  2527. {
  2528. struct snd_soc_component *component =
  2529. snd_soc_kcontrol_component(kcontrol);
  2530. struct wcd9378_priv *wcd9378 =
  2531. snd_soc_component_get_drvdata(component);
  2532. int value = ucontrol->value.integer.value[0];
  2533. wcd9378->va_amic_en = value;
  2534. return 0;
  2535. }
  2536. static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2537. struct snd_kcontrol *kcontrol,
  2538. int event)
  2539. {
  2540. struct snd_soc_component *component =
  2541. snd_soc_dapm_to_component(w->dapm);
  2542. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2543. struct wcd9378_pdata *pdata = NULL;
  2544. int ret = 0;
  2545. pdata = dev_get_platdata(wcd9378->dev);
  2546. if (!pdata) {
  2547. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2548. return -EINVAL;
  2549. }
  2550. if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
  2551. wcd9378->supplies,
  2552. pdata->regulator,
  2553. pdata->num_supplies,
  2554. "cdc-vdd-buck"))
  2555. return 0;
  2556. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2557. w->name, event);
  2558. switch (event) {
  2559. case SND_SOC_DAPM_PRE_PMU:
  2560. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  2561. dev_dbg(component->dev,
  2562. "%s: buck already in enabled state\n",
  2563. __func__);
  2564. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2565. return 0;
  2566. }
  2567. ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
  2568. wcd9378->supplies,
  2569. pdata->regulator,
  2570. pdata->num_supplies,
  2571. "cdc-vdd-buck");
  2572. if (ret == -EINVAL) {
  2573. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2574. __func__);
  2575. return ret;
  2576. }
  2577. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2578. /*
  2579. * 200us sleep is required after LDO is enabled as per
  2580. * HW requirement
  2581. */
  2582. usleep_range(200, 250);
  2583. break;
  2584. case SND_SOC_DAPM_POST_PMD:
  2585. set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2586. break;
  2587. }
  2588. return 0;
  2589. }
  2590. const char * const tx_master_ch_text[] = {
  2591. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2592. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2593. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2594. "SWRM_PCM_IN",
  2595. };
  2596. const struct soc_enum tx_master_ch_enum =
  2597. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2598. tx_master_ch_text);
  2599. static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2600. {
  2601. u8 ch_type = 0;
  2602. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2603. ch_type = ADC1;
  2604. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2605. ch_type = ADC2;
  2606. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2607. ch_type = ADC3;
  2608. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2609. ch_type = ADC4;
  2610. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2611. ch_type = DMIC0;
  2612. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2613. ch_type = DMIC1;
  2614. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2615. ch_type = MBHC;
  2616. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2617. ch_type = DMIC2;
  2618. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2619. ch_type = DMIC3;
  2620. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2621. ch_type = DMIC4;
  2622. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2623. ch_type = DMIC5;
  2624. else
  2625. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2626. if (ch_type)
  2627. *ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
  2628. else
  2629. *ch_idx = -EINVAL;
  2630. }
  2631. static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2632. struct snd_ctl_elem_value *ucontrol)
  2633. {
  2634. struct snd_soc_component *component =
  2635. snd_soc_kcontrol_component(kcontrol);
  2636. struct wcd9378_priv *wcd9378 = NULL;
  2637. int slave_ch_idx = -EINVAL;
  2638. if (component == NULL)
  2639. return -EINVAL;
  2640. wcd9378 = snd_soc_component_get_drvdata(component);
  2641. if (wcd9378 == NULL)
  2642. return -EINVAL;
  2643. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2644. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2645. return -EINVAL;
  2646. ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
  2647. wcd9378->tx_master_ch_map[slave_ch_idx]);
  2648. return 0;
  2649. }
  2650. static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2651. struct snd_ctl_elem_value *ucontrol)
  2652. {
  2653. struct snd_soc_component *component =
  2654. snd_soc_kcontrol_component(kcontrol);
  2655. struct wcd9378_priv *wcd9378 = NULL;
  2656. int slave_ch_idx = -EINVAL, idx = 0;
  2657. if (component == NULL)
  2658. return -EINVAL;
  2659. wcd9378 = snd_soc_component_get_drvdata(component);
  2660. if (wcd9378 == NULL)
  2661. return -EINVAL;
  2662. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2663. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2664. return -EINVAL;
  2665. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2666. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2667. __func__, ucontrol->value.enumerated.item[0]);
  2668. idx = ucontrol->value.enumerated.item[0];
  2669. if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
  2670. return -EINVAL;
  2671. wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
  2672. return 0;
  2673. }
  2674. static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
  2675. struct snd_ctl_elem_value *ucontrol)
  2676. {
  2677. struct snd_soc_component *component =
  2678. snd_soc_kcontrol_component(kcontrol);
  2679. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2680. ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
  2681. return 0;
  2682. }
  2683. static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
  2684. struct snd_ctl_elem_value *ucontrol)
  2685. {
  2686. struct snd_soc_component *component =
  2687. snd_soc_kcontrol_component(kcontrol);
  2688. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2689. wcd9378->bcs_dis = ucontrol->value.integer.value[0];
  2690. return 0;
  2691. }
  2692. static const char * const sys_usage_text[] = {
  2693. "NOSJ_SA_STEREO_3SM", "SJ_SA_AUX_2SM", "NOSJ_SA_STEREO_3SM_1HDR",
  2694. "SJ_SA_AUX_2SM_1HDR", "NOSJ_SA_EAR_3SM", "SJ_SA_EAR_2SM", "NOSJ_SA_EAR_3SM_1HDR",
  2695. "SJ_SA_EAR_2SM_1HDR", "SJ_1HDR_SA_AUX_1SM", "SJ_1HDR_SA_EAR_1SM",
  2696. "SJ_SA_STEREO_2SM", "SJ_NOMIC_SA_EAR_3SM", "SJ_NOMIC_SA_AUX_3SM",
  2697. };
  2698. static const struct soc_enum sys_usage_enum =
  2699. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sys_usage_text),
  2700. sys_usage_text);
  2701. static const char * const loopback_mode_text[] = {
  2702. "NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
  2703. };
  2704. static const struct soc_enum loopback_mode_enum =
  2705. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
  2706. loopback_mode_text);
  2707. static const char * const aux_dsm_text[] = {
  2708. "TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
  2709. };
  2710. static const struct soc_enum aux_dsm_enum =
  2711. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
  2712. aux_dsm_text);
  2713. static const char * const hph_dsm_text[] = {
  2714. "HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
  2715. };
  2716. static const struct soc_enum hph_dsm_enum =
  2717. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
  2718. hph_dsm_text);
  2719. static const char * const tx_mode_mux_text[] = {
  2720. "ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
  2721. };
  2722. static const struct soc_enum tx_mode_mux_enum =
  2723. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2724. tx_mode_mux_text);
  2725. static const char * const micb_sel_text[] = {
  2726. "NO_MICB", "MICB1", "MICB2", "MICB3",
  2727. };
  2728. static const struct soc_enum sm_micb_enum =
  2729. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micb_sel_text),
  2730. micb_sel_text);
  2731. static const char * const rx2_mode_text[] = {
  2732. "HP", "NORMAL",
  2733. };
  2734. static const struct soc_enum rx2_mode_enum =
  2735. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
  2736. rx2_mode_text);
  2737. static const char * const rx_hph_mode_mux_text[] = {
  2738. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2739. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2740. };
  2741. static const struct soc_enum rx_hph_mode_mux_enum =
  2742. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2743. rx_hph_mode_mux_text);
  2744. static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
  2745. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2746. wcd9378_get_compander, wcd9378_set_compander),
  2747. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2748. wcd9378_get_compander, wcd9378_set_compander),
  2749. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2750. wcd9378_bcs_get, wcd9378_bcs_put),
  2751. SOC_SINGLE_EXT("VA_AMIC_MIXER Switch", SND_SOC_NOPM, 0, 1, 0,
  2752. wcd9378_get_va_amic_switch, wcd9378_set_va_amic_switch),
  2753. SOC_ENUM_EXT("SYS_USAGE Mode", sys_usage_enum,
  2754. wcd9378_sys_usage_get, wcd9378_sys_usage_put),
  2755. SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
  2756. wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
  2757. SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
  2758. wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
  2759. SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
  2760. wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
  2761. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2762. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2763. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2764. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2765. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2766. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2767. SOC_ENUM_EXT("SM0 MICB SEL", sm_micb_enum,
  2768. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2769. SOC_ENUM_EXT("SM1 MICB SEL", sm_micb_enum,
  2770. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2771. SOC_ENUM_EXT("SM2 MICB SEL", sm_micb_enum,
  2772. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2773. SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
  2774. NULL, wcd9378_rx2_mode_put),
  2775. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2776. wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
  2777. SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
  2778. wcd9378_hph_get_gain, wcd9378_hph_put_gain),
  2779. WCD9378_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD9378_ANA_EAR_COMPANDER_CTL,
  2780. 2, 0x10, 0, ear_pa_gain),
  2781. WCD9378_AUX_PA_GAIN_TLV("AUX_PA Volume", WCD9378_AUX_INT_MISC,
  2782. 0, 0x8, 0, aux_pa_gain),
  2783. SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
  2784. analog_gain),
  2785. SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
  2786. analog_gain),
  2787. SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
  2788. analog_gain),
  2789. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2790. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2791. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2792. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2793. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2794. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2795. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2796. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2797. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2798. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2799. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2800. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2801. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2802. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2803. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2804. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2805. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2806. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2807. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2808. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2809. };
  2810. static const struct snd_kcontrol_new dmic1_switch[] = {
  2811. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2812. };
  2813. static const struct snd_kcontrol_new dmic2_switch[] = {
  2814. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2815. };
  2816. static const struct snd_kcontrol_new dmic3_switch[] = {
  2817. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2818. };
  2819. static const struct snd_kcontrol_new dmic4_switch[] = {
  2820. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2821. };
  2822. static const struct snd_kcontrol_new dmic5_switch[] = {
  2823. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2824. };
  2825. static const struct snd_kcontrol_new dmic6_switch[] = {
  2826. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2827. };
  2828. static const char * const adc1_mux_text[] = {
  2829. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
  2830. };
  2831. static const char * const adc2_mux_text[] = {
  2832. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
  2833. };
  2834. static const char * const adc3_mux_text[] = {
  2835. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC2", "CH3_AMIC3", "CH3_AMIC4"
  2836. };
  2837. static const char * const ear_mux_text[] = {
  2838. "RX2", "RX0"
  2839. };
  2840. static const char * const aux_mux_text[] = {
  2841. "RX2", "RX1"
  2842. };
  2843. static const struct soc_enum adc1_enum =
  2844. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2845. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
  2846. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  2847. static const struct soc_enum adc2_enum =
  2848. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2849. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
  2850. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2851. static const struct soc_enum adc3_enum =
  2852. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
  2853. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
  2854. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2855. static const struct soc_enum ear_enum =
  2856. SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
  2857. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT,
  2858. ARRAY_SIZE(ear_mux_text), ear_mux_text);
  2859. static const struct soc_enum aux_enum =
  2860. SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
  2861. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT,
  2862. ARRAY_SIZE(aux_mux_text), aux_mux_text);
  2863. static const struct snd_kcontrol_new tx_adc1_mux =
  2864. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  2865. static const struct snd_kcontrol_new tx_adc2_mux =
  2866. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2867. static const struct snd_kcontrol_new tx_adc3_mux =
  2868. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2869. static const struct snd_kcontrol_new ear_mux =
  2870. SOC_DAPM_ENUM("EAR Mux", ear_enum);
  2871. static const struct snd_kcontrol_new aux_mux =
  2872. SOC_DAPM_ENUM("AUX Mux", aux_enum);
  2873. static const struct snd_kcontrol_new dac1_switch[] = {
  2874. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2875. };
  2876. static const struct snd_kcontrol_new dac2_switch[] = {
  2877. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2878. };
  2879. static const struct snd_kcontrol_new ear_mixer_switch[] = {
  2880. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2881. };
  2882. static const struct snd_kcontrol_new aux_mixer_switch[] = {
  2883. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2884. };
  2885. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2886. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2887. };
  2888. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2889. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2890. };
  2891. static const struct snd_kcontrol_new rx0_switch[] = {
  2892. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2893. };
  2894. static const struct snd_kcontrol_new rx1_switch[] = {
  2895. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2896. };
  2897. static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
  2898. /*input widgets*/
  2899. SND_SOC_DAPM_INPUT("AMIC1"),
  2900. SND_SOC_DAPM_INPUT("AMIC2"),
  2901. SND_SOC_DAPM_INPUT("AMIC3"),
  2902. SND_SOC_DAPM_INPUT("AMIC4"),
  2903. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2904. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2905. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2906. /*tx widgets*/
  2907. SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
  2908. NULL, 0, wcd9378_tx_sequencer_enable,
  2909. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2910. SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
  2911. NULL, 0, wcd9378_tx_sequencer_enable,
  2912. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2913. SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
  2914. NULL, 0, wcd9378_tx_sequencer_enable,
  2915. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2916. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  2917. &tx_adc1_mux),
  2918. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2919. &tx_adc2_mux),
  2920. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2921. &tx_adc3_mux),
  2922. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2923. wcd9378_codec_enable_dmic,
  2924. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2925. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2926. wcd9378_codec_enable_dmic,
  2927. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2928. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2929. wcd9378_codec_enable_dmic,
  2930. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2931. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2932. wcd9378_codec_enable_dmic,
  2933. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2934. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2935. wcd9378_codec_enable_dmic,
  2936. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2937. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2938. wcd9378_codec_enable_dmic,
  2939. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2940. /*rx widgets*/
  2941. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2942. wcd9378_codec_hphl_dac_event,
  2943. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2944. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2945. wcd9378_codec_hphr_dac_event,
  2946. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2947. SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
  2948. wcd9378_hph_sequencer_enable,
  2949. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2950. SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2951. wcd9378_codec_enable_hphl_pa,
  2952. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2953. SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2954. wcd9378_codec_enable_hphr_pa,
  2955. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2956. SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
  2957. NULL, 0, wcd9378_sa_sequencer_enable,
  2958. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2959. SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2960. wcd9378_codec_ear_dac_event,
  2961. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2962. SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2963. wcd9378_codec_aux_dac_event,
  2964. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2965. SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2966. wcd9378_codec_enable_ear_pa,
  2967. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2968. SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2969. wcd9378_codec_enable_aux_pa,
  2970. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2971. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2972. wcd9378_codec_enable_vdd_buck,
  2973. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2974. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2975. wcd9378_enable_clsh,
  2976. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2977. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2978. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2979. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2980. SND_SOC_DAPM_POST_PMD),
  2981. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  2982. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2983. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2984. SND_SOC_DAPM_POST_PMD),
  2985. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  2986. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  2987. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2988. SND_SOC_DAPM_POST_PMD),
  2989. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  2990. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  2991. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2992. SND_SOC_DAPM_POST_PMD),
  2993. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  2994. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  2995. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2996. SND_SOC_DAPM_POST_PMD),
  2997. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  2998. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  2999. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3000. SND_SOC_DAPM_POST_PMD),
  3001. /* rx mixer widgets*/
  3002. SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
  3003. SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
  3004. SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
  3005. ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
  3006. SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
  3007. aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
  3008. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
  3009. dac1_switch, ARRAY_SIZE(dac1_switch)),
  3010. SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
  3011. dac2_switch, ARRAY_SIZE(dac2_switch)),
  3012. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3013. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3014. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3015. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3016. /*output widgets tx*/
  3017. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  3018. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  3019. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  3020. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  3021. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  3022. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  3023. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  3024. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  3025. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  3026. /*output widgets rx*/
  3027. SND_SOC_DAPM_OUTPUT("EAR"),
  3028. SND_SOC_DAPM_OUTPUT("AUX"),
  3029. SND_SOC_DAPM_OUTPUT("HPHL"),
  3030. SND_SOC_DAPM_OUTPUT("HPHR"),
  3031. };
  3032. static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
  3033. /*ADC-1 (channel-1)*/
  3034. {"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
  3035. {"TX0 SEQUENCER", NULL, "ADC1 MUX"},
  3036. {"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
  3037. {"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
  3038. {"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
  3039. {"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
  3040. /*ADC-2 (channel-2)*/
  3041. {"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
  3042. {"TX1 SEQUENCER", NULL, "ADC2 MUX"},
  3043. {"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
  3044. {"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
  3045. {"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
  3046. {"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
  3047. /*ADC-3 (channel-3)*/
  3048. {"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
  3049. {"TX2 SEQUENCER", NULL, "ADC3 MUX"},
  3050. {"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
  3051. {"ADC3 MUX", "CH3_AMIC2", "AMIC2"},
  3052. {"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
  3053. {"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
  3054. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  3055. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3056. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  3057. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3058. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  3059. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3060. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  3061. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3062. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  3063. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3064. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  3065. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3066. /*Headphone playback*/
  3067. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3068. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3069. {"HPH SEQUENCER", NULL, "IN1_HPHL"},
  3070. {"RDAC1", NULL, "HPH SEQUENCER"},
  3071. {"HPHL_RDAC", "Switch", "RDAC1"},
  3072. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3073. {"HPHL", NULL, "HPHL PGA"},
  3074. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3075. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3076. {"HPH SEQUENCER", NULL, "IN2_HPHR"},
  3077. {"RDAC2", NULL, "HPH SEQUENCER"},
  3078. {"HPHR_RDAC", "Switch", "RDAC2"},
  3079. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3080. {"HPHR", NULL, "HPHR PGA"},
  3081. /*Amplier playback*/
  3082. {"IN3_AUX", NULL, "VDD_BUCK"},
  3083. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3084. {"EAR_MUX", "RX0", "IN1_HPHL"},
  3085. {"EAR_MUX", "RX2", "IN3_AUX"},
  3086. {"DAC1", "Switch", "EAR_MUX"},
  3087. {"EAR_RDAC", NULL, "DAC1"},
  3088. {"SA SEQUENCER", NULL, "EAR_RDAC"},
  3089. {"EAR_MIXER", "Switch", "SA SEQUENCER"},
  3090. {"EAR PGA", NULL, "EAR_MIXER"},
  3091. {"EAR", NULL, "EAR PGA"},
  3092. {"AUX_MUX", "RX1", "IN2_HPHR"},
  3093. {"AUX_MUX", "RX2", "IN3_AUX"},
  3094. {"DAC2", "Switch", "AUX_MUX"},
  3095. {"AUX_RDAC", NULL, "DAC2"},
  3096. {"SA SEQUENCER", NULL, "AUX_RDAC"},
  3097. {"AUX_MIXER", "Switch", "SA SEQUENCER",},
  3098. {"AUX PGA", NULL, "AUX_MIXER"},
  3099. {"AUX", NULL, "AUX PGA"},
  3100. };
  3101. static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
  3102. void *file_private_data,
  3103. struct file *file,
  3104. char __user *buf, size_t count,
  3105. loff_t pos)
  3106. {
  3107. struct wcd9378_priv *priv;
  3108. char buffer[WCD9378_VERSION_ENTRY_SIZE];
  3109. int len = 0;
  3110. priv = (struct wcd9378_priv *) entry->private_data;
  3111. if (!priv) {
  3112. pr_err("%s: wcd9378 priv is null\n", __func__);
  3113. return -EINVAL;
  3114. }
  3115. switch (priv->version) {
  3116. case WCD9378_VERSION_1_0:
  3117. len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
  3118. break;
  3119. default:
  3120. len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3121. }
  3122. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3123. }
  3124. static struct snd_info_entry_ops wcd9378_info_ops = {
  3125. .read = wcd9378_version_read,
  3126. };
  3127. /*
  3128. * wcd9378_info_create_codec_entry - creates wcd9378 module
  3129. * @codec_root: The parent directory
  3130. * @component: component instance
  3131. *
  3132. * Creates wcd9378 module, version entry under the given
  3133. * parent directory.
  3134. *
  3135. * Return: 0 on success or negative error code on failure.
  3136. */
  3137. int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
  3138. struct snd_soc_component *component)
  3139. {
  3140. struct snd_info_entry *version_entry;
  3141. struct wcd9378_priv *priv;
  3142. struct snd_soc_card *card;
  3143. if (!codec_root || !component)
  3144. return -EINVAL;
  3145. priv = snd_soc_component_get_drvdata(component);
  3146. if (priv->entry) {
  3147. dev_dbg(priv->dev,
  3148. "%s:wcd9378 module already created\n", __func__);
  3149. return 0;
  3150. }
  3151. card = component->card;
  3152. priv->entry = snd_info_create_module_entry(codec_root->module,
  3153. "wcd9378", codec_root);
  3154. if (!priv->entry) {
  3155. dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
  3156. __func__);
  3157. return -ENOMEM;
  3158. }
  3159. priv->entry->mode = S_IFDIR | 0555;
  3160. if (snd_info_register(priv->entry) < 0) {
  3161. snd_info_free_entry(priv->entry);
  3162. return -ENOMEM;
  3163. }
  3164. version_entry = snd_info_create_card_entry(card->snd_card,
  3165. "version",
  3166. priv->entry);
  3167. if (!version_entry) {
  3168. dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
  3169. __func__);
  3170. snd_info_free_entry(priv->entry);
  3171. return -ENOMEM;
  3172. }
  3173. version_entry->private_data = priv;
  3174. version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
  3175. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3176. version_entry->c.ops = &wcd9378_info_ops;
  3177. if (snd_info_register(version_entry) < 0) {
  3178. snd_info_free_entry(version_entry);
  3179. snd_info_free_entry(priv->entry);
  3180. return -ENOMEM;
  3181. }
  3182. priv->version_entry = version_entry;
  3183. return 0;
  3184. }
  3185. EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
  3186. static void wcd9378_class_load(struct snd_soc_component *component)
  3187. {
  3188. /*SMP AMP CLASS LOADING*/
  3189. snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
  3190. WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3191. usleep_range(20000, 20010);
  3192. snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
  3193. WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3194. /*SMP JACK CLASS LOADING*/
  3195. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
  3196. WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3197. usleep_range(30000, 30010);
  3198. snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
  3199. WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
  3200. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
  3201. WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3202. /*SMP MIC0 CLASS LOADING*/
  3203. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
  3204. WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3205. usleep_range(5000, 5010);
  3206. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
  3207. WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3208. /*SMP MIC1 CLASS LOADING*/
  3209. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
  3210. WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3211. usleep_range(5000, 5010);
  3212. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
  3213. WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3214. /*SMP MIC2 CLASS LOADING*/
  3215. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
  3216. WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3217. usleep_range(5000, 5010);
  3218. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
  3219. WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3220. }
  3221. static int wcd9378_sys_usage_set(struct snd_soc_component *component)
  3222. {
  3223. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3224. int ret = 0;
  3225. ret = of_property_read_u32(wcd9378->dev->of_node, "qcom,wcd-sys-usage",
  3226. &wcd9378->sys_usage);
  3227. if (ret) {
  3228. dev_dbg(component->dev, "%s:sys_usage read failed, use default\n",
  3229. __func__);
  3230. wcd9378->sys_usage = NOSJ_SA_STEREO_3SM;
  3231. } else {
  3232. if (wcd9378->sys_usage >= WCD_SYS_USAGE_MAX) {
  3233. dev_err(component->dev, "%s: invalid sys-usage, pls check\n", __func__);
  3234. return -EINVAL;
  3235. }
  3236. }
  3237. snd_soc_component_update_bits(component,
  3238. WCD9378_SYS_USAGE_CTRL,
  3239. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  3240. wcd9378->sys_usage);
  3241. return 0;
  3242. }
  3243. static void wcd9378_micb_value_convert(struct snd_soc_component *component)
  3244. {
  3245. struct wcd9378_priv *wcd9378 =
  3246. snd_soc_component_get_drvdata(component);
  3247. struct wcd9378_pdata *pdata =
  3248. dev_get_platdata(wcd9378->dev);
  3249. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  3250. mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
  3251. mb->micb1_mv, MIC_BIAS_1);
  3252. mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
  3253. mb->micb2_mv, MIC_BIAS_2);
  3254. mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
  3255. mb->micb3_mv, MIC_BIAS_3);
  3256. pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
  3257. mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
  3258. }
  3259. static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
  3260. {
  3261. struct wcd9378_priv *wcd9378 =
  3262. snd_soc_component_get_drvdata(component);
  3263. if (snd_soc_component_read(component,
  3264. WCD9378_EFUSE_REG_29)
  3265. & WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
  3266. if (((snd_soc_component_read(component,
  3267. WCD9378_EFUSE_REG_29) &
  3268. WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
  3269. return true;
  3270. else
  3271. return false;
  3272. } else {
  3273. if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
  3274. & WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
  3275. return true;
  3276. else
  3277. return false;
  3278. }
  3279. return 0;
  3280. }
  3281. static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
  3282. {
  3283. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3284. struct snd_soc_dapm_context *dapm =
  3285. snd_soc_component_get_dapm(component);
  3286. int ret = -EINVAL;
  3287. wcd9378 = snd_soc_component_get_drvdata(component);
  3288. if (!wcd9378)
  3289. return -EINVAL;
  3290. wcd9378->component = component;
  3291. snd_soc_component_init_regmap(component, wcd9378->regmap);
  3292. devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
  3293. ret = wcd9378_wcd_mode_check(component);
  3294. if (!ret) {
  3295. dev_err(component->dev, "wcd mode check failed\n");
  3296. ret = -EINVAL;
  3297. goto exit;
  3298. }
  3299. ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
  3300. if (ret) {
  3301. pr_err("%s: mbhc initialization failed\n", __func__);
  3302. ret = -EINVAL;
  3303. goto exit;
  3304. }
  3305. dev_dbg(component->dev, "%s: mbhc init done\n", __func__);
  3306. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3307. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3308. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3309. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3310. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3311. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3312. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3313. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  3314. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  3315. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  3316. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3317. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3318. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3319. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3320. snd_soc_dapm_sync(dapm);
  3321. wcd_cls_h_init(&wcd9378->clsh_info);
  3322. wcd9378_init_reg(component);
  3323. wcd9378_sys_usage_set(component);
  3324. wcd9378_class_load(component);
  3325. wcd9378_micb_value_convert(component);
  3326. wcd9378->version = WCD9378_VERSION_1_0;
  3327. /* Register event notifier */
  3328. wcd9378->nblock.notifier_call = wcd9378_event_notify;
  3329. if (wcd9378->register_notifier) {
  3330. ret = wcd9378->register_notifier(wcd9378->handle,
  3331. &wcd9378->nblock,
  3332. true);
  3333. if (ret) {
  3334. dev_err(component->dev,
  3335. "%s: Failed to register notifier %d\n",
  3336. __func__, ret);
  3337. return ret;
  3338. }
  3339. }
  3340. exit:
  3341. return ret;
  3342. }
  3343. static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
  3344. {
  3345. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3346. if (!wcd9378) {
  3347. dev_err(component->dev, "%s: wcd9378 is already NULL\n",
  3348. __func__);
  3349. return;
  3350. }
  3351. if (wcd9378->register_notifier)
  3352. wcd9378->register_notifier(wcd9378->handle,
  3353. &wcd9378->nblock,
  3354. false);
  3355. }
  3356. static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
  3357. {
  3358. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3359. if (!wcd9378)
  3360. return 0;
  3361. wcd9378->dapm_bias_off = true;
  3362. return 0;
  3363. }
  3364. static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
  3365. {
  3366. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3367. if (!wcd9378)
  3368. return 0;
  3369. wcd9378->dapm_bias_off = false;
  3370. return 0;
  3371. }
  3372. static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
  3373. .name = WCD9378_DRV_NAME,
  3374. .probe = wcd9378_soc_codec_probe,
  3375. .remove = wcd9378_soc_codec_remove,
  3376. .controls = wcd9378_snd_controls,
  3377. .num_controls = ARRAY_SIZE(wcd9378_snd_controls),
  3378. .dapm_widgets = wcd9378_dapm_widgets,
  3379. .num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
  3380. .dapm_routes = wcd9378_audio_map,
  3381. .num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
  3382. .suspend = wcd9378_soc_codec_suspend,
  3383. .resume = wcd9378_soc_codec_resume,
  3384. };
  3385. static int wcd9378_reset(struct device *dev)
  3386. {
  3387. struct wcd9378_priv *wcd9378 = NULL;
  3388. int rc = 0;
  3389. int value = 0;
  3390. if (!dev)
  3391. return -ENODEV;
  3392. wcd9378 = dev_get_drvdata(dev);
  3393. if (!wcd9378)
  3394. return -EINVAL;
  3395. if (!wcd9378->rst_np) {
  3396. dev_err(dev, "%s: reset gpio device node not specified\n",
  3397. __func__);
  3398. return -EINVAL;
  3399. }
  3400. value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
  3401. if (value > 0)
  3402. return 0;
  3403. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3404. if (rc) {
  3405. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3406. __func__);
  3407. return rc;
  3408. }
  3409. /* 20us sleep required after pulling the reset gpio to LOW */
  3410. usleep_range(20, 30);
  3411. rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
  3412. if (rc) {
  3413. dev_err(dev, "%s: wcd active state request fail!\n",
  3414. __func__);
  3415. return rc;
  3416. }
  3417. /* 20us sleep required after pulling the reset gpio to HIGH */
  3418. usleep_range(20, 30);
  3419. return rc;
  3420. }
  3421. static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
  3422. u32 *val)
  3423. {
  3424. int rc = 0;
  3425. rc = of_property_read_u32(dev->of_node, name, val);
  3426. if (rc)
  3427. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3428. __func__, name, dev->of_node->full_name);
  3429. return rc;
  3430. }
  3431. static void wcd9378_dt_parse_micbias_info(struct device *dev,
  3432. struct wcd9378_micbias_setting *mb)
  3433. {
  3434. u32 prop_val = 0;
  3435. int rc = 0;
  3436. /* MB1 */
  3437. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3438. NULL)) {
  3439. rc = wcd9378_read_of_property_u32(dev,
  3440. "qcom,cdc-micbias1-mv",
  3441. &prop_val);
  3442. if (!rc)
  3443. mb->micb1_mv = prop_val;
  3444. } else {
  3445. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3446. __func__);
  3447. }
  3448. /* MB2 */
  3449. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3450. NULL)) {
  3451. rc = wcd9378_read_of_property_u32(dev,
  3452. "qcom,cdc-micbias2-mv",
  3453. &prop_val);
  3454. if (!rc)
  3455. mb->micb2_mv = prop_val;
  3456. } else {
  3457. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3458. __func__);
  3459. }
  3460. /* MB3 */
  3461. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3462. NULL)) {
  3463. rc = wcd9378_read_of_property_u32(dev,
  3464. "qcom,cdc-micbias3-mv",
  3465. &prop_val);
  3466. if (!rc)
  3467. mb->micb3_mv = prop_val;
  3468. } else {
  3469. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3470. __func__);
  3471. }
  3472. }
  3473. static int wcd9378_reset_low(struct device *dev)
  3474. {
  3475. struct wcd9378_priv *wcd9378 = NULL;
  3476. int rc = 0;
  3477. if (!dev)
  3478. return -ENODEV;
  3479. wcd9378 = dev_get_drvdata(dev);
  3480. if (!wcd9378)
  3481. return -EINVAL;
  3482. if (!wcd9378->rst_np) {
  3483. dev_err(dev, "%s: reset gpio device node not specified\n",
  3484. __func__);
  3485. return -EINVAL;
  3486. }
  3487. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3488. if (rc) {
  3489. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3490. __func__);
  3491. return rc;
  3492. }
  3493. /* 20us sleep required after pulling the reset gpio to LOW */
  3494. usleep_range(20, 30);
  3495. return rc;
  3496. }
  3497. struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
  3498. {
  3499. struct wcd9378_pdata *pdata = NULL;
  3500. pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
  3501. GFP_KERNEL);
  3502. if (!pdata)
  3503. return NULL;
  3504. pdata->rst_np = of_parse_phandle(dev->of_node,
  3505. "qcom,wcd-rst-gpio-node", 0);
  3506. if (!pdata->rst_np) {
  3507. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3508. __func__, "qcom,wcd-rst-gpio-node",
  3509. dev->of_node->full_name);
  3510. return NULL;
  3511. }
  3512. /* Parse power supplies */
  3513. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3514. &pdata->num_supplies);
  3515. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3516. dev_err(dev, "%s: no power supplies defined for codec\n",
  3517. __func__);
  3518. return NULL;
  3519. }
  3520. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3521. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3522. wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
  3523. return pdata;
  3524. }
  3525. static struct snd_soc_dai_driver wcd9378_dai[] = {
  3526. {
  3527. .name = "wcd9378_cdc",
  3528. .playback = {
  3529. .stream_name = "WCD9378_AIF Playback",
  3530. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3531. .formats = WCD9378_FORMATS,
  3532. .rate_max = 384000,
  3533. .rate_min = 8000,
  3534. .channels_min = 1,
  3535. .channels_max = 4,
  3536. },
  3537. .capture = {
  3538. .stream_name = "WCD9378_AIF Capture",
  3539. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3540. .formats = WCD9378_FORMATS,
  3541. .rate_max = 384000,
  3542. .rate_min = 8000,
  3543. .channels_min = 1,
  3544. .channels_max = 4,
  3545. },
  3546. },
  3547. };
  3548. static int wcd9378_bind(struct device *dev)
  3549. {
  3550. int ret = 0;
  3551. struct wcd9378_pdata *pdata = dev_get_platdata(dev);
  3552. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3553. /*
  3554. * Add 5msec delay to provide sufficient time for
  3555. * soundwire auto enumeration of slave devices as
  3556. * per HW requirement.
  3557. */
  3558. usleep_range(5000, 5010);
  3559. ret = component_bind_all(dev, wcd9378);
  3560. if (ret) {
  3561. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3562. __func__, ret);
  3563. return ret;
  3564. }
  3565. wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3566. if (!wcd9378->rx_swr_dev) {
  3567. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3568. __func__);
  3569. ret = -ENODEV;
  3570. goto err;
  3571. }
  3572. wcd9378->rx_swr_dev->paging_support = true;
  3573. wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3574. if (!wcd9378->tx_swr_dev) {
  3575. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3576. __func__);
  3577. ret = -ENODEV;
  3578. goto err;
  3579. }
  3580. wcd9378->tx_swr_dev->paging_support = true;
  3581. swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
  3582. wcd9378->swr_tx_port_params);
  3583. wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
  3584. &wcd9378_regmap_config);
  3585. if (!wcd9378->regmap) {
  3586. dev_err(dev, "%s: Regmap init failed\n",
  3587. __func__);
  3588. goto err;
  3589. }
  3590. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
  3591. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
  3592. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
  3593. wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
  3594. wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
  3595. wcd9378->irq_info.codec_name = "WCD9378";
  3596. wcd9378->irq_info.regmap = wcd9378->regmap;
  3597. wcd9378->irq_info.dev = dev;
  3598. ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
  3599. if (ret) {
  3600. dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
  3601. __func__, ret);
  3602. goto err;
  3603. }
  3604. dev_err(wcd9378->dev, "%s: wcd irq init done\n",
  3605. __func__);
  3606. wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
  3607. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
  3608. wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
  3609. if (ret) {
  3610. dev_err(dev, "%s: Codec registration failed\n",
  3611. __func__);
  3612. goto err_irq;
  3613. }
  3614. wcd9378->dev_up = true;
  3615. return ret;
  3616. err_irq:
  3617. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3618. err:
  3619. component_unbind_all(dev, wcd9378);
  3620. return ret;
  3621. }
  3622. static void wcd9378_unbind(struct device *dev)
  3623. {
  3624. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3625. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3626. snd_soc_unregister_component(dev);
  3627. component_unbind_all(dev, wcd9378);
  3628. }
  3629. static const struct of_device_id wcd9378_dt_match[] = {
  3630. { .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
  3631. {}
  3632. };
  3633. static const struct component_master_ops wcd9378_comp_ops = {
  3634. .bind = wcd9378_bind,
  3635. .unbind = wcd9378_unbind,
  3636. };
  3637. static int wcd9378_compare_of(struct device *dev, void *data)
  3638. {
  3639. return dev->of_node == data;
  3640. }
  3641. static void wcd9378_release_of(struct device *dev, void *data)
  3642. {
  3643. of_node_put(data);
  3644. }
  3645. static int wcd9378_add_slave_components(struct device *dev,
  3646. struct component_match **matchptr)
  3647. {
  3648. struct device_node *np, *rx_node, *tx_node;
  3649. np = dev->of_node;
  3650. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3651. if (!rx_node) {
  3652. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3653. return -ENODEV;
  3654. }
  3655. of_node_get(rx_node);
  3656. component_match_add_release(dev, matchptr,
  3657. wcd9378_release_of,
  3658. wcd9378_compare_of,
  3659. rx_node);
  3660. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3661. if (!tx_node) {
  3662. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3663. return -ENODEV;
  3664. }
  3665. of_node_get(tx_node);
  3666. component_match_add_release(dev, matchptr,
  3667. wcd9378_release_of,
  3668. wcd9378_compare_of,
  3669. tx_node);
  3670. return 0;
  3671. }
  3672. static int wcd9378_probe(struct platform_device *pdev)
  3673. {
  3674. struct component_match *match = NULL;
  3675. struct wcd9378_priv *wcd9378 = NULL;
  3676. struct wcd9378_pdata *pdata = NULL;
  3677. struct wcd_ctrl_platform_data *plat_data = NULL;
  3678. struct device *dev = &pdev->dev;
  3679. int ret;
  3680. wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
  3681. GFP_KERNEL);
  3682. if (!wcd9378)
  3683. return -ENOMEM;
  3684. dev_set_drvdata(dev, wcd9378);
  3685. wcd9378->dev = dev;
  3686. pdata = wcd9378_populate_dt_data(dev);
  3687. if (!pdata) {
  3688. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3689. return -EINVAL;
  3690. }
  3691. dev->platform_data = pdata;
  3692. wcd9378->rst_np = pdata->rst_np;
  3693. ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
  3694. pdata->regulator, pdata->num_supplies);
  3695. if (!wcd9378->supplies) {
  3696. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3697. __func__);
  3698. return ret;
  3699. }
  3700. plat_data = dev_get_platdata(dev->parent);
  3701. if (!plat_data) {
  3702. dev_err(dev, "%s: platform data from parent is NULL\n",
  3703. __func__);
  3704. return -EINVAL;
  3705. }
  3706. wcd9378->handle = (void *)plat_data->handle;
  3707. if (!wcd9378->handle) {
  3708. dev_err(dev, "%s: handle is NULL\n", __func__);
  3709. return -EINVAL;
  3710. }
  3711. wcd9378->update_wcd_event = plat_data->update_wcd_event;
  3712. if (!wcd9378->update_wcd_event) {
  3713. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3714. __func__);
  3715. return -EINVAL;
  3716. }
  3717. wcd9378->register_notifier = plat_data->register_notifier;
  3718. if (!wcd9378->register_notifier) {
  3719. dev_err(dev, "%s: register_notifier api is null!\n",
  3720. __func__);
  3721. return -EINVAL;
  3722. }
  3723. ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
  3724. &wcd9378->wcd_mode);
  3725. if (ret) {
  3726. dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
  3727. __func__);
  3728. wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
  3729. }
  3730. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
  3731. pdata->regulator,
  3732. pdata->num_supplies);
  3733. if (ret) {
  3734. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3735. __func__);
  3736. return ret;
  3737. }
  3738. ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3739. CODEC_RX);
  3740. ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3741. CODEC_TX);
  3742. if (ret) {
  3743. dev_err(dev, "Failed to read port mapping\n");
  3744. goto err;
  3745. }
  3746. ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
  3747. CODEC_TX);
  3748. if (ret) {
  3749. dev_err(dev, "Failed to read port params\n");
  3750. goto err;
  3751. }
  3752. mutex_init(&wcd9378->wakeup_lock);
  3753. mutex_init(&wcd9378->micb_lock);
  3754. ret = wcd9378_add_slave_components(dev, &match);
  3755. if (ret)
  3756. goto err_lock_init;
  3757. wcd9378_reset(dev);
  3758. wcd9378->wakeup = wcd9378_wakeup;
  3759. return component_master_add_with_match(dev,
  3760. &wcd9378_comp_ops, match);
  3761. err_lock_init:
  3762. mutex_destroy(&wcd9378->micb_lock);
  3763. mutex_destroy(&wcd9378->wakeup_lock);
  3764. err:
  3765. return ret;
  3766. }
  3767. static int wcd9378_remove(struct platform_device *pdev)
  3768. {
  3769. struct wcd9378_priv *wcd9378 = NULL;
  3770. wcd9378 = platform_get_drvdata(pdev);
  3771. component_master_del(&pdev->dev, &wcd9378_comp_ops);
  3772. mutex_destroy(&wcd9378->micb_lock);
  3773. mutex_destroy(&wcd9378->wakeup_lock);
  3774. dev_set_drvdata(&pdev->dev, NULL);
  3775. return 0;
  3776. }
  3777. #ifdef CONFIG_PM_SLEEP
  3778. static int wcd9378_suspend(struct device *dev)
  3779. {
  3780. struct wcd9378_priv *wcd9378 = NULL;
  3781. int ret = 0;
  3782. struct wcd9378_pdata *pdata = NULL;
  3783. if (!dev)
  3784. return -ENODEV;
  3785. wcd9378 = dev_get_drvdata(dev);
  3786. if (!wcd9378)
  3787. return -EINVAL;
  3788. pdata = dev_get_platdata(wcd9378->dev);
  3789. if (!pdata) {
  3790. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3791. return -EINVAL;
  3792. }
  3793. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  3794. ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
  3795. wcd9378->supplies,
  3796. pdata->regulator,
  3797. pdata->num_supplies,
  3798. "cdc-vdd-buck");
  3799. if (ret == -EINVAL) {
  3800. dev_err(dev, "%s: vdd buck is not disabled\n",
  3801. __func__);
  3802. return 0;
  3803. }
  3804. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  3805. }
  3806. if (wcd9378->dapm_bias_off) {
  3807. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3808. wcd9378->supplies,
  3809. pdata->regulator,
  3810. pdata->num_supplies,
  3811. true);
  3812. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3813. }
  3814. return 0;
  3815. }
  3816. static int wcd9378_resume(struct device *dev)
  3817. {
  3818. struct wcd9378_priv *wcd9378 = NULL;
  3819. struct wcd9378_pdata *pdata = NULL;
  3820. if (!dev)
  3821. return -ENODEV;
  3822. wcd9378 = dev_get_drvdata(dev);
  3823. if (!wcd9378)
  3824. return -EINVAL;
  3825. pdata = dev_get_platdata(wcd9378->dev);
  3826. if (!pdata) {
  3827. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3828. return -EINVAL;
  3829. }
  3830. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
  3831. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3832. wcd9378->supplies,
  3833. pdata->regulator,
  3834. pdata->num_supplies,
  3835. false);
  3836. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3837. }
  3838. return 0;
  3839. }
  3840. static const struct dev_pm_ops wcd9378_dev_pm_ops = {
  3841. .suspend_late = wcd9378_suspend,
  3842. .resume_early = wcd9378_resume,
  3843. };
  3844. #endif
  3845. static struct platform_driver wcd9378_codec_driver = {
  3846. .probe = wcd9378_probe,
  3847. .remove = wcd9378_remove,
  3848. .driver = {
  3849. .name = "wcd9378_codec",
  3850. .of_match_table = of_match_ptr(wcd9378_dt_match),
  3851. #ifdef CONFIG_PM_SLEEP
  3852. .pm = &wcd9378_dev_pm_ops,
  3853. #endif
  3854. .suppress_bind_attrs = true,
  3855. },
  3856. };
  3857. module_platform_driver(wcd9378_codec_driver);
  3858. MODULE_DESCRIPTION("WCD9378 Codec driver");
  3859. MODULE_LICENSE("GPL");