فهرست منبع

qcacmn: Add HAL layer changes for full monitor mode

Add HAL layer changes for full monitor mode.

Define HAL API and Data structures to read sw_monitor_ring
descriptor.

CRs-Fixed: 2630982
Change-Id: I015fa106d9da74222bef092d50e96fc70a117a4a
Amir 5 سال پیش
والد
کامیت
252b67e048

+ 17 - 24
hal/wifi3.0/hal_api.h

@@ -66,30 +66,6 @@
  */
 #define MAPPED_REF_OFF 0xFE0
 
-/**
- * hal_ring_desc - opaque handle for DP ring descriptor
- */
-struct hal_ring_desc;
-typedef struct hal_ring_desc *hal_ring_desc_t;
-
-/**
- * hal_link_desc - opaque handle for DP link descriptor
- */
-struct hal_link_desc;
-typedef struct hal_link_desc *hal_link_desc_t;
-
-/**
- * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor
- */
-struct hal_rxdma_desc;
-typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
-
-/**
- * hal_buff_addrinfo - opaque handle for DP buffer address info
- */
-struct hal_buff_addrinfo;
-typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
-
 #ifdef ENABLE_VERBOSE_DEBUG
 static inline void
 hal_set_verbose_debug(bool flag)
@@ -2036,4 +2012,21 @@ static inline void hal_srng_inc_flush_cnt(hal_ring_handle_t hal_ring_hdl)
 
 	srng->flush_count++;
 }
+
+/**
+ * hal_rx_sw_mon_desc_info_get () - Get SW monitor desc info
+ *
+ * @hal: Core HAL soc handle
+ * @ring_desc: Mon dest ring descriptor
+ * @desc_info: Desc info to be populated
+ *
+ * Return void
+ */
+static inline void
+hal_rx_sw_mon_desc_info_get(struct hal_soc *hal,
+			    hal_ring_desc_t ring_desc,
+			    hal_rx_mon_desc_info_t desc_info)
+{
+	return hal->ops->hal_rx_sw_mon_desc_info_get(ring_desc, desc_info);
+}
 #endif /* _HAL_APIH_ */

+ 25 - 0
hal/wifi3.0/hal_api_mon.h

@@ -155,6 +155,31 @@
 /* Max pilot count */
 #define HAL_RX_MAX_SU_EVM_COUNT 32
 
+/**
+ * struct hal_rx_mon_desc_info () - HAL Rx Monitor descriptor info
+ *
+ * @ppdu_id:                 PHY ppdu id
+ * @status_buf_count:        number of status buffer count
+ * @rxdma_push_reason:       rxdma push reason
+ * @rxdma_error_code:        rxdma error code
+ * @msdu_cnt:                msdu count
+ * @end_of_ppdu:             end of ppdu
+ * @link_desc:               msdu link descriptor address
+ * @status_buf:              for a PPDU, status buffers can span acrosss
+ *                           multiple buffers, status_buf points to first
+ *                           status buffer address of PPDU
+ */
+struct hal_rx_mon_desc_info {
+	uint16_t ppdu_id;
+	uint8_t status_buf_count;
+	uint8_t rxdma_push_reason;
+	uint8_t rxdma_error_code;
+	uint8_t msdu_count;
+	uint8_t end_of_ppdu;
+	struct hal_buf_info link_desc;
+	struct hal_buf_info status_buf;
+};
+
 /*
  * Struct hal_rx_su_evm_info - SU evm info
  * @number_of_symbols: number of symbols

+ 32 - 0
hal/wifi3.0/hal_internal.h

@@ -68,6 +68,36 @@ extern bool is_hal_verbose_debug_enabled;
 struct hal_soc_handle;
 typedef struct hal_soc_handle *hal_soc_handle_t;
 
+/**
+ * hal_ring_desc - opaque handle for DP ring descriptor
+ */
+struct hal_ring_desc;
+typedef struct hal_ring_desc *hal_ring_desc_t;
+
+/**
+ * hal_link_desc - opaque handle for DP link descriptor
+ */
+struct hal_link_desc;
+typedef struct hal_link_desc *hal_link_desc_t;
+
+/**
+ * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor
+ */
+struct hal_rxdma_desc;
+typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
+
+/**
+ * hal_buff_addrinfo - opaque handle for DP buffer address info
+ */
+struct hal_buff_addrinfo;
+typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
+
+/**
+ * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info
+ */
+struct hal_rx_mon_desc_info;
+typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
+
 /* TBD: This should be movded to shared HW header file */
 enum hal_srng_ring_id {
 	/* UMAC rings */
@@ -558,6 +588,8 @@ struct hal_hw_txrx_ops {
 	uint8_t (*hal_rx_get_fisa_flow_agg_count)(uint8_t *buf);
 	bool (*hal_rx_get_fisa_timeout)(uint8_t *buf);
 	uint8_t (*hal_rx_mpdu_start_tlv_tag_valid)(void *rx_tlv_hdr);
+	void (*hal_rx_sw_mon_desc_info_get)(hal_ring_desc_t rxdma_dst_ring_desc,
+					    hal_rx_mon_desc_info_t mon_desc_info);
 };
 
 /**

+ 2 - 0
hal/wifi3.0/qca6390/hal_6390.c

@@ -1087,6 +1087,8 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
 	NULL,
 	NULL,
 	NULL,
+	NULL,
+	NULL,
 };
 
 struct hal_hw_srng_config hw_srng_table_6390[] = {

+ 2 - 0
hal/wifi3.0/qca6490/hal_6490.c

@@ -1510,6 +1510,8 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
 	hal_rx_get_flow_agg_continuation_6490,
 	hal_rx_get_flow_agg_count_6490,
 	hal_rx_get_fisa_timeout_6490,
+	NULL,
+	NULL,
 };
 
 struct hal_hw_srng_config hw_srng_table_6490[] = {

+ 1 - 0
hal/wifi3.0/qca8074v1/hal_8074v1.c

@@ -1113,6 +1113,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
 	NULL,
 	NULL,
 	hal_rx_mpdu_start_tlv_tag_valid_8074v1,
+	NULL,
 };
 
 struct hal_hw_srng_config hw_srng_table_8074[] = {

+ 1 - 0
hal/wifi3.0/qca8074v2/hal_8074v2.c

@@ -1116,6 +1116,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
 	NULL,
 	NULL,
 	hal_rx_mpdu_start_tlv_tag_valid_8074v2,
+	NULL,
 };
 
 struct hal_hw_srng_config hw_srng_table_8074v2[] = {

+ 59 - 1
hal/wifi3.0/qcn9000/hal_9000.c

@@ -21,6 +21,9 @@
 #include "target_type.h"
 #include "wcss_version.h"
 #include "qdf_module.h"
+#include "hal_9000_rx.h"
+#include "hal_api_mon.h"
+
 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
 	RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
@@ -116,6 +119,60 @@
 #include <hal_generic_api.h>
 #include <hal_wbm.h>
 
+/**
+ * hal_rx_sw_mon_desc_info_get_9000(): API to read the
+ * sw monitor ring descriptor
+ *
+ * @rxdma_dst_ring_desc: sw monitor ring descriptor
+ * @desc_info_buf: Descriptor info buffer to which
+ * sw monitor ring descriptor is populated to
+ *
+ * Return: void
+ */
+static void
+hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc,
+				 hal_rx_mon_desc_info_t desc_info_buf)
+{
+	struct sw_monitor_ring *sw_mon_ring =
+		(struct sw_monitor_ring *)rxdma_dst_ring_desc;
+	struct buffer_addr_info *buf_addr_info;
+	uint32_t *mpdu_info;
+	uint32_t loop_cnt;
+	struct hal_rx_mon_desc_info *desc_info;
+
+	desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf;
+	mpdu_info = (uint32_t *)&sw_mon_ring->
+			reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
+
+	loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT);
+	desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
+
+	/* Get msdu link descriptor buf_addr_info */
+	buf_addr_info = &sw_mon_ring->
+		reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
+	desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info)
+			| ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(
+			buf_addr_info)) << 32);
+	desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
+	buf_addr_info = &sw_mon_ring->status_buff_addr_info;
+	desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info)
+			| ((uint64_t)
+			  (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32);
+	desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
+	desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring,
+					    SW_MONITOR_RING_6,
+					    END_OF_PPDU);
+	desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring,
+						 SW_MONITOR_RING_6,
+						 STATUS_BUF_COUNT);
+	desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring,
+						  SW_MONITOR_RING_6,
+						  RXDMA_PUSH_REASON);
+	desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring,
+					SW_MONITOR_RING_7,
+					PHY_PPDU_ID);
+}
+
 /**
  * hal_rx_msdu_start_nss_get_9000(): API to get the NSS
  * Interval from rx_msdu_start
@@ -1490,6 +1547,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
 	NULL,
 	NULL,
 	hal_rx_mpdu_start_tlv_tag_valid_9000,
+	hal_rx_sw_mon_desc_info_get_9000,
 };
 
 struct hal_hw_srng_config hw_srng_table_9000[] = {
@@ -1852,7 +1910,7 @@ struct hal_hw_srng_config hw_srng_table_9000[] = {
 	{ /* RXDMA_MONITOR_DST */
 		.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
 		.max_rings = 1,
-		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
+		.entry_size = sizeof(struct sw_monitor_ring) >> 2,
 		.lmac_ring = TRUE,
 		.ring_dir = HAL_SRNG_DST_RING,
 		/* reg_start is not set because LMAC rings are not accessed

+ 4 - 0
hal/wifi3.0/qcn9000/hal_9000_rx.h

@@ -16,6 +16,10 @@
  * PERFORMANCE OF THIS SOFTWARE.
  */
 
+#include "sw_monitor_ring.h"
+#include "hal_rx.h"
+#include "hal_api_mon.h"
+
 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va)      \
 	((uint8_t *)(link_desc_va) +			\
 	RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)