asoc: codec: add support for wcd939x for pineapple target

Update wcd939x api and marcro in pineapple driver
Update wcd939x macro in wcd939x driver.

Change-Id: Id87fc550e0a3aff61efee61644fd6bc15ea7c66d
Signed-off-by: Prasad Kumpatla <[email protected]>

Android.mk

@@ -338,6 +338,24 @@ LOCAL_MODULE_TAGS         := optional
 LOCAL_MODULE_DEBUG_ENABLE := true
 LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
 include $(DLKM_DIR)/Build_external_kernelmodule.mk
+########################### WCD939x CODEC  ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd939x_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd939x/wcd939x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd939x_slave_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd939x/wcd939x_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
 endif
 ###########################################################
 

Kbuild

@@ -1 +1 @@
-obj-y := dsp/ ipc/ soc/ asoc/ asoc/codecs/ asoc/codecs/lpass-cdc/ asoc/codecs/bolero/ asoc/codecs/wsa884x/ asoc/codecs/wcd938x/ asoc/codecs/wsa883x/ asoc/codecs/wcd937x/
+obj-y := dsp/ ipc/ soc/ asoc/ asoc/codecs/ asoc/codecs/lpass-cdc/ asoc/codecs/bolero/ asoc/codecs/wcd939x/ asoc/codecs/wsa884x/ asoc/codecs/wcd938x/ asoc/codecs/wsa883x/ asoc/codecs/wcd937x/

asoc/codecs/Kbuild

@@ -255,6 +255,7 @@ ifeq ($(KERNEL_BUILD), 1)
 	obj-y	+= wcd934x/
 	obj-y	+= wcd937x/
 	obj-y	+= wcd938x/
+	obj-y	+= wcd939x/
 	obj-y	+= bolero/
 	obj-y	+= lpass-cdc/
 	obj-y	+= wsa884x/

asoc/codecs/wcd939x/Kbuild

@@ -0,0 +1,121 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_KONA), y)
+		include $(AUDIO_ROOT)/config/konaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/konaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_LITO), y)
+		include $(AUDIO_ROOT)/config/litoauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/litoautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_WAIPIO), y)
+		include $(AUDIO_ROOT)/config/waipioauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/waipioautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KALAMA), y)
+		include $(AUDIO_ROOT)/config/kalamaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/kalamaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
+		include $(AUDIO_ROOT)/config/pineappleauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pineappleautoconf.h
+	endif
+
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ WCD939X ############
+
+# for WCD939X Codec
+ifdef CONFIG_SND_SOC_WCD939X
+	WCD939X_OBJS += wcd939x.o
+	WCD939X_OBJS += wcd939x-regmap.o
+	WCD939X_OBJS += wcd939x-tables.o
+	WCD939X_OBJS += wcd939x-mbhc.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD939X_SLAVE
+	WCD939X_SLAVE_OBJS += wcd939x-slave.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+EXTRA_CFLAGS += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+EXTRA_CFLAGS += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+EXTRA_CFLAGS += -Wheader-guard
+endif
+
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_WCD939X) += wcd939x_dlkm.o
+wcd939x_dlkm-y := $(WCD939X_OBJS)
+
+obj-$(CONFIG_SND_SOC_WCD939X_SLAVE) += wcd939x_slave_dlkm.o
+wcd939x_slave_dlkm-y := $(WCD939X_SLAVE_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

asoc/codecs/wcd939x/Makefile

@@ -0,0 +1,6 @@
+modules:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
+modules_install:
+	$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

asoc/codecs/wcd939x/internal.h

@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _WCD939X_INTERNAL_H
+#define _WCD939X_INTERNAL_H
+
+#include <asoc/wcd-mbhc-v2.h>
+#include <asoc/wcd-irq.h>
+#include <asoc/wcd-clsh.h>
+#include <soc/soundwire.h>
+#include "wcd939x-mbhc.h"
+#include "wcd939x.h"
+
+#define SWR_SCP_CONTROL    0x44
+#define SWR_SCP_HOST_CLK_DIV2_CTL_BANK 0xE0
+#define WCD939X_MAX_MICBIAS 4
+
+/* Convert from vout ctl to micbias voltage in mV */
+#define  WCD_VOUT_CTL_TO_MICB(v)  (1000 + v * 50)
+#define MAX_PORT 8
+#define MAX_CH_PER_PORT 8
+#define TX_ADC_MAX 4
+#define SWR_NUM_PORTS	4
+
+enum {
+	TX_HDR12 = 0,
+	TX_HDR34,
+	TX_HDR_MAX,
+};
+
+extern struct regmap_config wcd939x_regmap_config;
+
+struct codec_port_info {
+	u32 slave_port_type;
+	u32 master_port_type;
+	u32 ch_mask;
+	u32 num_ch;
+	u32 ch_rate;
+};
+
+struct wcd939x_priv {
+	struct device *dev;
+
+	int variant;
+	struct snd_soc_component *component;
+	struct device_node *rst_np;
+	struct regmap *regmap;
+
+	struct swr_device *rx_swr_dev;
+	struct swr_device *tx_swr_dev;
+
+	s32 micb_ref[WCD939X_MAX_MICBIAS];
+	s32 pullup_ref[WCD939X_MAX_MICBIAS];
+
+	struct fw_info *fw_data;
+	struct device_node *wcd_rst_np;
+
+	struct mutex micb_lock;
+	struct mutex wakeup_lock;
+	s32 dmic_0_1_clk_cnt;
+	s32 dmic_2_3_clk_cnt;
+	s32 dmic_4_5_clk_cnt;
+	s32 dmic_6_7_clk_cnt;
+	int hdr_en[TX_HDR_MAX];
+	/* class h specific info */
+	struct wcd_clsh_cdc_info clsh_info;
+	/* mbhc module */
+	struct wcd939x_mbhc *mbhc;
+
+	u32 hph_mode;
+	u32 tx_mode[TX_ADC_MAX];
+	s32 adc_count;
+	bool comp1_enable;
+	bool comp2_enable;
+	bool ldoh;
+	bool bcs_dis;
+	bool dapm_bias_off;
+	struct irq_domain *virq;
+	struct wcd_irq_info irq_info;
+	u32 rx_clk_cnt;
+	int num_irq_regs;
+	/* to track the status */
+	unsigned long status_mask;
+
+	u8 num_tx_ports;
+	u8 num_rx_ports;
+	struct codec_port_info
+			tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
+	struct codec_port_info
+			rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
+	struct swr_port_params tx_port_params[SWR_UC_MAX][SWR_NUM_PORTS];
+	struct swr_dev_frame_config swr_tx_port_params[SWR_UC_MAX];
+	struct regulator_bulk_data *supplies;
+	struct notifier_block nblock;
+	/* wcd callback to bolero */
+	void *handle;
+	int (*update_wcd_event)(void *handle, u16 event, u32 data);
+	int (*register_notifier)(void *handle,
+				struct notifier_block *nblock,
+				bool enable);
+	int (*wakeup)(void *handle, bool enable);
+	u32 version;
+	/* Entry for version info */
+	struct snd_info_entry *entry;
+	struct snd_info_entry *version_entry;
+	struct snd_info_entry *variant_entry;
+	int flyback_cur_det_disable;
+	int ear_rx_path;
+	bool dev_up;
+	u8 tx_master_ch_map[WCD939X_MAX_SLAVE_CH_TYPES];
+	bool usbc_hs_status;
+	/* wcd to swr dmic notification */
+	bool notify_swr_dmic;
+	struct blocking_notifier_head notifier;
+};
+
+struct wcd939x_micbias_setting {
+	u8 ldoh_v;
+	u32 cfilt1_mv;
+	u32 micb1_mv;
+	u32 micb2_mv;
+	u32 micb3_mv;
+	u32 micb4_mv;
+	u8 bias1_cfilt_sel;
+};
+
+struct wcd939x_pdata {
+	struct device_node *rst_np;
+	struct device_node *rx_slave;
+	struct device_node *tx_slave;
+	struct wcd939x_micbias_setting micbias;
+
+	struct cdc_regulator *regulator;
+	int num_supplies;
+};
+
+struct wcd_ctrl_platform_data {
+	void *handle;
+	int (*update_wcd_event)(void *handle, u16 event, u32 data);
+	int (*register_notifier)(void *handle,
+				 struct notifier_block *nblock,
+				 bool enable);
+};
+
+enum {
+	WCD_RX1,
+	WCD_RX2,
+	WCD_RX3
+};
+
+enum {
+	/* INTR_CTRL_INT_MASK_0 */
+	WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
+	WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET,
+	WCD939X_IRQ_MBHC_ELECT_INS_REM_DET,
+	WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
+	WCD939X_IRQ_MBHC_SW_DET,
+	WCD939X_IRQ_HPHR_OCP_INT,
+	WCD939X_IRQ_HPHR_CNP_INT,
+	WCD939X_IRQ_HPHL_OCP_INT,
+
+	/* INTR_CTRL_INT_MASK_1 */
+	WCD939X_IRQ_HPHL_CNP_INT,
+	WCD939X_IRQ_EAR_CNP_INT,
+	WCD939X_IRQ_EAR_SCD_INT,
+	WCD939X_IRQ_HPHL_PDM_WD_INT,
+	WCD939X_IRQ_HPHR_PDM_WD_INT,
+	WCD939X_IRQ_EAR_PDM_WD_INT,
+
+	/* INTR_CTRL_INT_MASK_2 */
+	WCD939X_IRQ_LDORT_SCD_INT,
+	WCD939X_IRQ_MBHC_MOISTURE_INT,
+	WCD939X_IRQ_HPHL_SURGE_DET_INT,
+	WCD939X_IRQ_HPHR_SURGE_DET_INT,
+	WCD939X_NUM_IRQS,
+};
+
+extern struct wcd939x_mbhc *wcd939x_soc_get_mbhc(
+				struct snd_soc_component *component);
+extern void wcd939x_disable_bcs_before_slow_insert(
+				struct snd_soc_component *component,
+				bool bcs_disable);
+extern int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
+					int volt, int micb_num);
+extern int wcd939x_get_micb_vout_ctl_val(u32 micb_mv);
+extern int wcd939x_micbias_control(struct snd_soc_component *component,
+			int micb_num, int req, bool is_dapm);
+#endif /* _WCD939X_INTERNAL_H */

asoc/codecs/wcd939x/wcd939x-mbhc.c

@@ -0,0 +1,1146 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/printk.h>
+#include <linux/ratelimit.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/regmap.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <asoc/wcdcal-hwdep.h>
+#include <asoc/wcd-mbhc-v2-api.h>
+#include "wcd939x-registers.h"
+#include "internal.h"
+
+#define WCD939X_ZDET_SUPPORTED          false
+/* Z value defined in milliohm */
+#define WCD939X_ZDET_VAL_32             32000
+#define WCD939X_ZDET_VAL_400            400000
+#define WCD939X_ZDET_VAL_1200           1200000
+#define WCD939X_ZDET_VAL_100K           100000000
+/* Z floating defined in ohms */
+#define WCD939X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
+
+#define WCD939X_ZDET_NUM_MEASUREMENTS   900
+#define WCD939X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
+#define WCD939X_MBHC_GET_X1(x)          (x & 0x3FFF)
+/* Z value compared in milliOhm */
+#define WCD939X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
+#define WCD939X_MBHC_ZDET_CONST         (86 * 16384)
+#define WCD939X_MBHC_MOISTURE_RREF      R_24_KOHM
+
+static struct wcd_mbhc_register
+	wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = {
+	WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN",
+			  WCD939X_MBHC_MECH, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_GND_DET_EN",
+			  WCD939X_MBHC_MECH, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MECH_DETECTION_TYPE",
+			  WCD939X_MBHC_MECH, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MIC_CLAMP_CTL",
+			  WCD939X_PLUG_DETECT_CTL, 0x30, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_DETECTION_TYPE",
+			  WCD939X_MBHC_ELECT, 0x08, 3, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_CTRL",
+			  WCD939X_MECH_DET_CURRENT, 0x1F, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL",
+			  WCD939X_MBHC_MECH, 0x04, 2, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PLUG_TYPE",
+			  WCD939X_MBHC_MECH, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_GND_PLUG_TYPE",
+			  WCD939X_MBHC_MECH, 0x08, 3, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_SW_HPH_LP_100K_TO_GND",
+			  WCD939X_MBHC_MECH, 0x01, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_SCHMT_ISRC",
+			  WCD939X_MBHC_ELECT, 0x06, 1, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_FSM_EN",
+			  WCD939X_MBHC_ELECT, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_INSREM_DBNC",
+			  WCD939X_PLUG_DETECT_CTL, 0x0F, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_BTN_DBNC",
+			  WCD939X_CTL_1, 0x03, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HS_VREF",
+			  WCD939X_CTL_2, 0x03, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HS_COMP_RESULT",
+			  WCD939X_MBHC_RESULT_3, 0x08, 3, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_IN2P_CLAMP_STATE",
+			  WCD939X_MBHC_RESULT_3, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MIC_SCHMT_RESULT",
+			  WCD939X_MBHC_RESULT_3, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_SCHMT_RESULT",
+			  WCD939X_MBHC_RESULT_3, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_SCHMT_RESULT",
+			  WCD939X_MBHC_RESULT_3, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_OCP_FSM_EN",
+			  WCD939X_HPH_OCP_CTL, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_BTN_RESULT",
+			  WCD939X_MBHC_RESULT_3, 0x07, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_BTN_ISRC_CTL",
+			  WCD939X_MBHC_ELECT, 0x70, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
+			  WCD939X_MBHC_RESULT_3, 0xFF, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
+			  WCD939X_MICB2, 0xC0, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
+			  WCD939X_CNP_WG_TIME, 0xFF, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",
+			  WCD939X_HPH, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PA_EN",
+			  WCD939X_HPH, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPH_PA_EN",
+			  WCD939X_HPH, 0xC0, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_SWCH_LEVEL_REMOVE",
+			  WCD939X_MBHC_RESULT_3, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_PULLDOWN_CTRL",
+			  0, 0, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ANC_DET_EN",
+			  WCD939X_CTL_BCS, 0x02, 1, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_FSM_STATUS",
+			  WCD939X_FSM_STATUS, 0x01, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MUX_CTL",
+			  WCD939X_CTL_2, 0x70, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MOISTURE_STATUS",
+			  WCD939X_FSM_STATUS, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_GND",
+			  WCD939X_PA_CTL2, 0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_GND",
+			  WCD939X_PA_CTL2, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_OCP_DET_EN",
+			  WCD939X_L_TEST, 0x01, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_OCP_DET_EN",
+			  WCD939X_R_TEST, 0x01, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHL_OCP_STATUS",
+			  WCD939X_INTR_STATUS_0, 0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_HPHR_OCP_STATUS",
+			  WCD939X_INTR_STATUS_0, 0x20, 5, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_EN",
+			  WCD939X_CTL_1, 0x08, 3, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_COMPLETE", WCD939X_FSM_STATUS,
+			  0x40, 6, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_TIMEOUT", WCD939X_FSM_STATUS,
+			  0x80, 7, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_RESULT", WCD939X_ADC_RESULT,
+			  0xFF, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_MICB2_VOUT", WCD939X_MICB2, 0x3F, 0, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ADC_MODE",
+			  WCD939X_CTL_1, 0x10, 4, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_DETECTION_DONE",
+			  WCD939X_CTL_1, 0x04, 2, 0),
+	WCD_MBHC_REGISTER("WCD_MBHC_ELECT_ISRC_EN",
+			  WCD939X_MBHC_ZDET, 0x02, 1, 0),
+};
+
+static const struct wcd_mbhc_intr intr_ids = {
+	.mbhc_sw_intr =  WCD939X_IRQ_MBHC_SW_DET,
+	.mbhc_btn_press_intr = WCD939X_IRQ_MBHC_BUTTON_PRESS_DET,
+	.mbhc_btn_release_intr = WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET,
+	.mbhc_hs_ins_intr = WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
+	.mbhc_hs_rem_intr = WCD939X_IRQ_MBHC_ELECT_INS_REM_DET,
+	.hph_left_ocp = WCD939X_IRQ_HPHL_OCP_INT,
+	.hph_right_ocp = WCD939X_IRQ_HPHR_OCP_INT,
+};
+
+struct wcd939x_mbhc_zdet_param {
+	u16 ldo_ctl;
+	u16 noff;
+	u16 nshift;
+	u16 btn5;
+	u16 btn6;
+	u16 btn7;
+};
+
+static int wcd939x_mbhc_request_irq(struct snd_soc_component *component,
+				  int irq, irq_handler_t handler,
+				  const char *name, void *data)
+{
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
+
+	return wcd_request_irq(&wcd939x->irq_info, irq, name, handler, data);
+}
+
+static void wcd939x_mbhc_irq_control(struct snd_soc_component *component,
+				   int irq, bool enable)
+{
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
+
+	if (enable)
+		wcd_enable_irq(&wcd939x->irq_info, irq);
+	else
+		wcd_disable_irq(&wcd939x->irq_info, irq);
+}
+
+static int wcd939x_mbhc_free_irq(struct snd_soc_component *component,
+			       int irq, void *data)
+{
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
+
+	wcd_free_irq(&wcd939x->irq_info, irq, data);
+
+	return 0;
+}
+
+static void wcd939x_mbhc_clk_setup(struct snd_soc_component *component,
+				 bool enable)
+{
+	if (enable)
+		snd_soc_component_update_bits(component, WCD939X_CTL_1,
+				    0x80, 0x80);
+	else
+		snd_soc_component_update_bits(component, WCD939X_CTL_1,
+				    0x80, 0x00);
+}
+
+static int wcd939x_mbhc_btn_to_num(struct snd_soc_component *component)
+{
+	return snd_soc_component_read(component, WCD939X_MBHC_RESULT_3) & 0x7;
+}
+
+static void wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
+					 bool enable)
+{
+	if (enable)
+		snd_soc_component_update_bits(component, WCD939X_MBHC_ELECT,
+				    0x01, 0x01);
+	else
+		snd_soc_component_update_bits(component, WCD939X_MBHC_ELECT,
+				    0x01, 0x00);
+}
+
+static void wcd939x_mbhc_program_btn_thr(struct snd_soc_component *component,
+				       s16 *btn_low, s16 *btn_high,
+				       int num_btn, bool is_micbias)
+{
+	int i;
+	int vth;
+
+	if (num_btn > WCD_MBHC_DEF_BUTTONS) {
+		dev_err_ratelimited(component->dev, "%s: invalid number of buttons: %d\n",
+			__func__, num_btn);
+		return;
+	}
+
+	for (i = 0; i < num_btn; i++) {
+		vth = ((btn_high[i] * 2) / 25) & 0x3F;
+		snd_soc_component_update_bits(component, WCD939X_MBHC_BTN0 + i,
+				    0xFC, vth << 2);
+		dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
+			__func__, i, btn_high[i], vth);
+	}
+}
+
+static bool wcd939x_mbhc_lock_sleep(struct wcd_mbhc *mbhc, bool lock)
+{
+	struct snd_soc_component *component = mbhc->component;
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
+
+	wcd939x->wakeup((void*)wcd939x, lock);
+
+	return true;
+}
+
+static int wcd939x_mbhc_register_notifier(struct wcd_mbhc *mbhc,
+					struct notifier_block *nblock,
+					bool enable)
+{
+	struct wcd939x_mbhc *wcd939x_mbhc;
+
+	wcd939x_mbhc = container_of(mbhc, struct wcd939x_mbhc, wcd_mbhc);
+
+	if (enable)
+		return blocking_notifier_chain_register(&wcd939x_mbhc->notifier,
+							nblock);
+	else
+		return blocking_notifier_chain_unregister(
+				&wcd939x_mbhc->notifier, nblock);
+}
+
+static bool wcd939x_mbhc_micb_en_status(struct wcd_mbhc *mbhc, int micb_num)
+{
+	u8 val = 0;
+
+	if (micb_num == MIC_BIAS_2) {
+		val = ((snd_soc_component_read(mbhc->component,
+								WCD939X_MICB2) & 0xC0)
+			>> 6);
+		if (val == 0x01)
+			return true;
+	}
+	return false;
+}
+
+static bool wcd939x_mbhc_hph_pa_on_status(struct snd_soc_component *component)
+{
+	return (snd_soc_component_read(component, WCD939X_HPH) & 0xC0) ?
+									true : false;
+}
+
+static void wcd939x_mbhc_hph_l_pull_up_control(
+							struct snd_soc_component *component,
+							int pull_up_cur)
+{
+	/* Default pull up current to 2uA */
+	if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA ||
+	    pull_up_cur == HS_PULLUP_I_DEFAULT)
+		pull_up_cur = HS_PULLUP_I_2P0_UA;
+
+	dev_dbg(component->dev, "%s: HS pull up current:%d\n",
+		__func__, pull_up_cur);
+
+	snd_soc_component_update_bits(component,
+				WCD939X_MECH_DET_CURRENT,
+			    0x1F, pull_up_cur);
+}
+
+static int wcd939x_mbhc_request_micbias(struct snd_soc_component *component,
+					int micb_num, int req)
+{
+	int ret = 0;
+
+	ret = wcd939x_micbias_control(component, micb_num, req, false);
+
+	return ret;
+}
+
+static void wcd939x_mbhc_micb_ramp_control(struct snd_soc_component *component,
+					   bool enable)
+{
+	if (enable) {
+		snd_soc_component_update_bits(component, WCD939X_MICB2_RAMP,
+				    0x1C, 0x0C);
+		snd_soc_component_update_bits(component, WCD939X_MICB2_RAMP,
+				    0x80, 0x80);
+	} else {
+		snd_soc_component_update_bits(component, WCD939X_MICB2_RAMP,
+				    0x80, 0x00);
+		snd_soc_component_update_bits(component, WCD939X_MICB2_RAMP,
+				    0x1C, 0x00);
+	}
+}
+
+static struct firmware_cal *wcd939x_get_hwdep_fw_cal(struct wcd_mbhc *mbhc,
+						   enum wcd_cal_type type)
+{
+	struct wcd939x_mbhc *wcd939x_mbhc;
+	struct firmware_cal *hwdep_cal;
+	struct snd_soc_component *component = mbhc->component;
+
+	wcd939x_mbhc = container_of(mbhc, struct wcd939x_mbhc, wcd_mbhc);
+
+	if (!component) {
+		pr_err_ratelimited("%s: NULL component pointer\n", __func__);
+		return NULL;
+	}
+	hwdep_cal = wcdcal_get_fw_cal(wcd939x_mbhc->fw_data, type);
+	if (!hwdep_cal)
+		dev_err_ratelimited(component->dev, "%s: cal not sent by %d\n",
+			__func__, type);
+
+	return hwdep_cal;
+}
+
+static int wcd939x_mbhc_micb_ctrl_threshold_mic(
+							struct snd_soc_component *component,
+							int micb_num, bool req_en)
+{
+	struct wcd939x_pdata *pdata = dev_get_platdata(component->dev);
+	int rc, micb_mv;
+
+	if (micb_num != MIC_BIAS_2)
+		return -EINVAL;
+	/*
+	 * If device tree micbias level is already above the minimum
+	 * voltage needed to detect threshold microphone, then do
+	 * not change the micbias, just return.
+	 */
+	if (pdata->micbias.micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
+		return 0;
+
+	micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : pdata->micbias.micb2_mv;
+
+	rc = wcd939x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
+
+	return rc;
+}
+
+static inline void wcd939x_mbhc_get_result_params(struct wcd939x_priv *wcd939x,
+						s16 *d1_a, u16 noff,
+						int32_t *zdet)
+{
+	int i;
+	int val, val1;
+	s16 c1;
+	s32 x1, d1;
+	int32_t denom;
+	int minCode_param[] = {
+			3277, 1639, 820, 410, 205, 103, 52, 26
+	};
+
+	regmap_update_bits(wcd939x->regmap, WCD939X_MBHC_ZDET, 0x20, 0x20);
+	for (i = 0; i < WCD939X_ZDET_NUM_MEASUREMENTS; i++) {
+		regmap_read(wcd939x->regmap, WCD939X_MBHC_RESULT_2, &val);
+		if (val & 0x80)
+			break;
+	}
+	val = val << 0x8;
+	regmap_read(wcd939x->regmap, WCD939X_MBHC_RESULT_1, &val1);
+	val |= val1;
+	regmap_update_bits(wcd939x->regmap, WCD939X_MBHC_ZDET, 0x20, 0x00);
+	x1 = WCD939X_MBHC_GET_X1(val);
+	c1 = WCD939X_MBHC_GET_C1(val);
+	/* If ramp is not complete, give additional 5ms */
+	if ((c1 < 2) && x1)
+		usleep_range(5000, 5050);
+
+	if (!c1 || !x1) {
+		dev_dbg(wcd939x->dev,
+			"%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
+			__func__, c1, x1);
+		goto ramp_down;
+	}
+	d1 = d1_a[c1];
+	denom = (x1 * d1) - (1 << (14 - noff));
+	if (denom > 0)
+		*zdet = (WCD939X_MBHC_ZDET_CONST * 1000) / denom;
+	else if (x1 < minCode_param[noff])
+		*zdet = WCD939X_ZDET_FLOATING_IMPEDANCE;
+
+	dev_dbg(wcd939x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
+		__func__, d1, c1, x1, *zdet);
+ramp_down:
+	i = 0;
+	while (x1) {
+		regmap_read(wcd939x->regmap,
+				 WCD939X_MBHC_RESULT_1, &val);
+		regmap_read(wcd939x->regmap,
+				 WCD939X_MBHC_RESULT_2, &val1);
+		val = val << 0x08;
+		val |= val1;
+		x1 = WCD939X_MBHC_GET_X1(val);
+		i++;
+		if (i == WCD939X_ZDET_NUM_MEASUREMENTS)
+			break;
+	}
+}
+
+static void wcd939x_mbhc_zdet_ramp(struct snd_soc_component *component,
+				 struct wcd939x_mbhc_zdet_param *zdet_param,
+				 int32_t *zl, int32_t *zr, s16 *d1_a)
+{
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
+	int32_t zdet = 0;
+
+	snd_soc_component_update_bits(component, WCD939X_ZDET_ANA_CTL,
+				0x70, zdet_param->ldo_ctl << 4);
+	snd_soc_component_update_bits(component, WCD939X_MBHC_BTN5, 0xFC,
+			    zdet_param->btn5);
+	snd_soc_component_update_bits(component, WCD939X_MBHC_BTN6, 0xFC,
+			    zdet_param->btn6);
+	snd_soc_component_update_bits(component, WCD939X_MBHC_BTN7, 0xFC,
+			    zdet_param->btn7);
+	snd_soc_component_update_bits(component, WCD939X_ZDET_ANA_CTL,
+				0x0F, zdet_param->noff);
+	snd_soc_component_update_bits(component, WCD939X_ZDET_RAMP_CTL,
+				0x0F, zdet_param->nshift);
+
+	if (!zl)
+		goto z_right;
+	/* Start impedance measurement for HPH_L */
+	regmap_update_bits(wcd939x->regmap,
+			   WCD939X_MBHC_ZDET, 0x80, 0x80);
+	dev_dbg(wcd939x->dev, "%s: ramp for HPH_L, noff = %d\n",
+		__func__, zdet_param->noff);
+	wcd939x_mbhc_get_result_params(wcd939x, d1_a, zdet_param->noff, &zdet);
+	regmap_update_bits(wcd939x->regmap,
+			   WCD939X_MBHC_ZDET, 0x80, 0x00);
+
+	*zl = zdet;
+
+z_right:
+	if (!zr)
+		return;
+	/* Start impedance measurement for HPH_R */
+	regmap_update_bits(wcd939x->regmap,
+			   WCD939X_MBHC_ZDET, 0x40, 0x40);
+	dev_dbg(wcd939x->dev, "%s: ramp for HPH_R, noff = %d\n",
+		__func__, zdet_param->noff);
+	wcd939x_mbhc_get_result_params(wcd939x, d1_a, zdet_param->noff, &zdet);
+	regmap_update_bits(wcd939x->regmap,
+			   WCD939X_MBHC_ZDET, 0x40, 0x00);
+
+	*zr = zdet;
+}
+
+static inline void wcd939x_wcd_mbhc_qfuse_cal(
+					struct snd_soc_component *component,
+					int32_t *z_val, int flag_l_r)
+{
+	s16 q1;
+	int q1_cal;
+
+	if (*z_val < (WCD939X_ZDET_VAL_400/1000))
+		q1 = snd_soc_component_read(component,
+			WCD939X_EFUSE_REG_23 + (2 * flag_l_r));
+	else
+		q1 = snd_soc_component_read(component,
+			WCD939X_EFUSE_REG_24 + (2 * flag_l_r));
+	if (q1 & 0x80)
+		q1_cal = (10000 - ((q1 & 0x7F) * 25));
+	else
+		q1_cal = (10000 + (q1 * 25));
+	if (q1_cal > 0)
+		*z_val = ((*z_val) * 10000) / q1_cal;
+}
+
+static void wcd939x_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl,
+					  uint32_t *zr)
+{
+	struct snd_soc_component *component = mbhc->component;
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
+	s16 reg0, reg1, reg2, reg3, reg4;
+	int32_t z1L, z1R, z1Ls;
+	int zMono, z_diff1, z_diff2;
+	bool is_fsm_disable = false;
+	struct wcd939x_mbhc_zdet_param zdet_param[] = {
+		{4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
+		{2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
+		{1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
+		{1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
+	};
+	struct wcd939x_mbhc_zdet_param *zdet_param_ptr = NULL;
+	s16 d1_a[][4] = {
+		{0, 30, 90, 30},
+		{0, 30, 30, 5},
+		{0, 30, 30, 5},
+		{0, 30, 30, 5},
+	};
+	s16 *d1 = NULL;
+
+	WCD_MBHC_RSC_ASSERT_LOCKED(mbhc);
+
+	reg0 = snd_soc_component_read(component, WCD939X_MBHC_BTN5);
+	reg1 = snd_soc_component_read(component, WCD939X_MBHC_BTN6);
+	reg2 = snd_soc_component_read(component, WCD939X_MBHC_BTN7);
+	reg3 = snd_soc_component_read(component, WCD939X_CTL_CLK);
+	reg4 = snd_soc_component_read(component, WCD939X_ZDET_ANA_CTL);
+
+	if (snd_soc_component_read(component, WCD939X_MBHC_ELECT) & 0x80) {
+		is_fsm_disable = true;
+		regmap_update_bits(wcd939x->regmap,
+				   WCD939X_MBHC_ELECT, 0x80, 0x00);
+	}
+
+	/* For NO-jack, disable L_DET_EN before Z-det measurements */
+	if (mbhc->hphl_swh)
+		regmap_update_bits(wcd939x->regmap,
+				   WCD939X_MBHC_MECH, 0x80, 0x00);
+
+	/* Turn off 100k pull down on HPHL */
+	regmap_update_bits(wcd939x->regmap,
+			   WCD939X_MBHC_MECH, 0x01, 0x00);
+
+	/* Disable surge protection before impedance detection.
+	 * This is done to give correct value for high impedance.
+	 */
+	regmap_update_bits(wcd939x->regmap,
+                          WCD939X_HPHLR_SURGE_EN, 0xC0, 0x00);
+	/* 1ms delay needed after disable surge protection */
+	usleep_range(1000, 1010);
+
+	/* First get impedance on Left */
+	d1 = d1_a[1];
+	zdet_param_ptr = &zdet_param[1];
+	wcd939x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
+
+	if (!WCD939X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
+		goto left_ch_impedance;
+
+	/* Second ramp for left ch */
+	if (z1L < WCD939X_ZDET_VAL_32) {
+		zdet_param_ptr = &zdet_param[0];
+		d1 = d1_a[0];
+	} else if ((z1L > WCD939X_ZDET_VAL_400) &&
+		  (z1L <= WCD939X_ZDET_VAL_1200)) {
+		zdet_param_ptr = &zdet_param[2];
+		d1 = d1_a[2];
+	} else if (z1L > WCD939X_ZDET_VAL_1200) {
+		zdet_param_ptr = &zdet_param[3];
+		d1 = d1_a[3];
+	}
+	wcd939x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
+
+left_ch_impedance:
+	if ((z1L == WCD939X_ZDET_FLOATING_IMPEDANCE) ||
+		(z1L > WCD939X_ZDET_VAL_100K)) {
+		*zl = WCD939X_ZDET_FLOATING_IMPEDANCE;
+		zdet_param_ptr = &zdet_param[1];
+		d1 = d1_a[1];
+	} else {
+		*zl = z1L/1000;
+		wcd939x_wcd_mbhc_qfuse_cal(component, zl, 0);
+	}
+	dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
+		__func__, *zl);
+
+	/* Start of right impedance ramp and calculation */
+	wcd939x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
+	if (WCD939X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
+		if (((z1R > WCD939X_ZDET_VAL_1200) &&
+			(zdet_param_ptr->noff == 0x6)) ||
+			((*zl) != WCD939X_ZDET_FLOATING_IMPEDANCE))
+			goto right_ch_impedance;
+		/* Second ramp for right ch */
+		if (z1R < WCD939X_ZDET_VAL_32) {
+			zdet_param_ptr = &zdet_param[0];
+			d1 = d1_a[0];
+		} else if ((z1R > WCD939X_ZDET_VAL_400) &&
+			(z1R <= WCD939X_ZDET_VAL_1200)) {
+			zdet_param_ptr = &zdet_param[2];
+			d1 = d1_a[2];
+		} else if (z1R > WCD939X_ZDET_VAL_1200) {
+			zdet_param_ptr = &zdet_param[3];
+			d1 = d1_a[3];
+		}
+		wcd939x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
+	}
+right_ch_impedance:
+	if ((z1R == WCD939X_ZDET_FLOATING_IMPEDANCE) ||
+		(z1R > WCD939X_ZDET_VAL_100K)) {
+		*zr = WCD939X_ZDET_FLOATING_IMPEDANCE;
+	} else {
+		*zr = z1R/1000;
+		wcd939x_wcd_mbhc_qfuse_cal(component, zr, 1);
+	}
+	dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
+		__func__, *zr);
+
+	/* Mono/stereo detection */
+	if ((*zl == WCD939X_ZDET_FLOATING_IMPEDANCE) &&
+		(*zr == WCD939X_ZDET_FLOATING_IMPEDANCE)) {
+		dev_dbg(component->dev,
+			"%s: plug type is invalid or extension cable\n",
+			__func__);
+		goto zdet_complete;
+	}
+	if ((*zl == WCD939X_ZDET_FLOATING_IMPEDANCE) ||
+	    (*zr == WCD939X_ZDET_FLOATING_IMPEDANCE) ||
+	    ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
+	    ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
+		dev_dbg(component->dev,
+			"%s: Mono plug type with one ch floating or shorted to GND\n",
+			__func__);
+		mbhc->hph_type = WCD_MBHC_HPH_MONO;
+		goto zdet_complete;
+	}
+	snd_soc_component_update_bits(component, WCD939X_R_ATEST, 0x02, 0x02);
+	snd_soc_component_update_bits(component, WCD939X_PA_CTL2, 0x40, 0x01);
+	if (*zl < (WCD939X_ZDET_VAL_32/1000))
+		wcd939x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
+	else
+		wcd939x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
+	snd_soc_component_update_bits(component, WCD939X_PA_CTL2, 0x40, 0x00);
+	snd_soc_component_update_bits(component, WCD939X_R_ATEST, 0x02, 0x00);
+	z1Ls /= 1000;
+	wcd939x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
+	/* Parallel of left Z and 9 ohm pull down resistor */
+	zMono = ((*zl) * 9) / ((*zl) + 9);
+	z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
+	z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
+	if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
+		dev_dbg(component->dev, "%s: stereo plug type detected\n",
+			__func__);
+		mbhc->hph_type = WCD_MBHC_HPH_STEREO;
+	} else {
+		dev_dbg(component->dev, "%s: MONO plug type detected\n",
+			__func__);
+		mbhc->hph_type = WCD_MBHC_HPH_MONO;
+	}
+
+	/* Enable surge protection again after impedance detection */
+	regmap_update_bits(wcd939x->regmap,
+			   WCD939X_HPHLR_SURGE_EN, 0xC0, 0xC0);
+zdet_complete:
+	snd_soc_component_write(component, WCD939X_MBHC_BTN5, reg0);
+	snd_soc_component_write(component, WCD939X_MBHC_BTN6, reg1);
+	snd_soc_component_write(component, WCD939X_MBHC_BTN7, reg2);
+	/* Turn on 100k pull down on HPHL */
+	regmap_update_bits(wcd939x->regmap,
+			   WCD939X_MBHC_MECH, 0x01, 0x01);
+
+	/* For NO-jack, re-enable L_DET_EN after Z-det measurements */
+	if (mbhc->hphl_swh)
+		regmap_update_bits(wcd939x->regmap,
+				   WCD939X_MBHC_MECH, 0x80, 0x80);
+
+	snd_soc_component_write(component, WCD939X_ZDET_ANA_CTL, reg4);
+	snd_soc_component_write(component, WCD939X_CTL_CLK, reg3);
+	if (is_fsm_disable)
+		regmap_update_bits(wcd939x->regmap,
+				   WCD939X_MBHC_ELECT, 0x80, 0x80);
+}
+
+static void wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
+			bool enable)
+{
+	if (enable) {
+		snd_soc_component_update_bits(component, WCD939X_MBHC_MECH,
+				    0x02, 0x02);
+		snd_soc_component_update_bits(component, WCD939X_MBHC_MECH,
+				    0x40, 0x40);
+	} else {
+		snd_soc_component_update_bits(component, WCD939X_MBHC_MECH,
+				    0x40, 0x00);
+		snd_soc_component_update_bits(component, WCD939X_MBHC_MECH,
+				    0x02, 0x00);
+	}
+}
+
+static void wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
+					  bool enable)
+{
+	if (enable) {
+		snd_soc_component_update_bits(component, WCD939X_PA_CTL2,
+				    0x40, 0x40);
+		snd_soc_component_update_bits(component, WCD939X_PA_CTL2,
+				    0x10, 0x10);
+	} else {
+		snd_soc_component_update_bits(component, WCD939X_PA_CTL2,
+				    0x40, 0x00);
+		snd_soc_component_update_bits(component, WCD939X_PA_CTL2,
+				    0x10, 0x00);
+	}
+}
+
+static void wcd939x_mbhc_moisture_config(struct wcd_mbhc *mbhc)
+{
+	struct snd_soc_component *component = mbhc->component;
+
+	if ((mbhc->moist_rref == R_OFF) ||
+	    (mbhc->mbhc_cfg->enable_usbc_analog)) {
+		snd_soc_component_update_bits(component, WCD939X_CTL_2,
+				    0x0C, R_OFF << 2);
+		return;
+	}
+
+	/* Do not enable moisture detection if jack type is NC */
+	if (!mbhc->hphl_swh) {
+		dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
+			__func__);
+		snd_soc_component_update_bits(component, WCD939X_CTL_2,
+				    0x0C, R_OFF << 2);
+		return;
+	}
+
+	snd_soc_component_update_bits(component, WCD939X_CTL_2,
+			    0x0C, mbhc->moist_rref << 2);
+}
+
+static void wcd939x_mbhc_moisture_detect_en(struct wcd_mbhc *mbhc, bool enable)
+{
+	struct snd_soc_component *component = mbhc->component;
+
+	if (enable)
+		snd_soc_component_update_bits(component, WCD939X_CTL_2,
+					0x0C, mbhc->moist_rref << 2);
+	else
+		snd_soc_component_update_bits(component, WCD939X_CTL_2,
+				    0x0C, R_OFF << 2);
+}
+
+static bool wcd939x_mbhc_get_moisture_status(struct wcd_mbhc *mbhc)
+{
+	struct snd_soc_component *component = mbhc->component;
+	bool ret = false;
+
+	if ((mbhc->moist_rref == R_OFF) ||
+	    (mbhc->mbhc_cfg->enable_usbc_analog)) {
+		snd_soc_component_update_bits(component, WCD939X_CTL_2,
+				    0x0C, R_OFF << 2);
+		goto done;
+	}
+
+	/* Do not enable moisture detection if jack type is NC */
+	if (!mbhc->hphl_swh) {
+		dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
+			__func__);
+		snd_soc_component_update_bits(component, WCD939X_CTL_2,
+				    0x0C, R_OFF << 2);
+		goto done;
+	}
+
+	/*
+	 * If moisture_en is already enabled, then skip to plug type
+	 * detection.
+	 */
+	if ((snd_soc_component_read(component, WCD939X_CTL_2) & 0x0C))
+		goto done;
+
+	wcd939x_mbhc_moisture_detect_en(mbhc, true);
+	/* Read moisture comparator status */
+	ret = ((snd_soc_component_read(component, WCD939X_FSM_STATUS)
+				& 0x20) ? 0 : 1);
+
+done:
+	return ret;
+
+}
+
+static void wcd939x_mbhc_moisture_polling_ctrl(struct wcd_mbhc *mbhc,
+						bool enable)
+{
+	struct snd_soc_component *component = mbhc->component;
+
+	snd_soc_component_update_bits(component,
+			WCD939X_MOISTURE_DET_POLLING_CTRL,
+			0x04, (enable << 2));
+}
+
+static void wcd939x_mbhc_bcs_enable(struct wcd_mbhc *mbhc,
+						  bool bcs_enable)
+{
+	if (bcs_enable)
+		wcd939x_disable_bcs_before_slow_insert(mbhc->component, false);
+	else
+		wcd939x_disable_bcs_before_slow_insert(mbhc->component, true);
+}
+
+static const struct wcd_mbhc_cb mbhc_cb = {
+	.request_irq = wcd939x_mbhc_request_irq,
+	.irq_control = wcd939x_mbhc_irq_control,
+	.free_irq = wcd939x_mbhc_free_irq,
+	.clk_setup = wcd939x_mbhc_clk_setup,
+	.map_btn_code_to_num = wcd939x_mbhc_btn_to_num,
+	.mbhc_bias = wcd939x_mbhc_mbhc_bias_control,
+	.set_btn_thr = wcd939x_mbhc_program_btn_thr,
+	.lock_sleep = wcd939x_mbhc_lock_sleep,
+	.register_notifier = wcd939x_mbhc_register_notifier,
+	.micbias_enable_status = wcd939x_mbhc_micb_en_status,
+	.hph_pa_on_status = wcd939x_mbhc_hph_pa_on_status,
+	.hph_pull_up_control_v2 = wcd939x_mbhc_hph_l_pull_up_control,
+	.mbhc_micbias_control = wcd939x_mbhc_request_micbias,
+	.mbhc_micb_ramp_control = wcd939x_mbhc_micb_ramp_control,
+	.get_hwdep_fw_cal = wcd939x_get_hwdep_fw_cal,
+	.mbhc_micb_ctrl_thr_mic = wcd939x_mbhc_micb_ctrl_threshold_mic,
+	.compute_impedance = wcd939x_wcd_mbhc_calc_impedance,
+	.mbhc_gnd_det_ctrl = wcd939x_mbhc_gnd_det_ctrl,
+	.hph_pull_down_ctrl = wcd939x_mbhc_hph_pull_down_ctrl,
+	.mbhc_moisture_config = wcd939x_mbhc_moisture_config,
+	.mbhc_get_moisture_status = wcd939x_mbhc_get_moisture_status,
+	.mbhc_moisture_polling_ctrl = wcd939x_mbhc_moisture_polling_ctrl,
+	.mbhc_moisture_detect_en = wcd939x_mbhc_moisture_detect_en,
+	.bcs_enable = wcd939x_mbhc_bcs_enable,
+};
+
+static int wcd939x_get_hph_type(struct snd_kcontrol *kcontrol,
+			      struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+					snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_mbhc *wcd939x_mbhc = wcd939x_soc_get_mbhc(component);
+	struct wcd_mbhc *mbhc;
+
+	if (!wcd939x_mbhc) {
+		dev_err_ratelimited(component->dev, "%s: mbhc not initialized!\n", __func__);
+		return -EINVAL;
+	}
+
+	mbhc = &wcd939x_mbhc->wcd_mbhc;
+
+	ucontrol->value.integer.value[0] = (u32) mbhc->hph_type;
+	dev_dbg(component->dev, "%s: hph_type = %u\n", __func__, mbhc->hph_type);
+
+	return 0;
+}
+
+static int wcd939x_hph_impedance_get(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	uint32_t zl, zr;
+	bool hphr;
+	struct soc_multi_mixer_control *mc;
+	struct snd_soc_component *component =
+					snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_mbhc *wcd939x_mbhc = wcd939x_soc_get_mbhc(component);
+
+	if (!wcd939x_mbhc) {
+		dev_err_ratelimited(component->dev, "%s: mbhc not initialized!\n", __func__);
+		return -EINVAL;
+	}
+
+	mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
+	hphr = mc->shift;
+	wcd_mbhc_get_impedance(&wcd939x_mbhc->wcd_mbhc, &zl, &zr);
+	dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
+	ucontrol->value.integer.value[0] = hphr ? zr : zl;
+
+	return 0;
+}
+
+static const struct snd_kcontrol_new hph_type_detect_controls[] = {
+	SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
+		       wcd939x_get_hph_type, NULL),
+};
+
+static const struct snd_kcontrol_new impedance_detect_controls[] = {
+	SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
+		       wcd939x_hph_impedance_get, NULL),
+	SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
+		       wcd939x_hph_impedance_get, NULL),
+};
+
+/*
+ * wcd939x_mbhc_get_impedance: get impedance of headphone
+ * left and right channels
+ * @wcd939x_mbhc: handle to struct wcd939x_mbhc *
+ * @zl: handle to left-ch impedance
+ * @zr: handle to right-ch impedance
+ * return 0 for success or error code in case of failure
+ */
+int wcd939x_mbhc_get_impedance(struct wcd939x_mbhc *wcd939x_mbhc,
+			     uint32_t *zl, uint32_t *zr)
+{
+	if (!wcd939x_mbhc) {
+		pr_err_ratelimited("%s: mbhc not initialized!\n", __func__);
+		return -EINVAL;
+	}
+	if (!zl || !zr) {
+		pr_err_ratelimited("%s: zl or zr null!\n", __func__);
+		return -EINVAL;
+	}
+
+	return wcd_mbhc_get_impedance(&wcd939x_mbhc->wcd_mbhc, zl, zr);
+}
+EXPORT_SYMBOL(wcd939x_mbhc_get_impedance);
+
+/*
+ * wcd939x_mbhc_hs_detect: starts mbhc insertion/removal functionality
+ * @codec: handle to snd_soc_component *
+ * @mbhc_cfg: handle to mbhc configuration structure
+ * return 0 if mbhc_start is success or error code in case of failure
+ */
+int wcd939x_mbhc_hs_detect(struct snd_soc_component *component,
+			 struct wcd_mbhc_config *mbhc_cfg)
+{
+	struct wcd939x_priv *wcd939x = NULL;
+	struct wcd939x_mbhc *wcd939x_mbhc = NULL;
+
+	if (!component) {
+		pr_err_ratelimited("%s: component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd939x = snd_soc_component_get_drvdata(component);
+	if (!wcd939x) {
+		pr_err_ratelimited("%s: wcd939x is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd939x_mbhc = wcd939x->mbhc;
+	if (!wcd939x_mbhc) {
+		dev_err_ratelimited(component->dev, "%s: mbhc not initialized!\n", __func__);
+		return -EINVAL;
+	}
+
+	return wcd_mbhc_start(&wcd939x_mbhc->wcd_mbhc, mbhc_cfg);
+}
+EXPORT_SYMBOL(wcd939x_mbhc_hs_detect);
+
+/*
+ * wcd939x_mbhc_hs_detect_exit: stop mbhc insertion/removal functionality
+ * @component: handle to snd_soc_component *
+ */
+void wcd939x_mbhc_hs_detect_exit(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x = NULL;
+	struct wcd939x_mbhc *wcd939x_mbhc = NULL;
+
+	if (!component) {
+		pr_err_ratelimited("%s: component is NULL\n", __func__);
+		return;
+	}
+
+	wcd939x = snd_soc_component_get_drvdata(component);
+	if (!wcd939x) {
+		pr_err_ratelimited("%s: wcd939x is NULL\n", __func__);
+		return;
+	}
+
+	wcd939x_mbhc = wcd939x->mbhc;
+	if (!wcd939x_mbhc) {
+		dev_err_ratelimited(component->dev, "%s: mbhc not initialized!\n", __func__);
+		return;
+	}
+	wcd_mbhc_stop(&wcd939x_mbhc->wcd_mbhc);
+}
+EXPORT_SYMBOL(wcd939x_mbhc_hs_detect_exit);
+
+/*
+ * wcd939x_mbhc_ssr_down: stop mbhc during
+ * wcd939x subsystem restart
+ * mbhc: pointer to wcd937x_mbhc structure
+ * component: handle to snd_soc_component *
+ */
+void wcd939x_mbhc_ssr_down(struct wcd939x_mbhc *mbhc,
+			struct snd_soc_component *component)
+{
+	struct wcd_mbhc *wcd_mbhc = NULL;
+
+	if (!mbhc || !component)
+		return;
+
+	wcd_mbhc = &mbhc->wcd_mbhc;
+	if (!wcd_mbhc) {
+		dev_err_ratelimited(component->dev, "%s: wcd_mbhc is NULL\n", __func__);
+		return;
+	}
+
+	wcd939x_mbhc_hs_detect_exit(component);
+	wcd_mbhc_deinit(wcd_mbhc);
+}
+EXPORT_SYMBOL(wcd939x_mbhc_ssr_down);
+
+/*
+ * wcd939x_mbhc_post_ssr_init: initialize mbhc for
+ * wcd939x post subsystem restart
+ * @mbhc: poniter to wcd939x_mbhc structure
+ * @component: handle to snd_soc_component *
+ *
+ * return 0 if mbhc_init is success or error code in case of failure
+ */
+int wcd939x_mbhc_post_ssr_init(struct wcd939x_mbhc *mbhc,
+			     struct snd_soc_component *component)
+{
+	int ret = 0;
+	struct wcd_mbhc *wcd_mbhc = NULL;
+
+	if (!mbhc || !component)
+		return -EINVAL;
+
+	wcd_mbhc = &mbhc->wcd_mbhc;
+	if (wcd_mbhc == NULL) {
+		pr_err("%s: wcd_mbhc is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Reset detection type to insertion after SSR recovery */
+	snd_soc_component_update_bits(component, WCD939X_MBHC_MECH,
+				0x20, 0x20);
+	ret = wcd_mbhc_init(wcd_mbhc, component, &mbhc_cb, &intr_ids,
+			    wcd_mbhc_registers, WCD939X_ZDET_SUPPORTED);
+	if (ret) {
+		dev_err(component->dev, "%s: mbhc initialization failed\n",
+			__func__);
+		goto done;
+	}
+
+done:
+	return ret;
+}
+EXPORT_SYMBOL(wcd939x_mbhc_post_ssr_init);
+
+/*
+ * wcd939x_mbhc_init: initialize mbhc for wcd939x
+ * @mbhc: poniter to wcd939x_mbhc struct pointer to store the configs
+ * @codec: handle to snd_soc_component *
+ * @fw_data: handle to firmware data
+ *
+ * return 0 if mbhc_init is success or error code in case of failure
+ */
+int wcd939x_mbhc_init(struct wcd939x_mbhc **mbhc,
+				struct snd_soc_component *component,
+				struct fw_info *fw_data)
+{
+	struct wcd939x_mbhc *wcd939x_mbhc = NULL;
+	struct wcd_mbhc *wcd_mbhc = NULL;
+	int ret = 0;
+	struct wcd939x_pdata *pdata;
+
+	if (!component) {
+		pr_err("%s: component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd939x_mbhc = devm_kzalloc(component->dev, sizeof(struct wcd939x_mbhc),
+				    GFP_KERNEL);
+	if (!wcd939x_mbhc)
+		return -ENOMEM;
+
+	wcd939x_mbhc->fw_data = fw_data;
+	BLOCKING_INIT_NOTIFIER_HEAD(&wcd939x_mbhc->notifier);
+	wcd_mbhc = &wcd939x_mbhc->wcd_mbhc;
+	if (wcd_mbhc == NULL) {
+		pr_err("%s: wcd_mbhc is NULL\n", __func__);
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* Setting default mbhc detection logic to ADC */
+	wcd_mbhc->mbhc_detection_logic = WCD_DETECTION_ADC;
+
+	pdata = dev_get_platdata(component->dev);
+	if (!pdata) {
+		dev_err(component->dev, "%s: pdata pointer is NULL\n",
+			__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	wcd_mbhc->micb_mv = pdata->micbias.micb2_mv;
+
+	ret = wcd_mbhc_init(wcd_mbhc, component, &mbhc_cb,
+				&intr_ids, wcd_mbhc_registers,
+				WCD939X_ZDET_SUPPORTED);
+	if (ret) {
+		dev_err(component->dev, "%s: mbhc initialization failed\n",
+			__func__);
+		goto err;
+	}
+
+	(*mbhc) = wcd939x_mbhc;
+	snd_soc_add_component_controls(component, impedance_detect_controls,
+				   ARRAY_SIZE(impedance_detect_controls));
+	snd_soc_add_component_controls(component, hph_type_detect_controls,
+				   ARRAY_SIZE(hph_type_detect_controls));
+
+	return 0;
+err:
+	devm_kfree(component->dev, wcd939x_mbhc);
+	return ret;
+}
+EXPORT_SYMBOL(wcd939x_mbhc_init);
+
+/*
+ * wcd939x_mbhc_deinit: deinitialize mbhc for wcd939x
+ * @codec: handle to snd_soc_component *
+ */
+void wcd939x_mbhc_deinit(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x;
+	struct wcd939x_mbhc *wcd939x_mbhc;
+
+	if (!component) {
+		pr_err("%s: component is NULL\n", __func__);
+		return;
+	}
+
+	wcd939x = snd_soc_component_get_drvdata(component);
+	if (!wcd939x) {
+		pr_err("%s: wcd939x is NULL\n", __func__);
+		return;
+	}
+
+	wcd939x_mbhc = wcd939x->mbhc;
+	if (wcd939x_mbhc) {
+		wcd_mbhc_deinit(&wcd939x_mbhc->wcd_mbhc);
+		devm_kfree(component->dev, wcd939x_mbhc);
+	}
+}
+EXPORT_SYMBOL(wcd939x_mbhc_deinit);

asoc/codecs/wcd939x/wcd939x-mbhc.h

@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#ifndef __WCD939X_MBHC_H__
+#define __WCD939X_MBHC_H__
+#include <asoc/wcd-mbhc-v2.h>
+
+struct wcd939x_mbhc {
+	struct wcd_mbhc wcd_mbhc;
+	struct blocking_notifier_head notifier;
+	struct fw_info *fw_data;
+};
+
+#if IS_ENABLED(CONFIG_SND_SOC_WCD939X)
+extern int wcd939x_mbhc_init(struct wcd939x_mbhc **mbhc,
+			   struct snd_soc_component *component,
+			   struct fw_info *fw_data);
+extern void wcd939x_mbhc_hs_detect_exit(struct snd_soc_component *component);
+extern int wcd939x_mbhc_hs_detect(struct snd_soc_component *component,
+				struct wcd_mbhc_config *mbhc_cfg);
+extern void wcd939x_mbhc_deinit(struct snd_soc_component *component);
+extern void wcd939x_mbhc_ssr_down(struct wcd939x_mbhc *mbhc,
+				struct snd_soc_component *component);
+extern int wcd939x_mbhc_post_ssr_init(struct wcd939x_mbhc *mbhc,
+				    struct snd_soc_component *component);
+extern int wcd939x_mbhc_get_impedance(struct wcd939x_mbhc *wcd939x_mbhc,
+				    uint32_t *zl, uint32_t *zr);
+#else
+static inline int wcd939x_mbhc_init(struct wcd939x_mbhc **mbhc,
+				  struct snd_soc_component *component,
+				  struct fw_info *fw_data)
+{
+	return 0;
+}
+static inline void wcd939x_mbhc_hs_detect_exit(
+					struct snd_soc_component *component)
+{
+}
+static inline int wcd939x_mbhc_hs_detect(struct snd_soc_component *component,
+				       struct wcd_mbhc_config *mbhc_cfg)
+{
+		return 0;
+}
+static inline void wcd939x_mbhc_deinit(struct snd_soc_component *component)
+{
+}
+static inline void wcd939x_mbhc_ssr_down(struct wcd939x_mbhc *mbhc,
+					struct snd_soc_component *component)
+{
+}
+static inline int wcd939x_mbhc_post_ssr_init(struct wcd939x_mbhc *mbhc,
+					   struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static inline int wcd939x_mbhc_get_impedance(struct wcd939x_mbhc *wcd939x_mbhc,
+					   uint32_t *zl, uint32_t *zr)
+{
+	if (zl)
+		*zl = 0;
+	if (zr)
+		*zr = 0;
+	return -EINVAL;
+}
+#endif
+
+#endif /* __WCD939X_MBHC_H__ */

asoc/codecs/wcd939x/wcd939x-reg-masks.h

@@ -0,0 +1,2673 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef WCD939X_REG_MASKS_H
+#define WCD939X_REG_MASKS_H
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd939x-registers.h"
+
+/* Use in conjunction with wcd939x-reg-shifts.c for field values. */
+/* field_value = (register_value & field_mask) >> field_shift */
+
+#define FIELD_MASK(register_name, field_name) \
+WCD939X_##register_name##_##field_name##_MASK
+
+/* WCD939X_ANA_PAGE Fields: */
+#define WCD939X_ANA_PAGE_VALUE_MASK                                      0xff
+
+/* WCD939X_BIAS Fields: */
+#define WCD939X_BIAS_ANALOG_BIAS_EN_MASK                                 0x80
+#define WCD939X_BIAS_PRECHRG_EN_MASK                                     0x40
+#define WCD939X_BIAS_PRECHRG_CTL_MODE_MASK                               0x20
+
+/* WCD939X_RX_SUPPLIES Fields: */
+#define WCD939X_RX_SUPPLIES_VPOS_EN_MASK                                 0x80
+#define WCD939X_RX_SUPPLIES_VNEG_EN_MASK                                 0x40
+#define WCD939X_RX_SUPPLIES_VPOS_PWR_LVL_MASK                            0x08
+#define WCD939X_RX_SUPPLIES_VNEG_PWR_LVL_MASK                            0x04
+#define WCD939X_RX_SUPPLIES_REGULATOR_MODE_MASK                          0x02
+#define WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE_MASK                          0x01
+
+/* WCD939X_HPH Fields: */
+#define WCD939X_HPH_HPHL_ENABLE_MASK                                     0x80
+#define WCD939X_HPH_HPHR_ENABLE_MASK                                     0x40
+#define WCD939X_HPH_HPHL_REF_ENABLE_MASK                                 0x20
+#define WCD939X_HPH_HPHR_REF_ENABLE_MASK                                 0x10
+#define WCD939X_HPH_PWR_LEVEL_MASK                                       0x0c
+
+/* WCD939X_EAR Fields: */
+#define WCD939X_EAR_ENABLE_MASK                                          0x80
+#define WCD939X_EAR_SHORT_PROT_EN_MASK                                   0x40
+#define WCD939X_EAR_OUT_IMPEDANCE_MASK                                   0x20
+
+/* WCD939X_EAR_COMPANDER_CTL Fields: */
+#define WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG_MASK                     0x80
+#define WCD939X_EAR_COMPANDER_CTL_EAR_GAIN_MASK                          0x7c
+#define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_BYP_MASK                      0x02
+#define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_CLK_EDGE_MASK                 0x01
+
+/* WCD939X_TX_CH1 Fields: */
+#define WCD939X_TX_CH1_ENABLE_MASK                                       0x80
+#define WCD939X_TX_CH1_PWR_LEVEL_MASK                                    0x60
+#define WCD939X_TX_CH1_GAIN_MASK                                         0x1f
+
+/* WCD939X_TX_CH2 Fields: */
+#define WCD939X_TX_CH2_ENABLE_MASK                                       0x80
+#define WCD939X_TX_CH2_HPF1_INIT_MASK                                    0x40
+#define WCD939X_TX_CH2_HPF2_INIT_MASK                                    0x20
+#define WCD939X_TX_CH2_GAIN_MASK                                         0x1f
+
+/* WCD939X_TX_CH3 Fields: */
+#define WCD939X_TX_CH3_ENABLE_MASK                                       0x80
+#define WCD939X_TX_CH3_PWR_LEVEL_MASK                                    0x60
+#define WCD939X_TX_CH3_GAIN_MASK                                         0x1f
+
+/* WCD939X_TX_CH4 Fields: */
+#define WCD939X_TX_CH4_ENABLE_MASK                                       0x80
+#define WCD939X_TX_CH4_HPF3_INIT_MASK                                    0x40
+#define WCD939X_TX_CH4_HPF4_INIT_MASK                                    0x20
+#define WCD939X_TX_CH4_GAIN_MASK                                         0x1f
+
+/* WCD939X_MICB1_MICB2_DSP_EN_LOGIC Fields: */
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC_MICB1_DSP_OVERRIDE_MASK         0x80
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC_MICB1_DSP_CTRL_MASK             0x60
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC_MICB2_DSP_OVERRIDE_MASK         0x10
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC_MICB2_DSP_CTRL_MASK             0x0c
+
+/* WCD939X_MICB3_DSP_EN_LOGIC Fields: */
+#define WCD939X_MICB3_DSP_EN_LOGIC_MICB3_DSP_OVERRIDE_MASK               0x80
+#define WCD939X_MICB3_DSP_EN_LOGIC_MICB3_DSP_CTRL_MASK                   0x60
+
+/* WCD939X_MBHC_MECH Fields: */
+#define WCD939X_MBHC_MECH_L_DET_EN_MASK                                  0x80
+#define WCD939X_MBHC_MECH_GND_DET_EN_MASK                                0x40
+#define WCD939X_MBHC_MECH_MECH_DETECT_TYPE_MASK                          0x20
+#define WCD939X_MBHC_MECH_HPHL_PLUG_TYPE_MASK                            0x10
+#define WCD939X_MBHC_MECH_GND_PLUG_TYPE_MASK                             0x08
+#define WCD939X_MBHC_MECH_MECH_HS_L_PULLUP_COMP_EN_MASK                  0x04
+#define WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN_MASK                  0x02
+#define WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND_MASK                    0x01
+
+/* WCD939X_MBHC_ELECT Fields: */
+#define WCD939X_MBHC_ELECT_FSM_EN_MASK                                   0x80
+#define WCD939X_MBHC_ELECT_BTNDET_ISRC_CTL_MASK                          0x70
+#define WCD939X_MBHC_ELECT_ELECT_DET_TYPE_MASK                           0x08
+#define WCD939X_MBHC_ELECT_ELECT_SCHMT_ISRC_CTL_MASK                     0x06
+#define WCD939X_MBHC_ELECT_BIAS_EN_MASK                                  0x01
+
+/* WCD939X_MBHC_ZDET Fields: */
+#define WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN_MASK                            0x80
+#define WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN_MASK                            0x40
+#define WCD939X_MBHC_ZDET_ZDET_CHG_EN_MASK                               0x20
+#define WCD939X_MBHC_ZDET_ZDET_ILEAK_COMP_EN_MASK                        0x10
+#define WCD939X_MBHC_ZDET_ELECT_ISRC_EN_MASK                             0x02
+
+/* WCD939X_MBHC_RESULT_1 Fields: */
+#define WCD939X_MBHC_RESULT_1_Z_RESULT_LSB_MASK                          0xff
+
+/* WCD939X_MBHC_RESULT_2 Fields: */
+#define WCD939X_MBHC_RESULT_2_Z_RESULT_MSB_MASK                          0xff
+
+/* WCD939X_MBHC_RESULT_3 Fields: */
+#define WCD939X_MBHC_RESULT_3_MIC_SCHMT_RESULT_MASK                      0x20
+#define WCD939X_MBHC_RESULT_3_IN2P_CLAMP_STATE_MASK                      0x10
+#define WCD939X_MBHC_RESULT_3_BTN_RESULT_MASK                            0x07
+
+/* WCD939X_MBHC_BTN0 Fields: */
+#define WCD939X_MBHC_BTN0_VTH_MASK                                       0xfc
+
+/* WCD939X_MBHC_BTN1 Fields: */
+#define WCD939X_MBHC_BTN1_VTH_MASK                                       0xfc
+
+/* WCD939X_MBHC_BTN2 Fields: */
+#define WCD939X_MBHC_BTN2_VTH_MASK                                       0xfc
+
+/* WCD939X_MBHC_BTN3 Fields: */
+#define WCD939X_MBHC_BTN3_VTH_MASK                                       0xfc
+
+/* WCD939X_MBHC_BTN4 Fields: */
+#define WCD939X_MBHC_BTN4_VTH_MASK                                       0xfc
+
+/* WCD939X_MBHC_BTN5 Fields: */
+#define WCD939X_MBHC_BTN5_VTH_MASK                                       0xfc
+
+/* WCD939X_MBHC_BTN6 Fields: */
+#define WCD939X_MBHC_BTN6_VTH_MASK                                       0xfc
+
+/* WCD939X_MBHC_BTN7 Fields: */
+#define WCD939X_MBHC_BTN7_VTH_MASK                                       0xfc
+
+/* WCD939X_MICB1 Fields: */
+#define WCD939X_MICB1_ENABLE_MASK                                        0xc0
+#define WCD939X_MICB1_VOUT_CTL_MASK                                      0x3f
+
+/* WCD939X_MICB2 Fields: */
+#define WCD939X_MICB2_ENABLE_MASK                                        0xc0
+#define WCD939X_MICB2_VOUT_CTL_MASK                                      0x3f
+
+/* WCD939X_MICB2_RAMP Fields: */
+#define WCD939X_MICB2_RAMP_RAMP_ENABLE_MASK                              0x80
+#define WCD939X_MICB2_RAMP_MB2_IN2P_SHORT_ENABLE_MASK                    0x40
+#define WCD939X_MICB2_RAMP_ALLSW_OVRD_ENABLE_MASK                        0x20
+#define WCD939X_MICB2_RAMP_SHIFT_CTL_MASK                                0x1c
+#define WCD939X_MICB2_RAMP_USB_MGDET_MICB2_RAMP_MASK                     0x03
+
+/* WCD939X_MICB3 Fields: */
+#define WCD939X_MICB3_ENABLE_MASK                                        0xc0
+
+/* WCD939X_MICB4 Fields: */
+#define WCD939X_MICB4_ENABLE_MASK                                        0xc0
+
+
+/* WCD939X_CTL Fields: */
+#define WCD939X_CTL_BG_FAST_MODE_EN_MASK                                 0x80
+#define WCD939X_CTL_TX_SCBIAS_REF_SEL_MASK                               0x40
+#define WCD939X_CTL_DC_START_UP_EN_MASK                                  0x20
+#define WCD939X_CTL_TRAN_START_UP_EN_MASK                                0x10
+#define WCD939X_CTL_OTA_BIAS_CTL_MASK                                    0x08
+#define WCD939X_CTL_ATEST_CTL_MASK                                       0x04
+#define WCD939X_CTL_EFUSE_EN_MASK                                        0x02
+
+/* WCD939X_VBG_FINE_ADJ Fields: */
+#define WCD939X_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK                           0xf0
+#define WCD939X_VBG_FINE_ADJ_EN_DTEST_BG_STATUS_MASK                     0x08
+#define WCD939X_VBG_FINE_ADJ_PRECHARGE_TIMER_COUNT_MASK                  0x07
+
+
+/* WCD939X_VDDCX_ADJUST Fields: */
+#define WCD939X_VDDCX_ADJUST_RC_ZERO_FREQ_TUNE_MASK                      0x0c
+#define WCD939X_VDDCX_ADJUST_VDDCX_ADJUST_MASK                           0x03
+
+/* WCD939X_DISABLE_LDOL Fields: */
+#define WCD939X_DISABLE_LDOL_DISABLE_LDOL_MASK                           0x01
+
+
+/* WCD939X_CTL_CLK Fields: */
+#define WCD939X_CTL_CLK_CLK_SEL_MASK                                     0x40
+#define WCD939X_CTL_CLK_COMP_CLK_CTL_MASK                                0x30
+#define WCD939X_CTL_CLK_COMP_AZ_CTL_MASK                                 0x0c
+#define WCD939X_CTL_CLK_TEST_CLK_EN_MASK                                 0x02
+#define WCD939X_CTL_CLK_COMP_AVG_BYP_EN_MASK                             0x01
+
+/* WCD939X_CTL_ANA Fields: */
+#define WCD939X_CTL_ANA_BIAS_SEL_MASK                                    0x80
+
+/* WCD939X_ZDET_VNEG_CTL Fields: */
+#define WCD939X_ZDET_VNEG_CTL_SPARE_BITS_7_6_MASK                        0xc0
+#define WCD939X_ZDET_VNEG_CTL_VPOS_EN_MASK                               0x20
+#define WCD939X_ZDET_VNEG_CTL_VNEGDAC_LDO_EN_MASK                        0x10
+#define WCD939X_ZDET_VNEG_CTL_RXBIAS_EN_MASK                             0x08
+#define WCD939X_ZDET_VNEG_CTL_VNEG_MODE_MASK                             0x04
+#define WCD939X_ZDET_VNEG_CTL_VNEG_EN_MASK                               0x02
+#define WCD939X_ZDET_VNEG_CTL_HPH_DISABLE_MASK                           0x01
+
+/* WCD939X_ZDET_BIAS_CTL Fields: */
+#define WCD939X_ZDET_BIAS_CTL_ZDET_ILEAK_EN_OVR_MASK                     0x80
+#define WCD939X_ZDET_BIAS_CTL_ZDET_ILEAK_COMP_CTL_MASK                   0x70
+#define WCD939X_ZDET_BIAS_CTL_ZDET_LDO_IREF_MASK                         0x0c
+#define WCD939X_ZDET_BIAS_CTL_ZDET_COMP_IREF_MASK                        0x03
+
+/* WCD939X_CTL_BCS Fields: */
+#define WCD939X_CTL_BCS_FAST_INT_OVRD_EN_MASK                            0x80
+#define WCD939X_CTL_BCS_ELECT_REM_FAST_REG_OVRD_MASK                     0x40
+#define WCD939X_CTL_BCS_BTN_RELEASE_FAST_REG_OVRD_MASK                   0x20
+#define WCD939X_CTL_BCS_BTN_PRESS_FAST_REG_OVRD_MASK                     0x10
+#define WCD939X_CTL_BCS_ANC_DET_EN_MASK                                  0x02
+#define WCD939X_CTL_BCS_DEBUG_1_MASK                                     0x01
+
+/* WCD939X_MOISTURE_DET_FSM_STATUS Fields: */
+#define WCD939X_MOISTURE_DET_FSM_STATUS_ELECT_IN2P_COMP_MASK             0x80
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MECH_HS_G_COMP_MASK              0x40
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MECH_HS_M_COMP_MASK              0x20
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MECH_HS_L_COMP_MASK              0x10
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MOISTURE_INTR_MASK               0x08
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MOISTURE_GTPOLLING_STATUS_MASK   0x04
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MOISTURE_DET_STATUS_MASK         0x02
+#define WCD939X_MOISTURE_DET_FSM_STATUS_ZDET_TIMER_MASK                  0x01
+
+/* WCD939X_TEST_CTL Fields: */
+#define WCD939X_TEST_CTL_FAST_DBNC_TIMER_MASK                            0x30
+#define WCD939X_TEST_CTL_ATEST_MASK                                      0x0f
+
+
+/* WCD939X_MODE Fields: */
+#define WCD939X_MODE_LDOH_EN_MASK                                        0x80
+#define WCD939X_MODE_PWRDN_STATE_MASK                                    0x40
+#define WCD939X_MODE_SLOWRAMP_EN_MASK                                    0x20
+#define WCD939X_MODE_VOUT_ADJUST_MASK                                    0x18
+#define WCD939X_MODE_VOUT_COARSE_ADJ_MASK                                0x07
+
+/* WCD939X_LDOH_BIAS Fields: */
+#define WCD939X_LDOH_BIAS_IBIAS_REF_MASK                                 0xe0
+#define WCD939X_LDOH_BIAS_IBIAS_ERR_AMP_MASK                             0x18
+#define WCD939X_LDOH_BIAS_IBIAS_NATIVE_DEVICE_MASK                       0x04
+#define WCD939X_LDOH_BIAS_IBIAS_BUFFER_BLEED_MASK                        0x02
+#define WCD939X_LDOH_BIAS_INRUSH_CURRENT_FIX_DIS_MASK                    0x01
+
+/* WCD939X_STB_LOADS Fields: */
+#define WCD939X_STB_LOADS_STB_LOADS_1_UA_MASK                            0xf0
+#define WCD939X_STB_LOADS_STB_LOAD_10_UA_MASK                            0x08
+#define WCD939X_STB_LOADS_FORCE_EN_60K_MASK                              0x04
+#define WCD939X_STB_LOADS_CLK_GATE_MASK                                  0x02
+
+/* WCD939X_SLOWRAMP Fields: */
+#define WCD939X_SLOWRAMP_SLOWRAMP_IBIAS_MASK                             0xc0
+#define WCD939X_SLOWRAMP_SLOWRAMP_RESET_TIME_MASK                        0x30
+
+
+/* WCD939X_TEST_CTL_1 Fields: */
+#define WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL_MASK                       0xe0
+#define WCD939X_TEST_CTL_1_EN_VREFGEN_MASK                               0x10
+#define WCD939X_TEST_CTL_1_EN_LDO_MASK                                   0x08
+#define WCD939X_TEST_CTL_1_LDO_BLEEDER_I_CTRL_MASK                       0x07
+
+/* WCD939X_TEST_CTL_2 Fields: */
+#define WCD939X_TEST_CTL_2_IBIAS_VREFGEN_MASK                            0xc0
+#define WCD939X_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_MASK                   0x20
+#define WCD939X_TEST_CTL_2_SPAREBIT_MASK                                 0x18
+#define WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK                         0x07
+
+/* WCD939X_TEST_CTL_3 Fields: */
+#define WCD939X_TEST_CTL_3_CFILT_REF_EN_MASK                             0x80
+#define WCD939X_TEST_CTL_3_RZ_LDO_VAL_MASK                               0x70
+#define WCD939X_TEST_CTL_3_IBIAS_LDO_STG3_MASK                           0x0c
+#define WCD939X_TEST_CTL_3_ATEST_CTRL_MASK                               0x03
+
+
+/* WCD939X_MICB2_TEST_CTL_1 Fields: */
+#define WCD939X_MICB2_TEST_CTL_1_NOISE_FILT_RES_VAL_MASK                 0xe0
+#define WCD939X_MICB2_TEST_CTL_1_EN_VREFGEN_MASK                         0x10
+#define WCD939X_MICB2_TEST_CTL_1_EN_LDO_MASK                             0x08
+#define WCD939X_MICB2_TEST_CTL_1_LDO_BLEEDER_I_CTRL_MASK                 0x07
+
+/* WCD939X_MICB2_TEST_CTL_2 Fields: */
+#define WCD939X_MICB2_TEST_CTL_2_IBIAS_VREFGEN_MASK                      0xc0
+#define WCD939X_MICB2_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_MASK             0x20
+#define WCD939X_MICB2_TEST_CTL_2_SPAREBIT_MASK                           0x18
+#define WCD939X_MICB2_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK                   0x07
+
+/* WCD939X_MICB2_TEST_CTL_3 Fields: */
+#define WCD939X_MICB2_TEST_CTL_3_CFILT_REF_EN_MASK                       0x80
+#define WCD939X_MICB2_TEST_CTL_3_RZ_LDO_VAL_MASK                         0x70
+#define WCD939X_MICB2_TEST_CTL_3_IBIAS_LDO_STG3_MASK                     0x0c
+#define WCD939X_MICB2_TEST_CTL_3_ATEST_CTRL_MASK                         0x03
+
+
+/* WCD939X_MICB3_TEST_CTL_1 Fields: */
+#define WCD939X_MICB3_TEST_CTL_1_NOISE_FILT_RES_VAL_MASK                 0xe0
+#define WCD939X_MICB3_TEST_CTL_1_EN_VREFGEN_MASK                         0x10
+#define WCD939X_MICB3_TEST_CTL_1_EN_LDO_MASK                             0x08
+#define WCD939X_MICB3_TEST_CTL_1_LDO_BLEEDER_I_CTRL_MASK                 0x07
+
+/* WCD939X_MICB3_TEST_CTL_2 Fields: */
+#define WCD939X_MICB3_TEST_CTL_2_IBIAS_VREFGEN_MASK                      0xc0
+#define WCD939X_MICB3_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_MASK             0x20
+#define WCD939X_MICB3_TEST_CTL_2_SPAREBIT_MASK                           0x18
+#define WCD939X_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK                   0x07
+
+/* WCD939X_MICB3_TEST_CTL_3 Fields: */
+#define WCD939X_MICB3_TEST_CTL_3_CFILT_REF_EN_MASK                       0x80
+#define WCD939X_MICB3_TEST_CTL_3_RZ_LDO_VAL_MASK                         0x70
+#define WCD939X_MICB3_TEST_CTL_3_IBIAS_LDO_STG3_MASK                     0x0c
+#define WCD939X_MICB3_TEST_CTL_3_ATEST_CTRL_MASK                         0x03
+
+
+/* WCD939X_MICB4_TEST_CTL_1 Fields: */
+#define WCD939X_MICB4_TEST_CTL_1_NOISE_FILT_RES_VAL_MASK                 0xe0
+#define WCD939X_MICB4_TEST_CTL_1_EN_VREFGEN_MASK                         0x10
+#define WCD939X_MICB4_TEST_CTL_1_EN_LDO_MASK                             0x08
+#define WCD939X_MICB4_TEST_CTL_1_LDO_BLEEDER_I_CTRL_MASK                 0x07
+
+/* WCD939X_MICB4_TEST_CTL_2 Fields: */
+#define WCD939X_MICB4_TEST_CTL_2_IBIAS_VREFGEN_MASK                      0xc0
+#define WCD939X_MICB4_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_MASK             0x20
+#define WCD939X_MICB4_TEST_CTL_2_SPAREBIT_MASK                           0x18
+#define WCD939X_MICB4_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK                   0x07
+
+/* WCD939X_MICB4_TEST_CTL_3 Fields: */
+#define WCD939X_MICB4_TEST_CTL_3_CFILT_REF_EN_MASK                       0x80
+#define WCD939X_MICB4_TEST_CTL_3_RZ_LDO_VAL_MASK                         0x70
+#define WCD939X_MICB4_TEST_CTL_3_IBIAS_LDO_STG3_MASK                     0x0c
+#define WCD939X_MICB4_TEST_CTL_3_ATEST_CTRL_MASK                         0x03
+
+
+/* WCD939X_ADC_VCM Fields: */
+#define WCD939X_ADC_VCM_FLL_ATEST_EN_MASK                                0x40
+#define WCD939X_ADC_VCM_VCM_L2_12P288_MASK                               0x30
+#define WCD939X_ADC_VCM_VCM_L2_9P6_MASK                                  0x0c
+#define WCD939X_ADC_VCM_VCM_DEFAULT_MASK                                 0x03
+
+/* WCD939X_BIAS_ATEST Fields: */
+#define WCD939X_BIAS_ATEST_TX_CURR_EN_MASK                               0x80
+#define WCD939X_BIAS_ATEST_SC_BIAS_EN_MASK                               0x40
+#define WCD939X_BIAS_ATEST_SC_BIAS_VREF_SEL_MASK                         0x20
+#define WCD939X_BIAS_ATEST_ATEST4_EN_MASK                                0x08
+#define WCD939X_BIAS_ATEST_ATEST3_EN_MASK                                0x04
+#define WCD939X_BIAS_ATEST_ATEST2_EN_MASK                                0x02
+#define WCD939X_BIAS_ATEST_ATEST1_EN_MASK                                0x01
+
+/* WCD939X_SPARE1 Fields: */
+#define WCD939X_SPARE1_SPARE_BITS_7_0_MASK                               0xff
+
+/* WCD939X_SPARE2 Fields: */
+#define WCD939X_SPARE2_SPARE_BITS_7_0_MASK                               0xff
+
+/* WCD939X_TXFE_DIV_CTL Fields: */
+#define WCD939X_TXFE_DIV_CTL_FB_SW_DRIVE_MASK                            0x20
+#define WCD939X_TXFE_DIV_CTL_EN_CKGEN_INIT_MASK                          0x10
+#define WCD939X_TXFE_DIV_CTL_N_PAUSE_MASK                                0x03
+
+/* WCD939X_TXFE_DIV_START Fields: */
+#define WCD939X_TXFE_DIV_START_DIV_MASK                                  0xff
+
+/* WCD939X_SPARE3 Fields: */
+#define WCD939X_SPARE3_SPARE_BITS_7_0_MASK                               0xff
+
+/* WCD939X_SPARE4 Fields: */
+#define WCD939X_SPARE4_SPARE_BITS_7_0_MASK                               0xff
+
+
+/* WCD939X_TEST_EN Fields: */
+#define WCD939X_TEST_EN_TXFE1_EN_MASK                                    0x80
+#define WCD939X_TEST_EN_ADC1_EN_MASK                                     0x40
+#define WCD939X_TEST_EN_TXFE1_BYPASS_MASK                                0x20
+#define WCD939X_TEST_EN_TXFE1_CLK_MODE_MASK                              0x10
+#define WCD939X_TEST_EN_TXFE2_EN_MASK                                    0x08
+#define WCD939X_TEST_EN_ADC2_EN_MASK                                     0x04
+#define WCD939X_TEST_EN_TXFE2_BYPASS_MASK                                0x02
+#define WCD939X_TEST_EN_TXFE2_CLK_MODE_MASK                              0x01
+
+/* WCD939X_ADC_IB Fields: */
+#define WCD939X_ADC_IB_ADC2_DEM_MODE_MASK                                0xc0
+#define WCD939X_ADC_IB_ADC2_DEM_OPERATION_MASK                           0x30
+#define WCD939X_ADC_IB_L2_DAC_DLY_MASK                                   0x0c
+#define WCD939X_ADC_IB_DEFAULT_DAC_DLY_MASK                              0x03
+
+/* WCD939X_ATEST_REFCTL Fields: */
+#define WCD939X_ATEST_REFCTL_ATEST_CTL_MASK                              0xf0
+#define WCD939X_ATEST_REFCTL_TXFE_INCM_REF_MASK                          0x0c
+#define WCD939X_ATEST_REFCTL_TXFE_HP_GAIN_MODE_MASK                      0x02
+#define WCD939X_ATEST_REFCTL_ADCREF_ULPRES_EN_MASK                       0x01
+
+/* WCD939X_TX_1_2_TEST_CTL Fields: */
+#define WCD939X_TX_1_2_TEST_CTL_TXFE_HP_GAIN_MASK                        0x80
+#define WCD939X_TX_1_2_TEST_CTL_REF_CAP_MASK                             0x40
+#define WCD939X_TX_1_2_TEST_CTL_ADC1_DEM_MODE_MASK                       0x30
+#define WCD939X_TX_1_2_TEST_CTL_ADC1_DEM_OPERATION_MASK                  0x0c
+#define WCD939X_TX_1_2_TEST_CTL_SAR_ERR_DET_EN_MASK                      0x02
+#define WCD939X_TX_1_2_TEST_CTL_SAR_EXT_DELAY_EN_MASK                    0x01
+
+/* WCD939X_TEST_BLK_EN1 Fields: */
+#define WCD939X_TEST_BLK_EN1_ADC1_INT1_EN_MASK                           0x80
+#define WCD939X_TEST_BLK_EN1_ADC1_INT2_EN_MASK                           0x40
+#define WCD939X_TEST_BLK_EN1_ADC1_SAR_EN_MASK                            0x20
+#define WCD939X_TEST_BLK_EN1_ADC1_CMGEN_EN_MASK                          0x10
+#define WCD939X_TEST_BLK_EN1_ADC1_CLKGEN_EN_MASK                         0x08
+#define WCD939X_TEST_BLK_EN1_REF_EN_MASK                                 0x04
+#define WCD939X_TEST_BLK_EN1_TXFE1_CLKDIV_EN_MASK                        0x02
+#define WCD939X_TEST_BLK_EN1_TXFE2_CLKDIV_EN_MASK                        0x01
+
+/* WCD939X_TXFE1_CLKDIV Fields: */
+#define WCD939X_TXFE1_CLKDIV_DIV_MASK                                    0xff
+
+/* WCD939X_SAR2_ERR Fields: */
+#define WCD939X_SAR2_ERR_SAR_ERR_COUNT_MASK                              0xff
+
+/* WCD939X_SAR1_ERR Fields: */
+#define WCD939X_SAR1_ERR_SAR_ERR_COUNT_MASK                              0xff
+
+
+/* WCD939X_TX_3_4_TEST_EN Fields: */
+#define WCD939X_TX_3_4_TEST_EN_TXFE3_EN_MASK                             0x80
+#define WCD939X_TX_3_4_TEST_EN_ADC3_EN_MASK                              0x40
+#define WCD939X_TX_3_4_TEST_EN_TXFE3_BYPASS_MASK                         0x20
+#define WCD939X_TX_3_4_TEST_EN_TXFE3_CLK_MODE_MASK                       0x10
+#define WCD939X_TX_3_4_TEST_EN_TXFE4_EN_MASK                             0x08
+#define WCD939X_TX_3_4_TEST_EN_ADC4_EN_MASK                              0x04
+#define WCD939X_TX_3_4_TEST_EN_TXFE4_BYPASS_MASK                         0x02
+#define WCD939X_TX_3_4_TEST_EN_TXFE4_CLK_MODE_MASK                       0x01
+
+/* WCD939X_TX_3_4_ADC_IB Fields: */
+#define WCD939X_TX_3_4_ADC_IB_ADC4_DEM_MODE_MASK                         0xc0
+#define WCD939X_TX_3_4_ADC_IB_ADC4_DEM_OPERATION_MASK                    0x30
+#define WCD939X_TX_3_4_ADC_IB_L2_DAC_DLY_MASK                            0x0c
+#define WCD939X_TX_3_4_ADC_IB_DEFAULT_DAC_DLY_MASK                       0x03
+
+/* WCD939X_TX_3_4_ATEST_REFCTL Fields: */
+#define WCD939X_TX_3_4_ATEST_REFCTL_ATEST_CTL_MASK                       0xf0
+#define WCD939X_TX_3_4_ATEST_REFCTL_TXFE_INCM_REF_MASK                   0x0c
+#define WCD939X_TX_3_4_ATEST_REFCTL_TXFE_HP_GAIN_MODE_MASK               0x02
+#define WCD939X_TX_3_4_ATEST_REFCTL_ADCREF_ULPRES_EN_MASK                0x01
+
+/* WCD939X_TX_3_4_TEST_CTL Fields: */
+#define WCD939X_TX_3_4_TEST_CTL_TXFE_HP_GAIN_MASK                        0x80
+#define WCD939X_TX_3_4_TEST_CTL_REF_CAP_MASK                             0x40
+#define WCD939X_TX_3_4_TEST_CTL_ADC3_DEM_MODE_MASK                       0x30
+#define WCD939X_TX_3_4_TEST_CTL_ADC3_DEM_OPERATION_MASK                  0x0c
+#define WCD939X_TX_3_4_TEST_CTL_SAR_ERR_DET_EN_MASK                      0x02
+#define WCD939X_TX_3_4_TEST_CTL_SAR_EXT_DELAY_EN_MASK                    0x01
+
+/* WCD939X_TEST_BLK_EN3 Fields: */
+#define WCD939X_TEST_BLK_EN3_ADC3_INT1_EN_MASK                           0x80
+#define WCD939X_TEST_BLK_EN3_ADC3_INT2_EN_MASK                           0x40
+#define WCD939X_TEST_BLK_EN3_ADC3_SAR_EN_MASK                            0x20
+#define WCD939X_TEST_BLK_EN3_ADC3_CMGEN_EN_MASK                          0x10
+#define WCD939X_TEST_BLK_EN3_ADC3_CLKGEN_EN_MASK                         0x08
+#define WCD939X_TEST_BLK_EN3_REF_EN_MASK                                 0x04
+#define WCD939X_TEST_BLK_EN3_TXFE3_CLKDIV_EN_MASK                        0x02
+#define WCD939X_TEST_BLK_EN3_TXFE4_CLKDIV_EN_MASK                        0x01
+
+/* WCD939X_TXFE3_CLKDIV Fields: */
+#define WCD939X_TXFE3_CLKDIV_DIV_MASK                                    0xff
+
+/* WCD939X_SAR4_ERR Fields: */
+#define WCD939X_SAR4_ERR_SAR_ERR_COUNT_MASK                              0xff
+
+/* WCD939X_SAR3_ERR Fields: */
+#define WCD939X_SAR3_ERR_SAR_ERR_COUNT_MASK                              0xff
+
+/* WCD939X_TEST_BLK_EN2 Fields: */
+#define WCD939X_TEST_BLK_EN2_ADC2_INT1_EN_MASK                           0x80
+#define WCD939X_TEST_BLK_EN2_ADC2_INT2_EN_MASK                           0x40
+#define WCD939X_TEST_BLK_EN2_ADC2_SAR_EN_MASK                            0x20
+#define WCD939X_TEST_BLK_EN2_ADC2_CMGEN_EN_MASK                          0x10
+#define WCD939X_TEST_BLK_EN2_ADC2_CLKGEN_EN_MASK                         0x08
+#define WCD939X_TEST_BLK_EN2_ADC12_VREF_NONL2_MASK                       0x06
+#define WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN_MASK                   0x01
+
+/* WCD939X_TXFE2_CLKDIV Fields: */
+#define WCD939X_TXFE2_CLKDIV_DIV_MASK                                    0xff
+
+/* WCD939X_TX_3_4_SPARE1 Fields: */
+#define WCD939X_TX_3_4_SPARE1_SPARE_BITS_7_0_MASK                        0xff
+
+/* WCD939X_TEST_BLK_EN4 Fields: */
+#define WCD939X_TEST_BLK_EN4_ADC4_INT1_EN_MASK                           0x80
+#define WCD939X_TEST_BLK_EN4_ADC4_INT2_EN_MASK                           0x40
+#define WCD939X_TEST_BLK_EN4_ADC4_SAR_EN_MASK                            0x20
+#define WCD939X_TEST_BLK_EN4_ADC4_CMGEN_EN_MASK                          0x10
+#define WCD939X_TEST_BLK_EN4_ADC4_CLKGEN_EN_MASK                         0x08
+#define WCD939X_TEST_BLK_EN4_ADC34_VREF_NONL2_MASK                       0x06
+#define WCD939X_TEST_BLK_EN4_SPARE_BITS_0_0_MASK                         0x01
+
+/* WCD939X_TXFE4_CLKDIV Fields: */
+#define WCD939X_TXFE4_CLKDIV_DIV_MASK                                    0xff
+
+/* WCD939X_TX_3_4_SPARE2 Fields: */
+#define WCD939X_TX_3_4_SPARE2_SPARE_BITS_7_0_MASK                        0xff
+
+
+/* WCD939X_MODE_1 Fields: */
+#define WCD939X_MODE_1_BUCK_EN_DELAY_SEL_MASK                            0x60
+#define WCD939X_MODE_1_BUCK_EN_RESET_BY_EXT_MASK                         0x10
+
+/* WCD939X_MODE_2 Fields: */
+#define WCD939X_MODE_2_VREF_I2C_MASK                                     0xff
+
+/* WCD939X_MODE_3 Fields: */
+#define WCD939X_MODE_3_DELTA_IPEAK_2VPK_MASK                             0xf0
+#define WCD939X_MODE_3_DELTA_IPEAK_OVERRIDE_MASK                         0x04
+#define WCD939X_MODE_3_CTRL_VREF_BY_MASK                                 0x02
+#define WCD939X_MODE_3_MANUAL_PWR_OPT_HPH_MASK                           0x01
+
+/* WCD939X_CTRL_VCL_1 Fields: */
+#define WCD939X_CTRL_VCL_1_DELTA_V_SEL_MASK                              0xf0
+#define WCD939X_CTRL_VCL_1_VDD_BUCK_FILT_2VPK_MASK                       0x0c
+#define WCD939X_CTRL_VCL_1_VREF_DELTA_GEN_GAIN_SEL_MASK                  0x03
+
+/* WCD939X_CTRL_VCL_2 Fields: */
+#define WCD939X_CTRL_VCL_2_VDD_BUCK_FILT_MASK                            0xc0
+#define WCD939X_CTRL_VCL_2_VREF_FILT_1_MASK                              0x30
+#define WCD939X_CTRL_VCL_2_VREF_FILT_2_MASK                              0x0e
+
+/* WCD939X_CTRL_CCL_1 Fields: */
+#define WCD939X_CTRL_CCL_1_DELTA_IPEAK_MASK                              0xf0
+#define WCD939X_CTRL_CCL_1_DELTA_IVALLEY_MASK                            0x0f
+
+/* WCD939X_CTRL_CCL_2 Fields: */
+#define WCD939X_CTRL_CCL_2_CHOOSE_I_LIM_MASK                             0xfc
+#define WCD939X_CTRL_CCL_2_BUCK_BYPASS_OVERRIDE_MASK                     0x02
+#define WCD939X_CTRL_CCL_2_BUCK_BYPASS_EN_MASK                           0x01
+
+/* WCD939X_CTRL_CCL_3 Fields: */
+#define WCD939X_CTRL_CCL_3_MIN_PON_MASK                                  0xc0
+#define WCD939X_CTRL_CCL_3_MIN_NON_MASK                                  0x30
+
+/* WCD939X_CTRL_CCL_4 Fields: */
+#define WCD939X_CTRL_CCL_4_P_BLNK_INV1_LOAD_MASK                         0x80
+#define WCD939X_CTRL_CCL_4_P_BLNK_INV2_LOAD_MASK                         0x40
+#define WCD939X_CTRL_CCL_4_N_BLNK_INV1_LOAD_MASK                         0x20
+#define WCD939X_CTRL_CCL_4_N_BLNK_INV2_LOAD_MASK                         0x10
+#define WCD939X_CTRL_CCL_4_RST_PW_INV_LOAD_MASK                          0x02
+#define WCD939X_CTRL_CCL_4_INZ_RST_SW_CTRL_MASK                          0x01
+
+/* WCD939X_CTRL_CCL_5 Fields: */
+#define WCD939X_CTRL_CCL_5_IPK_FRC_RST_MASK                              0xe0
+
+/* WCD939X_BUCK_TMUX_A_D Fields: */
+#define WCD939X_BUCK_TMUX_A_D_ATEST_SEL_MASK                             0x80
+#define WCD939X_BUCK_TMUX_A_D_DTEST_MUX_EN_MASK                          0x08
+#define WCD939X_BUCK_TMUX_A_D_DTEST_BRK_4_BRK_3_BRK_2_BRK_1_MASK         0x07
+
+/* WCD939X_BUCK_SW_DRV_CNTL Fields: */
+#define WCD939X_BUCK_SW_DRV_CNTL_PSW_DRV_CNTL_MASK                       0xf0
+#define WCD939X_BUCK_SW_DRV_CNTL_NSW_DRV_CNTL_MASK                       0x0f
+
+/* WCD939X_SPARE Fields: */
+#define WCD939X_SPARE_CHOOSE_I_LIM_2VPK_MASK                             0xfc
+
+
+/* WCD939X_EN Fields: */
+#define WCD939X_EN_FLYBACK_EN_DELAY_SEL_MASK                             0x60
+#define WCD939X_EN_FLYBACK_EN_RESET_BY_EXT_MASK                          0x10
+#define WCD939X_EN_EN_PWSV_MASK                                          0x08
+#define WCD939X_EN_EN_CUR_DET_MASK                                       0x04
+#define WCD939X_EN_EN_BLEEDER_MASK                                       0x02
+#define WCD939X_EN_VREF_PWR_DAC_SEL_OVERRIDE_MASK                        0x01
+
+/* WCD939X_VNEG_CTRL_1 Fields: */
+#define WCD939X_VNEG_CTRL_1_VREF_DELTA_GEN_LP_MASK                       0xe0
+#define WCD939X_VNEG_CTRL_1_VREF_DELTA_GEN_UHQA_MASK                     0x1c
+#define WCD939X_VNEG_CTRL_1_DRV_PSW_LC_MASK                              0x02
+#define WCD939X_VNEG_CTRL_1_DRV_PSW_HC_MASK                              0x01
+
+/* WCD939X_VNEG_CTRL_2 Fields: */
+#define WCD939X_VNEG_CTRL_2_MIN_PON_MASK                                 0xc0
+#define WCD939X_VNEG_CTRL_2_MIN_NON_MASK                                 0x20
+#define WCD939X_VNEG_CTRL_2_RST_PW_MASK                                  0x10
+#define WCD939X_VNEG_CTRL_2_P_BLNK_MASK                                  0x0c
+#define WCD939X_VNEG_CTRL_2_N_BLNK_MASK                                  0x03
+
+/* WCD939X_VNEG_CTRL_3 Fields: */
+#define WCD939X_VNEG_CTRL_3_EN_IVLY_FRC_RST_MASK                         0x10
+#define WCD939X_VNEG_CTRL_3_IVLY_FRC_RST_MASK                            0x0c
+#define WCD939X_VNEG_CTRL_3_INZ_RDY_CTL_MASK                             0x02
+#define WCD939X_VNEG_CTRL_3_INIT_MINPON_CTL_MASK                         0x01
+
+/* WCD939X_VNEG_CTRL_4 Fields: */
+#define WCD939X_VNEG_CTRL_4_ILIM_SEL_MASK                                0xf0
+#define WCD939X_VNEG_CTRL_4_PW_BUF_POS_MASK                              0x0c
+#define WCD939X_VNEG_CTRL_4_PW_BUF_NEG_MASK                              0x03
+
+/* WCD939X_VNEG_CTRL_5 Fields: */
+#define WCD939X_VNEG_CTRL_5_IPK_DELTA_VNEG_LP_MASK                       0xf0
+#define WCD939X_VNEG_CTRL_5_IPK_DELTA_VNEG_UHQA_MASK                     0x0f
+
+/* WCD939X_VNEG_CTRL_6 Fields: */
+#define WCD939X_VNEG_CTRL_6_VREF_THIGH_POS_MASK                          0xf0
+#define WCD939X_VNEG_CTRL_6_VREF_TLOW_POS_MASK                           0x0f
+
+/* WCD939X_VNEG_CTRL_7 Fields: */
+#define WCD939X_VNEG_CTRL_7_VREF_THIGH_NEG_MASK                          0xf0
+#define WCD939X_VNEG_CTRL_7_VREF_TLOW_NEG_MASK                           0x0f
+
+/* WCD939X_VNEG_CTRL_8 Fields: */
+#define WCD939X_VNEG_CTRL_8_SW_POS_EN_DLY_MASK                           0xc0
+#define WCD939X_VNEG_CTRL_8_SW_NEG_EN_DLY_MASK                           0x30
+#define WCD939X_VNEG_CTRL_8_VNEG_EN_DLY_MASK                             0x0e
+#define WCD939X_VNEG_CTRL_8_EN_IVLYCMP_STATIC_MASK                       0x01
+
+/* WCD939X_VNEG_CTRL_9 Fields: */
+#define WCD939X_VNEG_CTRL_9_CUR_DET_TH_MASK                              0xc0
+#define WCD939X_VNEG_CTRL_9_MAXPON_SEL_MASK                              0x38
+#define WCD939X_VNEG_CTRL_9_EN_MAXPON_FRC_MASK                           0x04
+#define WCD939X_VNEG_CTRL_9_VREF_PWR_DAC_SEL_MASK                        0x02
+
+/* WCD939X_VNEGDAC_CTRL_1 Fields: */
+#define WCD939X_VNEGDAC_CTRL_1_VREF_DAC_DELTA_GEN_LP_MASK                0xe0
+#define WCD939X_VNEGDAC_CTRL_1_VREF_DAC_DELTA_GEN_UHQA_MASK              0x1c
+#define WCD939X_VNEGDAC_CTRL_1_N_BLNK_DAC_MASK                           0x03
+
+/* WCD939X_VNEGDAC_CTRL_2 Fields: */
+#define WCD939X_VNEGDAC_CTRL_2_VREF_DAC_SEL_MASK                         0xe0
+#define WCD939X_VNEGDAC_CTRL_2_VNEGDAC_1P8REF_EN_DLY_MASK                0x18
+#define WCD939X_VNEGDAC_CTRL_2_VREF_BLEEDER_MASK                         0x06
+#define WCD939X_VNEGDAC_CTRL_2_N_ICHRG_BLNK_DAC_MASK                     0x01
+
+/* WCD939X_VNEGDAC_CTRL_3 Fields: */
+#define WCD939X_VNEGDAC_CTRL_3_IPK_DELTA_VNEGDAC_LP_MASK                 0xf0
+#define WCD939X_VNEGDAC_CTRL_3_IPK_DELTA_VNEGDAC_UHQA_MASK               0x0f
+
+/* WCD939X_CTRL_1 Fields: */
+#define WCD939X_CTRL_1_ICHRG_VREF_MASK                                   0xc0
+#define WCD939X_CTRL_1_EN_INZCMP_CTL_1_MASK                              0x20
+#define WCD939X_CTRL_1_EN_INZCMP_CTL_2_MASK                              0x10
+#define WCD939X_CTRL_1_DELTAV_STEP_CTL_MASK                              0x08
+#define WCD939X_CTRL_1_EN_MAXNON_FRC_MASK                                0x04
+#define WCD939X_CTRL_1_MAXNON_SEL_MASK                                   0x03
+
+/* WCD939X_FLYBACK_TEST_CTL Fields: */
+#define WCD939X_FLYBACK_TEST_CTL_DTEST_MUX_SEL_MASK                      0x80
+#define WCD939X_FLYBACK_TEST_CTL_ILIM_SEL_2VPK_MASK                      0x0f
+
+
+/* WCD939X_AUX_SW_CTL Fields: */
+#define WCD939X_AUX_SW_CTL_AUXL_SW_EN_MASK                               0x80
+#define WCD939X_AUX_SW_CTL_AUXR_SW_EN_MASK                               0x40
+#define WCD939X_AUX_SW_CTL_AUXL2R_SW_EN_MASK                             0x20
+
+/* WCD939X_PA_AUX_IN_CONN Fields: */
+#define WCD939X_PA_AUX_IN_CONN_HPHL_AUX_IN_MASK                          0x80
+#define WCD939X_PA_AUX_IN_CONN_HPHR_AUX_IN_MASK                          0x40
+#define WCD939X_PA_AUX_IN_CONN_EAR_AUX_IN_MASK                           0x20
+#define WCD939X_PA_AUX_IN_CONN_SPARE_BITS0_MASK                          0x10
+#define WCD939X_PA_AUX_IN_CONN_SPARE_BITS1_MASK                          0x0e
+#define WCD939X_PA_AUX_IN_CONN_RX_CLK_PHASE_INV_MASK                     0x01
+
+/* WCD939X_TIMER_DIV Fields: */
+#define WCD939X_TIMER_DIV_RX_CLK_DIVIDER_OVWT_MASK                       0x80
+#define WCD939X_TIMER_DIV_RX_CLK_DIVIDER_MASK                            0x7f
+
+/* WCD939X_OCP_CTL Fields: */
+#define WCD939X_OCP_CTL_SPARE_BITS_MASK                                  0xf0
+#define WCD939X_OCP_CTL_N_CONNECTION_ATTEMPTS_MASK                       0x0f
+
+/* WCD939X_OCP_COUNT Fields: */
+#define WCD939X_OCP_COUNT_RUN_N_CYCLES_MASK                              0xf0
+#define WCD939X_OCP_COUNT_WAIT_N_CYCLES_MASK                             0x0f
+
+/* WCD939X_BIAS_EAR_DAC Fields: */
+#define WCD939X_BIAS_EAR_DAC_EAR_DAC_5_UA_MASK                           0xf0
+#define WCD939X_BIAS_EAR_DAC_ATEST_RX_BIAS_MASK                          0x0f
+
+/* WCD939X_BIAS_EAR_AMP Fields: */
+#define WCD939X_BIAS_EAR_AMP_EAR_AMP_10_UA_MASK                          0xf0
+#define WCD939X_BIAS_EAR_AMP_EAR_AMP_5_UA_MASK                           0x0f
+
+/* WCD939X_BIAS_HPH_LDO Fields: */
+#define WCD939X_BIAS_HPH_LDO_HPH_NVLDO2_5_UA_MASK                        0xf0
+#define WCD939X_BIAS_HPH_LDO_HPH_NVLDO1_4P5_UA_MASK                      0x0f
+
+/* WCD939X_BIAS_HPH_PA Fields: */
+#define WCD939X_BIAS_HPH_PA_HPH_CONSTOP_5_UA_MASK                        0xf0
+#define WCD939X_BIAS_HPH_PA_HPH_AMP_5_UA_MASK                            0x0f
+
+/* WCD939X_BIAS_HPH_RDACBUFF_CNP2 Fields: */
+#define WCD939X_BIAS_HPH_RDACBUFF_CNP2_RDAC_BUF_3_UA_MASK                0xf0
+#define WCD939X_BIAS_HPH_RDACBUFF_CNP2_HPH_CNP_10_UA_MASK                0x0f
+
+/* WCD939X_BIAS_HPH_RDAC_LDO Fields: */
+#define WCD939X_BIAS_HPH_RDAC_LDO_RDAC_LDO_1P65_4_UA_MASK                0xf0
+#define WCD939X_BIAS_HPH_RDAC_LDO_RDAC_LDO_N1P65_4_UA_MASK               0x0f
+
+/* WCD939X_BIAS_HPH_CNP1 Fields: */
+#define WCD939X_BIAS_HPH_CNP1_HPH_CNP_4_UA_MASK                          0xf0
+#define WCD939X_BIAS_HPH_CNP1_HPH_CNP_3_UA_MASK                          0x0f
+
+/* WCD939X_BIAS_HPH_LOWPOWER Fields: */
+#define WCD939X_BIAS_HPH_LOWPOWER_HPH_AMP_LP_1P5_UA_MASK                 0xf0
+#define WCD939X_BIAS_HPH_LOWPOWER_RDAC_BUF_LP_0P25_UA_MASK               0x0f
+
+/* WCD939X_BIAS_AUX_DAC Fields: */
+#define WCD939X_BIAS_AUX_DAC_SPARE_BITS0_MASK                            0xf0
+#define WCD939X_BIAS_AUX_DAC_SPARE_BITS1_MASK                            0x0f
+
+/* WCD939X_BIAS_AUX_AMP Fields: */
+#define WCD939X_BIAS_AUX_AMP_SPARE_BITS0_MASK                            0xf0
+#define WCD939X_BIAS_AUX_AMP_SPARE_BITS1_MASK                            0x0f
+
+/* WCD939X_BIAS_VNEGDAC_BLEEDER Fields: */
+#define WCD939X_BIAS_VNEGDAC_BLEEDER_BLEEDER_CTRL_MASK                   0xf0
+
+/* WCD939X_BIAS_MISC Fields: */
+#define WCD939X_BIAS_MISC_SPARE_BITS_MASK                                0xff
+
+/* WCD939X_BIAS_BUCK_RST Fields: */
+#define WCD939X_BIAS_BUCK_RST_BUCK_RST_2_UA_MASK                         0x0f
+
+/* WCD939X_BIAS_BUCK_VREF_ERRAMP Fields: */
+#define WCD939X_BIAS_BUCK_VREF_ERRAMP_BUCK_VREF_1_UA_MASK                0xf0
+#define WCD939X_BIAS_BUCK_VREF_ERRAMP_BUCK_ERRAMP_1_UA_MASK              0x0f
+
+/* WCD939X_BIAS_FLYB_ERRAMP Fields: */
+#define WCD939X_BIAS_FLYB_ERRAMP_FLYB_ERRAMP_1_UA_MASK                   0xf0
+
+/* WCD939X_BIAS_FLYB_BUFF Fields: */
+#define WCD939X_BIAS_FLYB_BUFF_FLYB_VNEG_5_UA_MASK                       0xf0
+#define WCD939X_BIAS_FLYB_BUFF_FLYB_VPOS_5_UA_MASK                       0x0f
+
+/* WCD939X_BIAS_FLYB_MID_RST Fields: */
+#define WCD939X_BIAS_FLYB_MID_RST_FLYB_MID_1_UA_MASK                     0xf0
+#define WCD939X_BIAS_FLYB_MID_RST_FLYB_RST_1_UA_MASK                     0x0f
+
+
+/* WCD939X_L_STATUS Fields: */
+#define WCD939X_L_STATUS_CMPDR_GAIN_MASK                                 0xf8
+#define WCD939X_L_STATUS_OCP_COMP_DETECT_MASK                            0x04
+#define WCD939X_L_STATUS_OCP_LIMIT_MASK                                  0x02
+#define WCD939X_L_STATUS_PA_READY_MASK                                   0x01
+
+/* WCD939X_R_STATUS Fields: */
+#define WCD939X_R_STATUS_CMPDR_GAIN_MASK                                 0xf8
+#define WCD939X_R_STATUS_OCP_COMP_DETECT_MASK                            0x04
+#define WCD939X_R_STATUS_OCP_LIMIT_MASK                                  0x02
+#define WCD939X_R_STATUS_PA_READY_MASK                                   0x01
+
+/* WCD939X_CNP_EN Fields: */
+#define WCD939X_CNP_EN_FSM_CLK_EN_MASK                                   0x80
+#define WCD939X_CNP_EN_FSM_RESET_MASK                                    0x40
+#define WCD939X_CNP_EN_CNP_IREF_SEL_MASK                                 0x20
+#define WCD939X_CNP_EN_FSM_OVERRIDE_EN_MASK                              0x08
+#define WCD939X_CNP_EN_WG_LR_SEL_MASK                                    0x04
+#define WCD939X_CNP_EN_DBG_CURR_DIRECTION_R_MASK                         0x02
+#define WCD939X_CNP_EN_DBG_VREF_EN_MASK                                  0x01
+
+/* WCD939X_CNP_WG_CTL Fields: */
+#define WCD939X_CNP_WG_CTL_GM3_BOOST_EN_MASK                             0x80
+#define WCD939X_CNP_WG_CTL_NO_PD_SEQU_MASK                               0x40
+#define WCD939X_CNP_WG_CTL_VREF_TIMER_MASK                               0x38
+#define WCD939X_CNP_WG_CTL_CURR_LDIV_CTL_MASK                            0x07
+
+/* WCD939X_CNP_WG_TIME Fields: */
+#define WCD939X_CNP_WG_TIME_WG_FINE_TIMER_MASK                           0xff
+
+/* WCD939X_HPH_OCP_CTL Fields: */
+#define WCD939X_HPH_OCP_CTL_OCP_CURR_LIMIT_MASK                          0xe0
+#define WCD939X_HPH_OCP_CTL_OCP_FSM_EN_MASK                              0x10
+#define WCD939X_HPH_OCP_CTL_SPARE_BITS_MASK                              0x08
+#define WCD939X_HPH_OCP_CTL_SCD_OP_EN_MASK                               0x02
+
+/* WCD939X_AUTO_CHOP Fields: */
+#define WCD939X_AUTO_CHOP_GM3_CASCODE_CTL_2VPK_MASK                      0xc0
+#define WCD939X_AUTO_CHOP_AUTO_CHOPPER_MODE_MASK                         0x20
+#define WCD939X_AUTO_CHOP_GAIN_THRESHOLD_MASK                            0x1f
+
+/* WCD939X_CHOP_CTL Fields: */
+#define WCD939X_CHOP_CTL_CHOPPER_EN_MASK                                 0x80
+#define WCD939X_CHOP_CTL_CLK_INV_MASK                                    0x40
+#define WCD939X_CHOP_CTL_SPARE_BITS_MASK                                 0x38
+#define WCD939X_CHOP_CTL_DIV2_DIV_BY_2_MASK                              0x04
+#define WCD939X_CHOP_CTL_DIV2_DIV_BY_2_4_6_8_MASK                        0x03
+
+/* WCD939X_PA_CTL1 Fields: */
+#define WCD939X_PA_CTL1_GM3_IBIAS_CTL_MASK                               0xf0
+#define WCD939X_PA_CTL1_GM3_IB_SCALE_MASK                                0x0e
+#define WCD939X_PA_CTL1_SPARE_BITS_MASK                                  0x01
+
+/* WCD939X_PA_CTL2 Fields: */
+#define WCD939X_PA_CTL2_SPARE_BITS0_MASK                                 0x80
+#define WCD939X_PA_CTL2_HPHPA_GND_R_MASK                                 0x40
+#define WCD939X_PA_CTL2_SPARE_BITS1_MASK                                 0x20
+#define WCD939X_PA_CTL2_HPHPA_GND_L_MASK                                 0x10
+#define WCD939X_PA_CTL2_SPARE_BITS2_MASK                                 0x0c
+#define WCD939X_PA_CTL2_GM3_CASCODE_CTL_NORMAL_MASK                      0x03
+
+/* WCD939X_L_EN Fields: */
+#define WCD939X_L_EN_CONST_SEL_L_MASK                                    0xc0
+#define WCD939X_L_EN_GAIN_SOURCE_SEL_MASK                                0x20
+#define WCD939X_L_EN_SPARE_BITS_MASK                                     0x1f
+
+/* WCD939X_L_TEST Fields: */
+#define WCD939X_L_TEST_PDN_EN_MASK                                       0x80
+#define WCD939X_L_TEST_PDN_AMP2_EN_MASK                                  0x40
+#define WCD939X_L_TEST_PDN_AMP_EN_MASK                                   0x20
+#define WCD939X_L_TEST_PA_CNP_SW_CONN_MASK                               0x10
+#define WCD939X_L_TEST_PA_CNP_SW_OFF_MASK                                0x08
+#define WCD939X_L_TEST_PA_CNP_SW_ON_MASK                                 0x04
+#define WCD939X_L_TEST_SPARE_BITS_MASK                                   0x02
+#define WCD939X_L_TEST_OCP_DET_EN_MASK                                   0x01
+
+/* WCD939X_L_ATEST Fields: */
+#define WCD939X_L_ATEST_DACL_REF_ATEST1_CONN_MASK                        0x80
+#define WCD939X_L_ATEST_LDO1_L_ATEST2_CONN_MASK                          0x40
+#define WCD939X_L_ATEST_LDO_L_ATEST2_CAL_MASK                            0x20
+#define WCD939X_L_ATEST_LDO2_L_ATEST2_CONN_MASK                          0x10
+#define WCD939X_L_ATEST_HPHPA_GND_OVR_MASK                               0x08
+#define WCD939X_L_ATEST_SPARE_BITS_MASK                                  0x04
+#define WCD939X_L_ATEST_CNP_EXD2_MASK                                    0x02
+#define WCD939X_L_ATEST_CNP_EXD1_MASK                                    0x01
+
+/* WCD939X_R_EN Fields: */
+#define WCD939X_R_EN_CONST_SEL_R_MASK                                    0xc0
+#define WCD939X_R_EN_GAIN_SOURCE_SEL_MASK                                0x20
+#define WCD939X_R_EN_SPARE_BITS_MASK                                     0x1f
+
+/* WCD939X_R_TEST Fields: */
+#define WCD939X_R_TEST_PDN_EN_MASK                                       0x80
+#define WCD939X_R_TEST_PDN_AMP2_EN_MASK                                  0x40
+#define WCD939X_R_TEST_PDN_AMP_EN_MASK                                   0x20
+#define WCD939X_R_TEST_PA_CNP_SW_CONN_MASK                               0x10
+#define WCD939X_R_TEST_PA_CNP_SW_OFF_MASK                                0x08
+#define WCD939X_R_TEST_PA_CNP_SW_ON_MASK                                 0x04
+#define WCD939X_R_TEST_SPARE_BITS_MASK                                   0x02
+#define WCD939X_R_TEST_OCP_DET_EN_MASK                                   0x01
+
+/* WCD939X_R_ATEST Fields: */
+#define WCD939X_R_ATEST_DACR_REF_ATEST1_CONN_MASK                        0x80
+#define WCD939X_R_ATEST_LDO1_R_ATEST2_CONN_MASK                          0x40
+#define WCD939X_R_ATEST_LDO_R_ATEST2_CAL_MASK                            0x20
+#define WCD939X_R_ATEST_LDO2_R_ATEST2_CONN_MASK                          0x10
+#define WCD939X_R_ATEST_LDO_1P65V_ATEST1_CONN_MASK                       0x08
+#define WCD939X_R_ATEST_SPARE_BITS0_MASK                                 0x04
+#define WCD939X_R_ATEST_HPH_GND_OVR_MASK                                 0x02
+#define WCD939X_R_ATEST_SPARE_BITS1_MASK                                 0x01
+
+/* WCD939X_RDAC_CLK_CTL1 Fields: */
+#define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK                     0x80
+#define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_DIV_CTRL_MASK               0x70
+#define WCD939X_RDAC_CLK_CTL1_SPARE_BITS_MASK                            0x0f
+
+/* WCD939X_RDAC_CLK_CTL2 Fields: */
+#define WCD939X_RDAC_CLK_CTL2_SPARE_BITS_MASK                            0xf0
+#define WCD939X_RDAC_CLK_CTL2_PREREF_SC_CLK_EN_MASK                      0x08
+#define WCD939X_RDAC_CLK_CTL2_PREREF_SC_CLK_DIVIDER_CTRL_MASK            0x07
+
+/* WCD939X_RDAC_LDO_CTL Fields: */
+#define WCD939X_RDAC_LDO_CTL_LDO_1P65_BYPASS_MASK                        0x80
+#define WCD939X_RDAC_LDO_CTL_LDO_1P65_OUTCTL_MASK                        0x70
+#define WCD939X_RDAC_LDO_CTL_N1P65V_LDO_BYPASS_MASK                      0x08
+#define WCD939X_RDAC_LDO_CTL_N1P65_LDO_OUTCTL_MASK                       0x07
+
+/* WCD939X_RDAC_CHOP_CLK_LP_CTL Fields: */
+#define WCD939X_RDAC_CHOP_CLK_LP_CTL_OPAMP_CHOP_CLK_EN_LP_MASK           0x80
+#define WCD939X_RDAC_CHOP_CLK_LP_CTL_SPARE_BITS_MASK                     0x7f
+
+/* WCD939X_REFBUFF_UHQA_CTL Fields: */
+#define WCD939X_REFBUFF_UHQA_CTL_SPARE_BITS_MASK                         0xc0
+#define WCD939X_REFBUFF_UHQA_CTL_HPH_VNEGREG2_COMP_CTL_OV_MASK           0x20
+#define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_RBIAS_ADJUST_MASK               0x10
+#define WCD939X_REFBUFF_UHQA_CTL_REFBUFP_IOUT_CTL_MASK                   0x0c
+#define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_IOUT_CTL_MASK                   0x03
+
+/* WCD939X_REFBUFF_LP_CTL Fields: */
+#define WCD939X_REFBUFF_LP_CTL_HPH_VNEGREG2_CURR_COMP_MASK               0xc0
+#define WCD939X_REFBUFF_LP_CTL_SPARE_BITS_MASK                           0x30
+#define WCD939X_REFBUFF_LP_CTL_EN_PREREF_FILT_STARTUP_CLKDIV_MASK        0x08
+#define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_STARTUP_CLKDIV_CTL_MASK       0x06
+#define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS_MASK                   0x01
+
+/* WCD939X_L_DAC_CTL Fields: */
+#define WCD939X_L_DAC_CTL_SPARE_BITS_MASK                                0x80
+#define WCD939X_L_DAC_CTL_DAC_REF_EN_MASK                                0x40
+#define WCD939X_L_DAC_CTL_DAC_SAMPLE_EDGE_SELECT_MASK                    0x20
+#define WCD939X_L_DAC_CTL_DATA_RESET_MASK                                0x10
+#define WCD939X_L_DAC_CTL_INV_DATA_MASK                                  0x08
+#define WCD939X_L_DAC_CTL_DAC_L_EN_OV_MASK                               0x04
+#define WCD939X_L_DAC_CTL_DAC_LDO_UHQA_OV_MASK                           0x02
+#define WCD939X_L_DAC_CTL_DAC_LDO_POWERMODE_MASK                         0x01
+
+/* WCD939X_R_DAC_CTL Fields: */
+#define WCD939X_R_DAC_CTL_SPARE_BITS_MASK                                0x80
+#define WCD939X_R_DAC_CTL_DAC_REF_EN_MASK                                0x40
+#define WCD939X_R_DAC_CTL_DAC_SAMPLE_EDGE_SELECT_MASK                    0x20
+#define WCD939X_R_DAC_CTL_DATA_RESET_MASK                                0x10
+#define WCD939X_R_DAC_CTL_INV_DATA_MASK                                  0x08
+#define WCD939X_R_DAC_CTL_DAC_R_EN_OV_MASK                               0x04
+#define WCD939X_R_DAC_CTL_DAC_PREREF_UHQA_OV_MASK                        0x02
+#define WCD939X_R_DAC_CTL_DAC_PREREF_POWERMODE_MASK                      0x01
+
+
+/* WCD939X_HPHLR_SURGE_COMP_SEL Fields: */
+#define WCD939X_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHL_PSURGE_MASK       0xc0
+#define WCD939X_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHL_NSURGE_MASK       0x30
+#define WCD939X_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHR_PSURGE_MASK       0x0c
+#define WCD939X_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHR_NSURGE_MASK       0x03
+
+/* WCD939X_HPHLR_SURGE_EN Fields: */
+#define WCD939X_HPHLR_SURGE_EN_EN_SURGE_PROTECTION_HPHL_MASK             0x80
+#define WCD939X_HPHLR_SURGE_EN_EN_SURGE_PROTECTION_HPHR_MASK             0x40
+#define WCD939X_HPHLR_SURGE_EN_SEL_SURGE_COMP_IQ_MASK                    0x30
+#define WCD939X_HPHLR_SURGE_EN_SURGE_VOLT_MODE_SHUTOFF_EN_MASK           0x08
+#define WCD939X_HPHLR_SURGE_EN_LATCH_INTR_OP_STG_HIZ_EN_MASK             0x04
+#define WCD939X_HPHLR_SURGE_EN_SURGE_LATCH_REG_RESET_MASK                0x02
+#define WCD939X_HPHLR_SURGE_EN_SWTICH_VN_VNDAC_NSURGE_EN_MASK            0x01
+
+/* WCD939X_HPHLR_SURGE_MISC1 Fields: */
+#define WCD939X_HPHLR_SURGE_MISC1_EN_VNEG_PULLDN_MASK                    0x80
+#define WCD939X_HPHLR_SURGE_MISC1_EN_OFFSET_36MV_NSURGE_RESLADDER_MASK   0x40
+#define WCD939X_HPHLR_SURGE_MISC1_EN_NMOS_LAMP_MASK                      0x20
+#define WCD939X_HPHLR_SURGE_MISC1_EN_NCLAMP_REG_HPHL_MASK                0x10
+#define WCD939X_HPHLR_SURGE_MISC1_EN_NCLAMP_REG_HPHR_MASK                0x08
+#define WCD939X_HPHLR_SURGE_MISC1_SPARE_BITS_MASK                        0x07
+
+/* WCD939X_HPHLR_SURGE_STATUS Fields: */
+#define WCD939X_HPHLR_SURGE_STATUS_HPHL_CLAMP_SW_STATUS_MASK             0x80
+#define WCD939X_HPHLR_SURGE_STATUS_HPHR_CLAMP_SW_STATUS_MASK             0x40
+#define WCD939X_HPHLR_SURGE_STATUS_HPHL_PSURGE_COMP_STATUS_MASK          0x20
+#define WCD939X_HPHLR_SURGE_STATUS_HPHL_NSURGE_COMP_STATUS_MASK          0x10
+#define WCD939X_HPHLR_SURGE_STATUS_HPHR_PSURGE_COMP_STATUS_MASK          0x08
+#define WCD939X_HPHLR_SURGE_STATUS_HPHR_NSURGE_COMP_STATUS_MASK          0x04
+#define WCD939X_HPHLR_SURGE_STATUS_HPHL_SURGE_DET_INTR_EN_MASK           0x02
+#define WCD939X_HPHLR_SURGE_STATUS_HPHR_SURGE_DET_INTR_EN_MASK           0x01
+
+
+/* WCD939X_EAR_EN_REG Fields: */
+#define WCD939X_EAR_EN_REG_EAR_DAC_DATA_RESET_MASK                       0x80
+#define WCD939X_EAR_EN_REG_EAR_DAC_DATA_EN_MASK                          0x40
+#define WCD939X_EAR_EN_REG_EAR_DAC_REF_EN_MASK                           0x20
+#define WCD939X_EAR_EN_REG_EAR_VCM_EN_MASK                               0x10
+#define WCD939X_EAR_EN_REG_EAR_AMP_EN_MASK                               0x08
+#define WCD939X_EAR_EN_REG_EAR_BIAS_EN_MASK                              0x04
+#define WCD939X_EAR_EN_REG_EAR_CNP_FSM_EN_MASK                           0x02
+#define WCD939X_EAR_EN_REG_EAR_OUTPUT_SHORT_MASK                         0x01
+
+/* WCD939X_EAR_PA_CON Fields: */
+#define WCD939X_EAR_PA_CON_EAR_ANA_AUX_EN_MASK                           0x80
+#define WCD939X_EAR_PA_CON_EAR_CMFB_SF_BYPASS_MASK                       0x40
+#define WCD939X_EAR_PA_CON_EAR_SF_CURR_MASK                              0x20
+#define WCD939X_EAR_PA_CON_EAR_BTI_CTL_MASK                              0x10
+#define WCD939X_EAR_PA_CON_EAR_GM3_IBIAS_CTL_MASK                        0x0f
+
+/* WCD939X_EAR_SP_CON Fields: */
+#define WCD939X_EAR_SP_CON_EAR_SP_INT_EN_MASK                            0x80
+#define WCD939X_EAR_SP_CON_EAR_SP_AUTO_SHT_DWN_MASK                      0x40
+#define WCD939X_EAR_SP_CON_SP_LIMIT_CURR_NMOS_MASK                       0x38
+#define WCD939X_EAR_SP_CON_SP_LIMIT_CURR_PMOS_MASK                       0x07
+
+/* WCD939X_EAR_DAC_CON Fields: */
+#define WCD939X_EAR_DAC_CON_DAC_SAMPLE_EDGE_SEL_MASK                     0x80
+#define WCD939X_EAR_DAC_CON_REF_DBG_EN_MASK                              0x40
+#define WCD939X_EAR_DAC_CON_REF_DBG_GAIN_MASK                            0x38
+#define WCD939X_EAR_DAC_CON_GAIN_DAC_MASK                                0x06
+#define WCD939X_EAR_DAC_CON_INV_DATA_MASK                                0x01
+
+/* WCD939X_EAR_CNP_FSM_CON Fields: */
+#define WCD939X_EAR_CNP_FSM_CON_CNP_FSM_CLK_DIV1_MASK                    0xf0
+#define WCD939X_EAR_CNP_FSM_CON_CNP_FSM_CLK_DIV2_MASK                    0x0c
+#define WCD939X_EAR_CNP_FSM_CON_SCD_FSM_DEGLITCH_SEL_MASK                0x03
+
+/* WCD939X_EAR_TEST_CTL Fields: */
+#define WCD939X_EAR_TEST_CTL_DTEST_EN_MASK                               0x80
+#define WCD939X_EAR_TEST_CTL_DTEST_SEL_2_MASK                            0x40
+#define WCD939X_EAR_TEST_CTL_EAR_RDAC_ATEST_EN_MASK                      0x20
+#define WCD939X_EAR_TEST_CTL_EAR_PA_ATEST_SEL_MASK                       0x1f
+
+/* WCD939X_STATUS_REG_1 Fields: */
+#define WCD939X_STATUS_REG_1_SP_INT_MASK                                 0x80
+#define WCD939X_STATUS_REG_1_SP_ALL_OUT_MASK                             0x40
+#define WCD939X_STATUS_REG_1_SP_NMOS_OUT_MASK                            0x20
+#define WCD939X_STATUS_REG_1_SP_PMOS_OUT_MASK                            0x10
+#define WCD939X_STATUS_REG_1_PA_READY_MASK                               0x08
+#define WCD939X_STATUS_REG_1_CNP_FSM_STATUS_MASK                         0x04
+
+/* WCD939X_STATUS_REG_2 Fields: */
+#define WCD939X_STATUS_REG_2_PA_EN_MASK                                  0x80
+#define WCD939X_STATUS_REG_2_BIAS_EN_MASK                                0x40
+#define WCD939X_STATUS_REG_2_DAC_EN_MASK                                 0x20
+#define WCD939X_STATUS_REG_2_VCM_EN_MASK                                 0x10
+#define WCD939X_STATUS_REG_2_CLK_EN_MASK                                 0x08
+#define WCD939X_STATUS_REG_2_SCD_EN_MASK                                 0x04
+#define WCD939X_STATUS_REG_2_SHORT_EN_MASK                               0x02
+#define WCD939X_STATUS_REG_2_DAC_RESET_MASK                              0x01
+
+
+/* WCD939X_ANA_NEW_PAGE Fields: */
+#define WCD939X_ANA_NEW_PAGE_VALUE_MASK                                  0xff
+
+
+/* WCD939X_ANA_HPH2 Fields: */
+#define WCD939X_ANA_HPH2_HIFI_2VPK_PA_GAIN_CTL_MASK                      0x80
+#define WCD939X_ANA_HPH2_ULP_VREF_CTL_MASK                               0x40
+#define WCD939X_ANA_HPH2_SPARE_BITS_MASK                                 0x3f
+
+/* WCD939X_ANA_HPH3 Fields: */
+#define WCD939X_ANA_HPH3_SPARE_BITS_MASK                                 0xff
+
+
+/* WCD939X_SLEEP_CTL Fields: */
+#define WCD939X_SLEEP_CTL_SPARE_BITS_MASK                                0x80
+#define WCD939X_SLEEP_CTL_LDOL_BG_SEL_MASK                               0x10
+#define WCD939X_SLEEP_CTL_BG_CTL_MASK                                    0x0e
+#define WCD939X_SLEEP_CTL_DTEST_EN_MASK                                  0x01
+
+/* WCD939X_WATCHDOG_CTL Fields: */
+#define WCD939X_WATCHDOG_CTL_EN_WATCHDOG_MASK                            0x80
+#define WCD939X_WATCHDOG_CTL_EN_WATCHDOG_VREFGEN_MASK                    0x40
+#define WCD939X_WATCHDOG_CTL_BYPASS_WATCHDOG_MASK                        0x20
+#define WCD939X_WATCHDOG_CTL_ATEST_CTL_MASK                              0x1c
+
+
+/* WCD939X_ELECT_REM_CLAMP_CTL Fields: */
+#define WCD939X_ELECT_REM_CLAMP_CTL_FSM_ELECT_CLAMP_EN_MASK              0x80
+#define WCD939X_ELECT_REM_CLAMP_CTL_SLNQ_ELECT_CLAMP_EN_MASK             0x40
+#define WCD939X_ELECT_REM_CLAMP_CTL_SLNQ_FAIL_CLAMP_EN_MASK              0x20
+#define WCD939X_ELECT_REM_CLAMP_CTL_SLNQ_ELECT_REM_RST_MASK              0x10
+
+/* WCD939X_CTL_1 Fields: */
+#define WCD939X_CTL_1_RCO_EN_MASK                                        0x80
+#define WCD939X_CTL_1_ADC_MODE_MASK                                      0x10
+#define WCD939X_CTL_1_ADC_ENABLE_MASK                                    0x08
+#define WCD939X_CTL_1_DETECTION_DONE_MASK                                0x04
+#define WCD939X_CTL_1_BTN_DBNC_CTL_MASK                                  0x03
+
+/* WCD939X_CTL_2 Fields: */
+#define WCD939X_CTL_2_MUX_CTL_MASK                                       0x70
+#define WCD939X_CTL_2_M_RTH_CTL_MASK                                     0x0c
+#define WCD939X_CTL_2_HS_VREF_CTL_MASK                                   0x03
+
+/* WCD939X_PLUG_DETECT_CTL Fields: */
+#define WCD939X_PLUG_DETECT_CTL_SPARE_BITS_7_6_MASK                      0xc0
+#define WCD939X_PLUG_DETECT_CTL_MIC_CLAMP_CTL_MASK                       0x30
+#define WCD939X_PLUG_DETECT_CTL_INSREM_DBNC_CTL_MASK                     0x0f
+
+/* WCD939X_ZDET_ANA_CTL Fields: */
+#define WCD939X_ZDET_ANA_CTL_AVERAGING_EN_MASK                           0x80
+#define WCD939X_ZDET_ANA_CTL_ZDET_MAXV_CTL_MASK                          0x70
+#define WCD939X_ZDET_ANA_CTL_ZDET_RANGE_CTL_MASK                         0x0f
+
+/* WCD939X_ZDET_RAMP_CTL Fields: */
+#define WCD939X_ZDET_RAMP_CTL_ZDET_ACC1_MIN_CTL_MASK                     0x70
+#define WCD939X_ZDET_RAMP_CTL_ZDET_RAMP_TIME_CTL_MASK                    0x0f
+
+/* WCD939X_FSM_STATUS Fields: */
+#define WCD939X_FSM_STATUS_ADC_TIMEOUT_MASK                              0x80
+#define WCD939X_FSM_STATUS_ADC_COMPLETE_MASK                             0x40
+#define WCD939X_FSM_STATUS_HS_M_COMP_STATUS_MASK                         0x20
+#define WCD939X_FSM_STATUS_FAST_PRESS_FLAG_STATUS_MASK                   0x10
+#define WCD939X_FSM_STATUS_FAST_REMOVAL_FLAG_STATUS_MASK                 0x08
+#define WCD939X_FSM_STATUS_REMOVAL_FLAG_STATUS_MASK                      0x04
+#define WCD939X_FSM_STATUS_ELECT_REM_RT_STATUS_MASK                      0x02
+#define WCD939X_FSM_STATUS_BTN_STATUS_MASK                               0x01
+
+/* WCD939X_ADC_RESULT Fields: */
+#define WCD939X_ADC_RESULT_ADC_RESULT_MASK                               0xff
+
+
+/* WCD939X_TX_CH12_MUX Fields: */
+#define WCD939X_TX_CH12_MUX_SPARE_BITS_MASK                              0xc0
+#define WCD939X_TX_CH12_MUX_CH2_SEL_MASK                                 0x38
+#define WCD939X_TX_CH12_MUX_CH1_SEL_MASK                                 0x07
+
+/* WCD939X_TX_CH34_MUX Fields: */
+#define WCD939X_TX_CH34_MUX_SPARE_BITS_MASK                              0xc0
+#define WCD939X_TX_CH34_MUX_CH4_SEL_MASK                                 0x38
+#define WCD939X_TX_CH34_MUX_CH3_SEL_MASK                                 0x07
+
+
+/* WCD939X_DIE_CRK_DET_EN Fields: */
+#define WCD939X_DIE_CRK_DET_EN_DIE_CRK_DET_EN_MASK                       0x80
+#define WCD939X_DIE_CRK_DET_EN_SEL_CURR_INJCT_PT_MRING_MASK              0x40
+
+/* WCD939X_DIE_CRK_DET_OUT Fields: */
+#define WCD939X_DIE_CRK_DET_OUT_DIE_CRK_DET_OUT_MASK                     0x80
+
+
+/* WCD939X_RDAC_GAIN_CTL Fields: */
+#define WCD939X_RDAC_GAIN_CTL_SPARE_BITS_MASK                            0xff
+
+/* WCD939X_PA_GAIN_CTL_L Fields: */
+#define WCD939X_PA_GAIN_CTL_L_EN_HPHPA_2VPK_MASK                         0x80
+#define WCD939X_PA_GAIN_CTL_L_RX_SUPPLY_LEVEL_MASK                       0x40
+#define WCD939X_PA_GAIN_CTL_L_DAC_DR_BOOST_MASK                          0x20
+#define WCD939X_PA_GAIN_CTL_L_PA_GAIN_L_MASK                             0x1f
+
+/* WCD939X_RDAC_VREF_CTL Fields: */
+#define WCD939X_RDAC_VREF_CTL_DAC_REF_EFUSE_TUNE_EN_MASK                 0x80
+#define WCD939X_RDAC_VREF_CTL_DAC_VREFN_TUNE_MASK                        0x70
+#define WCD939X_RDAC_VREF_CTL_REFCURRENT_2UA_MASK                        0x08
+#define WCD939X_RDAC_VREF_CTL_DAC_VREFP_TUNE_MASK                        0x07
+
+/* WCD939X_RDAC_OVERRIDE_CTL Fields: */
+#define WCD939X_RDAC_OVERRIDE_CTL_VDDRX_LDO_LIFT_BYPASS_MASK             0x80
+#define WCD939X_RDAC_OVERRIDE_CTL_REFBUF_IREF_OVRIDE_MASK                0x40
+#define WCD939X_RDAC_OVERRIDE_CTL_SPARE_BITS1_MASK                       0x30
+#define WCD939X_RDAC_OVERRIDE_CTL_RDAC_IDLE_DETECT_OVERRIDE_MASK         0x08
+#define WCD939X_RDAC_OVERRIDE_CTL_SPARE_BITS2_MASK                       0x07
+
+/* WCD939X_PA_GAIN_CTL_R Fields: */
+#define WCD939X_PA_GAIN_CTL_R_D_RCO_CLK_EN_MASK                          0x80
+#define WCD939X_PA_GAIN_CTL_R_SPARE_BITS_MASK                            0x60
+#define WCD939X_PA_GAIN_CTL_R_PA_GAIN_R_MASK                             0x1f
+
+/* WCD939X_PA_MISC1 Fields: */
+#define WCD939X_PA_MISC1_EN_AUTO_CMPDR_DETECTION_MASK                    0x80
+#define WCD939X_PA_MISC1_EN_PA_IDLE_DETECT_OVERRIDE_MASK                 0x40
+#define WCD939X_PA_MISC1_D_PZ_INF_EN_MASK                                0x20
+#define WCD939X_PA_MISC1_HPHPA_BW_PROG_MASK                              0x18
+#define WCD939X_PA_MISC1_PA_CHOP_EN_OVERRIDE_MASK                        0x04
+#define WCD939X_PA_MISC1_OCP_FSM_LOCK_EN_MASK                            0x02
+#define WCD939X_PA_MISC1_AUTOCHOP_PDN_SEQ_OVERRIDE_MASK                  0x01
+
+/* WCD939X_PA_MISC2 Fields: */
+#define WCD939X_PA_MISC2_HPHPA_HI_Z_MASK                                 0x80
+#define WCD939X_PA_MISC2_HPH_PSRR_ENH_MASK                               0x40
+#define WCD939X_PA_MISC2_FORCE_IQCTRL_MASK                               0x20
+#define WCD939X_PA_MISC2_FORCE_PSRREH_MASK                               0x10
+#define WCD939X_PA_MISC2_CHOP_CLKLAP_SEL_MASK                            0x08
+#define WCD939X_PA_MISC2_SPARE_BITS_MASK                                 0x04
+#define WCD939X_PA_MISC2_IDLE_DETECT_L_DTEST_ENABLE_MASK                 0x02
+#define WCD939X_PA_MISC2_IDLE_DETECT_R_DTEST_ENABLE_MASK                 0x01
+
+/* WCD939X_PA_RDAC_MISC Fields: */
+#define WCD939X_PA_RDAC_MISC_CNP_WG_FINE_TIME_LSB_CTL_MASK               0xf0
+#define WCD939X_PA_RDAC_MISC_RDAC_NSW_REG_CTL_MASK                       0x08
+#define WCD939X_PA_RDAC_MISC_RDAC_PSW_NSW_CTL_OVERRIDE_MASK              0x04
+#define WCD939X_PA_RDAC_MISC_RDAC_PSW_NSW_REG_CTL_MASK                   0x03
+
+/* WCD939X_HPH_TIMER1 Fields: */
+#define WCD939X_HPH_TIMER1_CURR_IDIV_CTL_CMPDR_OFF_MASK                  0xe0
+#define WCD939X_HPH_TIMER1_CURR_IDIV_CTL_AUTOCHOP_MASK                   0x1c
+#define WCD939X_HPH_TIMER1_AUTOCHOP_TIMER_CTL_EN_MASK                    0x02
+#define WCD939X_HPH_TIMER1_SPARE_BITS_MASK                               0x01
+
+/* WCD939X_HPH_TIMER2 Fields: */
+#define WCD939X_HPH_TIMER2_VREF_TIMER_IDLESTATE_MASK                     0xe0
+#define WCD939X_HPH_TIMER2_CNP_WG_FINE_TIME_LSB_CTL_IDLE_MASK            0x1e
+#define WCD939X_HPH_TIMER2_SPARE_BITS_MASK                               0x01
+
+/* WCD939X_HPH_TIMER3 Fields: */
+#define WCD939X_HPH_TIMER3_WG_FINE_TIMER_CMPDR_OFF_MASK                  0xff
+
+/* WCD939X_HPH_TIMER4 Fields: */
+#define WCD939X_HPH_TIMER4_WG_FINE_TIMER_AUTOCHOP_MASK                   0xff
+
+/* WCD939X_PA_RDAC_MISC2 Fields: */
+#define WCD939X_PA_RDAC_MISC2_SPARE_BITS_MASK                            0xe0
+#define WCD939X_PA_RDAC_MISC2_RDAC_DNW_RES_FORCE_BYPASS_MASK             0x10
+#define WCD939X_PA_RDAC_MISC2_SCLPF_BYPASS_TIMER_STG1_MASK               0x0c
+#define WCD939X_PA_RDAC_MISC2_SCLPF_BYPASS_TIMER_STG2_MASK               0x03
+
+/* WCD939X_PA_RDAC_MISC3 Fields: */
+#define WCD939X_PA_RDAC_MISC3_SPARE_BITS_MASK                            0xff
+
+/* WCD939X_RDAC_HD2_CTL_L Fields: */
+#define WCD939X_RDAC_HD2_CTL_L_EN_HD2_RES_DIV_L_MASK                     0x80
+#define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_PULLGND_L_MASK                0x40
+#define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK                    0x3f
+
+/* WCD939X_RDAC_HD2_CTL_R Fields: */
+#define WCD939X_RDAC_HD2_CTL_R_EN_HD2_RES_DIV_R_MASK                     0x80
+#define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_PULLGND_L_MASK                0x40
+#define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK                    0x3f
+
+
+/* WCD939X_HPH_RDAC_BIAS_LOHIFI Fields: */
+#define WCD939X_HPH_RDAC_BIAS_LOHIFI_HPHPA_BIAS_LOHIFI_MASK              0xf0
+#define WCD939X_HPH_RDAC_BIAS_LOHIFI_HPHRDAC_BIAS_LOHIFI_MASK            0x0f
+
+/* WCD939X_HPH_RDAC_BIAS_ULP Fields: */
+#define WCD939X_HPH_RDAC_BIAS_ULP_SLEEPBG_PWR_SEL_MASK                   0x80
+#define WCD939X_HPH_RDAC_BIAS_ULP_SLEEPBG_PWR_SEL_OVERRIDE_MASK          0x40
+#define WCD939X_HPH_RDAC_BIAS_ULP_CDC_3P5MM_LEGACY_IN_MASK               0x20
+#define WCD939X_HPH_RDAC_BIAS_ULP_SPARE_BITS1_MASK                       0x10
+#define WCD939X_HPH_RDAC_BIAS_ULP_HPHRDAC_BIAS_ULP_MASK                  0x0f
+
+/* WCD939X_HPH_RDAC_LDO_LP Fields: */
+#define WCD939X_HPH_RDAC_LDO_LP_HPHRDAC_1P6VLDO_BIAS_LP_MASK             0xf0
+#define WCD939X_HPH_RDAC_LDO_LP_HPHRDAC_N1P6VLDO_BIAS_LP_MASK            0x0f
+
+
+/* WCD939X_MOISTURE_DET_DC_CTRL Fields: */
+#define WCD939X_MOISTURE_DET_DC_CTRL_ONCOUNT_MASK                        0x60
+#define WCD939X_MOISTURE_DET_DC_CTRL_OFFCOUNT_MASK                       0x1f
+
+/* WCD939X_MOISTURE_DET_POLLING_CTRL Fields: */
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_HPHL_PA_EN_MASK                0x40
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_DTEST_EN_MASK                  0x30
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOISTURE_OVRD_POLLING_MASK     0x08
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOISTURE_EN_POLLING_MASK       0x04
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOISTURE_DBNC_TIME_MASK        0x03
+
+/* WCD939X_MECH_DET_CURRENT Fields: */
+#define WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL_MASK                   0x1f
+
+/* WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW Fields: */
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_SPARE_BITS_7_MASK          0x80
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_ZDET_CLK_SEL_MASK          0x40
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_ZDET_SUBSEL_OV_MASK        0x20
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_ZDET_CLK_EN_CTL_MASK       0x10
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_MOIS_CURRENT_CTL_SEL_MASK  0x08
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_MOIS_CURRENT_ADD_MASK      0x04
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_MECH_REF_SEL_MASK          0x03
+
+
+/* WCD939X_EAR_CHOPPER_CON Fields: */
+#define WCD939X_EAR_CHOPPER_CON_EAR_CHOPPER_EN_MASK                      0x80
+#define WCD939X_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_DIV_MASK                 0x78
+#define WCD939X_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_INV_MASK                 0x04
+#define WCD939X_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_OVERLAP_MASK             0x02
+#define WCD939X_EAR_CHOPPER_CON_SCD_SHTDWN_FAST_PATH_DIS_MASK            0x01
+
+/* WCD939X_CNP_VCM_CON1 Fields: */
+#define WCD939X_CNP_VCM_CON1_SCD_EN_TIME_SEL_MASK                        0x80
+#define WCD939X_CNP_VCM_CON1_NO_DYN_BIAS_DURING_STARTUP_MASK             0x40
+#define WCD939X_CNP_VCM_CON1_CNP_VCM_GEN_START_MASK                      0x3f
+
+/* WCD939X_CNP_VCM_CON2 Fields: */
+#define WCD939X_CNP_VCM_CON2_DTEST_SEL_MASK                              0xc0
+#define WCD939X_CNP_VCM_CON2_CNP_VCM_GEN_STOP_MASK                       0x3f
+
+/* WCD939X_EAR_DYNAMIC_BIAS Fields: */
+#define WCD939X_EAR_DYNAMIC_BIAS_EAR_DYN_BIAS_SEL_MASK                   0xe0
+#define WCD939X_EAR_DYNAMIC_BIAS_EAR_BIAS_CURR_MASK                      0x1f
+
+
+/* WCD939X_WATCHDOG_CTL_1 Fields: */
+#define WCD939X_WATCHDOG_CTL_1_VREF_HI_CTL_MASK                          0x1f
+
+/* WCD939X_WATCHDOG_CTL_2 Fields: */
+#define WCD939X_WATCHDOG_CTL_2_VREF_LO_CTL_MASK                          0x1f
+
+
+/* WCD939X_DIE_CRK_DET_INT1 Fields: */
+#define WCD939X_DIE_CRK_DET_INT1_SEL_EDGE_DET_MASK                       0xc0
+#define WCD939X_DIE_CRK_DET_INT1_EN_RINGM_ATEST_MASK                     0x20
+#define WCD939X_DIE_CRK_DET_INT1_EN_RINGP_ATEST_MASK                     0x10
+#define WCD939X_DIE_CRK_DET_INT1_RING_CURR_SEL_MASK                      0x0e
+#define WCD939X_DIE_CRK_DET_INT1_EN_VREF_ATEST_MASK                      0x01
+
+/* WCD939X_DIE_CRK_DET_INT2 Fields: */
+#define WCD939X_DIE_CRK_DET_INT2_REF_CURR_SEL_MASK                       0xe0
+#define WCD939X_DIE_CRK_DET_INT2_COMP_STG1_IBIAS_MASK                    0x18
+#define WCD939X_DIE_CRK_DET_INT2_COMP_STG2_IBIAS_MASK                    0x06
+#define WCD939X_DIE_CRK_DET_INT2_EN_ATEST_MASK                           0x01
+
+
+/* WCD939X_TXFE_DIVSTOP_L2 Fields: */
+#define WCD939X_TXFE_DIVSTOP_L2_DIV_L2_MASK                              0xff
+
+/* WCD939X_TXFE_DIVSTOP_L1 Fields: */
+#define WCD939X_TXFE_DIVSTOP_L1_DIV_L1_MASK                              0xff
+
+/* WCD939X_TXFE_DIVSTOP_L0 Fields: */
+#define WCD939X_TXFE_DIVSTOP_L0_DIV_L0_MASK                              0xff
+
+/* WCD939X_TXFE_DIVSTOP_ULP1P2M Fields: */
+#define WCD939X_TXFE_DIVSTOP_ULP1P2M_DIV_ULP1P2M_MASK                    0xff
+
+/* WCD939X_TXFE_DIVSTOP_ULP0P6M Fields: */
+#define WCD939X_TXFE_DIVSTOP_ULP0P6M_DIV_ULP0P6M_MASK                    0xff
+
+/* WCD939X_TXFE_ICTRL_STG1_L2L1 Fields: */
+#define WCD939X_TXFE_ICTRL_STG1_L2L1_NINIT_L2_MASK                       0xc0
+#define WCD939X_TXFE_ICTRL_STG1_L2L1_ICTRL_STG1_L2L1_MASK                0x1f
+
+/* WCD939X_TXFE_ICTRL_STG1_L0 Fields: */
+#define WCD939X_TXFE_ICTRL_STG1_L0_NINIT_L1_MASK                         0xc0
+#define WCD939X_TXFE_ICTRL_STG1_L0_ICTRL_STG1_L0_MASK                    0x1f
+
+/* WCD939X_TXFE_ICTRL_STG1_ULP Fields: */
+#define WCD939X_TXFE_ICTRL_STG1_ULP_NINIT_L0_MASK                        0xc0
+#define WCD939X_TXFE_ICTRL_STG1_ULP_ICTRL_STG1_ULP_MASK                  0x1f
+
+/* WCD939X_TXFE_ICTRL_STG2MAIN_L2L1 Fields: */
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L2L1_NINIT_ULP1P2M_MASK              0xc0
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L2L1_ICTRL_STG2MAIN_L2L1_MASK        0x1f
+
+/* WCD939X_TXFE_ICTRL_STG2MAIN_L0 Fields: */
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L0_NINIT_ULP0P6M_MASK                0xc0
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L0_ADCREF_ULPIBIAS_EN_MASK           0x20
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L0_ICTRL_STG2MAIN_L0_MASK            0x1f
+
+/* WCD939X_TXFE_ICTRL_STG2MAIN_ULP Fields: */
+#define WCD939X_TXFE_ICTRL_STG2MAIN_ULP_ICTRL_STG2MAIN_ULP_MASK          0x1f
+
+/* WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0 Fields: */
+#define WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0_ICTRL_STG2CASC_L2L1_MASK      0xf0
+#define WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0_ICTRL_STG2CASC_L0_MASK        0x0f
+
+/* WCD939X_TXFE_ICTRL_STG2CASC_ULP Fields: */
+#define WCD939X_TXFE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M_MASK        0xf0
+#define WCD939X_TXFE_ICTRL_STG2CASC_ULP_ICTRL_STG2CASC_ULP_MASK          0x0f
+
+/* WCD939X_TXADC_SCBIAS_L2L1 Fields: */
+#define WCD939X_TXADC_SCBIAS_L2L1_ICTRL_SCBIAS_L2_MASK                   0xf0
+#define WCD939X_TXADC_SCBIAS_L2L1_ICTRL_SCBIAS_L1_MASK                   0x0f
+
+/* WCD939X_TXADC_SCBIAS_L0ULP Fields: */
+#define WCD939X_TXADC_SCBIAS_L0ULP_ICTRL_SCBIAS_L0_MASK                  0xf0
+#define WCD939X_TXADC_SCBIAS_L0ULP_ICTRL_SCBIAS_ULP1P2M_MASK             0x0f
+
+/* WCD939X_TXADC_INT_L2 Fields: */
+#define WCD939X_TXADC_INT_L2_INT1_L2_MASK                                0xf0
+#define WCD939X_TXADC_INT_L2_INT2_L2_MASK                                0x0f
+
+/* WCD939X_TXADC_INT_L1 Fields: */
+#define WCD939X_TXADC_INT_L1_INT1_L1_MASK                                0xf0
+#define WCD939X_TXADC_INT_L1_INT2_L1_MASK                                0x0f
+
+/* WCD939X_TXADC_INT_L0 Fields: */
+#define WCD939X_TXADC_INT_L0_INT1_L0_MASK                                0xf0
+#define WCD939X_TXADC_INT_L0_INT2_L0_MASK                                0x0f
+
+/* WCD939X_TXADC_INT_ULP Fields: */
+#define WCD939X_TXADC_INT_ULP_INT1_ULP_MASK                              0xf0
+#define WCD939X_TXADC_INT_ULP_INT2_ULP_MASK                              0x0f
+
+
+/* WCD939X_DIGITAL_PAGE Fields: */
+#define WCD939X_DIGITAL_PAGE_PAG_REG_MASK                                0xff
+
+/* WCD939X_CHIP_ID0 Fields: */
+#define WCD939X_CHIP_ID0_BYTE_0_MASK                                     0xff
+
+/* WCD939X_CHIP_ID1 Fields: */
+#define WCD939X_CHIP_ID1_BYTE_1_MASK                                     0xff
+
+/* WCD939X_CHIP_ID2 Fields: */
+#define WCD939X_CHIP_ID2_BYTE_2_MASK                                     0xff
+
+/* WCD939X_CHIP_ID3 Fields: */
+#define WCD939X_CHIP_ID3_BYTE_3_MASK                                     0xff
+
+/* WCD939X_SWR_TX_CLK_RATE Fields: */
+#define WCD939X_SWR_TX_CLK_RATE_CLK_RATE_BK_1_MASK                       0xf0
+#define WCD939X_SWR_TX_CLK_RATE_CLK_RATE_BK_0_MASK                       0x0f
+
+/* WCD939X_CDC_RST_CTL Fields: */
+#define WCD939X_CDC_RST_CTL_ANA_SW_RST_N_MASK                            0x02
+#define WCD939X_CDC_RST_CTL_DIG_SW_RST_N_MASK                            0x01
+
+/* WCD939X_TOP_CLK_CFG Fields: */
+#define WCD939X_TOP_CLK_CFG_RX_CLK_CFG_MASK                              0x06
+#define WCD939X_TOP_CLK_CFG_TX_CLK_CFG_MASK                              0x01
+
+/* WCD939X_CDC_ANA_CLK_CTL Fields: */
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV4_CLK_EN_MASK                  0x20
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN_MASK                  0x10
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN_MASK                       0x08
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN_MASK                  0x04
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN_MASK                  0x02
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN_MASK                       0x01
+
+/* WCD939X_CDC_DIG_CLK_CTL Fields: */
+#define WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN_MASK                         0x80
+#define WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN_MASK                         0x40
+#define WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN_MASK                         0x20
+#define WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN_MASK                         0x10
+#define WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN_MASK                         0x04
+#define WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN_MASK                         0x02
+#define WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN_MASK                         0x01
+
+/* WCD939X_SWR_RST_EN Fields: */
+#define WCD939X_SWR_RST_EN_RX_RESET_SYNC_LOST_EN_MASK                    0x20
+#define WCD939X_SWR_RST_EN_RX_RESET_SWR_BUS_EN_MASK                      0x10
+#define WCD939X_SWR_RST_EN_RX_RESET_SWR_REG_EN_MASK                      0x08
+#define WCD939X_SWR_RST_EN_TX_RESET_SYNC_LOST_EN_MASK                    0x04
+#define WCD939X_SWR_RST_EN_TX_RESET_SWR_BUS_EN_MASK                      0x02
+#define WCD939X_SWR_RST_EN_TX_RESET_SWR_REG_EN_MASK                      0x01
+
+/* WCD939X_CDC_PATH_MODE Fields: */
+#define WCD939X_CDC_PATH_MODE_EAR_MODE_MASK                              0x40
+#define WCD939X_CDC_PATH_MODE_TXD2_MODE_MASK                             0x30
+#define WCD939X_CDC_PATH_MODE_TXD1_MODE_MASK                             0x0c
+#define WCD939X_CDC_PATH_MODE_TXD0_MODE_MASK                             0x03
+
+/* WCD939X_CDC_RX_RST Fields: */
+#define WCD939X_CDC_RX_RST_RX2_SOFT_RST_MASK                             0x04
+#define WCD939X_CDC_RX_RST_RX1_SOFT_RST_MASK                             0x02
+#define WCD939X_CDC_RX_RST_RX0_SOFT_RST_MASK                             0x01
+
+/* WCD939X_CDC_RX0_CTL Fields: */
+#define WCD939X_CDC_RX0_CTL_DSM_DITHER_ENABLE_MASK                       0x80
+#define WCD939X_CDC_RX0_CTL_DEM_DITHER_ENABLE_MASK                       0x40
+#define WCD939X_CDC_RX0_CTL_DEM_MID_ENABLE_MASK                          0x20
+#define WCD939X_CDC_RX0_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_MASK          0x10
+#define WCD939X_CDC_RX0_CTL_DEM_SWITCHING_BLOCK_ENABLE_MASK              0x08
+#define WCD939X_CDC_RX0_CTL_DEM_SEGMENTING_BLOCK_ENABLE_MASK             0x04
+#define WCD939X_CDC_RX0_CTL_DEM_BYPASS_MASK                              0x02
+
+/* WCD939X_CDC_RX1_CTL Fields: */
+#define WCD939X_CDC_RX1_CTL_DSM_DITHER_ENABLE_MASK                       0x80
+#define WCD939X_CDC_RX1_CTL_DEM_DITHER_ENABLE_MASK                       0x40
+#define WCD939X_CDC_RX1_CTL_DEM_MID_ENABLE_MASK                          0x20
+#define WCD939X_CDC_RX1_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_MASK          0x10
+#define WCD939X_CDC_RX1_CTL_DEM_SWITCHING_BLOCK_ENABLE_MASK              0x08
+#define WCD939X_CDC_RX1_CTL_DEM_SEGMENTING_BLOCK_ENABLE_MASK             0x04
+#define WCD939X_CDC_RX1_CTL_DEM_BYPASS_MASK                              0x02
+
+/* WCD939X_CDC_RX2_CTL Fields: */
+#define WCD939X_CDC_RX2_CTL_DSM_DITHER_ENABLE_MASK                       0x80
+#define WCD939X_CDC_RX2_CTL_DEM_DITHER_ENABLE_MASK                       0x40
+#define WCD939X_CDC_RX2_CTL_DEM_MID_ENABLE_MASK                          0x20
+#define WCD939X_CDC_RX2_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_MASK          0x10
+#define WCD939X_CDC_RX2_CTL_DEM_SWITCHING_BLOCK_ENABLE_MASK              0x08
+#define WCD939X_CDC_RX2_CTL_DEM_SEGMENTING_BLOCK_ENABLE_MASK             0x04
+#define WCD939X_CDC_RX2_CTL_DEM_BYPASS_MASK                              0x02
+
+/* WCD939X_CDC_TX_ANA_MODE_0_1 Fields: */
+#define WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE_MASK                       0xf0
+#define WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE_MASK                       0x0f
+
+/* WCD939X_CDC_TX_ANA_MODE_2_3 Fields: */
+#define WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE_MASK                       0xf0
+#define WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE_MASK                       0x0f
+
+/* WCD939X_CDC_COMP_CTL_0 Fields: */
+#define WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK                         0x02
+#define WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK                         0x01
+
+/* WCD939X_CDC_ANA_TX_CLK_CTL Fields: */
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_MBHC_1P2M_CLK_EN_MASK             0x20
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX3_ADC_CLK_EN_MASK               0x10
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX2_ADC_CLK_EN_MASK               0x08
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX1_ADC_CLK_EN_MASK               0x04
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX0_ADC_CLK_EN_MASK               0x02
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN_MASK              0x01
+
+/* WCD939X_CDC_HPH_DSM_A1_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A1_0_COEF_A1_MASK                            0xff
+
+/* WCD939X_CDC_HPH_DSM_A1_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A1_1_COEF_A1_MASK                            0x01
+
+/* WCD939X_CDC_HPH_DSM_A2_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A2_0_COEF_A2_MASK                            0xff
+
+/* WCD939X_CDC_HPH_DSM_A2_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A2_1_COEF_A2_MASK                            0x0f
+
+/* WCD939X_CDC_HPH_DSM_A3_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A3_0_COEF_A3_MASK                            0xff
+
+/* WCD939X_CDC_HPH_DSM_A3_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A3_1_COEF_A3_MASK                            0x07
+
+/* WCD939X_CDC_HPH_DSM_A4_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A4_0_COEF_A4_MASK                            0xff
+
+/* WCD939X_CDC_HPH_DSM_A4_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A4_1_COEF_A4_MASK                            0x03
+
+/* WCD939X_CDC_HPH_DSM_A5_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A5_0_COEF_A5_MASK                            0xff
+
+/* WCD939X_CDC_HPH_DSM_A5_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A5_1_COEF_A5_MASK                            0x03
+
+/* WCD939X_CDC_HPH_DSM_A6_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A6_0_COEF_A6_MASK                            0xff
+
+/* WCD939X_CDC_HPH_DSM_A7_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A7_0_COEF_A7_MASK                            0xff
+
+/* WCD939X_CDC_HPH_DSM_C_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_C_0_COEF_C3_MASK                             0xf0
+#define WCD939X_CDC_HPH_DSM_C_0_COEF_C2_MASK                             0x0f
+
+/* WCD939X_CDC_HPH_DSM_C_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_C_1_COEF_C5_MASK                             0xf0
+#define WCD939X_CDC_HPH_DSM_C_1_COEF_C4_MASK                             0x0f
+
+/* WCD939X_CDC_HPH_DSM_C_2 Fields: */
+#define WCD939X_CDC_HPH_DSM_C_2_COEF_C7_MASK                             0xf0
+#define WCD939X_CDC_HPH_DSM_C_2_COEF_C6_MASK                             0x0f
+
+/* WCD939X_CDC_HPH_DSM_C_3 Fields: */
+#define WCD939X_CDC_HPH_DSM_C_3_COEF_C7_MASK                             0x3f
+
+/* WCD939X_CDC_HPH_DSM_R1 Fields: */
+#define WCD939X_CDC_HPH_DSM_R1_SAT_LIMIT_R1_MASK                         0xff
+
+/* WCD939X_CDC_HPH_DSM_R2 Fields: */
+#define WCD939X_CDC_HPH_DSM_R2_SAT_LIMIT_R2_MASK                         0xff
+
+/* WCD939X_CDC_HPH_DSM_R3 Fields: */
+#define WCD939X_CDC_HPH_DSM_R3_SAT_LIMIT_R3_MASK                         0xff
+
+/* WCD939X_CDC_HPH_DSM_R4 Fields: */
+#define WCD939X_CDC_HPH_DSM_R4_SAT_LIMIT_R4_MASK                         0xff
+
+/* WCD939X_CDC_HPH_DSM_R5 Fields: */
+#define WCD939X_CDC_HPH_DSM_R5_SAT_LIMIT_R5_MASK                         0xff
+
+/* WCD939X_CDC_HPH_DSM_R6 Fields: */
+#define WCD939X_CDC_HPH_DSM_R6_SAT_LIMIT_R6_MASK                         0xff
+
+/* WCD939X_CDC_HPH_DSM_R7 Fields: */
+#define WCD939X_CDC_HPH_DSM_R7_SAT_LIMIT_R7_MASK                         0xff
+
+/* WCD939X_CDC_EAR_DSM_A1_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A1_0_COEF_A1_MASK                            0xff
+
+/* WCD939X_CDC_EAR_DSM_A1_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A1_1_COEF_A1_MASK                            0x01
+
+/* WCD939X_CDC_EAR_DSM_A2_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A2_0_COEF_A2_MASK                            0xff
+
+/* WCD939X_CDC_EAR_DSM_A2_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A2_1_COEF_A2_MASK                            0x0f
+
+/* WCD939X_CDC_EAR_DSM_A3_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A3_0_COEF_A3_MASK                            0xff
+
+/* WCD939X_CDC_EAR_DSM_A3_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A3_1_COEF_A3_MASK                            0x07
+
+/* WCD939X_CDC_EAR_DSM_A4_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A4_0_COEF_A4_MASK                            0xff
+
+/* WCD939X_CDC_EAR_DSM_A4_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A4_1_COEF_A4_MASK                            0x03
+
+/* WCD939X_CDC_EAR_DSM_A5_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A5_0_COEF_A5_MASK                            0xff
+
+/* WCD939X_CDC_EAR_DSM_A5_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A5_1_COEF_A5_MASK                            0x03
+
+/* WCD939X_CDC_EAR_DSM_A6_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A6_0_COEF_A6_MASK                            0xff
+
+/* WCD939X_CDC_EAR_DSM_A7_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A7_0_COEF_A7_MASK                            0xff
+
+/* WCD939X_CDC_EAR_DSM_C_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_C_0_COEF_C3_MASK                             0xf0
+#define WCD939X_CDC_EAR_DSM_C_0_COEF_C2_MASK                             0x0f
+
+/* WCD939X_CDC_EAR_DSM_C_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_C_1_COEF_C5_MASK                             0xf0
+#define WCD939X_CDC_EAR_DSM_C_1_COEF_C4_MASK                             0x0f
+
+/* WCD939X_CDC_EAR_DSM_C_2 Fields: */
+#define WCD939X_CDC_EAR_DSM_C_2_COEF_C7_MASK                             0xf0
+#define WCD939X_CDC_EAR_DSM_C_2_COEF_C6_MASK                             0x0f
+
+/* WCD939X_CDC_EAR_DSM_C_3 Fields: */
+#define WCD939X_CDC_EAR_DSM_C_3_COEF_C7_MASK                             0x3f
+
+/* WCD939X_CDC_EAR_DSM_R1 Fields: */
+#define WCD939X_CDC_EAR_DSM_R1_SAT_LIMIT_R1_MASK                         0xff
+
+/* WCD939X_CDC_EAR_DSM_R2 Fields: */
+#define WCD939X_CDC_EAR_DSM_R2_SAT_LIMIT_R2_MASK                         0xff
+
+/* WCD939X_CDC_EAR_DSM_R3 Fields: */
+#define WCD939X_CDC_EAR_DSM_R3_SAT_LIMIT_R3_MASK                         0xff
+
+/* WCD939X_CDC_EAR_DSM_R4 Fields: */
+#define WCD939X_CDC_EAR_DSM_R4_SAT_LIMIT_R4_MASK                         0xff
+
+/* WCD939X_CDC_EAR_DSM_R5 Fields: */
+#define WCD939X_CDC_EAR_DSM_R5_SAT_LIMIT_R5_MASK                         0xff
+
+/* WCD939X_CDC_EAR_DSM_R6 Fields: */
+#define WCD939X_CDC_EAR_DSM_R6_SAT_LIMIT_R6_MASK                         0xff
+
+/* WCD939X_CDC_EAR_DSM_R7 Fields: */
+#define WCD939X_CDC_EAR_DSM_R7_SAT_LIMIT_R7_MASK                         0xff
+
+/* WCD939X_CDC_HPH_GAIN_RX_0 Fields: */
+#define WCD939X_CDC_HPH_GAIN_RX_0_GAIN_RX_MASK                           0xff
+
+/* WCD939X_CDC_HPH_GAIN_RX_1 Fields: */
+#define WCD939X_CDC_HPH_GAIN_RX_1_GAIN_RX_MASK                           0xff
+
+/* WCD939X_CDC_HPH_GAIN_DSD_0 Fields: */
+#define WCD939X_CDC_HPH_GAIN_DSD_0_GAIN_DSD_MASK                         0xff
+
+/* WCD939X_CDC_HPH_GAIN_DSD_1 Fields: */
+#define WCD939X_CDC_HPH_GAIN_DSD_1_GAIN_DSD_MASK                         0xff
+
+/* WCD939X_CDC_HPH_GAIN_DSD_2 Fields: */
+#define WCD939X_CDC_HPH_GAIN_DSD_2_GAIN_LATCH_MASK                       0x02
+#define WCD939X_CDC_HPH_GAIN_DSD_2_GAIN_DSD_MASK                         0x01
+
+/* WCD939X_CDC_EAR_GAIN_DSD_0 Fields: */
+#define WCD939X_CDC_EAR_GAIN_DSD_0_GAIN_DSD_MASK                         0xff
+
+/* WCD939X_CDC_EAR_GAIN_DSD_1 Fields: */
+#define WCD939X_CDC_EAR_GAIN_DSD_1_GAIN_DSD_MASK                         0xff
+
+/* WCD939X_CDC_EAR_GAIN_DSD_2 Fields: */
+#define WCD939X_CDC_EAR_GAIN_DSD_2_GAIN_LATCH_MASK                       0x02
+#define WCD939X_CDC_EAR_GAIN_DSD_2_GAIN_DSD_MASK                         0x01
+
+/* WCD939X_CDC_HPH_GAIN_CTL Fields: */
+#define WCD939X_CDC_HPH_GAIN_CTL_HPH_STEREO_EN_MASK                      0x10
+#define WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK                         0x08
+#define WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK                         0x04
+#define WCD939X_CDC_HPH_GAIN_CTL_HPHR_DSD_EN_MASK                        0x02
+#define WCD939X_CDC_HPH_GAIN_CTL_HPHL_DSD_EN_MASK                        0x01
+
+/* WCD939X_CDC_EAR_GAIN_CTL Fields: */
+#define WCD939X_CDC_EAR_GAIN_CTL_EAR_EN_MASK                             0x01
+
+/* WCD939X_CDC_EAR_PATH_CTL Fields: */
+#define WCD939X_CDC_EAR_PATH_CTL_EAR_GAIN_CTL_MASK                       0x3e
+#define WCD939X_CDC_EAR_PATH_CTL_EAR_MUX_SEL_MASK                        0x01
+
+/* WCD939X_CDC_SWR_CLH Fields: */
+#define WCD939X_CDC_SWR_CLH_CLH_CTL_MASK                                 0xff
+
+/* WCD939X_SWR_CLH_BYP Fields: */
+#define WCD939X_SWR_CLH_BYP_SWR_CLH_BYP_MASK                             0x01
+
+/* WCD939X_CDC_TX0_CTL Fields: */
+#define WCD939X_CDC_TX0_CTL_REQ_FB_SEL_MASK                              0x40
+#define WCD939X_CDC_TX0_CTL_TX_DITHER_EN_MASK                            0x20
+#define WCD939X_CDC_TX0_CTL_RANDOM_REGION_MASK                           0x1f
+
+/* WCD939X_CDC_TX1_CTL Fields: */
+#define WCD939X_CDC_TX1_CTL_REQ_FB_SEL_MASK                              0x40
+#define WCD939X_CDC_TX1_CTL_TX_DITHER_EN_MASK                            0x20
+#define WCD939X_CDC_TX1_CTL_RANDOM_REGION_MASK                           0x1f
+
+/* WCD939X_CDC_TX2_CTL Fields: */
+#define WCD939X_CDC_TX2_CTL_REQ_FB_SEL_MASK                              0x40
+#define WCD939X_CDC_TX2_CTL_TX_DITHER_EN_MASK                            0x20
+#define WCD939X_CDC_TX2_CTL_RANDOM_REGION_MASK                           0x1f
+
+/* WCD939X_CDC_TX_RST Fields: */
+#define WCD939X_CDC_TX_RST_TX3_SOFT_RST_MASK                             0x08
+#define WCD939X_CDC_TX_RST_TX2_SOFT_RST_MASK                             0x04
+#define WCD939X_CDC_TX_RST_TX1_SOFT_RST_MASK                             0x02
+#define WCD939X_CDC_TX_RST_TX0_SOFT_RST_MASK                             0x01
+
+/* WCD939X_CDC_REQ_CTL Fields: */
+#define WCD939X_CDC_REQ_CTL_TX3_WIDE_BAND_MASK                           0x20
+#define WCD939X_CDC_REQ_CTL_TX2_WIDE_BAND_MASK                           0x10
+#define WCD939X_CDC_REQ_CTL_TX1_WIDE_BAND_MASK                           0x08
+#define WCD939X_CDC_REQ_CTL_TX0_WIDE_BAND_MASK                           0x04
+#define WCD939X_CDC_REQ_CTL_FS_RATE_4P8_MASK                             0x02
+#define WCD939X_CDC_REQ_CTL_NO_NOTCH_MASK                                0x01
+
+/* WCD939X_CDC_RST Fields: */
+#define WCD939X_CDC_RST_TX_SOFT_RST_MASK                                 0x02
+#define WCD939X_CDC_RST_RX_SOFT_RST_MASK                                 0x01
+
+/* WCD939X_CDC_AMIC_CTL Fields: */
+#define WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL_MASK                           0x08
+#define WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL_MASK                           0x04
+#define WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL_MASK                           0x02
+#define WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL_MASK                           0x01
+
+/* WCD939X_CDC_DMIC_CTL Fields: */
+#define WCD939X_CDC_DMIC_CTL_DMIC_LEGACY_SW_MODE_MASK                    0x08
+#define WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN_MASK                        0x04
+#define WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN_MASK                           0x02
+#define WCD939X_CDC_DMIC_CTL_SOFT_RESET_MASK                             0x01
+
+/* WCD939X_CDC_DMIC1_CTL Fields: */
+#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SCALE_SEL_MASK                    0x70
+#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN_MASK                           0x08
+#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SEL_MASK                          0x07
+
+/* WCD939X_CDC_DMIC2_CTL Fields: */
+#define WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN_MASK                          0x80
+#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SCALE_SEL_MASK                    0x70
+#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN_MASK                           0x08
+#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SEL_MASK                          0x07
+
+/* WCD939X_CDC_DMIC3_CTL Fields: */
+#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SCALE_SEL_MASK                    0x70
+#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN_MASK                           0x08
+#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SEL_MASK                          0x07
+
+/* WCD939X_CDC_DMIC4_CTL Fields: */
+#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SCALE_SEL_MASK                    0x70
+#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN_MASK                           0x08
+#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SEL_MASK                          0x07
+
+/* WCD939X_EFUSE_PRG_CTL Fields: */
+#define WCD939X_EFUSE_PRG_CTL_PRG_ADDR_MASK                              0xff
+
+/* WCD939X_EFUSE_CTL Fields: */
+#define WCD939X_EFUSE_CTL_EFUSE_ST_CNT_MASK                              0x3c
+#define WCD939X_EFUSE_CTL_EFUSE_SOFT_RST_N_MASK                          0x02
+#define WCD939X_EFUSE_CTL_EFUSE_EN_MASK                                  0x01
+
+/* WCD939X_CDC_DMIC_RATE_1_2 Fields: */
+#define WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE_MASK                        0xf0
+#define WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE_MASK                        0x0f
+
+/* WCD939X_CDC_DMIC_RATE_3_4 Fields: */
+#define WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE_MASK                        0xf0
+#define WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE_MASK                        0x0f
+
+/* WCD939X_PDM_WD_CTL0 Fields: */
+#define WCD939X_PDM_WD_CTL0_HOLD_OFF_MASK                                0x10
+#define WCD939X_PDM_WD_CTL0_TIME_OUT_SEL_MASK                            0x08
+#define WCD939X_PDM_WD_CTL0_PDM_WD_EN_MASK                               0x07
+
+/* WCD939X_PDM_WD_CTL1 Fields: */
+#define WCD939X_PDM_WD_CTL1_HOLD_OFF_MASK                                0x10
+#define WCD939X_PDM_WD_CTL1_TIME_OUT_SEL_MASK                            0x08
+#define WCD939X_PDM_WD_CTL1_PDM_WD_EN_MASK                               0x07
+
+/* WCD939X_PDM_WD_CTL2 Fields: */
+#define WCD939X_PDM_WD_CTL2_HOLD_OFF_MASK                                0x04
+#define WCD939X_PDM_WD_CTL2_TIME_OUT_SEL_MASK                            0x02
+#define WCD939X_PDM_WD_CTL2_PDM_WD_EN_MASK                               0x01
+
+/* WCD939X_INTR_MODE Fields: */
+#define WCD939X_INTR_MODE_SWR_PULSE_CLR_MASK                             0x20
+#define WCD939X_INTR_MODE_SWR_RX_INT_OUT_EN_MASK                         0x10
+#define WCD939X_INTR_MODE_SWR_INTR_LEVEL_MASK                            0x02
+#define WCD939X_INTR_MODE_INT_POLARITY_MASK                              0x01
+
+/* WCD939X_INTR_MASK_0 Fields: */
+#define WCD939X_INTR_MASK_0_HPHL_OCP_INT_MASK                            0x80
+#define WCD939X_INTR_MASK_0_HPHR_CNP_INT_MASK                            0x40
+#define WCD939X_INTR_MASK_0_HPHR_OCP_INT_MASK                            0x20
+#define WCD939X_INTR_MASK_0_MBHC_SW_INT_MASK                             0x10
+#define WCD939X_INTR_MASK_0_MBHC_ELECT_INS_REM_LEG_INT_MASK              0x08
+#define WCD939X_INTR_MASK_0_MBHC_ELECT_INS_REM_INT_MASK                  0x04
+#define WCD939X_INTR_MASK_0_MBHC_BTN_RELEASE_INT_MASK                    0x02
+#define WCD939X_INTR_MASK_0_MBHC_BTN_PRESS_INT_MASK                      0x01
+
+/* WCD939X_INTR_MASK_1 Fields: */
+#define WCD939X_INTR_MASK_1_EAR_PDM_WD_INT_MASK                          0x80
+#define WCD939X_INTR_MASK_1_HPHR_PDM_WD_INT_MASK                         0x40
+#define WCD939X_INTR_MASK_1_HPHL_PDM_WD_INT_MASK                         0x20
+#define WCD939X_INTR_MASK_1_EAR_SCD_INT_MASK                             0x04
+#define WCD939X_INTR_MASK_1_EAR_CNP_INT_MASK                             0x02
+#define WCD939X_INTR_MASK_1_HPHL_CNP_INT_MASK                            0x01
+
+/* WCD939X_INTR_MASK_2 Fields: */
+#define WCD939X_INTR_MASK_2_HPHL_SURGE_DET_INT_MASK                      0x08
+#define WCD939X_INTR_MASK_2_HPHR_SURGE_DET_INT_MASK                      0x04
+#define WCD939X_INTR_MASK_2_MBHC_MOISTRUE_INT_MASK                       0x02
+
+/* WCD939X_INTR_STATUS_0 Fields: */
+#define WCD939X_INTR_STATUS_0_HPHL_OCP_INT_MASK                          0x80
+#define WCD939X_INTR_STATUS_0_HPHR_CNP_INT_MASK                          0x40
+#define WCD939X_INTR_STATUS_0_HPHR_OCP_INT_MASK                          0x20
+#define WCD939X_INTR_STATUS_0_MBHC_SW_INT_MASK                           0x10
+#define WCD939X_INTR_STATUS_0_MBHC_ELECT_INS_REM_LEG_INT_MASK            0x08
+#define WCD939X_INTR_STATUS_0_MBHC_ELECT_INS_REM_INT_MASK                0x04
+#define WCD939X_INTR_STATUS_0_MBHC_BTN_RELEASE_INT_MASK                  0x02
+#define WCD939X_INTR_STATUS_0_MBHC_BTN_PRESS_INT_MASK                    0x01
+
+/* WCD939X_INTR_STATUS_1 Fields: */
+#define WCD939X_INTR_STATUS_1_EAR_PDM_WD_INT_MASK                        0x80
+#define WCD939X_INTR_STATUS_1_HPHR_PDM_WD_INT_MASK                       0x40
+#define WCD939X_INTR_STATUS_1_HPHL_PDM_WD_INT_MASK                       0x20
+#define WCD939X_INTR_STATUS_1_EAR_SCD_INT_MASK                           0x04
+#define WCD939X_INTR_STATUS_1_EAR_CNP_INT_MASK                           0x02
+#define WCD939X_INTR_STATUS_1_HPHL_CNP_INT_MASK                          0x01
+
+/* WCD939X_INTR_STATUS_2 Fields: */
+#define WCD939X_INTR_STATUS_2_HPHL_SURGE_DET_INT_MASK                    0x08
+#define WCD939X_INTR_STATUS_2_HPHR_SURGE_DET_INT_MASK                    0x04
+#define WCD939X_INTR_STATUS_2_MBHC_MOISTRUE_INT_MASK                     0x02
+
+/* WCD939X_INTR_CLEAR_0 Fields: */
+#define WCD939X_INTR_CLEAR_0_HPHL_OCP_INT_MASK                           0x80
+#define WCD939X_INTR_CLEAR_0_HPHR_CNP_INT_MASK                           0x40
+#define WCD939X_INTR_CLEAR_0_HPHR_OCP_INT_MASK                           0x20
+#define WCD939X_INTR_CLEAR_0_MBHC_SW_INT_MASK                            0x10
+#define WCD939X_INTR_CLEAR_0_MBHC_ELECT_INS_REM_LEG_INT_MASK             0x08
+#define WCD939X_INTR_CLEAR_0_MBHC_ELECT_INS_REM_INT_MASK                 0x04
+#define WCD939X_INTR_CLEAR_0_MBHC_BTN_RELEASE_INT_MASK                   0x02
+#define WCD939X_INTR_CLEAR_0_MBHC_BTN_PRESS_INT_MASK                     0x01
+
+/* WCD939X_INTR_CLEAR_1 Fields: */
+#define WCD939X_INTR_CLEAR_1_EAR_PDM_WD_INT_MASK                         0x80
+#define WCD939X_INTR_CLEAR_1_HPHR_PDM_WD_INT_MASK                        0x40
+#define WCD939X_INTR_CLEAR_1_HPHL_PDM_WD_INT_MASK                        0x20
+#define WCD939X_INTR_CLEAR_1_EAR_SCD_INT_MASK                            0x04
+#define WCD939X_INTR_CLEAR_1_EAR_CNP_INT_MASK                            0x02
+#define WCD939X_INTR_CLEAR_1_HPHL_CNP_INT_MASK                           0x01
+
+/* WCD939X_INTR_CLEAR_2 Fields: */
+#define WCD939X_INTR_CLEAR_2_HPHL_SURGE_DET_INT_MASK                     0x08
+#define WCD939X_INTR_CLEAR_2_HPHR_SURGE_DET_INT_MASK                     0x04
+#define WCD939X_INTR_CLEAR_2_MBHC_MOISTRUE_INT_MASK                      0x02
+
+/* WCD939X_INTR_LEVEL_0 Fields: */
+#define WCD939X_INTR_LEVEL_0_HPHL_OCP_INT_MASK                           0x80
+#define WCD939X_INTR_LEVEL_0_HPHR_CNP_INT_MASK                           0x40
+#define WCD939X_INTR_LEVEL_0_HPHR_OCP_INT_MASK                           0x20
+#define WCD939X_INTR_LEVEL_0_MBHC_SW_INT_MASK                            0x10
+#define WCD939X_INTR_LEVEL_0_MBHC_ELECT_INS_REM_LEG_INT_MASK             0x08
+#define WCD939X_INTR_LEVEL_0_MBHC_ELECT_INS_REM_INT_MASK                 0x04
+#define WCD939X_INTR_LEVEL_0_MBHC_BTN_RELEASE_INT_MASK                   0x02
+#define WCD939X_INTR_LEVEL_0_MBHC_BTN_PRESS_INT_MASK                     0x01
+
+/* WCD939X_INTR_LEVEL_1 Fields: */
+#define WCD939X_INTR_LEVEL_1_EAR_PDM_WD_INT_MASK                         0x80
+#define WCD939X_INTR_LEVEL_1_HPHR_PDM_WD_INT_MASK                        0x40
+#define WCD939X_INTR_LEVEL_1_HPHL_PDM_WD_INT_MASK                        0x20
+#define WCD939X_INTR_LEVEL_1_EAR_SCD_INT_MASK                            0x04
+#define WCD939X_INTR_LEVEL_1_EAR_CNP_INT_MASK                            0x02
+#define WCD939X_INTR_LEVEL_1_HPHL_CNP_INT_MASK                           0x01
+
+/* WCD939X_INTR_LEVEL_2 Fields: */
+#define WCD939X_INTR_LEVEL_2_HPHL_SURGE_DET_INT_MASK                     0x08
+#define WCD939X_INTR_LEVEL_2_HPHR_SURGE_DET_INT_MASK                     0x04
+#define WCD939X_INTR_LEVEL_2_MBHC_MOISTRUE_INT_MASK                      0x02
+
+/* WCD939X_INTR_SET_0 Fields: */
+#define WCD939X_INTR_SET_0_HPHL_OCP_INT_MASK                             0x80
+#define WCD939X_INTR_SET_0_HPHR_CNP_INT_MASK                             0x40
+#define WCD939X_INTR_SET_0_HPHR_OCP_INT_MASK                             0x20
+#define WCD939X_INTR_SET_0_MBHC_SW_INT_MASK                              0x10
+#define WCD939X_INTR_SET_0_MBHC_ELECT_INS_REM_LEG_INT_MASK               0x08
+#define WCD939X_INTR_SET_0_MBHC_ELECT_INS_REM_INT_MASK                   0x04
+#define WCD939X_INTR_SET_0_MBHC_BTN_RELEASE_INT_MASK                     0x02
+#define WCD939X_INTR_SET_0_MBHC_BTN_PRESS_INT_MASK                       0x01
+
+/* WCD939X_INTR_SET_1 Fields: */
+#define WCD939X_INTR_SET_1_EAR_PDM_WD_INT_MASK                           0x80
+#define WCD939X_INTR_SET_1_HPHR_PDM_WD_INT_MASK                          0x40
+#define WCD939X_INTR_SET_1_HPHL_PDM_WD_INT_MASK                          0x20
+#define WCD939X_INTR_SET_1_EAR_SCD_INT_MASK                              0x04
+#define WCD939X_INTR_SET_1_EAR_CNP_INT_MASK                              0x02
+#define WCD939X_INTR_SET_1_HPHL_CNP_INT_MASK                             0x01
+
+/* WCD939X_INTR_SET_2 Fields: */
+#define WCD939X_INTR_SET_2_HPHL_SURGE_DET_INT_MASK                       0x08
+#define WCD939X_INTR_SET_2_HPHR_SURGE_DET_INT_MASK                       0x04
+#define WCD939X_INTR_SET_2_MBHC_MOISTRUE_INT_MASK                        0x02
+
+/* WCD939X_INTR_TEST_0 Fields: */
+#define WCD939X_INTR_TEST_0_HPHL_OCP_INT_MASK                            0x80
+#define WCD939X_INTR_TEST_0_HPHR_CNP_INT_MASK                            0x40
+#define WCD939X_INTR_TEST_0_HPHR_OCP_INT_MASK                            0x20
+#define WCD939X_INTR_TEST_0_MBHC_SW_INT_MASK                             0x10
+#define WCD939X_INTR_TEST_0_MBHC_ELECT_INS_REM_LEG_INT_MASK              0x08
+#define WCD939X_INTR_TEST_0_MBHC_ELECT_INS_REM_INT_MASK                  0x04
+#define WCD939X_INTR_TEST_0_MBHC_BTN_RELEASE_INT_MASK                    0x02
+#define WCD939X_INTR_TEST_0_MBHC_BTN_PRESS_INT_MASK                      0x01
+
+/* WCD939X_INTR_TEST_1 Fields: */
+#define WCD939X_INTR_TEST_1_EAR_PDM_WD_INT_MASK                          0x80
+#define WCD939X_INTR_TEST_1_HPHR_PDM_WD_INT_MASK                         0x40
+#define WCD939X_INTR_TEST_1_HPHL_PDM_WD_INT_MASK                         0x20
+#define WCD939X_INTR_TEST_1_EAR_SCD_INT_MASK                             0x04
+#define WCD939X_INTR_TEST_1_EAR_CNP_INT_MASK                             0x02
+#define WCD939X_INTR_TEST_1_HPHL_CNP_INT_MASK                            0x01
+
+/* WCD939X_INTR_TEST_2 Fields: */
+#define WCD939X_INTR_TEST_2_HPHL_SURGE_DET_INT_MASK                      0x08
+#define WCD939X_INTR_TEST_2_HPHR_SURGE_DET_INT_MASK                      0x04
+#define WCD939X_INTR_TEST_2_MBHC_MOISTRUE_INT_MASK                       0x02
+
+/* WCD939X_TX_MODE_DBG_EN Fields: */
+#define WCD939X_TX_MODE_DBG_EN_TXD3_MODE_DBG_EN_MASK                     0x08
+#define WCD939X_TX_MODE_DBG_EN_TXD2_MODE_DBG_EN_MASK                     0x04
+#define WCD939X_TX_MODE_DBG_EN_TXD1_MODE_DBG_EN_MASK                     0x02
+#define WCD939X_TX_MODE_DBG_EN_TXD0_MODE_DBG_EN_MASK                     0x01
+
+/* WCD939X_TX_MODE_DBG_0_1 Fields: */
+#define WCD939X_TX_MODE_DBG_0_1_TXD1_MODE_DBG_MASK                       0xf0
+#define WCD939X_TX_MODE_DBG_0_1_TXD0_MODE_DBG_MASK                       0x0f
+
+/* WCD939X_TX_MODE_DBG_2_3 Fields: */
+#define WCD939X_TX_MODE_DBG_2_3_TXD3_MODE_DBG_MASK                       0xf0
+#define WCD939X_TX_MODE_DBG_2_3_TXD2_MODE_DBG_MASK                       0x0f
+
+/* WCD939X_LB_IN_SEL_CTL Fields: */
+#define WCD939X_LB_IN_SEL_CTL_EAR_LB_IN_SEL_MASK                         0x0c
+#define WCD939X_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK                         0x03
+
+/* WCD939X_LOOP_BACK_MODE Fields: */
+#define WCD939X_LOOP_BACK_MODE_TX_DATA_EDGE_MASK                         0x10
+#define WCD939X_LOOP_BACK_MODE_RX_DATA_EDGE_MASK                         0x08
+#define WCD939X_LOOP_BACK_MODE_LOOPBACK_MODE_MASK                        0x07
+
+/* WCD939X_SWR_DAC_TEST Fields: */
+#define WCD939X_SWR_DAC_TEST_SWR_DAC_TEST_MASK                           0x01
+
+/* WCD939X_SWR_HM_TEST_RX_0 Fields: */
+#define WCD939X_SWR_HM_TEST_RX_0_ALT_MODE_MASK                           0x80
+#define WCD939X_SWR_HM_TEST_RX_0_IO_MODE_MASK                            0x40
+#define WCD939X_SWR_HM_TEST_RX_0_LN2_T_DATA_OE_MASK                      0x20
+#define WCD939X_SWR_HM_TEST_RX_0_LN2_T_DATA_OUT_MASK                     0x10
+#define WCD939X_SWR_HM_TEST_RX_0_LN2_T_KEEPER_EN_MASK                    0x08
+#define WCD939X_SWR_HM_TEST_RX_0_LN1_T_DATA_OE_MASK                      0x04
+#define WCD939X_SWR_HM_TEST_RX_0_LN1_T_DATA_OUT_MASK                     0x02
+#define WCD939X_SWR_HM_TEST_RX_0_LN1_T_KEEPER_EN_MASK                    0x01
+
+/* WCD939X_SWR_HM_TEST_TX_0 Fields: */
+#define WCD939X_SWR_HM_TEST_TX_0_ALT_MODE_MASK                           0x80
+#define WCD939X_SWR_HM_TEST_TX_0_IO_MODE_MASK                            0x40
+#define WCD939X_SWR_HM_TEST_TX_0_LN2_T_DATA_OE_MASK                      0x20
+#define WCD939X_SWR_HM_TEST_TX_0_LN2_T_DATA_OUT_MASK                     0x10
+#define WCD939X_SWR_HM_TEST_TX_0_LN2_T_KEEPER_EN_MASK                    0x08
+#define WCD939X_SWR_HM_TEST_TX_0_LN1_T_DATA_OE_MASK                      0x04
+#define WCD939X_SWR_HM_TEST_TX_0_LN1_T_DATA_OUT_MASK                     0x02
+#define WCD939X_SWR_HM_TEST_TX_0_LN1_T_KEEPER_EN_MASK                    0x01
+
+/* WCD939X_SWR_HM_TEST_RX_1 Fields: */
+#define WCD939X_SWR_HM_TEST_RX_1_DTEST_SEL_MASK                          0x1c
+#define WCD939X_SWR_HM_TEST_RX_1_LN2_DLY_CELL_TEST_EN_MASK               0x02
+#define WCD939X_SWR_HM_TEST_RX_1_LN1_DLY_CELL_TEST_EN_MASK               0x01
+
+/* WCD939X_SWR_HM_TEST_TX_1 Fields: */
+#define WCD939X_SWR_HM_TEST_TX_1_DTEST_SEL_MASK                          0x78
+#define WCD939X_SWR_HM_TEST_TX_1_LN3_DLY_CELL_TEST_EN_MASK               0x04
+#define WCD939X_SWR_HM_TEST_TX_1_LN2_DLY_CELL_TEST_EN_MASK               0x02
+#define WCD939X_SWR_HM_TEST_TX_1_LN1_DLY_CELL_TEST_EN_MASK               0x01
+
+/* WCD939X_SWR_HM_TEST_TX_2 Fields: */
+#define WCD939X_SWR_HM_TEST_TX_2_LN3_T_DATA_OE_MASK                      0x04
+#define WCD939X_SWR_HM_TEST_TX_2_LN3_T_DATA_OUT_MASK                     0x02
+#define WCD939X_SWR_HM_TEST_TX_2_LN3_T_KEEPER_EN_MASK                    0x01
+
+/* WCD939X_SWR_HM_TEST_0 Fields: */
+#define WCD939X_SWR_HM_TEST_0_TX_LN2_T_DATA_IN_MASK                      0x80
+#define WCD939X_SWR_HM_TEST_0_TX_LN2_T_CLK_IN_MASK                       0x40
+#define WCD939X_SWR_HM_TEST_0_TX_LN1_T_DATA_IN_MASK                      0x20
+#define WCD939X_SWR_HM_TEST_0_TX_LN1_T_CLK_IN_MASK                       0x10
+#define WCD939X_SWR_HM_TEST_0_RX_LN2_T_DATA_IN_MASK                      0x08
+#define WCD939X_SWR_HM_TEST_0_RX_LN2_T_CLK_IN_MASK                       0x04
+#define WCD939X_SWR_HM_TEST_0_RX_LN1_T_DATA_IN_MASK                      0x02
+#define WCD939X_SWR_HM_TEST_0_RX_LN1_T_CLK_IN_MASK                       0x01
+
+/* WCD939X_SWR_HM_TEST_1 Fields: */
+#define WCD939X_SWR_HM_TEST_1_TX_LN3_T_DATA_IN_MASK                      0x02
+#define WCD939X_SWR_HM_TEST_1_TX_LN3_T_CLK_IN_MASK                       0x01
+
+/* WCD939X_PAD_CTL_SWR_0 Fields: */
+#define WCD939X_PAD_CTL_SWR_0_SWR_SLEW_PRG_MASK                          0xf0
+#define WCD939X_PAD_CTL_SWR_0_SWR_DRIVE_PRG_MASK                         0x0f
+
+/* WCD939X_PAD_CTL_SWR_1 Fields: */
+#define WCD939X_PAD_CTL_SWR_1_SWR_TDZ_PRG_MASK                           0x0f
+
+/* WCD939X_I2C_CTL Fields: */
+#define WCD939X_I2C_CTL_ACTIVE_MODE_MASK                                 0x01
+
+/* WCD939X_CDC_TX_TANGGU_SW_MODE Fields: */
+#define WCD939X_CDC_TX_TANGGU_SW_MODE_LEGACY_SW_MODE_MASK                0x01
+
+/* WCD939X_EFUSE_TEST_CTL_0 Fields: */
+#define WCD939X_EFUSE_TEST_CTL_0_EFUSE_TEST_CTL_LSB_MASK                 0xff
+
+/* WCD939X_EFUSE_TEST_CTL_1 Fields: */
+#define WCD939X_EFUSE_TEST_CTL_1_EFUSE_TEST_CTL_MSB_MASK                 0xff
+
+/* WCD939X_EFUSE_T_DATA_0 Fields: */
+#define WCD939X_EFUSE_T_DATA_0_EFUSE_DATA_MASK                           0xff
+
+/* WCD939X_EFUSE_T_DATA_1 Fields: */
+#define WCD939X_EFUSE_T_DATA_1_EFUSE_DATA_MASK                           0xff
+
+/* WCD939X_PAD_CTL_PDM_RX0 Fields: */
+#define WCD939X_PAD_CTL_PDM_RX0_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD939X_PAD_CTL_PDM_RX0_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD939X_PAD_CTL_PDM_RX1 Fields: */
+#define WCD939X_PAD_CTL_PDM_RX1_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD939X_PAD_CTL_PDM_RX1_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD939X_PAD_CTL_PDM_TX0 Fields: */
+#define WCD939X_PAD_CTL_PDM_TX0_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD939X_PAD_CTL_PDM_TX0_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD939X_PAD_CTL_PDM_TX1 Fields: */
+#define WCD939X_PAD_CTL_PDM_TX1_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD939X_PAD_CTL_PDM_TX1_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD939X_PAD_CTL_PDM_TX2 Fields: */
+#define WCD939X_PAD_CTL_PDM_TX2_PDM_SLEW_PRG_MASK                        0xf0
+#define WCD939X_PAD_CTL_PDM_TX2_PDM_DRIVE_PRG_MASK                       0x0f
+
+/* WCD939X_PAD_INP_DIS_0 Fields: */
+#define WCD939X_PAD_INP_DIS_0_DMIC3_CLK_MASK                             0x20
+#define WCD939X_PAD_INP_DIS_0_DMIC3_DATA_MASK                            0x10
+#define WCD939X_PAD_INP_DIS_0_DMIC2_CLK_MASK                             0x08
+#define WCD939X_PAD_INP_DIS_0_DMIC2_DATA_MASK                            0x04
+#define WCD939X_PAD_INP_DIS_0_DMIC1_CLK_MASK                             0x02
+#define WCD939X_PAD_INP_DIS_0_DMIC1_DATA_MASK                            0x01
+
+/* WCD939X_PAD_INP_DIS_1 Fields: */
+#define WCD939X_PAD_INP_DIS_1_DMIC4_CLK_MASK                             0x10
+#define WCD939X_PAD_INP_DIS_1_DMIC4_DATA_MASK                            0x08
+
+/* WCD939X_DRIVE_STRENGTH_0 Fields: */
+#define WCD939X_DRIVE_STRENGTH_0_DS_DMIC2_CLK_MASK                       0xc0
+#define WCD939X_DRIVE_STRENGTH_0_DS_DMIC2_DATA_MASK                      0x30
+#define WCD939X_DRIVE_STRENGTH_0_DS_DMIC1_CLK_MASK                       0x0c
+#define WCD939X_DRIVE_STRENGTH_0_DS_DMIC1_DATA_MASK                      0x03
+
+/* WCD939X_DRIVE_STRENGTH_1 Fields: */
+#define WCD939X_DRIVE_STRENGTH_1_DS_DMIC3_CLK_MASK                       0x0c
+#define WCD939X_DRIVE_STRENGTH_1_DS_DMIC3_DATA_MASK                      0x03
+
+/* WCD939X_DRIVE_STRENGTH_2 Fields: */
+#define WCD939X_DRIVE_STRENGTH_2_DS_DMIC4_CLK_MASK                       0xc0
+#define WCD939X_DRIVE_STRENGTH_2_DS_DMIC4_DATA_MASK                      0x30
+
+/* WCD939X_RX_DATA_EDGE_CTL Fields: */
+#define WCD939X_RX_DATA_EDGE_CTL_HPH_CLH_EDGE_MASK                       0x20
+#define WCD939X_RX_DATA_EDGE_CTL_EAR_DOUT_EDGE_MASK                      0x10
+#define WCD939X_RX_DATA_EDGE_CTL_HPHR_DOUT_EDGE_MASK                     0x08
+#define WCD939X_RX_DATA_EDGE_CTL_HPHL_DOUT_EDGE_MASK                     0x04
+#define WCD939X_RX_DATA_EDGE_CTL_HPHR_GAIN_EDGE_MASK                     0x02
+#define WCD939X_RX_DATA_EDGE_CTL_HPHL_GAIN_EDGE_MASK                     0x01
+
+/* WCD939X_TX_DATA_EDGE_CTL Fields: */
+#define WCD939X_TX_DATA_EDGE_CTL_TX_WE_DLY_MASK                          0xc0
+#define WCD939X_TX_DATA_EDGE_CTL_TX3_DIN_EDGE_MASK                       0x08
+#define WCD939X_TX_DATA_EDGE_CTL_TX2_DIN_EDGE_MASK                       0x04
+#define WCD939X_TX_DATA_EDGE_CTL_TX1_DIN_EDGE_MASK                       0x02
+#define WCD939X_TX_DATA_EDGE_CTL_TX0_DIN_EDGE_MASK                       0x01
+
+/* WCD939X_GPIO_MODE Fields: */
+#define WCD939X_GPIO_MODE_GPIO_3_EN_MASK                                 0x04
+#define WCD939X_GPIO_MODE_GPIO_2_EN_MASK                                 0x02
+#define WCD939X_GPIO_MODE_TEST_MODE_MASK                                 0x01
+
+/* WCD939X_PIN_CTL_OE Fields: */
+#define WCD939X_PIN_CTL_OE_TEST_PIN_CTL_OE_MASK                          0x10
+#define WCD939X_PIN_CTL_OE_GPIO_3_PIN_CTL_OE_MASK                        0x08
+#define WCD939X_PIN_CTL_OE_GPIO_2_PIN_CTL_OE_MASK                        0x04
+
+/* WCD939X_PIN_CTL_DATA_0 Fields: */
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC3_CLK_MASK                        0x20
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC3_DATA_MASK                       0x10
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC2_CLK_MASK                        0x08
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC2_DATA_MASK                       0x04
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC1_CLK_MASK                        0x02
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC1_DATA_MASK                       0x01
+
+/* WCD939X_PIN_CTL_DATA_1 Fields: */
+#define WCD939X_PIN_CTL_DATA_1_PAD_DMIC4_CLK_MASK                        0x08
+#define WCD939X_PIN_CTL_DATA_1_PAD_DMIC4_DATA_MASK                       0x04
+
+/* WCD939X_PIN_STATUS_0 Fields: */
+#define WCD939X_PIN_STATUS_0_PAD_DMIC3_CLK_MASK                          0x20
+#define WCD939X_PIN_STATUS_0_PAD_DMIC3_DATA_MASK                         0x10
+#define WCD939X_PIN_STATUS_0_PAD_DMIC2_CLK_MASK                          0x08
+#define WCD939X_PIN_STATUS_0_PAD_DMIC2_DATA_MASK                         0x04
+#define WCD939X_PIN_STATUS_0_PAD_DMIC1_CLK_MASK                          0x02
+#define WCD939X_PIN_STATUS_0_PAD_DMIC1_DATA_MASK                         0x01
+
+/* WCD939X_PIN_STATUS_1 Fields: */
+#define WCD939X_PIN_STATUS_1_PAD_DMIC4_CLK_MASK                          0x08
+#define WCD939X_PIN_STATUS_1_PAD_DMIC4_DATA_MASK                         0x04
+
+/* WCD939X_DIG_DEBUG_CTL Fields: */
+#define WCD939X_DIG_DEBUG_CTL_DIG_DEBUG_CTL_MASK                         0x7f
+
+/* WCD939X_DIG_DEBUG_EN Fields: */
+#define WCD939X_DIG_DEBUG_EN_TX_DBG_MODE_MASK                            0x04
+#define WCD939X_DIG_DEBUG_EN_RX_DBG_MODE_1_MASK                          0x02
+#define WCD939X_DIG_DEBUG_EN_RX_DBG_MODE_0_MASK                          0x01
+
+/* WCD939X_ANA_CSR_DBG_ADD Fields: */
+#define WCD939X_ANA_CSR_DBG_ADD_ADD_MASK                                 0xff
+
+/* WCD939X_ANA_CSR_DBG_CTL Fields: */
+#define WCD939X_ANA_CSR_DBG_CTL_WR_VALUE_MASK                            0xc0
+#define WCD939X_ANA_CSR_DBG_CTL_RD_VALUE_MASK                            0x38
+#define WCD939X_ANA_CSR_DBG_CTL_DBG_PAGE_SEL_MASK                        0x06
+#define WCD939X_ANA_CSR_DBG_CTL_DBG_EN_MASK                              0x01
+
+/* WCD939X_SSP_DBG Fields: */
+#define WCD939X_SSP_DBG_RX_SSP_DBG_MASK                                  0x02
+#define WCD939X_SSP_DBG_TX_SSP_DBG_MASK                                  0x01
+
+/* WCD939X_MODE_STATUS_0 Fields: */
+#define WCD939X_MODE_STATUS_0_ATE_7_MASK                                 0x80
+#define WCD939X_MODE_STATUS_0_ATE_6_MASK                                 0x40
+#define WCD939X_MODE_STATUS_0_ATE_5_MASK                                 0x20
+#define WCD939X_MODE_STATUS_0_ATE_4_MASK                                 0x10
+#define WCD939X_MODE_STATUS_0_ATE_3_MASK                                 0x08
+#define WCD939X_MODE_STATUS_0_ATE_2_MASK                                 0x04
+#define WCD939X_MODE_STATUS_0_ATE_1_MASK                                 0x02
+#define WCD939X_MODE_STATUS_0_SWR_TEST_MASK                              0x01
+
+/* WCD939X_MODE_STATUS_1 Fields: */
+#define WCD939X_MODE_STATUS_1_SWR_PAD_TEST_MASK                          0x02
+#define WCD939X_MODE_STATUS_1_EFUSE_MODE_MASK                            0x01
+
+/* WCD939X_SPARE_0 Fields: */
+#define WCD939X_SPARE_0_SPARE_REG_0_MASK                                 0xff
+
+/* WCD939X_SPARE_1 Fields: */
+#define WCD939X_SPARE_1_SPARE_REG_1_MASK                                 0xff
+
+/* WCD939X_SPARE_2 Fields: */
+#define WCD939X_SPARE_2_SPARE_REG_2_MASK                                 0xff
+
+/* WCD939X_EFUSE_REG_0 Fields: */
+#define WCD939X_EFUSE_REG_0_SPARE_BITS_MASK                              0xe0
+#define WCD939X_EFUSE_REG_0_WCD939X_ID_MASK                              0x1e
+#define WCD939X_EFUSE_REG_0_EFUSE_BLOWN_MASK                             0x01
+
+/* WCD939X_EFUSE_REG_1 Fields: */
+#define WCD939X_EFUSE_REG_1_LOT_ID_0_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_2 Fields: */
+#define WCD939X_EFUSE_REG_2_LOT_ID_1_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_3 Fields: */
+#define WCD939X_EFUSE_REG_3_LOT_ID_2_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_4 Fields: */
+#define WCD939X_EFUSE_REG_4_LOT_ID_3_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_5 Fields: */
+#define WCD939X_EFUSE_REG_5_LOT_ID_4_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_6 Fields: */
+#define WCD939X_EFUSE_REG_6_LOT_ID_5_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_7 Fields: */
+#define WCD939X_EFUSE_REG_7_LOT_ID_6_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_8 Fields: */
+#define WCD939X_EFUSE_REG_8_LOT_ID_7_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_9 Fields: */
+#define WCD939X_EFUSE_REG_9_LOT_ID_8_MASK                                0xff
+
+/* WCD939X_EFUSE_REG_10 Fields: */
+#define WCD939X_EFUSE_REG_10_LOT_ID_9_MASK                               0xff
+
+/* WCD939X_EFUSE_REG_11 Fields: */
+#define WCD939X_EFUSE_REG_11_LOT_ID_10_MASK                              0xff
+
+/* WCD939X_EFUSE_REG_12 Fields: */
+#define WCD939X_EFUSE_REG_12_LOT_ID_11_MASK                              0xff
+
+/* WCD939X_EFUSE_REG_13 Fields: */
+#define WCD939X_EFUSE_REG_13_WAFER_ID_MASK                               0xff
+
+/* WCD939X_EFUSE_REG_14 Fields: */
+#define WCD939X_EFUSE_REG_14_X_DIE_LOCATION_MASK                         0xff
+
+/* WCD939X_EFUSE_REG_15 Fields: */
+#define WCD939X_EFUSE_REG_15_Y_DIE_LOCATION_MASK                         0xff
+
+/* WCD939X_EFUSE_REG_16 Fields: */
+#define WCD939X_EFUSE_REG_16_FAB_ID_MASK                                 0xff
+
+/* WCD939X_EFUSE_REG_17 Fields: */
+#define WCD939X_EFUSE_REG_17_TEST_PROGRAM_REV_MASK                       0xff
+
+/* WCD939X_EFUSE_REG_18 Fields: */
+#define WCD939X_EFUSE_REG_18_DIE_REVISION_MASK                           0xff
+
+/* WCD939X_EFUSE_REG_19 Fields: */
+#define WCD939X_EFUSE_REG_19_MFG_ID_SPARE_MASK                           0xff
+
+/* WCD939X_EFUSE_REG_20 Fields: */
+#define WCD939X_EFUSE_REG_20_I2C_SLV_ID_BLOWN_MASK                       0x80
+#define WCD939X_EFUSE_REG_20_I2C_SLAVE_ID_MASK                           0x7f
+
+/* WCD939X_EFUSE_REG_21 Fields: */
+#define WCD939X_EFUSE_REG_21_MBHC_IMP_DET_0_MASK                         0xff
+
+/* WCD939X_EFUSE_REG_22 Fields: */
+#define WCD939X_EFUSE_REG_22_MBHC_IMP_DET_1_MASK                         0xff
+
+/* WCD939X_EFUSE_REG_23 Fields: */
+#define WCD939X_EFUSE_REG_23_SWR_PAD_DRIVE_PRG_1P2V_MASK                 0xf0
+#define WCD939X_EFUSE_REG_23_SWR_SLEW_PRG_1P2V_MASK                      0x0f
+
+/* WCD939X_EFUSE_REG_24 Fields: */
+#define WCD939X_EFUSE_REG_24_SPARE_BITS_MASK                             0xe0
+#define WCD939X_EFUSE_REG_24_SWR_PAD_BLOWN_MASK                          0x10
+#define WCD939X_EFUSE_REG_24_SWR_TDZ_DELAY_PRG_1P2V_MASK                 0x0f
+
+/* WCD939X_EFUSE_REG_25 Fields: */
+#define WCD939X_EFUSE_REG_25_MBHC_IMP_DET_2_MASK                         0xff
+
+/* WCD939X_EFUSE_REG_26 Fields: */
+#define WCD939X_EFUSE_REG_26_MBHC_IMP_DET_3_MASK                         0xff
+
+/* WCD939X_EFUSE_REG_27 Fields: */
+#define WCD939X_EFUSE_REG_27_HPH_DSD_DIS_MASK                            0x80
+#define WCD939X_EFUSE_REG_27_BG_TUNE_BLOWN_MASK                          0x40
+#define WCD939X_EFUSE_REG_27_BG_TUNE_MASK                                0x30
+#define WCD939X_EFUSE_REG_27_EFUSE_HPH_MASK                              0x0f
+
+/* WCD939X_EFUSE_REG_28 Fields: */
+#define WCD939X_EFUSE_REG_28_HPH_CLH_DIS_MASK                            0x80
+#define WCD939X_EFUSE_REG_28_HPH_LOHIFI_DIS_MASK                         0x40
+#define WCD939X_EFUSE_REG_28_HPH_HIFI_DIS_MASK                           0x20
+#define WCD939X_EFUSE_REG_28_EAR_CLH_DIS_MASK                            0x10
+#define WCD939X_EFUSE_REG_28_DMIC_DIS_MASK                               0x08
+#define WCD939X_EFUSE_REG_28_TX_LP_DIS_MASK                              0x04
+#define WCD939X_EFUSE_REG_28_TX_HP_DIS_MASK                              0x02
+#define WCD939X_EFUSE_REG_28_SPARE_BITS_MASK                             0x01
+
+/* WCD939X_EFUSE_REG_29 Fields: */
+#define WCD939X_EFUSE_REG_29_TX_ULP1_DIS_MASK                            0x80
+#define WCD939X_EFUSE_REG_29_TX_ULP2_DIS_MASK                            0x40
+#define WCD939X_EFUSE_REG_29_SPARE_BITS_MASK                             0x30
+#define WCD939X_EFUSE_REG_29_SWR_PAD_DRIVE_PRG_1P8V_MASK                 0x0f
+
+/* WCD939X_EFUSE_REG_30 Fields: */
+#define WCD939X_EFUSE_REG_30_SWR_SLEW_PRG_1P8V_MASK                      0xf0
+#define WCD939X_EFUSE_REG_30_SWR_TDZ_DELAY_PRG_1P8V_MASK                 0x0f
+
+/* WCD939X_EFUSE_REG_31 Fields: */
+#define WCD939X_EFUSE_REG_31_SPARE_EFUSE_ANA_MASK                        0xff
+
+/* WCD939X_TX_REQ_FB_CTL_0 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_0_ULP2_FB_T2_MASK                          0xf0
+#define WCD939X_TX_REQ_FB_CTL_0_ULP2_FB_T1_MASK                          0x0f
+
+/* WCD939X_TX_REQ_FB_CTL_1 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_1_ULP1_FB_T2_MASK                          0xf0
+#define WCD939X_TX_REQ_FB_CTL_1_ULP1_FB_T1_MASK                          0x0f
+
+/* WCD939X_TX_REQ_FB_CTL_2 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_2_L0_FB_T2_MASK                            0xf0
+#define WCD939X_TX_REQ_FB_CTL_2_L0_FB_T1_MASK                            0x0f
+
+/* WCD939X_TX_REQ_FB_CTL_3 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_3_L1_FB_T2_MASK                            0xf0
+#define WCD939X_TX_REQ_FB_CTL_3_L1_FB_T1_MASK                            0x0f
+
+/* WCD939X_TX_REQ_FB_CTL_4 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_4_L2_FB_T2_MASK                            0xf0
+#define WCD939X_TX_REQ_FB_CTL_4_L2_FB_T1_MASK                            0x0f
+
+/* WCD939X_DEM_BYPASS_DATA0 Fields: */
+#define WCD939X_DEM_BYPASS_DATA0_DEM_BYPASS_DATA0_MASK                   0xff
+
+/* WCD939X_DEM_BYPASS_DATA1 Fields: */
+#define WCD939X_DEM_BYPASS_DATA1_DEM_BYPASS_DATA1_MASK                   0xff
+
+/* WCD939X_DEM_BYPASS_DATA2 Fields: */
+#define WCD939X_DEM_BYPASS_DATA2_DEM_BYPASS_DATA2_MASK                   0xff
+
+/* WCD939X_DEM_BYPASS_DATA3 Fields: */
+#define WCD939X_DEM_BYPASS_DATA3_DEM_BYPASS_DATA3_MASK                   0x0f
+
+/* WCD939X_DEM_SECOND_ORDER Fields: */
+#define WCD939X_DEM_SECOND_ORDER_DEM_1_2ND_ORDER_EN_MASK                 0x02
+#define WCD939X_DEM_SECOND_ORDER_DEM_0_2ND_ORDER_EN_MASK                 0x01
+
+/* WCD939X_DSM_CTRL Fields: */
+#define WCD939X_DSM_CTRL_DSM_1_STATIC_EN_MASK                            0x02
+#define WCD939X_DSM_CTRL_DSM_0_STATIC_EN_MASK                            0x01
+
+/* WCD939X_DSM_0_STATIC_DATA_0 Fields: */
+#define WCD939X_DSM_0_STATIC_DATA_0_DSM_0_STATIC_DATA0_MASK              0xff
+
+/* WCD939X_DSM_0_STATIC_DATA_1 Fields: */
+#define WCD939X_DSM_0_STATIC_DATA_1_DSM_0_STATIC_DATA1_MASK              0xff
+
+/* WCD939X_DSM_0_STATIC_DATA_2 Fields: */
+#define WCD939X_DSM_0_STATIC_DATA_2_DSM_0_STATIC_DATA2_MASK              0xff
+
+/* WCD939X_DSM_0_STATIC_DATA_3 Fields: */
+#define WCD939X_DSM_0_STATIC_DATA_3_DSM_0_STATIC_DATA3_MASK              0x07
+
+/* WCD939X_DSM_1_STATIC_DATA_0 Fields: */
+#define WCD939X_DSM_1_STATIC_DATA_0_DSM_1_STATIC_DATA0_MASK              0xff
+
+/* WCD939X_DSM_1_STATIC_DATA_1 Fields: */
+#define WCD939X_DSM_1_STATIC_DATA_1_DSM_1_STATIC_DATA1_MASK              0xff
+
+/* WCD939X_DSM_1_STATIC_DATA_2 Fields: */
+#define WCD939X_DSM_1_STATIC_DATA_2_DSM_1_STATIC_DATA2_MASK              0xff
+
+/* WCD939X_DSM_1_STATIC_DATA_3 Fields: */
+#define WCD939X_DSM_1_STATIC_DATA_3_DSM_1_STATIC_DATA3_MASK              0x07
+
+
+/* WCD939X_RX_PAGE Fields: */
+#define WCD939X_RX_PAGE_PAG_REG_MASK                                     0xff
+
+/* WCD939X_TOP_CFG0 Fields: */
+#define WCD939X_TOP_CFG0_HPH_DAC_RATE_SEL_MASK                           0x02
+#define WCD939X_TOP_CFG0_PGA_UPDATE_MASK                                 0x01
+
+/* WCD939X_HPHL_COMP_WR_LSB Fields: */
+#define WCD939X_HPHL_COMP_WR_LSB_COEFF_MASK                              0xff
+
+/* WCD939X_HPHL_COMP_WR_MSB Fields: */
+#define WCD939X_HPHL_COMP_WR_MSB_COEFF_MASK                              0x1f
+
+/* WCD939X_HPHL_COMP_LUT Fields: */
+#define WCD939X_HPHL_COMP_LUT_BYPASS_MASK                                0x80
+#define WCD939X_HPHL_COMP_LUT_MANUAL_RD_MASK                             0x40
+#define WCD939X_HPHL_COMP_LUT_MANUAL_WR_MASK                             0x20
+#define WCD939X_HPHL_COMP_LUT_ADDR_MASK                                  0x1f
+
+/* WCD939X_HPHL_COMP_RD_LSB Fields: */
+#define WCD939X_HPHL_COMP_RD_LSB_COEFF_MASK                              0xff
+
+/* WCD939X_HPHL_COMP_RD_MSB Fields: */
+#define WCD939X_HPHL_COMP_RD_MSB_COEFF_MASK                              0x1f
+
+/* WCD939X_HPHR_COMP_WR_LSB Fields: */
+#define WCD939X_HPHR_COMP_WR_LSB_COEFF_MASK                              0xff
+
+/* WCD939X_HPHR_COMP_WR_MSB Fields: */
+#define WCD939X_HPHR_COMP_WR_MSB_COEFF_MASK                              0x1f
+
+/* WCD939X_HPHR_COMP_LUT Fields: */
+#define WCD939X_HPHR_COMP_LUT_BYPASS_MASK                                0x80
+#define WCD939X_HPHR_COMP_LUT_MANUAL_RD_MASK                             0x40
+#define WCD939X_HPHR_COMP_LUT_MANUAL_WR_MASK                             0x20
+#define WCD939X_HPHR_COMP_LUT_ADDR_MASK                                  0x1f
+
+/* WCD939X_HPHR_COMP_RD_LSB Fields: */
+#define WCD939X_HPHR_COMP_RD_LSB_COEFF_MASK                              0xff
+
+/* WCD939X_HPHR_COMP_RD_MSB Fields: */
+#define WCD939X_HPHR_COMP_RD_MSB_COEFF_MASK                              0x1f
+
+/* WCD939X_DSD0_DEBUG_CFG1 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG1_DSD_UNPACKING_ORDER_MASK                 0x08
+#define WCD939X_DSD0_DEBUG_CFG1_DSD_DC_DET_EN_MASK                       0x04
+#define WCD939X_DSD0_DEBUG_CFG1_DSD_MUTE_DET_EN_MASK                     0x01
+
+/* WCD939X_DSD0_DEBUG_CFG2 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG2_MUTE_INI_VAL_MASK                        0x10
+#define WCD939X_DSD0_DEBUG_CFG2_DC_INTR_THRESHOLD_MASK                   0x0c
+#define WCD939X_DSD0_DEBUG_CFG2_DC_DET_THRESHOLD_MASK                    0x03
+
+/* WCD939X_DSD0_DEBUG_CFG3 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG3_DSD_POST_GAIN_MASK                       0x38
+#define WCD939X_DSD0_DEBUG_CFG3_DSD_GAIN_ADJ_MASK                        0x07
+
+/* WCD939X_DSD0_DEBUG_CFG4 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG4_DSD_INPUT_ZOH_MASK                       0x03
+
+/* WCD939X_DSD0_DEBUG_CFG5 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG5_DSD_DC_DET_MASK                          0x80
+#define WCD939X_DSD0_DEBUG_CFG5_DSD_PGA_GAIN_UPD_STATUS_MASK             0x40
+#define WCD939X_DSD0_DEBUG_CFG5_DSD_DC_SAMPLE_NUM_MSB_MASK               0x03
+
+/* WCD939X_DSD0_DEBUG_CFG6 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG6_DSD_DC_SAMPLE_NUM_LSB_MASK               0xff
+
+/* WCD939X_DSD1_DEBUG_CFG1 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG1_DSD_UNPACKING_ORDER_MASK                 0x04
+#define WCD939X_DSD1_DEBUG_CFG1_DSD_DC_DET_EN_MASK                       0x02
+#define WCD939X_DSD1_DEBUG_CFG1_DSD_MUTE_DET_EN_MASK                     0x01
+
+/* WCD939X_DSD1_DEBUG_CFG2 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG2_MUTE_INI_VAL_MASK                        0x10
+#define WCD939X_DSD1_DEBUG_CFG2_DC_INTR_THRESHOLD_MASK                   0x0c
+#define WCD939X_DSD1_DEBUG_CFG2_DC_DET_THRESHOLD_MASK                    0x03
+
+/* WCD939X_DSD1_DEBUG_CFG3 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG3_DSD_POST_GAIN_MASK                       0x38
+#define WCD939X_DSD1_DEBUG_CFG3_DSD_GAIN_ADJ_MASK                        0x07
+
+/* WCD939X_DSD1_DEBUG_CFG4 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG4_DSD_INPUT_ZOH_MASK                       0x03
+
+/* WCD939X_DSD1_DEBUG_CFG5 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG5_DSD_DC_DET_MASK                          0x80
+#define WCD939X_DSD1_DEBUG_CFG5_DSD_PGA_GAIN_UPD_STATUS_MASK             0x40
+#define WCD939X_DSD1_DEBUG_CFG5_DSD_DC_SAMPLE_NUM_MSB_MASK               0x03
+
+/* WCD939X_DSD1_DEBUG_CFG6 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG6_DSD_DC_SAMPLE_NUM_LSB_MASK               0xff
+
+/* WCD939X_HPHL_RX_PATH_CFG0 Fields: */
+#define WCD939X_HPHL_RX_PATH_CFG0_INT_EN_MASK                            0x02
+#define WCD939X_HPHL_RX_PATH_CFG0_DLY_ZN_EN_MASK                         0x01
+
+/* WCD939X_HPHL_RX_PATH_CFG1 Fields: */
+#define WCD939X_HPHL_RX_PATH_CFG1_DSM_SOFT_RST_MASK                      0x20
+#define WCD939X_HPHL_RX_PATH_CFG1_INT_SOFT_RST_MASK                      0x10
+#define WCD939X_HPHL_RX_PATH_CFG1_FMT_CONV_MASK                          0x08
+#define WCD939X_HPHL_RX_PATH_CFG1_IDLE_OVRD_EN_MASK                      0x04
+#define WCD939X_HPHL_RX_PATH_CFG1_RX_DC_DROOP_COEFF_SEL_MASK             0x03
+
+/* WCD939X_HPHR_RX_PATH_CFG0 Fields: */
+#define WCD939X_HPHR_RX_PATH_CFG0_INT_EN_MASK                            0x04
+#define WCD939X_HPHR_RX_PATH_CFG0_DLY_ZN_EN_MASK                         0x02
+
+/* WCD939X_HPHR_RX_PATH_CFG1 Fields: */
+#define WCD939X_HPHR_RX_PATH_CFG1_DSM_SOFT_RST_MASK                      0x20
+#define WCD939X_HPHR_RX_PATH_CFG1_INT_SOFT_RST_MASK                      0x10
+#define WCD939X_HPHR_RX_PATH_CFG1_FMT_CONV_MASK                          0x08
+#define WCD939X_HPHR_RX_PATH_CFG1_IDLE_OVRD_EN_MASK                      0x04
+#define WCD939X_HPHR_RX_PATH_CFG1_RX_DC_DROOP_COEFF_SEL_MASK             0x03
+
+/* WCD939X_RX_PATH_CFG2 Fields: */
+#define WCD939X_RX_PATH_CFG2_COMP_XTALK_EN_MASK                          0x08
+#define WCD939X_RX_PATH_CFG2_XTALK_NLIN_EN_MASK                          0x04
+#define WCD939X_RX_PATH_CFG2_XTALK_LIN_EN_MASK                           0x02
+#define WCD939X_RX_PATH_CFG2_XTALK_EN_MASK                               0x01
+
+/* WCD939X_HPHL_RX_PATH_SEC0 Fields: */
+#define WCD939X_HPHL_RX_PATH_SEC0_LIN_XTALK_POLARITY_MASK                0x20
+#define WCD939X_HPHL_RX_PATH_SEC0_LIN_XTALK_SCALE_MASK                   0x1f
+
+/* WCD939X_HPHL_RX_PATH_SEC1 Fields: */
+#define WCD939X_HPHL_RX_PATH_SEC1_LIN_XTALK_ALPHA_MASK                   0xff
+
+/* WCD939X_HPHL_RX_PATH_SEC2 Fields: */
+#define WCD939X_HPHL_RX_PATH_SEC2_NLIN_XTALK_POLARITY_MASK               0x40
+#define WCD939X_HPHL_RX_PATH_SEC2_NLIN_XTALK_BYPASS_MASK                 0x20
+#define WCD939X_HPHL_RX_PATH_SEC2_NLIN_XTALK_SCALE_MASK                  0x1f
+
+/* WCD939X_HPHL_RX_PATH_SEC3 Fields: */
+#define WCD939X_HPHL_RX_PATH_SEC3_NLIN_XTALK_ALPHA_MASK                  0xff
+
+/* WCD939X_HPHR_RX_PATH_SEC0 Fields: */
+#define WCD939X_HPHR_RX_PATH_SEC0_LIN_XTALK_POLARITY_MASK                0x20
+#define WCD939X_HPHR_RX_PATH_SEC0_LIN_XTALK_SCALE_MASK                   0x1f
+
+/* WCD939X_HPHR_RX_PATH_SEC1 Fields: */
+#define WCD939X_HPHR_RX_PATH_SEC1_LIN_XTALK_ALPHA_MASK                   0xff
+
+/* WCD939X_HPHR_RX_PATH_SEC2 Fields: */
+#define WCD939X_HPHR_RX_PATH_SEC2_NLIN_XTALK_POLARITY_MASK               0x40
+#define WCD939X_HPHR_RX_PATH_SEC2_NLIN_XTALK_BYPASS_MASK                 0x20
+#define WCD939X_HPHR_RX_PATH_SEC2_NLIN_XTALK_SCALE_MASK                  0x1f
+
+/* WCD939X_HPHR_RX_PATH_SEC3 Fields: */
+#define WCD939X_HPHR_RX_PATH_SEC3_NLIN_XTALK_ALPHA_MASK                  0xff
+
+/* WCD939X_RX_PATH_SEC4 Fields: */
+#define WCD939X_RX_PATH_SEC4_NLIN_CMB_POLARITY_MASK                      0x20
+#define WCD939X_RX_PATH_SEC4_NLIN_CMB_SCALE_MASK                         0x1f
+
+/* WCD939X_RX_PATH_SEC5 Fields: */
+#define WCD939X_RX_PATH_SEC5_NLIN_CMB_ALPHA_MASK                         0xff
+
+
+/* WCD939X_CTL0 Fields: */
+#define WCD939X_CTL0_SHUTDWN_TOUT_MASK                                   0x70
+#define WCD939X_CTL0_DROPOUT_EN_MASK                                     0x08
+#define WCD939X_CTL0_COMP_HALT_MASK                                      0x04
+#define WCD939X_CTL0_SOFT_RST_MASK                                       0x02
+#define WCD939X_CTL0_CLK_EN_MASK                                         0x01
+
+/* WCD939X_CTL1 Fields: */
+#define WCD939X_CTL1_LEVEL_METER_DIV_FACTOR_MASK                         0xf0
+#define WCD939X_CTL1_PEAK_METER_TOUT_MASK                                0x0f
+
+/* WCD939X_CTL2 Fields: */
+#define WCD939X_CTL2_LEVEL_METER_RESAMPLE_RATE_MASK                      0xff
+
+/* WCD939X_CTL3 Fields: */
+#define WCD939X_CTL3_STATIC_GAIN_OFFSET_MASK                             0x80
+#define WCD939X_CTL3_ZONE_SELECT_SHIFT_MASK                              0x70
+#define WCD939X_CTL3_ZONE_SELECT_ENTRY_MASK                              0x0f
+
+/* WCD939X_CTL4 Fields: */
+#define WCD939X_CTL4_DET_WINDOW_MASK                                     0xff
+
+/* WCD939X_CTL5 Fields: */
+#define WCD939X_CTL5_GAIN_MAX_THOLD_MASK                                 0x18
+#define WCD939X_CTL5_DET_WINDOW_MASK                                     0x07
+
+/* WCD939X_CTL6 Fields: */
+#define WCD939X_CTL6_STATUS_MASK                                         0x01
+
+/* WCD939X_CTL7 Fields: */
+#define WCD939X_CTL7_DIS_SCD_MASK                                        0x40
+#define WCD939X_CTL7_AGAIN_DELAY_MASK                                    0x1e
+
+/* WCD939X_CTL8 Fields: */
+#define WCD939X_CTL8_PEAK_TO_FLAG_DIS_MASK                               0x02
+#define WCD939X_CTL8_GAIN_STEP_SELECT_MASK                               0x01
+
+/* WCD939X_CTL9 Fields: */
+#define WCD939X_CTL9_ZONE0_RMS_MASK                                      0x7f
+
+/* WCD939X_CTL10 Fields: */
+#define WCD939X_CTL10_ZONE1_RMS_MASK                                     0x7f
+
+/* WCD939X_CTL11 Fields: */
+#define WCD939X_CTL11_ZONE2_RMS_MASK                                     0x7f
+
+/* WCD939X_CTL12 Fields: */
+#define WCD939X_CTL12_ZONE3_RMS_MASK                                     0x7f
+
+/* WCD939X_CTL13 Fields: */
+#define WCD939X_CTL13_ZONE4_RMS_MASK                                     0x7f
+
+/* WCD939X_CTL14 Fields: */
+#define WCD939X_CTL14_ZONE5_RMS_MASK                                     0x7f
+
+/* WCD939X_CTL15 Fields: */
+#define WCD939X_CTL15_ZONE6_RMS_MASK                                     0x7f
+
+/* WCD939X_CTL16 Fields: */
+#define WCD939X_CTL16_MAX_ATTN_MASK                                      0xff
+
+/* WCD939X_CTL17 Fields: */
+#define WCD939X_CTL17_PATH_GAIN_MASK                                     0x3f
+
+/* WCD939X_CTL18 Fields: */
+#define WCD939X_CTL18_ANA_ADDR_MAP_MASK                                  0x3f
+
+/* WCD939X_CTL19 Fields: */
+#define WCD939X_CTL19_RMS_TOUT_MASK                                      0x3e
+#define WCD939X_CTL19_RMS_TOUT_OVERRIDE_MASK                             0x01
+
+
+/* WCD939X_R_CTL0 Fields: */
+#define WCD939X_R_CTL0_SHUTDWN_TOUT_MASK                                 0x70
+#define WCD939X_R_CTL0_DROPOUT_EN_MASK                                   0x08
+#define WCD939X_R_CTL0_COMP_HALT_MASK                                    0x04
+#define WCD939X_R_CTL0_SOFT_RST_MASK                                     0x02
+#define WCD939X_R_CTL0_CLK_EN_MASK                                       0x01
+
+/* WCD939X_R_CTL1 Fields: */
+#define WCD939X_R_CTL1_LEVEL_METER_DIV_FACTOR_MASK                       0xf0
+#define WCD939X_R_CTL1_PEAK_METER_TOUT_MASK                              0x0f
+
+/* WCD939X_R_CTL2 Fields: */
+#define WCD939X_R_CTL2_LEVEL_METER_RESAMPLE_RATE_MASK                    0xff
+
+/* WCD939X_R_CTL3 Fields: */
+#define WCD939X_R_CTL3_STATIC_GAIN_OFFSET_MASK                           0x80
+#define WCD939X_R_CTL3_ZONE_SELECT_SHIFT_MASK                            0x70
+#define WCD939X_R_CTL3_ZONE_SELECT_ENTRY_MASK                            0x0f
+
+/* WCD939X_R_CTL4 Fields: */
+#define WCD939X_R_CTL4_DET_WINDOW_MASK                                   0xff
+
+/* WCD939X_R_CTL5 Fields: */
+#define WCD939X_R_CTL5_GAIN_MAX_THOLD_MASK                               0x18
+#define WCD939X_R_CTL5_DET_WINDOW_MASK                                   0x07
+
+/* WCD939X_R_CTL6 Fields: */
+#define WCD939X_R_CTL6_STATUS_MASK                                       0x01
+
+/* WCD939X_R_CTL7 Fields: */
+#define WCD939X_R_CTL7_DIS_SCD_MASK                                      0x40
+#define WCD939X_R_CTL7_AGAIN_DELAY_MASK                                  0x1e
+
+/* WCD939X_R_CTL8 Fields: */
+#define WCD939X_R_CTL8_PEAK_TO_FLAG_DIS_MASK                             0x02
+#define WCD939X_R_CTL8_GAIN_STEP_SELECT_MASK                             0x01
+
+/* WCD939X_R_CTL9 Fields: */
+#define WCD939X_R_CTL9_ZONE0_RMS_MASK                                    0x7f
+
+/* WCD939X_R_CTL10 Fields: */
+#define WCD939X_R_CTL10_ZONE1_RMS_MASK                                   0x7f
+
+/* WCD939X_R_CTL11 Fields: */
+#define WCD939X_R_CTL11_ZONE2_RMS_MASK                                   0x7f
+
+/* WCD939X_R_CTL12 Fields: */
+#define WCD939X_R_CTL12_ZONE3_RMS_MASK                                   0x7f
+
+/* WCD939X_R_CTL13 Fields: */
+#define WCD939X_R_CTL13_ZONE4_RMS_MASK                                   0x7f
+
+/* WCD939X_R_CTL14 Fields: */
+#define WCD939X_R_CTL14_ZONE5_RMS_MASK                                   0x7f
+
+/* WCD939X_R_CTL15 Fields: */
+#define WCD939X_R_CTL15_ZONE6_RMS_MASK                                   0x7f
+
+/* WCD939X_R_CTL16 Fields: */
+#define WCD939X_R_CTL16_MAX_ATTN_MASK                                    0xff
+
+/* WCD939X_R_CTL17 Fields: */
+#define WCD939X_R_CTL17_PATH_GAIN_MASK                                   0x3f
+
+/* WCD939X_R_CTL18 Fields: */
+#define WCD939X_R_CTL18_ANA_ADDR_MAP_MASK                                0x3f
+
+/* WCD939X_R_CTL19 Fields: */
+#define WCD939X_R_CTL19_RMS_TOUT_MASK                                    0x3e
+#define WCD939X_R_CTL19_RMS_TOUT_OVERRIDE_MASK                           0x01
+
+
+/* WCD939X_PATH_CTL Fields: */
+#define WCD939X_PATH_CTL_RESET_RIGHT_MASK                                0x08
+#define WCD939X_PATH_CTL_RESET_LEFT_MASK                                 0x04
+#define WCD939X_PATH_CTL_CLK_EN_RIGHT_MASK                               0x02
+#define WCD939X_PATH_CTL_CLK_EN_LEFT_MASK                                0x01
+
+/* WCD939X_CFG0 Fields: */
+#define WCD939X_CFG0_AUTO_DISABLE_ANC_MASK                               0x04
+#define WCD939X_CFG0_AUTO_DISABLE_DSD_MASK                               0x02
+#define WCD939X_CFG0_IDLE_STEREO_MASK                                    0x01
+
+/* WCD939X_CFG1 Fields: */
+#define WCD939X_CFG1_IDLE_N_HOLDOFF_LSB_MASK                             0xff
+
+/* WCD939X_CFG2 Fields: */
+#define WCD939X_CFG2_IDLE_N_HOLDOFF_MSB_MASK                             0x0f
+
+/* WCD939X_CFG3 Fields: */
+#define WCD939X_CFG3_IDLE_THRESHOLD_MASK                                 0xff
+
+
+/* WCD939X_DSD_HPHL_PATH_CTL Fields: */
+#define WCD939X_DSD_HPHL_PATH_CTL_RESET_MASK                             0x02
+#define WCD939X_DSD_HPHL_PATH_CTL_CLK_EN_MASK                            0x01
+
+/* WCD939X_DSD_HPHL_CFG0 Fields: */
+#define WCD939X_DSD_HPHL_CFG0_INP_SEL_MASK                               0x01
+
+/* WCD939X_DSD_HPHL_CFG1 Fields: */
+#define WCD939X_DSD_HPHL_CFG1_PGA_GAIN_MASK                              0xff
+
+/* WCD939X_DSD_HPHL_CFG2 Fields: */
+#define WCD939X_DSD_HPHL_CFG2_PGA_TIMER_MSB_EXT_MASK                     0x78
+#define WCD939X_DSD_HPHL_CFG2_PGA_MUTE_EN_MASK                           0x04
+#define WCD939X_DSD_HPHL_CFG2_PGA_MODE_MASK                              0x02
+#define WCD939X_DSD_HPHL_CFG2_PGA_HALF_DB_MASK                           0x01
+
+/* WCD939X_DSD_HPHL_CFG3 Fields: */
+#define WCD939X_DSD_HPHL_CFG3_PGA_TIMER_MASK                             0xff
+
+/* WCD939X_CFG4 Fields: */
+#define WCD939X_CFG4_TOGGLE_THRESHOLD_MASK                               0x18
+#define WCD939X_CFG4_MUTE_THRESHOLD_MASK                                 0x07
+
+/* WCD939X_CFG5 Fields: */
+#define WCD939X_CFG5_DATA_BIT_POLARITY_MASK                              0x02
+#define WCD939X_CFG5_INP_BIT_POLARITY_MASK                               0x01
+
+
+/* WCD939X_DSD_HPHR_PATH_CTL Fields: */
+#define WCD939X_DSD_HPHR_PATH_CTL_RESET_MASK                             0x02
+#define WCD939X_DSD_HPHR_PATH_CTL_CLK_EN_MASK                            0x01
+
+/* WCD939X_DSD_HPHR_CFG0 Fields: */
+#define WCD939X_DSD_HPHR_CFG0_INP_SEL_MASK                               0x01
+
+/* WCD939X_DSD_HPHR_CFG1 Fields: */
+#define WCD939X_DSD_HPHR_CFG1_PGA_GAIN_MASK                              0xff
+
+/* WCD939X_DSD_HPHR_CFG2 Fields: */
+#define WCD939X_DSD_HPHR_CFG2_PGA_TIMER_MSB_EXT_MASK                     0x78
+#define WCD939X_DSD_HPHR_CFG2_PGA_MUTE_EN_MASK                           0x04
+#define WCD939X_DSD_HPHR_CFG2_PGA_MODE_MASK                              0x02
+#define WCD939X_DSD_HPHR_CFG2_PGA_HALF_DB_MASK                           0x01
+
+/* WCD939X_DSD_HPHR_CFG3 Fields: */
+#define WCD939X_DSD_HPHR_CFG3_PGA_TIMER_MASK                             0xff
+
+/* WCD939X_DSD_HPHR_CFG4 Fields: */
+#define WCD939X_DSD_HPHR_CFG4_TOGGLE_THRESHOLD_MASK                      0x18
+#define WCD939X_DSD_HPHR_CFG4_MUTE_THRESHOLD_MASK                        0x07
+
+/* WCD939X_DSD_HPHR_CFG5 Fields: */
+#define WCD939X_DSD_HPHR_CFG5_DATA_BIT_POLARITY_MASK                     0x02
+#define WCD939X_DSD_HPHR_CFG5_INP_BIT_POLARITY_MASK                      0x01
+
+
+#endif /* WCD939X_REG_MASKS_H */

asoc/codecs/wcd939x/wcd939x-reg-shifts.h

@@ -0,0 +1,2673 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef WCD939X_REG_SHIFTS_H
+#define WCD939X_REG_SHIFTS_H
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd939x-registers.h"
+
+/* Use in conjunction with wcd939x-reg-masks.c for field values. */
+/* field_value = (register_value & field_mask) >> field_shift */
+
+#define FIELD_SHIFT(register_name, field_name) \
+WCD939X_##register_name##_##field_name##_SHIFT
+
+/* WCD939X_ANA_PAGE Fields: */
+#define WCD939X_ANA_PAGE_VALUE_SHIFT                                      0x00
+
+/* WCD939X_BIAS Fields: */
+#define WCD939X_BIAS_ANALOG_BIAS_EN_SHIFT                                 0x07
+#define WCD939X_BIAS_PRECHRG_EN_SHIFT                                     0x06
+#define WCD939X_BIAS_PRECHRG_CTL_MODE_SHIFT                               0x05
+
+/* WCD939X_RX_SUPPLIES Fields: */
+#define WCD939X_RX_SUPPLIES_VPOS_EN_SHIFT                                 0x07
+#define WCD939X_RX_SUPPLIES_VNEG_EN_SHIFT                                 0x06
+#define WCD939X_RX_SUPPLIES_VPOS_PWR_LVL_SHIFT                            0x03
+#define WCD939X_RX_SUPPLIES_VNEG_PWR_LVL_SHIFT                            0x02
+#define WCD939X_RX_SUPPLIES_REGULATOR_MODE_SHIFT                          0x01
+#define WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE_SHIFT                          0x00
+
+/* WCD939X_HPH Fields: */
+#define WCD939X_HPH_HPHL_ENABLE_SHIFT                                     0x07
+#define WCD939X_HPH_HPHR_ENABLE_SHIFT                                     0x06
+#define WCD939X_HPH_HPHL_REF_ENABLE_SHIFT                                 0x05
+#define WCD939X_HPH_HPHR_REF_ENABLE_SHIFT                                 0x04
+#define WCD939X_HPH_PWR_LEVEL_SHIFT                                       0x02
+
+/* WCD939X_EAR Fields: */
+#define WCD939X_EAR_ENABLE_SHIFT                                          0x07
+#define WCD939X_EAR_SHORT_PROT_EN_SHIFT                                   0x06
+#define WCD939X_EAR_OUT_IMPEDANCE_SHIFT                                   0x05
+
+/* WCD939X_EAR_COMPANDER_CTL Fields: */
+#define WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG_SHIFT                     0x07
+#define WCD939X_EAR_COMPANDER_CTL_EAR_GAIN_SHIFT                          0x02
+#define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_BYP_SHIFT                      0x01
+#define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_CLK_EDGE_SHIFT                 0x00
+
+/* WCD939X_TX_CH1 Fields: */
+#define WCD939X_TX_CH1_ENABLE_SHIFT                                       0x07
+#define WCD939X_TX_CH1_PWR_LEVEL_SHIFT                                    0x05
+#define WCD939X_TX_CH1_GAIN_SHIFT                                         0x00
+
+/* WCD939X_TX_CH2 Fields: */
+#define WCD939X_TX_CH2_ENABLE_SHIFT                                       0x07
+#define WCD939X_TX_CH2_HPF1_INIT_SHIFT                                    0x06
+#define WCD939X_TX_CH2_HPF2_INIT_SHIFT                                    0x05
+#define WCD939X_TX_CH2_GAIN_SHIFT                                         0x00
+
+/* WCD939X_TX_CH3 Fields: */
+#define WCD939X_TX_CH3_ENABLE_SHIFT                                       0x07
+#define WCD939X_TX_CH3_PWR_LEVEL_SHIFT                                    0x05
+#define WCD939X_TX_CH3_GAIN_SHIFT                                         0x00
+
+/* WCD939X_TX_CH4 Fields: */
+#define WCD939X_TX_CH4_ENABLE_SHIFT                                       0x07
+#define WCD939X_TX_CH4_HPF3_INIT_SHIFT                                    0x06
+#define WCD939X_TX_CH4_HPF4_INIT_SHIFT                                    0x05
+#define WCD939X_TX_CH4_GAIN_SHIFT                                         0x00
+
+/* WCD939X_MICB1_MICB2_DSP_EN_LOGIC Fields: */
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC_MICB1_DSP_OVERRIDE_SHIFT         0x07
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC_MICB1_DSP_CTRL_SHIFT             0x05
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC_MICB2_DSP_OVERRIDE_SHIFT         0x04
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC_MICB2_DSP_CTRL_SHIFT             0x02
+
+/* WCD939X_MICB3_DSP_EN_LOGIC Fields: */
+#define WCD939X_MICB3_DSP_EN_LOGIC_MICB3_DSP_OVERRIDE_SHIFT               0x07
+#define WCD939X_MICB3_DSP_EN_LOGIC_MICB3_DSP_CTRL_SHIFT                   0x05
+
+/* WCD939X_MBHC_MECH Fields: */
+#define WCD939X_MBHC_MECH_L_DET_EN_SHIFT                                  0x07
+#define WCD939X_MBHC_MECH_GND_DET_EN_SHIFT                                0x06
+#define WCD939X_MBHC_MECH_MECH_DETECT_TYPE_SHIFT                          0x05
+#define WCD939X_MBHC_MECH_HPHL_PLUG_TYPE_SHIFT                            0x04
+#define WCD939X_MBHC_MECH_GND_PLUG_TYPE_SHIFT                             0x03
+#define WCD939X_MBHC_MECH_MECH_HS_L_PULLUP_COMP_EN_SHIFT                  0x02
+#define WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN_SHIFT                  0x01
+#define WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND_SHIFT                    0x00
+
+/* WCD939X_MBHC_ELECT Fields: */
+#define WCD939X_MBHC_ELECT_FSM_EN_SHIFT                                   0x07
+#define WCD939X_MBHC_ELECT_BTNDET_ISRC_CTL_SHIFT                          0x04
+#define WCD939X_MBHC_ELECT_ELECT_DET_TYPE_SHIFT                           0x03
+#define WCD939X_MBHC_ELECT_ELECT_SCHMT_ISRC_CTL_SHIFT                     0x01
+#define WCD939X_MBHC_ELECT_BIAS_EN_SHIFT                                  0x00
+
+/* WCD939X_MBHC_ZDET Fields: */
+#define WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN_SHIFT                            0x07
+#define WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN_SHIFT                            0x06
+#define WCD939X_MBHC_ZDET_ZDET_CHG_EN_SHIFT                               0x05
+#define WCD939X_MBHC_ZDET_ZDET_ILEAK_COMP_EN_SHIFT                        0x04
+#define WCD939X_MBHC_ZDET_ELECT_ISRC_EN_SHIFT                             0x01
+
+/* WCD939X_MBHC_RESULT_1 Fields: */
+#define WCD939X_MBHC_RESULT_1_Z_RESULT_LSB_SHIFT                          0x00
+
+/* WCD939X_MBHC_RESULT_2 Fields: */
+#define WCD939X_MBHC_RESULT_2_Z_RESULT_MSB_SHIFT                          0x00
+
+/* WCD939X_MBHC_RESULT_3 Fields: */
+#define WCD939X_MBHC_RESULT_3_MIC_SCHMT_RESULT_SHIFT                      0x05
+#define WCD939X_MBHC_RESULT_3_IN2P_CLAMP_STATE_SHIFT                      0x04
+#define WCD939X_MBHC_RESULT_3_BTN_RESULT_SHIFT                            0x00
+
+/* WCD939X_MBHC_BTN0 Fields: */
+#define WCD939X_MBHC_BTN0_VTH_SHIFT                                       0x02
+
+/* WCD939X_MBHC_BTN1 Fields: */
+#define WCD939X_MBHC_BTN1_VTH_SHIFT                                       0x02
+
+/* WCD939X_MBHC_BTN2 Fields: */
+#define WCD939X_MBHC_BTN2_VTH_SHIFT                                       0x02
+
+/* WCD939X_MBHC_BTN3 Fields: */
+#define WCD939X_MBHC_BTN3_VTH_SHIFT                                       0x02
+
+/* WCD939X_MBHC_BTN4 Fields: */
+#define WCD939X_MBHC_BTN4_VTH_SHIFT                                       0x02
+
+/* WCD939X_MBHC_BTN5 Fields: */
+#define WCD939X_MBHC_BTN5_VTH_SHIFT                                       0x02
+
+/* WCD939X_MBHC_BTN6 Fields: */
+#define WCD939X_MBHC_BTN6_VTH_SHIFT                                       0x02
+
+/* WCD939X_MBHC_BTN7 Fields: */
+#define WCD939X_MBHC_BTN7_VTH_SHIFT                                       0x02
+
+/* WCD939X_MICB1 Fields: */
+#define WCD939X_MICB1_ENABLE_SHIFT                                        0x06
+#define WCD939X_MICB1_VOUT_CTL_SHIFT                                      0x00
+
+/* WCD939X_MICB2 Fields: */
+#define WCD939X_MICB2_ENABLE_SHIFT                                        0x06
+#define WCD939X_MICB2_VOUT_CTL_SHIFT                                      0x00
+
+/* WCD939X_MICB2_RAMP Fields: */
+#define WCD939X_MICB2_RAMP_RAMP_ENABLE_SHIFT                              0x07
+#define WCD939X_MICB2_RAMP_MB2_IN2P_SHORT_ENABLE_SHIFT                    0x06
+#define WCD939X_MICB2_RAMP_ALLSW_OVRD_ENABLE_SHIFT                        0x05
+#define WCD939X_MICB2_RAMP_SHIFT_CTL_SHIFT                                0x02
+#define WCD939X_MICB2_RAMP_USB_MGDET_MICB2_RAMP_SHIFT                     0x00
+
+/* WCD939X_MICB3 Fields: */
+#define WCD939X_MICB3_ENABLE_SHIFT                                        0x06
+
+/* WCD939X_MICB4 Fields: */
+#define WCD939X_MICB4_ENABLE_SHIFT                                        0x06
+
+
+/* WCD939X_CTL Fields: */
+#define WCD939X_CTL_BG_FAST_MODE_EN_SHIFT                                 0x07
+#define WCD939X_CTL_TX_SCBIAS_REF_SEL_SHIFT                               0x06
+#define WCD939X_CTL_DC_START_UP_EN_SHIFT                                  0x05
+#define WCD939X_CTL_TRAN_START_UP_EN_SHIFT                                0x04
+#define WCD939X_CTL_OTA_BIAS_CTL_SHIFT                                    0x03
+#define WCD939X_CTL_ATEST_CTL_SHIFT                                       0x02
+#define WCD939X_CTL_EFUSE_EN_SHIFT                                        0x01
+
+/* WCD939X_VBG_FINE_ADJ Fields: */
+#define WCD939X_VBG_FINE_ADJ_VBG_FINE_ADJ_SHIFT                           0x04
+#define WCD939X_VBG_FINE_ADJ_EN_DTEST_BG_STATUS_SHIFT                     0x03
+#define WCD939X_VBG_FINE_ADJ_PRECHARGE_TIMER_COUNT_SHIFT                  0x00
+
+
+/* WCD939X_VDDCX_ADJUST Fields: */
+#define WCD939X_VDDCX_ADJUST_RC_ZERO_FREQ_TUNE_SHIFT                      0x02
+#define WCD939X_VDDCX_ADJUST_VDDCX_ADJUST_SHIFT                           0x00
+
+/* WCD939X_DISABLE_LDOL Fields: */
+#define WCD939X_DISABLE_LDOL_DISABLE_LDOL_SHIFT                           0x00
+
+
+/* WCD939X_CTL_CLK Fields: */
+#define WCD939X_CTL_CLK_CLK_SEL_SHIFT                                     0x06
+#define WCD939X_CTL_CLK_COMP_CLK_CTL_SHIFT                                0x04
+#define WCD939X_CTL_CLK_COMP_AZ_CTL_SHIFT                                 0x02
+#define WCD939X_CTL_CLK_TEST_CLK_EN_SHIFT                                 0x01
+#define WCD939X_CTL_CLK_COMP_AVG_BYP_EN_SHIFT                             0x00
+
+/* WCD939X_CTL_ANA Fields: */
+#define WCD939X_CTL_ANA_BIAS_SEL_SHIFT                                    0x07
+
+/* WCD939X_ZDET_VNEG_CTL Fields: */
+#define WCD939X_ZDET_VNEG_CTL_SPARE_BITS_7_6_SHIFT                        0x06
+#define WCD939X_ZDET_VNEG_CTL_VPOS_EN_SHIFT                               0x05
+#define WCD939X_ZDET_VNEG_CTL_VNEGDAC_LDO_EN_SHIFT                        0x04
+#define WCD939X_ZDET_VNEG_CTL_RXBIAS_EN_SHIFT                             0x03
+#define WCD939X_ZDET_VNEG_CTL_VNEG_MODE_SHIFT                             0x02
+#define WCD939X_ZDET_VNEG_CTL_VNEG_EN_SHIFT                               0x01
+#define WCD939X_ZDET_VNEG_CTL_HPH_DISABLE_SHIFT                           0x00
+
+/* WCD939X_ZDET_BIAS_CTL Fields: */
+#define WCD939X_ZDET_BIAS_CTL_ZDET_ILEAK_EN_OVR_SHIFT                     0x07
+#define WCD939X_ZDET_BIAS_CTL_ZDET_ILEAK_COMP_CTL_SHIFT                   0x04
+#define WCD939X_ZDET_BIAS_CTL_ZDET_LDO_IREF_SHIFT                         0x02
+#define WCD939X_ZDET_BIAS_CTL_ZDET_COMP_IREF_SHIFT                        0x00
+
+/* WCD939X_CTL_BCS Fields: */
+#define WCD939X_CTL_BCS_FAST_INT_OVRD_EN_SHIFT                            0x07
+#define WCD939X_CTL_BCS_ELECT_REM_FAST_REG_OVRD_SHIFT                     0x06
+#define WCD939X_CTL_BCS_BTN_RELEASE_FAST_REG_OVRD_SHIFT                   0x05
+#define WCD939X_CTL_BCS_BTN_PRESS_FAST_REG_OVRD_SHIFT                     0x04
+#define WCD939X_CTL_BCS_ANC_DET_EN_SHIFT                                  0x01
+#define WCD939X_CTL_BCS_DEBUG_1_SHIFT                                     0x00
+
+/* WCD939X_MOISTURE_DET_FSM_STATUS Fields: */
+#define WCD939X_MOISTURE_DET_FSM_STATUS_ELECT_IN2P_COMP_SHIFT             0x07
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MECH_HS_G_COMP_SHIFT              0x06
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MECH_HS_M_COMP_SHIFT              0x05
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MECH_HS_L_COMP_SHIFT              0x04
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MOISTURE_INTR_SHIFT               0x03
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MOISTURE_GTPOLLING_STATUS_SHIFT   0x02
+#define WCD939X_MOISTURE_DET_FSM_STATUS_MOISTURE_DET_STATUS_SHIFT         0x01
+#define WCD939X_MOISTURE_DET_FSM_STATUS_ZDET_TIMER_SHIFT                  0x00
+
+/* WCD939X_TEST_CTL Fields: */
+#define WCD939X_TEST_CTL_FAST_DBNC_TIMER_SHIFT                            0x04
+#define WCD939X_TEST_CTL_ATEST_SHIFT                                      0x00
+
+
+/* WCD939X_MODE Fields: */
+#define WCD939X_MODE_LDOH_EN_SHIFT                                        0x07
+#define WCD939X_MODE_PWRDN_STATE_SHIFT                                    0x06
+#define WCD939X_MODE_SLOWRAMP_EN_SHIFT                                    0x05
+#define WCD939X_MODE_VOUT_ADJUST_SHIFT                                    0x03
+#define WCD939X_MODE_VOUT_COARSE_ADJ_SHIFT                                0x00
+
+/* WCD939X_LDOH_BIAS Fields: */
+#define WCD939X_LDOH_BIAS_IBIAS_REF_SHIFT                                 0x05
+#define WCD939X_LDOH_BIAS_IBIAS_ERR_AMP_SHIFT                             0x03
+#define WCD939X_LDOH_BIAS_IBIAS_NATIVE_DEVICE_SHIFT                       0x02
+#define WCD939X_LDOH_BIAS_IBIAS_BUFFER_BLEED_SHIFT                        0x01
+#define WCD939X_LDOH_BIAS_INRUSH_CURRENT_FIX_DIS_SHIFT                    0x00
+
+/* WCD939X_STB_LOADS Fields: */
+#define WCD939X_STB_LOADS_STB_LOADS_1_UA_SHIFT                            0x04
+#define WCD939X_STB_LOADS_STB_LOAD_10_UA_SHIFT                            0x03
+#define WCD939X_STB_LOADS_FORCE_EN_60K_SHIFT                              0x02
+#define WCD939X_STB_LOADS_CLK_GATE_SHIFT                                  0x01
+
+/* WCD939X_SLOWRAMP Fields: */
+#define WCD939X_SLOWRAMP_SLOWRAMP_IBIAS_SHIFT                             0x06
+#define WCD939X_SLOWRAMP_SLOWRAMP_RESET_TIME_SHIFT                        0x04
+
+
+/* WCD939X_TEST_CTL_1 Fields: */
+#define WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL_SHIFT                       0x05
+#define WCD939X_TEST_CTL_1_EN_VREFGEN_SHIFT                               0x04
+#define WCD939X_TEST_CTL_1_EN_LDO_SHIFT                                   0x03
+#define WCD939X_TEST_CTL_1_LDO_BLEEDER_I_CTRL_SHIFT                       0x00
+
+/* WCD939X_TEST_CTL_2 Fields: */
+#define WCD939X_TEST_CTL_2_IBIAS_VREFGEN_SHIFT                            0x06
+#define WCD939X_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_SHIFT                   0x05
+#define WCD939X_TEST_CTL_2_SPAREBIT_SHIFT                                 0x03
+#define WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER_SHIFT                         0x00
+
+/* WCD939X_TEST_CTL_3 Fields: */
+#define WCD939X_TEST_CTL_3_CFILT_REF_EN_SHIFT                             0x07
+#define WCD939X_TEST_CTL_3_RZ_LDO_VAL_SHIFT                               0x04
+#define WCD939X_TEST_CTL_3_IBIAS_LDO_STG3_SHIFT                           0x02
+#define WCD939X_TEST_CTL_3_ATEST_CTRL_SHIFT                               0x00
+
+
+/* WCD939X_MICB2_TEST_CTL_1 Fields: */
+#define WCD939X_MICB2_TEST_CTL_1_NOISE_FILT_RES_VAL_SHIFT                 0x05
+#define WCD939X_MICB2_TEST_CTL_1_EN_VREFGEN_SHIFT                         0x04
+#define WCD939X_MICB2_TEST_CTL_1_EN_LDO_SHIFT                             0x03
+#define WCD939X_MICB2_TEST_CTL_1_LDO_BLEEDER_I_CTRL_SHIFT                 0x00
+
+/* WCD939X_MICB2_TEST_CTL_2 Fields: */
+#define WCD939X_MICB2_TEST_CTL_2_IBIAS_VREFGEN_SHIFT                      0x06
+#define WCD939X_MICB2_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_SHIFT             0x05
+#define WCD939X_MICB2_TEST_CTL_2_SPAREBIT_SHIFT                           0x03
+#define WCD939X_MICB2_TEST_CTL_2_IBIAS_LDO_DRIVER_SHIFT                   0x00
+
+/* WCD939X_MICB2_TEST_CTL_3 Fields: */
+#define WCD939X_MICB2_TEST_CTL_3_CFILT_REF_EN_SHIFT                       0x07
+#define WCD939X_MICB2_TEST_CTL_3_RZ_LDO_VAL_SHIFT                         0x04
+#define WCD939X_MICB2_TEST_CTL_3_IBIAS_LDO_STG3_SHIFT                     0x02
+#define WCD939X_MICB2_TEST_CTL_3_ATEST_CTRL_SHIFT                         0x00
+
+
+/* WCD939X_MICB3_TEST_CTL_1 Fields: */
+#define WCD939X_MICB3_TEST_CTL_1_NOISE_FILT_RES_VAL_SHIFT                 0x05
+#define WCD939X_MICB3_TEST_CTL_1_EN_VREFGEN_SHIFT                         0x04
+#define WCD939X_MICB3_TEST_CTL_1_EN_LDO_SHIFT                             0x03
+#define WCD939X_MICB3_TEST_CTL_1_LDO_BLEEDER_I_CTRL_SHIFT                 0x00
+
+/* WCD939X_MICB3_TEST_CTL_2 Fields: */
+#define WCD939X_MICB3_TEST_CTL_2_IBIAS_VREFGEN_SHIFT                      0x06
+#define WCD939X_MICB3_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_SHIFT             0x05
+#define WCD939X_MICB3_TEST_CTL_2_SPAREBIT_SHIFT                           0x03
+#define WCD939X_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_SHIFT                   0x00
+
+/* WCD939X_MICB3_TEST_CTL_3 Fields: */
+#define WCD939X_MICB3_TEST_CTL_3_CFILT_REF_EN_SHIFT                       0x07
+#define WCD939X_MICB3_TEST_CTL_3_RZ_LDO_VAL_SHIFT                         0x04
+#define WCD939X_MICB3_TEST_CTL_3_IBIAS_LDO_STG3_SHIFT                     0x02
+#define WCD939X_MICB3_TEST_CTL_3_ATEST_CTRL_SHIFT                         0x00
+
+
+/* WCD939X_MICB4_TEST_CTL_1 Fields: */
+#define WCD939X_MICB4_TEST_CTL_1_NOISE_FILT_RES_VAL_SHIFT                 0x05
+#define WCD939X_MICB4_TEST_CTL_1_EN_VREFGEN_SHIFT                         0x04
+#define WCD939X_MICB4_TEST_CTL_1_EN_LDO_SHIFT                             0x03
+#define WCD939X_MICB4_TEST_CTL_1_LDO_BLEEDER_I_CTRL_SHIFT                 0x00
+
+/* WCD939X_MICB4_TEST_CTL_2 Fields: */
+#define WCD939X_MICB4_TEST_CTL_2_IBIAS_VREFGEN_SHIFT                      0x06
+#define WCD939X_MICB4_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS_SHIFT             0x05
+#define WCD939X_MICB4_TEST_CTL_2_SPAREBIT_SHIFT                           0x03
+#define WCD939X_MICB4_TEST_CTL_2_IBIAS_LDO_DRIVER_SHIFT                   0x00
+
+/* WCD939X_MICB4_TEST_CTL_3 Fields: */
+#define WCD939X_MICB4_TEST_CTL_3_CFILT_REF_EN_SHIFT                       0x07
+#define WCD939X_MICB4_TEST_CTL_3_RZ_LDO_VAL_SHIFT                         0x04
+#define WCD939X_MICB4_TEST_CTL_3_IBIAS_LDO_STG3_SHIFT                     0x02
+#define WCD939X_MICB4_TEST_CTL_3_ATEST_CTRL_SHIFT                         0x00
+
+
+/* WCD939X_ADC_VCM Fields: */
+#define WCD939X_ADC_VCM_FLL_ATEST_EN_SHIFT                                0x06
+#define WCD939X_ADC_VCM_VCM_L2_12P288_SHIFT                               0x04
+#define WCD939X_ADC_VCM_VCM_L2_9P6_SHIFT                                  0x02
+#define WCD939X_ADC_VCM_VCM_DEFAULT_SHIFT                                 0x00
+
+/* WCD939X_BIAS_ATEST Fields: */
+#define WCD939X_BIAS_ATEST_TX_CURR_EN_SHIFT                               0x07
+#define WCD939X_BIAS_ATEST_SC_BIAS_EN_SHIFT                               0x06
+#define WCD939X_BIAS_ATEST_SC_BIAS_VREF_SEL_SHIFT                         0x05
+#define WCD939X_BIAS_ATEST_ATEST4_EN_SHIFT                                0x03
+#define WCD939X_BIAS_ATEST_ATEST3_EN_SHIFT                                0x02
+#define WCD939X_BIAS_ATEST_ATEST2_EN_SHIFT                                0x01
+#define WCD939X_BIAS_ATEST_ATEST1_EN_SHIFT                                0x00
+
+/* WCD939X_SPARE1 Fields: */
+#define WCD939X_SPARE1_SPARE_BITS_7_0_SHIFT                               0x00
+
+/* WCD939X_SPARE2 Fields: */
+#define WCD939X_SPARE2_SPARE_BITS_7_0_SHIFT                               0x00
+
+/* WCD939X_TXFE_DIV_CTL Fields: */
+#define WCD939X_TXFE_DIV_CTL_FB_SW_DRIVE_SHIFT                            0x05
+#define WCD939X_TXFE_DIV_CTL_EN_CKGEN_INIT_SHIFT                          0x04
+#define WCD939X_TXFE_DIV_CTL_N_PAUSE_SHIFT                                0x00
+
+/* WCD939X_TXFE_DIV_START Fields: */
+#define WCD939X_TXFE_DIV_START_DIV_SHIFT                                  0x00
+
+/* WCD939X_SPARE3 Fields: */
+#define WCD939X_SPARE3_SPARE_BITS_7_0_SHIFT                               0x00
+
+/* WCD939X_SPARE4 Fields: */
+#define WCD939X_SPARE4_SPARE_BITS_7_0_SHIFT                               0x00
+
+
+/* WCD939X_TEST_EN Fields: */
+#define WCD939X_TEST_EN_TXFE1_EN_SHIFT                                    0x07
+#define WCD939X_TEST_EN_ADC1_EN_SHIFT                                     0x06
+#define WCD939X_TEST_EN_TXFE1_BYPASS_SHIFT                                0x05
+#define WCD939X_TEST_EN_TXFE1_CLK_MODE_SHIFT                              0x04
+#define WCD939X_TEST_EN_TXFE2_EN_SHIFT                                    0x03
+#define WCD939X_TEST_EN_ADC2_EN_SHIFT                                     0x02
+#define WCD939X_TEST_EN_TXFE2_BYPASS_SHIFT                                0x01
+#define WCD939X_TEST_EN_TXFE2_CLK_MODE_SHIFT                              0x00
+
+/* WCD939X_ADC_IB Fields: */
+#define WCD939X_ADC_IB_ADC2_DEM_MODE_SHIFT                                0x06
+#define WCD939X_ADC_IB_ADC2_DEM_OPERATION_SHIFT                           0x04
+#define WCD939X_ADC_IB_L2_DAC_DLY_SHIFT                                   0x02
+#define WCD939X_ADC_IB_DEFAULT_DAC_DLY_SHIFT                              0x00
+
+/* WCD939X_ATEST_REFCTL Fields: */
+#define WCD939X_ATEST_REFCTL_ATEST_CTL_SHIFT                              0x04
+#define WCD939X_ATEST_REFCTL_TXFE_INCM_REF_SHIFT                          0x02
+#define WCD939X_ATEST_REFCTL_TXFE_HP_GAIN_MODE_SHIFT                      0x01
+#define WCD939X_ATEST_REFCTL_ADCREF_ULPRES_EN_SHIFT                       0x00
+
+/* WCD939X_TX_1_2_TEST_CTL Fields: */
+#define WCD939X_TX_1_2_TEST_CTL_TXFE_HP_GAIN_SHIFT                        0x07
+#define WCD939X_TX_1_2_TEST_CTL_REF_CAP_SHIFT                             0x06
+#define WCD939X_TX_1_2_TEST_CTL_ADC1_DEM_MODE_SHIFT                       0x04
+#define WCD939X_TX_1_2_TEST_CTL_ADC1_DEM_OPERATION_SHIFT                  0x02
+#define WCD939X_TX_1_2_TEST_CTL_SAR_ERR_DET_EN_SHIFT                      0x01
+#define WCD939X_TX_1_2_TEST_CTL_SAR_EXT_DELAY_EN_SHIFT                    0x00
+
+/* WCD939X_TEST_BLK_EN1 Fields: */
+#define WCD939X_TEST_BLK_EN1_ADC1_INT1_EN_SHIFT                           0x07
+#define WCD939X_TEST_BLK_EN1_ADC1_INT2_EN_SHIFT                           0x06
+#define WCD939X_TEST_BLK_EN1_ADC1_SAR_EN_SHIFT                            0x05
+#define WCD939X_TEST_BLK_EN1_ADC1_CMGEN_EN_SHIFT                          0x04
+#define WCD939X_TEST_BLK_EN1_ADC1_CLKGEN_EN_SHIFT                         0x03
+#define WCD939X_TEST_BLK_EN1_REF_EN_SHIFT                                 0x02
+#define WCD939X_TEST_BLK_EN1_TXFE1_CLKDIV_EN_SHIFT                        0x01
+#define WCD939X_TEST_BLK_EN1_TXFE2_CLKDIV_EN_SHIFT                        0x00
+
+/* WCD939X_TXFE1_CLKDIV Fields: */
+#define WCD939X_TXFE1_CLKDIV_DIV_SHIFT                                    0x00
+
+/* WCD939X_SAR2_ERR Fields: */
+#define WCD939X_SAR2_ERR_SAR_ERR_COUNT_SHIFT                              0x00
+
+/* WCD939X_SAR1_ERR Fields: */
+#define WCD939X_SAR1_ERR_SAR_ERR_COUNT_SHIFT                              0x00
+
+
+/* WCD939X_TX_3_4_TEST_EN Fields: */
+#define WCD939X_TX_3_4_TEST_EN_TXFE3_EN_SHIFT                             0x07
+#define WCD939X_TX_3_4_TEST_EN_ADC3_EN_SHIFT                              0x06
+#define WCD939X_TX_3_4_TEST_EN_TXFE3_BYPASS_SHIFT                         0x05
+#define WCD939X_TX_3_4_TEST_EN_TXFE3_CLK_MODE_SHIFT                       0x04
+#define WCD939X_TX_3_4_TEST_EN_TXFE4_EN_SHIFT                             0x03
+#define WCD939X_TX_3_4_TEST_EN_ADC4_EN_SHIFT                              0x02
+#define WCD939X_TX_3_4_TEST_EN_TXFE4_BYPASS_SHIFT                         0x01
+#define WCD939X_TX_3_4_TEST_EN_TXFE4_CLK_MODE_SHIFT                       0x00
+
+/* WCD939X_TX_3_4_ADC_IB Fields: */
+#define WCD939X_TX_3_4_ADC_IB_ADC4_DEM_MODE_SHIFT                         0x06
+#define WCD939X_TX_3_4_ADC_IB_ADC4_DEM_OPERATION_SHIFT                    0x04
+#define WCD939X_TX_3_4_ADC_IB_L2_DAC_DLY_SHIFT                            0x02
+#define WCD939X_TX_3_4_ADC_IB_DEFAULT_DAC_DLY_SHIFT                       0x00
+
+/* WCD939X_TX_3_4_ATEST_REFCTL Fields: */
+#define WCD939X_TX_3_4_ATEST_REFCTL_ATEST_CTL_SHIFT                       0x04
+#define WCD939X_TX_3_4_ATEST_REFCTL_TXFE_INCM_REF_SHIFT                   0x02
+#define WCD939X_TX_3_4_ATEST_REFCTL_TXFE_HP_GAIN_MODE_SHIFT               0x01
+#define WCD939X_TX_3_4_ATEST_REFCTL_ADCREF_ULPRES_EN_SHIFT                0x00
+
+/* WCD939X_TX_3_4_TEST_CTL Fields: */
+#define WCD939X_TX_3_4_TEST_CTL_TXFE_HP_GAIN_SHIFT                        0x07
+#define WCD939X_TX_3_4_TEST_CTL_REF_CAP_SHIFT                             0x06
+#define WCD939X_TX_3_4_TEST_CTL_ADC3_DEM_MODE_SHIFT                       0x04
+#define WCD939X_TX_3_4_TEST_CTL_ADC3_DEM_OPERATION_SHIFT                  0x02
+#define WCD939X_TX_3_4_TEST_CTL_SAR_ERR_DET_EN_SHIFT                      0x01
+#define WCD939X_TX_3_4_TEST_CTL_SAR_EXT_DELAY_EN_SHIFT                    0x00
+
+/* WCD939X_TEST_BLK_EN3 Fields: */
+#define WCD939X_TEST_BLK_EN3_ADC3_INT1_EN_SHIFT                           0x07
+#define WCD939X_TEST_BLK_EN3_ADC3_INT2_EN_SHIFT                           0x06
+#define WCD939X_TEST_BLK_EN3_ADC3_SAR_EN_SHIFT                            0x05
+#define WCD939X_TEST_BLK_EN3_ADC3_CMGEN_EN_SHIFT                          0x04
+#define WCD939X_TEST_BLK_EN3_ADC3_CLKGEN_EN_SHIFT                         0x03
+#define WCD939X_TEST_BLK_EN3_REF_EN_SHIFT                                 0x02
+#define WCD939X_TEST_BLK_EN3_TXFE3_CLKDIV_EN_SHIFT                        0x01
+#define WCD939X_TEST_BLK_EN3_TXFE4_CLKDIV_EN_SHIFT                        0x00
+
+/* WCD939X_TXFE3_CLKDIV Fields: */
+#define WCD939X_TXFE3_CLKDIV_DIV_SHIFT                                    0x00
+
+/* WCD939X_SAR4_ERR Fields: */
+#define WCD939X_SAR4_ERR_SAR_ERR_COUNT_SHIFT                              0x00
+
+/* WCD939X_SAR3_ERR Fields: */
+#define WCD939X_SAR3_ERR_SAR_ERR_COUNT_SHIFT                              0x00
+
+/* WCD939X_TEST_BLK_EN2 Fields: */
+#define WCD939X_TEST_BLK_EN2_ADC2_INT1_EN_SHIFT                           0x07
+#define WCD939X_TEST_BLK_EN2_ADC2_INT2_EN_SHIFT                           0x06
+#define WCD939X_TEST_BLK_EN2_ADC2_SAR_EN_SHIFT                            0x05
+#define WCD939X_TEST_BLK_EN2_ADC2_CMGEN_EN_SHIFT                          0x04
+#define WCD939X_TEST_BLK_EN2_ADC2_CLKGEN_EN_SHIFT                         0x03
+#define WCD939X_TEST_BLK_EN2_ADC12_VREF_NONL2_SHIFT                       0x01
+#define WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN_SHIFT                   0x00
+
+/* WCD939X_TXFE2_CLKDIV Fields: */
+#define WCD939X_TXFE2_CLKDIV_DIV_SHIFT                                    0x00
+
+/* WCD939X_TX_3_4_SPARE1 Fields: */
+#define WCD939X_TX_3_4_SPARE1_SPARE_BITS_7_0_SHIFT                        0x00
+
+/* WCD939X_TEST_BLK_EN4 Fields: */
+#define WCD939X_TEST_BLK_EN4_ADC4_INT1_EN_SHIFT                           0x07
+#define WCD939X_TEST_BLK_EN4_ADC4_INT2_EN_SHIFT                           0x06
+#define WCD939X_TEST_BLK_EN4_ADC4_SAR_EN_SHIFT                            0x05
+#define WCD939X_TEST_BLK_EN4_ADC4_CMGEN_EN_SHIFT                          0x04
+#define WCD939X_TEST_BLK_EN4_ADC4_CLKGEN_EN_SHIFT                         0x03
+#define WCD939X_TEST_BLK_EN4_ADC34_VREF_NONL2_SHIFT                       0x01
+#define WCD939X_TEST_BLK_EN4_SPARE_BITS_0_0_SHIFT                         0x00
+
+/* WCD939X_TXFE4_CLKDIV Fields: */
+#define WCD939X_TXFE4_CLKDIV_DIV_SHIFT                                    0x00
+
+/* WCD939X_TX_3_4_SPARE2 Fields: */
+#define WCD939X_TX_3_4_SPARE2_SPARE_BITS_7_0_SHIFT                        0x00
+
+
+/* WCD939X_MODE_1 Fields: */
+#define WCD939X_MODE_1_BUCK_EN_DELAY_SEL_SHIFT                            0x05
+#define WCD939X_MODE_1_BUCK_EN_RESET_BY_EXT_SHIFT                         0x04
+
+/* WCD939X_MODE_2 Fields: */
+#define WCD939X_MODE_2_VREF_I2C_SHIFT                                     0x00
+
+/* WCD939X_MODE_3 Fields: */
+#define WCD939X_MODE_3_DELTA_IPEAK_2VPK_SHIFT                             0x04
+#define WCD939X_MODE_3_DELTA_IPEAK_OVERRIDE_SHIFT                         0x02
+#define WCD939X_MODE_3_CTRL_VREF_BY_SHIFT                                 0x01
+#define WCD939X_MODE_3_MANUAL_PWR_OPT_HPH_SHIFT                           0x00
+
+/* WCD939X_CTRL_VCL_1 Fields: */
+#define WCD939X_CTRL_VCL_1_DELTA_V_SEL_SHIFT                              0x04
+#define WCD939X_CTRL_VCL_1_VDD_BUCK_FILT_2VPK_SHIFT                       0x02
+#define WCD939X_CTRL_VCL_1_VREF_DELTA_GEN_GAIN_SEL_SHIFT                  0x00
+
+/* WCD939X_CTRL_VCL_2 Fields: */
+#define WCD939X_CTRL_VCL_2_VDD_BUCK_FILT_SHIFT                            0x06
+#define WCD939X_CTRL_VCL_2_VREF_FILT_1_SHIFT                              0x04
+#define WCD939X_CTRL_VCL_2_VREF_FILT_2_SHIFT                              0x01
+
+/* WCD939X_CTRL_CCL_1 Fields: */
+#define WCD939X_CTRL_CCL_1_DELTA_IPEAK_SHIFT                              0x04
+#define WCD939X_CTRL_CCL_1_DELTA_IVALLEY_SHIFT                            0x00
+
+/* WCD939X_CTRL_CCL_2 Fields: */
+#define WCD939X_CTRL_CCL_2_CHOOSE_I_LIM_SHIFT                             0x02
+#define WCD939X_CTRL_CCL_2_BUCK_BYPASS_OVERRIDE_SHIFT                     0x01
+#define WCD939X_CTRL_CCL_2_BUCK_BYPASS_EN_SHIFT                           0x00
+
+/* WCD939X_CTRL_CCL_3 Fields: */
+#define WCD939X_CTRL_CCL_3_MIN_PON_SHIFT                                  0x06
+#define WCD939X_CTRL_CCL_3_MIN_NON_SHIFT                                  0x04
+
+/* WCD939X_CTRL_CCL_4 Fields: */
+#define WCD939X_CTRL_CCL_4_P_BLNK_INV1_LOAD_SHIFT                         0x07
+#define WCD939X_CTRL_CCL_4_P_BLNK_INV2_LOAD_SHIFT                         0x06
+#define WCD939X_CTRL_CCL_4_N_BLNK_INV1_LOAD_SHIFT                         0x05
+#define WCD939X_CTRL_CCL_4_N_BLNK_INV2_LOAD_SHIFT                         0x04
+#define WCD939X_CTRL_CCL_4_RST_PW_INV_LOAD_SHIFT                          0x01
+#define WCD939X_CTRL_CCL_4_INZ_RST_SW_CTRL_SHIFT                          0x00
+
+/* WCD939X_CTRL_CCL_5 Fields: */
+#define WCD939X_CTRL_CCL_5_IPK_FRC_RST_SHIFT                              0x05
+
+/* WCD939X_BUCK_TMUX_A_D Fields: */
+#define WCD939X_BUCK_TMUX_A_D_ATEST_SEL_SHIFT                             0x07
+#define WCD939X_BUCK_TMUX_A_D_DTEST_MUX_EN_SHIFT                          0x03
+#define WCD939X_BUCK_TMUX_A_D_DTEST_BRK_4_BRK_3_BRK_2_BRK_1_SHIFT         0x00
+
+/* WCD939X_BUCK_SW_DRV_CNTL Fields: */
+#define WCD939X_BUCK_SW_DRV_CNTL_PSW_DRV_CNTL_SHIFT                       0x04
+#define WCD939X_BUCK_SW_DRV_CNTL_NSW_DRV_CNTL_SHIFT                       0x00
+
+/* WCD939X_SPARE Fields: */
+#define WCD939X_SPARE_CHOOSE_I_LIM_2VPK_SHIFT                             0x02
+
+
+/* WCD939X_EN Fields: */
+#define WCD939X_EN_FLYBACK_EN_DELAY_SEL_SHIFT                             0x05
+#define WCD939X_EN_FLYBACK_EN_RESET_BY_EXT_SHIFT                          0x04
+#define WCD939X_EN_EN_PWSV_SHIFT                                          0x03
+#define WCD939X_EN_EN_CUR_DET_SHIFT                                       0x02
+#define WCD939X_EN_EN_BLEEDER_SHIFT                                       0x01
+#define WCD939X_EN_VREF_PWR_DAC_SEL_OVERRIDE_SHIFT                        0x00
+
+/* WCD939X_VNEG_CTRL_1 Fields: */
+#define WCD939X_VNEG_CTRL_1_VREF_DELTA_GEN_LP_SHIFT                       0x05
+#define WCD939X_VNEG_CTRL_1_VREF_DELTA_GEN_UHQA_SHIFT                     0x02
+#define WCD939X_VNEG_CTRL_1_DRV_PSW_LC_SHIFT                              0x01
+#define WCD939X_VNEG_CTRL_1_DRV_PSW_HC_SHIFT                              0x00
+
+/* WCD939X_VNEG_CTRL_2 Fields: */
+#define WCD939X_VNEG_CTRL_2_MIN_PON_SHIFT                                 0x06
+#define WCD939X_VNEG_CTRL_2_MIN_NON_SHIFT                                 0x05
+#define WCD939X_VNEG_CTRL_2_RST_PW_SHIFT                                  0x04
+#define WCD939X_VNEG_CTRL_2_P_BLNK_SHIFT                                  0x02
+#define WCD939X_VNEG_CTRL_2_N_BLNK_SHIFT                                  0x00
+
+/* WCD939X_VNEG_CTRL_3 Fields: */
+#define WCD939X_VNEG_CTRL_3_EN_IVLY_FRC_RST_SHIFT                         0x04
+#define WCD939X_VNEG_CTRL_3_IVLY_FRC_RST_SHIFT                            0x02
+#define WCD939X_VNEG_CTRL_3_INZ_RDY_CTL_SHIFT                             0x01
+#define WCD939X_VNEG_CTRL_3_INIT_MINPON_CTL_SHIFT                         0x00
+
+/* WCD939X_VNEG_CTRL_4 Fields: */
+#define WCD939X_VNEG_CTRL_4_ILIM_SEL_SHIFT                                0x04
+#define WCD939X_VNEG_CTRL_4_PW_BUF_POS_SHIFT                              0x02
+#define WCD939X_VNEG_CTRL_4_PW_BUF_NEG_SHIFT                              0x00
+
+/* WCD939X_VNEG_CTRL_5 Fields: */
+#define WCD939X_VNEG_CTRL_5_IPK_DELTA_VNEG_LP_SHIFT                       0x04
+#define WCD939X_VNEG_CTRL_5_IPK_DELTA_VNEG_UHQA_SHIFT                     0x00
+
+/* WCD939X_VNEG_CTRL_6 Fields: */
+#define WCD939X_VNEG_CTRL_6_VREF_THIGH_POS_SHIFT                          0x04
+#define WCD939X_VNEG_CTRL_6_VREF_TLOW_POS_SHIFT                           0x00
+
+/* WCD939X_VNEG_CTRL_7 Fields: */
+#define WCD939X_VNEG_CTRL_7_VREF_THIGH_NEG_SHIFT                          0x04
+#define WCD939X_VNEG_CTRL_7_VREF_TLOW_NEG_SHIFT                           0x00
+
+/* WCD939X_VNEG_CTRL_8 Fields: */
+#define WCD939X_VNEG_CTRL_8_SW_POS_EN_DLY_SHIFT                           0x06
+#define WCD939X_VNEG_CTRL_8_SW_NEG_EN_DLY_SHIFT                           0x04
+#define WCD939X_VNEG_CTRL_8_VNEG_EN_DLY_SHIFT                             0x01
+#define WCD939X_VNEG_CTRL_8_EN_IVLYCMP_STATIC_SHIFT                       0x00
+
+/* WCD939X_VNEG_CTRL_9 Fields: */
+#define WCD939X_VNEG_CTRL_9_CUR_DET_TH_SHIFT                              0x06
+#define WCD939X_VNEG_CTRL_9_MAXPON_SEL_SHIFT                              0x03
+#define WCD939X_VNEG_CTRL_9_EN_MAXPON_FRC_SHIFT                           0x02
+#define WCD939X_VNEG_CTRL_9_VREF_PWR_DAC_SEL_SHIFT                        0x01
+
+/* WCD939X_VNEGDAC_CTRL_1 Fields: */
+#define WCD939X_VNEGDAC_CTRL_1_VREF_DAC_DELTA_GEN_LP_SHIFT                0x05
+#define WCD939X_VNEGDAC_CTRL_1_VREF_DAC_DELTA_GEN_UHQA_SHIFT              0x02
+#define WCD939X_VNEGDAC_CTRL_1_N_BLNK_DAC_SHIFT                           0x00
+
+/* WCD939X_VNEGDAC_CTRL_2 Fields: */
+#define WCD939X_VNEGDAC_CTRL_2_VREF_DAC_SEL_SHIFT                         0x05
+#define WCD939X_VNEGDAC_CTRL_2_VNEGDAC_1P8REF_EN_DLY_SHIFT                0x03
+#define WCD939X_VNEGDAC_CTRL_2_VREF_BLEEDER_SHIFT                         0x01
+#define WCD939X_VNEGDAC_CTRL_2_N_ICHRG_BLNK_DAC_SHIFT                     0x00
+
+/* WCD939X_VNEGDAC_CTRL_3 Fields: */
+#define WCD939X_VNEGDAC_CTRL_3_IPK_DELTA_VNEGDAC_LP_SHIFT                 0x04
+#define WCD939X_VNEGDAC_CTRL_3_IPK_DELTA_VNEGDAC_UHQA_SHIFT               0x00
+
+/* WCD939X_CTRL_1 Fields: */
+#define WCD939X_CTRL_1_ICHRG_VREF_SHIFT                                   0x06
+#define WCD939X_CTRL_1_EN_INZCMP_CTL_1_SHIFT                              0x05
+#define WCD939X_CTRL_1_EN_INZCMP_CTL_2_SHIFT                              0x04
+#define WCD939X_CTRL_1_DELTAV_STEP_CTL_SHIFT                              0x03
+#define WCD939X_CTRL_1_EN_MAXNON_FRC_SHIFT                                0x02
+#define WCD939X_CTRL_1_MAXNON_SEL_SHIFT                                   0x00
+
+/* WCD939X_FLYBACK_TEST_CTL Fields: */
+#define WCD939X_FLYBACK_TEST_CTL_DTEST_MUX_SEL_SHIFT                      0x07
+#define WCD939X_FLYBACK_TEST_CTL_ILIM_SEL_2VPK_SHIFT                      0x00
+
+
+/* WCD939X_AUX_SW_CTL Fields: */
+#define WCD939X_AUX_SW_CTL_AUXL_SW_EN_SHIFT                               0x07
+#define WCD939X_AUX_SW_CTL_AUXR_SW_EN_SHIFT                               0x06
+#define WCD939X_AUX_SW_CTL_AUXL2R_SW_EN_SHIFT                             0x05
+
+/* WCD939X_PA_AUX_IN_CONN Fields: */
+#define WCD939X_PA_AUX_IN_CONN_HPHL_AUX_IN_SHIFT                          0x07
+#define WCD939X_PA_AUX_IN_CONN_HPHR_AUX_IN_SHIFT                          0x06
+#define WCD939X_PA_AUX_IN_CONN_EAR_AUX_IN_SHIFT                           0x05
+#define WCD939X_PA_AUX_IN_CONN_SPARE_BITS0_SHIFT                          0x04
+#define WCD939X_PA_AUX_IN_CONN_SPARE_BITS1_SHIFT                          0x01
+#define WCD939X_PA_AUX_IN_CONN_RX_CLK_PHASE_INV_SHIFT                     0x00
+
+/* WCD939X_TIMER_DIV Fields: */
+#define WCD939X_TIMER_DIV_RX_CLK_DIVIDER_OVWT_SHIFT                       0x07
+#define WCD939X_TIMER_DIV_RX_CLK_DIVIDER_SHIFT                            0x00
+
+/* WCD939X_OCP_CTL Fields: */
+#define WCD939X_OCP_CTL_SPARE_BITS_SHIFT                                  0x04
+#define WCD939X_OCP_CTL_N_CONNECTION_ATTEMPTS_SHIFT                       0x00
+
+/* WCD939X_OCP_COUNT Fields: */
+#define WCD939X_OCP_COUNT_RUN_N_CYCLES_SHIFT                              0x04
+#define WCD939X_OCP_COUNT_WAIT_N_CYCLES_SHIFT                             0x00
+
+/* WCD939X_BIAS_EAR_DAC Fields: */
+#define WCD939X_BIAS_EAR_DAC_EAR_DAC_5_UA_SHIFT                           0x04
+#define WCD939X_BIAS_EAR_DAC_ATEST_RX_BIAS_SHIFT                          0x00
+
+/* WCD939X_BIAS_EAR_AMP Fields: */
+#define WCD939X_BIAS_EAR_AMP_EAR_AMP_10_UA_SHIFT                          0x04
+#define WCD939X_BIAS_EAR_AMP_EAR_AMP_5_UA_SHIFT                           0x00
+
+/* WCD939X_BIAS_HPH_LDO Fields: */
+#define WCD939X_BIAS_HPH_LDO_HPH_NVLDO2_5_UA_SHIFT                        0x04
+#define WCD939X_BIAS_HPH_LDO_HPH_NVLDO1_4P5_UA_SHIFT                      0x00
+
+/* WCD939X_BIAS_HPH_PA Fields: */
+#define WCD939X_BIAS_HPH_PA_HPH_CONSTOP_5_UA_SHIFT                        0x04
+#define WCD939X_BIAS_HPH_PA_HPH_AMP_5_UA_SHIFT                            0x00
+
+/* WCD939X_BIAS_HPH_RDACBUFF_CNP2 Fields: */
+#define WCD939X_BIAS_HPH_RDACBUFF_CNP2_RDAC_BUF_3_UA_SHIFT                0x04
+#define WCD939X_BIAS_HPH_RDACBUFF_CNP2_HPH_CNP_10_UA_SHIFT                0x00
+
+/* WCD939X_BIAS_HPH_RDAC_LDO Fields: */
+#define WCD939X_BIAS_HPH_RDAC_LDO_RDAC_LDO_1P65_4_UA_SHIFT                0x04
+#define WCD939X_BIAS_HPH_RDAC_LDO_RDAC_LDO_N1P65_4_UA_SHIFT               0x00
+
+/* WCD939X_BIAS_HPH_CNP1 Fields: */
+#define WCD939X_BIAS_HPH_CNP1_HPH_CNP_4_UA_SHIFT                          0x04
+#define WCD939X_BIAS_HPH_CNP1_HPH_CNP_3_UA_SHIFT                          0x00
+
+/* WCD939X_BIAS_HPH_LOWPOWER Fields: */
+#define WCD939X_BIAS_HPH_LOWPOWER_HPH_AMP_LP_1P5_UA_SHIFT                 0x04
+#define WCD939X_BIAS_HPH_LOWPOWER_RDAC_BUF_LP_0P25_UA_SHIFT               0x00
+
+/* WCD939X_BIAS_AUX_DAC Fields: */
+#define WCD939X_BIAS_AUX_DAC_SPARE_BITS0_SHIFT                            0x04
+#define WCD939X_BIAS_AUX_DAC_SPARE_BITS1_SHIFT                            0x00
+
+/* WCD939X_BIAS_AUX_AMP Fields: */
+#define WCD939X_BIAS_AUX_AMP_SPARE_BITS0_SHIFT                            0x04
+#define WCD939X_BIAS_AUX_AMP_SPARE_BITS1_SHIFT                            0x00
+
+/* WCD939X_BIAS_VNEGDAC_BLEEDER Fields: */
+#define WCD939X_BIAS_VNEGDAC_BLEEDER_BLEEDER_CTRL_SHIFT                   0x04
+
+/* WCD939X_BIAS_MISC Fields: */
+#define WCD939X_BIAS_MISC_SPARE_BITS_SHIFT                                0x00
+
+/* WCD939X_BIAS_BUCK_RST Fields: */
+#define WCD939X_BIAS_BUCK_RST_BUCK_RST_2_UA_SHIFT                         0x00
+
+/* WCD939X_BIAS_BUCK_VREF_ERRAMP Fields: */
+#define WCD939X_BIAS_BUCK_VREF_ERRAMP_BUCK_VREF_1_UA_SHIFT                0x04
+#define WCD939X_BIAS_BUCK_VREF_ERRAMP_BUCK_ERRAMP_1_UA_SHIFT              0x00
+
+/* WCD939X_BIAS_FLYB_ERRAMP Fields: */
+#define WCD939X_BIAS_FLYB_ERRAMP_FLYB_ERRAMP_1_UA_SHIFT                   0x04
+
+/* WCD939X_BIAS_FLYB_BUFF Fields: */
+#define WCD939X_BIAS_FLYB_BUFF_FLYB_VNEG_5_UA_SHIFT                       0x04
+#define WCD939X_BIAS_FLYB_BUFF_FLYB_VPOS_5_UA_SHIFT                       0x00
+
+/* WCD939X_BIAS_FLYB_MID_RST Fields: */
+#define WCD939X_BIAS_FLYB_MID_RST_FLYB_MID_1_UA_SHIFT                     0x04
+#define WCD939X_BIAS_FLYB_MID_RST_FLYB_RST_1_UA_SHIFT                     0x00
+
+
+/* WCD939X_L_STATUS Fields: */
+#define WCD939X_L_STATUS_CMPDR_GAIN_SHIFT                                 0x03
+#define WCD939X_L_STATUS_OCP_COMP_DETECT_SHIFT                            0x02
+#define WCD939X_L_STATUS_OCP_LIMIT_SHIFT                                  0x01
+#define WCD939X_L_STATUS_PA_READY_SHIFT                                   0x00
+
+/* WCD939X_R_STATUS Fields: */
+#define WCD939X_R_STATUS_CMPDR_GAIN_SHIFT                                 0x03
+#define WCD939X_R_STATUS_OCP_COMP_DETECT_SHIFT                            0x02
+#define WCD939X_R_STATUS_OCP_LIMIT_SHIFT                                  0x01
+#define WCD939X_R_STATUS_PA_READY_SHIFT                                   0x00
+
+/* WCD939X_CNP_EN Fields: */
+#define WCD939X_CNP_EN_FSM_CLK_EN_SHIFT                                   0x07
+#define WCD939X_CNP_EN_FSM_RESET_SHIFT                                    0x06
+#define WCD939X_CNP_EN_CNP_IREF_SEL_SHIFT                                 0x05
+#define WCD939X_CNP_EN_FSM_OVERRIDE_EN_SHIFT                              0x03
+#define WCD939X_CNP_EN_WG_LR_SEL_SHIFT                                    0x02
+#define WCD939X_CNP_EN_DBG_CURR_DIRECTION_R_SHIFT                         0x01
+#define WCD939X_CNP_EN_DBG_VREF_EN_SHIFT                                  0x00
+
+/* WCD939X_CNP_WG_CTL Fields: */
+#define WCD939X_CNP_WG_CTL_GM3_BOOST_EN_SHIFT                             0x07
+#define WCD939X_CNP_WG_CTL_NO_PD_SEQU_SHIFT                               0x06
+#define WCD939X_CNP_WG_CTL_VREF_TIMER_SHIFT                               0x03
+#define WCD939X_CNP_WG_CTL_CURR_LDIV_CTL_SHIFT                            0x00
+
+/* WCD939X_CNP_WG_TIME Fields: */
+#define WCD939X_CNP_WG_TIME_WG_FINE_TIMER_SHIFT                           0x00
+
+/* WCD939X_HPH_OCP_CTL Fields: */
+#define WCD939X_HPH_OCP_CTL_OCP_CURR_LIMIT_SHIFT                          0x05
+#define WCD939X_HPH_OCP_CTL_OCP_FSM_EN_SHIFT                              0x04
+#define WCD939X_HPH_OCP_CTL_SPARE_BITS_SHIFT                              0x03
+#define WCD939X_HPH_OCP_CTL_SCD_OP_EN_SHIFT                               0x01
+
+/* WCD939X_AUTO_CHOP Fields: */
+#define WCD939X_AUTO_CHOP_GM3_CASCODE_CTL_2VPK_SHIFT                      0x06
+#define WCD939X_AUTO_CHOP_AUTO_CHOPPER_MODE_SHIFT                         0x05
+#define WCD939X_AUTO_CHOP_GAIN_THRESHOLD_SHIFT                            0x00
+
+/* WCD939X_CHOP_CTL Fields: */
+#define WCD939X_CHOP_CTL_CHOPPER_EN_SHIFT                                 0x07
+#define WCD939X_CHOP_CTL_CLK_INV_SHIFT                                    0x06
+#define WCD939X_CHOP_CTL_SPARE_BITS_SHIFT                                 0x03
+#define WCD939X_CHOP_CTL_DIV2_DIV_BY_2_SHIFT                              0x02
+#define WCD939X_CHOP_CTL_DIV2_DIV_BY_2_4_6_8_SHIFT                        0x00
+
+/* WCD939X_PA_CTL1 Fields: */
+#define WCD939X_PA_CTL1_GM3_IBIAS_CTL_SHIFT                               0x04
+#define WCD939X_PA_CTL1_GM3_IB_SCALE_SHIFT                                0x01
+#define WCD939X_PA_CTL1_SPARE_BITS_SHIFT                                  0x00
+
+/* WCD939X_PA_CTL2 Fields: */
+#define WCD939X_PA_CTL2_SPARE_BITS0_SHIFT                                 0x07
+#define WCD939X_PA_CTL2_HPHPA_GND_R_SHIFT                                 0x06
+#define WCD939X_PA_CTL2_SPARE_BITS1_SHIFT                                 0x05
+#define WCD939X_PA_CTL2_HPHPA_GND_L_SHIFT                                 0x04
+#define WCD939X_PA_CTL2_SPARE_BITS2_SHIFT                                 0x02
+#define WCD939X_PA_CTL2_GM3_CASCODE_CTL_NORMAL_SHIFT                      0x00
+
+/* WCD939X_L_EN Fields: */
+#define WCD939X_L_EN_CONST_SEL_L_SHIFT                                    0x06
+#define WCD939X_L_EN_GAIN_SOURCE_SEL_SHIFT                                0x05
+#define WCD939X_L_EN_SPARE_BITS_SHIFT                                     0x00
+
+/* WCD939X_L_TEST Fields: */
+#define WCD939X_L_TEST_PDN_EN_SHIFT                                       0x07
+#define WCD939X_L_TEST_PDN_AMP2_EN_SHIFT                                  0x06
+#define WCD939X_L_TEST_PDN_AMP_EN_SHIFT                                   0x05
+#define WCD939X_L_TEST_PA_CNP_SW_CONN_SHIFT                               0x04
+#define WCD939X_L_TEST_PA_CNP_SW_OFF_SHIFT                                0x03
+#define WCD939X_L_TEST_PA_CNP_SW_ON_SHIFT                                 0x02
+#define WCD939X_L_TEST_SPARE_BITS_SHIFT                                   0x01
+#define WCD939X_L_TEST_OCP_DET_EN_SHIFT                                   0x00
+
+/* WCD939X_L_ATEST Fields: */
+#define WCD939X_L_ATEST_DACL_REF_ATEST1_CONN_SHIFT                        0x07
+#define WCD939X_L_ATEST_LDO1_L_ATEST2_CONN_SHIFT                          0x06
+#define WCD939X_L_ATEST_LDO_L_ATEST2_CAL_SHIFT                            0x05
+#define WCD939X_L_ATEST_LDO2_L_ATEST2_CONN_SHIFT                          0x04
+#define WCD939X_L_ATEST_HPHPA_GND_OVR_SHIFT                               0x03
+#define WCD939X_L_ATEST_SPARE_BITS_SHIFT                                  0x02
+#define WCD939X_L_ATEST_CNP_EXD2_SHIFT                                    0x01
+#define WCD939X_L_ATEST_CNP_EXD1_SHIFT                                    0x00
+
+/* WCD939X_R_EN Fields: */
+#define WCD939X_R_EN_CONST_SEL_R_SHIFT                                    0x06
+#define WCD939X_R_EN_GAIN_SOURCE_SEL_SHIFT                                0x05
+#define WCD939X_R_EN_SPARE_BITS_SHIFT                                     0x00
+
+/* WCD939X_R_TEST Fields: */
+#define WCD939X_R_TEST_PDN_EN_SHIFT                                       0x07
+#define WCD939X_R_TEST_PDN_AMP2_EN_SHIFT                                  0x06
+#define WCD939X_R_TEST_PDN_AMP_EN_SHIFT                                   0x05
+#define WCD939X_R_TEST_PA_CNP_SW_CONN_SHIFT                               0x04
+#define WCD939X_R_TEST_PA_CNP_SW_OFF_SHIFT                                0x03
+#define WCD939X_R_TEST_PA_CNP_SW_ON_SHIFT                                 0x02
+#define WCD939X_R_TEST_SPARE_BITS_SHIFT                                   0x01
+#define WCD939X_R_TEST_OCP_DET_EN_SHIFT                                   0x00
+
+/* WCD939X_R_ATEST Fields: */
+#define WCD939X_R_ATEST_DACR_REF_ATEST1_CONN_SHIFT                        0x07
+#define WCD939X_R_ATEST_LDO1_R_ATEST2_CONN_SHIFT                          0x06
+#define WCD939X_R_ATEST_LDO_R_ATEST2_CAL_SHIFT                            0x05
+#define WCD939X_R_ATEST_LDO2_R_ATEST2_CONN_SHIFT                          0x04
+#define WCD939X_R_ATEST_LDO_1P65V_ATEST1_CONN_SHIFT                       0x03
+#define WCD939X_R_ATEST_SPARE_BITS0_SHIFT                                 0x02
+#define WCD939X_R_ATEST_HPH_GND_OVR_SHIFT                                 0x01
+#define WCD939X_R_ATEST_SPARE_BITS1_SHIFT                                 0x00
+
+/* WCD939X_RDAC_CLK_CTL1 Fields: */
+#define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_SHIFT                     0x07
+#define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_DIV_CTRL_SHIFT               0x04
+#define WCD939X_RDAC_CLK_CTL1_SPARE_BITS_SHIFT                            0x00
+
+/* WCD939X_RDAC_CLK_CTL2 Fields: */
+#define WCD939X_RDAC_CLK_CTL2_SPARE_BITS_SHIFT                            0x04
+#define WCD939X_RDAC_CLK_CTL2_PREREF_SC_CLK_EN_SHIFT                      0x03
+#define WCD939X_RDAC_CLK_CTL2_PREREF_SC_CLK_DIVIDER_CTRL_SHIFT            0x00
+
+/* WCD939X_RDAC_LDO_CTL Fields: */
+#define WCD939X_RDAC_LDO_CTL_LDO_1P65_BYPASS_SHIFT                        0x07
+#define WCD939X_RDAC_LDO_CTL_LDO_1P65_OUTCTL_SHIFT                        0x04
+#define WCD939X_RDAC_LDO_CTL_N1P65V_LDO_BYPASS_SHIFT                      0x03
+#define WCD939X_RDAC_LDO_CTL_N1P65_LDO_OUTCTL_SHIFT                       0x00
+
+/* WCD939X_RDAC_CHOP_CLK_LP_CTL Fields: */
+#define WCD939X_RDAC_CHOP_CLK_LP_CTL_OPAMP_CHOP_CLK_EN_LP_SHIFT           0x07
+#define WCD939X_RDAC_CHOP_CLK_LP_CTL_SPARE_BITS_SHIFT                     0x00
+
+/* WCD939X_REFBUFF_UHQA_CTL Fields: */
+#define WCD939X_REFBUFF_UHQA_CTL_SPARE_BITS_SHIFT                         0x06
+#define WCD939X_REFBUFF_UHQA_CTL_HPH_VNEGREG2_COMP_CTL_OV_SHIFT           0x05
+#define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_RBIAS_ADJUST_SHIFT               0x04
+#define WCD939X_REFBUFF_UHQA_CTL_REFBUFP_IOUT_CTL_SHIFT                   0x02
+#define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_IOUT_CTL_SHIFT                   0x00
+
+/* WCD939X_REFBUFF_LP_CTL Fields: */
+#define WCD939X_REFBUFF_LP_CTL_HPH_VNEGREG2_CURR_COMP_SHIFT               0x06
+#define WCD939X_REFBUFF_LP_CTL_SPARE_BITS_SHIFT                           0x04
+#define WCD939X_REFBUFF_LP_CTL_EN_PREREF_FILT_STARTUP_CLKDIV_SHIFT        0x03
+#define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_STARTUP_CLKDIV_CTL_SHIFT       0x01
+#define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS_SHIFT                   0x00
+
+/* WCD939X_L_DAC_CTL Fields: */
+#define WCD939X_L_DAC_CTL_SPARE_BITS_SHIFT                                0x07
+#define WCD939X_L_DAC_CTL_DAC_REF_EN_SHIFT                                0x06
+#define WCD939X_L_DAC_CTL_DAC_SAMPLE_EDGE_SELECT_SHIFT                    0x05
+#define WCD939X_L_DAC_CTL_DATA_RESET_SHIFT                                0x04
+#define WCD939X_L_DAC_CTL_INV_DATA_SHIFT                                  0x03
+#define WCD939X_L_DAC_CTL_DAC_L_EN_OV_SHIFT                               0x02
+#define WCD939X_L_DAC_CTL_DAC_LDO_UHQA_OV_SHIFT                           0x01
+#define WCD939X_L_DAC_CTL_DAC_LDO_POWERMODE_SHIFT                         0x00
+
+/* WCD939X_R_DAC_CTL Fields: */
+#define WCD939X_R_DAC_CTL_SPARE_BITS_SHIFT                                0x07
+#define WCD939X_R_DAC_CTL_DAC_REF_EN_SHIFT                                0x06
+#define WCD939X_R_DAC_CTL_DAC_SAMPLE_EDGE_SELECT_SHIFT                    0x05
+#define WCD939X_R_DAC_CTL_DATA_RESET_SHIFT                                0x04
+#define WCD939X_R_DAC_CTL_INV_DATA_SHIFT                                  0x03
+#define WCD939X_R_DAC_CTL_DAC_R_EN_OV_SHIFT                               0x02
+#define WCD939X_R_DAC_CTL_DAC_PREREF_UHQA_OV_SHIFT                        0x01
+#define WCD939X_R_DAC_CTL_DAC_PREREF_POWERMODE_SHIFT                      0x00
+
+
+/* WCD939X_HPHLR_SURGE_COMP_SEL Fields: */
+#define WCD939X_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHL_PSURGE_SHIFT       0x06
+#define WCD939X_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHL_NSURGE_SHIFT       0x04
+#define WCD939X_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHR_PSURGE_SHIFT       0x02
+#define WCD939X_HPHLR_SURGE_COMP_SEL_COMP_REF_SEL_HPHR_NSURGE_SHIFT       0x00
+
+/* WCD939X_HPHLR_SURGE_EN Fields: */
+#define WCD939X_HPHLR_SURGE_EN_EN_SURGE_PROTECTION_HPHL_SHIFT             0x07
+#define WCD939X_HPHLR_SURGE_EN_EN_SURGE_PROTECTION_HPHR_SHIFT             0x06
+#define WCD939X_HPHLR_SURGE_EN_SEL_SURGE_COMP_IQ_SHIFT                    0x04
+#define WCD939X_HPHLR_SURGE_EN_SURGE_VOLT_MODE_SHUTOFF_EN_SHIFT           0x03
+#define WCD939X_HPHLR_SURGE_EN_LATCH_INTR_OP_STG_HIZ_EN_SHIFT             0x02
+#define WCD939X_HPHLR_SURGE_EN_SURGE_LATCH_REG_RESET_SHIFT                0x01
+#define WCD939X_HPHLR_SURGE_EN_SWTICH_VN_VNDAC_NSURGE_EN_SHIFT            0x00
+
+/* WCD939X_HPHLR_SURGE_MISC1 Fields: */
+#define WCD939X_HPHLR_SURGE_MISC1_EN_VNEG_PULLDN_SHIFT                    0x07
+#define WCD939X_HPHLR_SURGE_MISC1_EN_OFFSET_36MV_NSURGE_RESLADDER_SHIFT   0x06
+#define WCD939X_HPHLR_SURGE_MISC1_EN_NMOS_LAMP_SHIFT                      0x05
+#define WCD939X_HPHLR_SURGE_MISC1_EN_NCLAMP_REG_HPHL_SHIFT                0x04
+#define WCD939X_HPHLR_SURGE_MISC1_EN_NCLAMP_REG_HPHR_SHIFT                0x03
+#define WCD939X_HPHLR_SURGE_MISC1_SPARE_BITS_SHIFT                        0x00
+
+/* WCD939X_HPHLR_SURGE_STATUS Fields: */
+#define WCD939X_HPHLR_SURGE_STATUS_HPHL_CLAMP_SW_STATUS_SHIFT             0x07
+#define WCD939X_HPHLR_SURGE_STATUS_HPHR_CLAMP_SW_STATUS_SHIFT             0x06
+#define WCD939X_HPHLR_SURGE_STATUS_HPHL_PSURGE_COMP_STATUS_SHIFT          0x05
+#define WCD939X_HPHLR_SURGE_STATUS_HPHL_NSURGE_COMP_STATUS_SHIFT          0x04
+#define WCD939X_HPHLR_SURGE_STATUS_HPHR_PSURGE_COMP_STATUS_SHIFT          0x03
+#define WCD939X_HPHLR_SURGE_STATUS_HPHR_NSURGE_COMP_STATUS_SHIFT          0x02
+#define WCD939X_HPHLR_SURGE_STATUS_HPHL_SURGE_DET_INTR_EN_SHIFT           0x01
+#define WCD939X_HPHLR_SURGE_STATUS_HPHR_SURGE_DET_INTR_EN_SHIFT           0x00
+
+
+/* WCD939X_EAR_EN_REG Fields: */
+#define WCD939X_EAR_EN_REG_EAR_DAC_DATA_RESET_SHIFT                       0x07
+#define WCD939X_EAR_EN_REG_EAR_DAC_DATA_EN_SHIFT                          0x06
+#define WCD939X_EAR_EN_REG_EAR_DAC_REF_EN_SHIFT                           0x05
+#define WCD939X_EAR_EN_REG_EAR_VCM_EN_SHIFT                               0x04
+#define WCD939X_EAR_EN_REG_EAR_AMP_EN_SHIFT                               0x03
+#define WCD939X_EAR_EN_REG_EAR_BIAS_EN_SHIFT                              0x02
+#define WCD939X_EAR_EN_REG_EAR_CNP_FSM_EN_SHIFT                           0x01
+#define WCD939X_EAR_EN_REG_EAR_OUTPUT_SHORT_SHIFT                         0x00
+
+/* WCD939X_EAR_PA_CON Fields: */
+#define WCD939X_EAR_PA_CON_EAR_ANA_AUX_EN_SHIFT                           0x07
+#define WCD939X_EAR_PA_CON_EAR_CMFB_SF_BYPASS_SHIFT                       0x06
+#define WCD939X_EAR_PA_CON_EAR_SF_CURR_SHIFT                              0x05
+#define WCD939X_EAR_PA_CON_EAR_BTI_CTL_SHIFT                              0x04
+#define WCD939X_EAR_PA_CON_EAR_GM3_IBIAS_CTL_SHIFT                        0x00
+
+/* WCD939X_EAR_SP_CON Fields: */
+#define WCD939X_EAR_SP_CON_EAR_SP_INT_EN_SHIFT                            0x07
+#define WCD939X_EAR_SP_CON_EAR_SP_AUTO_SHT_DWN_SHIFT                      0x06
+#define WCD939X_EAR_SP_CON_SP_LIMIT_CURR_NMOS_SHIFT                       0x03
+#define WCD939X_EAR_SP_CON_SP_LIMIT_CURR_PMOS_SHIFT                       0x00
+
+/* WCD939X_EAR_DAC_CON Fields: */
+#define WCD939X_EAR_DAC_CON_DAC_SAMPLE_EDGE_SEL_SHIFT                     0x07
+#define WCD939X_EAR_DAC_CON_REF_DBG_EN_SHIFT                              0x06
+#define WCD939X_EAR_DAC_CON_REF_DBG_GAIN_SHIFT                            0x03
+#define WCD939X_EAR_DAC_CON_GAIN_DAC_SHIFT                                0x01
+#define WCD939X_EAR_DAC_CON_INV_DATA_SHIFT                                0x00
+
+/* WCD939X_EAR_CNP_FSM_CON Fields: */
+#define WCD939X_EAR_CNP_FSM_CON_CNP_FSM_CLK_DIV1_SHIFT                    0x04
+#define WCD939X_EAR_CNP_FSM_CON_CNP_FSM_CLK_DIV2_SHIFT                    0x02
+#define WCD939X_EAR_CNP_FSM_CON_SCD_FSM_DEGLITCH_SEL_SHIFT                0x00
+
+/* WCD939X_EAR_TEST_CTL Fields: */
+#define WCD939X_EAR_TEST_CTL_DTEST_EN_SHIFT                               0x07
+#define WCD939X_EAR_TEST_CTL_DTEST_SEL_2_SHIFT                            0x06
+#define WCD939X_EAR_TEST_CTL_EAR_RDAC_ATEST_EN_SHIFT                      0x05
+#define WCD939X_EAR_TEST_CTL_EAR_PA_ATEST_SEL_SHIFT                       0x00
+
+/* WCD939X_STATUS_REG_1 Fields: */
+#define WCD939X_STATUS_REG_1_SP_INT_SHIFT                                 0x07
+#define WCD939X_STATUS_REG_1_SP_ALL_OUT_SHIFT                             0x06
+#define WCD939X_STATUS_REG_1_SP_NMOS_OUT_SHIFT                            0x05
+#define WCD939X_STATUS_REG_1_SP_PMOS_OUT_SHIFT                            0x04
+#define WCD939X_STATUS_REG_1_PA_READY_SHIFT                               0x03
+#define WCD939X_STATUS_REG_1_CNP_FSM_STATUS_SHIFT                         0x02
+
+/* WCD939X_STATUS_REG_2 Fields: */
+#define WCD939X_STATUS_REG_2_PA_EN_SHIFT                                  0x07
+#define WCD939X_STATUS_REG_2_BIAS_EN_SHIFT                                0x06
+#define WCD939X_STATUS_REG_2_DAC_EN_SHIFT                                 0x05
+#define WCD939X_STATUS_REG_2_VCM_EN_SHIFT                                 0x04
+#define WCD939X_STATUS_REG_2_CLK_EN_SHIFT                                 0x03
+#define WCD939X_STATUS_REG_2_SCD_EN_SHIFT                                 0x02
+#define WCD939X_STATUS_REG_2_SHORT_EN_SHIFT                               0x01
+#define WCD939X_STATUS_REG_2_DAC_RESET_SHIFT                              0x00
+
+
+/* WCD939X_ANA_NEW_PAGE Fields: */
+#define WCD939X_ANA_NEW_PAGE_VALUE_SHIFT                                  0x00
+
+
+/* WCD939X_ANA_HPH2 Fields: */
+#define WCD939X_ANA_HPH2_HIFI_2VPK_PA_GAIN_CTL_SHIFT                      0x07
+#define WCD939X_ANA_HPH2_ULP_VREF_CTL_SHIFT                               0x06
+#define WCD939X_ANA_HPH2_SPARE_BITS_SHIFT                                 0x00
+
+/* WCD939X_ANA_HPH3 Fields: */
+#define WCD939X_ANA_HPH3_SPARE_BITS_SHIFT                                 0x00
+
+
+/* WCD939X_SLEEP_CTL Fields: */
+#define WCD939X_SLEEP_CTL_SPARE_BITS_SHIFT                                0x07
+#define WCD939X_SLEEP_CTL_LDOL_BG_SEL_SHIFT                               0x04
+#define WCD939X_SLEEP_CTL_BG_CTL_SHIFT                                    0x01
+#define WCD939X_SLEEP_CTL_DTEST_EN_SHIFT                                  0x00
+
+/* WCD939X_WATCHDOG_CTL Fields: */
+#define WCD939X_WATCHDOG_CTL_EN_WATCHDOG_SHIFT                            0x07
+#define WCD939X_WATCHDOG_CTL_EN_WATCHDOG_VREFGEN_SHIFT                    0x06
+#define WCD939X_WATCHDOG_CTL_BYPASS_WATCHDOG_SHIFT                        0x05
+#define WCD939X_WATCHDOG_CTL_ATEST_CTL_SHIFT                              0x02
+
+
+/* WCD939X_ELECT_REM_CLAMP_CTL Fields: */
+#define WCD939X_ELECT_REM_CLAMP_CTL_FSM_ELECT_CLAMP_EN_SHIFT              0x07
+#define WCD939X_ELECT_REM_CLAMP_CTL_SLNQ_ELECT_CLAMP_EN_SHIFT             0x06
+#define WCD939X_ELECT_REM_CLAMP_CTL_SLNQ_FAIL_CLAMP_EN_SHIFT              0x05
+#define WCD939X_ELECT_REM_CLAMP_CTL_SLNQ_ELECT_REM_RST_SHIFT              0x04
+
+/* WCD939X_CTL_1 Fields: */
+#define WCD939X_CTL_1_RCO_EN_SHIFT                                        0x07
+#define WCD939X_CTL_1_ADC_MODE_SHIFT                                      0x04
+#define WCD939X_CTL_1_ADC_ENABLE_SHIFT                                    0x03
+#define WCD939X_CTL_1_DETECTION_DONE_SHIFT                                0x02
+#define WCD939X_CTL_1_BTN_DBNC_CTL_SHIFT                                  0x00
+
+/* WCD939X_CTL_2 Fields: */
+#define WCD939X_CTL_2_MUX_CTL_SHIFT                                       0x04
+#define WCD939X_CTL_2_M_RTH_CTL_SHIFT                                     0x02
+#define WCD939X_CTL_2_HS_VREF_CTL_SHIFT                                   0x00
+
+/* WCD939X_PLUG_DETECT_CTL Fields: */
+#define WCD939X_PLUG_DETECT_CTL_SPARE_BITS_7_6_SHIFT                      0x06
+#define WCD939X_PLUG_DETECT_CTL_MIC_CLAMP_CTL_SHIFT                       0x04
+#define WCD939X_PLUG_DETECT_CTL_INSREM_DBNC_CTL_SHIFT                     0x00
+
+/* WCD939X_ZDET_ANA_CTL Fields: */
+#define WCD939X_ZDET_ANA_CTL_AVERAGING_EN_SHIFT                           0x07
+#define WCD939X_ZDET_ANA_CTL_ZDET_MAXV_CTL_SHIFT                          0x04
+#define WCD939X_ZDET_ANA_CTL_ZDET_RANGE_CTL_SHIFT                         0x00
+
+/* WCD939X_ZDET_RAMP_CTL Fields: */
+#define WCD939X_ZDET_RAMP_CTL_ZDET_ACC1_MIN_CTL_SHIFT                     0x04
+#define WCD939X_ZDET_RAMP_CTL_ZDET_RAMP_TIME_CTL_SHIFT                    0x00
+
+/* WCD939X_FSM_STATUS Fields: */
+#define WCD939X_FSM_STATUS_ADC_TIMEOUT_SHIFT                              0x07
+#define WCD939X_FSM_STATUS_ADC_COMPLETE_SHIFT                             0x06
+#define WCD939X_FSM_STATUS_HS_M_COMP_STATUS_SHIFT                         0x05
+#define WCD939X_FSM_STATUS_FAST_PRESS_FLAG_STATUS_SHIFT                   0x04
+#define WCD939X_FSM_STATUS_FAST_REMOVAL_FLAG_STATUS_SHIFT                 0x03
+#define WCD939X_FSM_STATUS_REMOVAL_FLAG_STATUS_SHIFT                      0x02
+#define WCD939X_FSM_STATUS_ELECT_REM_RT_STATUS_SHIFT                      0x01
+#define WCD939X_FSM_STATUS_BTN_STATUS_SHIFT                               0x00
+
+/* WCD939X_ADC_RESULT Fields: */
+#define WCD939X_ADC_RESULT_ADC_RESULT_SHIFT                               0x00
+
+
+/* WCD939X_TX_CH12_MUX Fields: */
+#define WCD939X_TX_CH12_MUX_SPARE_BITS_SHIFT                              0x06
+#define WCD939X_TX_CH12_MUX_CH2_SEL_SHIFT                                 0x03
+#define WCD939X_TX_CH12_MUX_CH1_SEL_SHIFT                                 0x00
+
+/* WCD939X_TX_CH34_MUX Fields: */
+#define WCD939X_TX_CH34_MUX_SPARE_BITS_SHIFT                              0x06
+#define WCD939X_TX_CH34_MUX_CH4_SEL_SHIFT                                 0x03
+#define WCD939X_TX_CH34_MUX_CH3_SEL_SHIFT                                 0x00
+
+
+/* WCD939X_DIE_CRK_DET_EN Fields: */
+#define WCD939X_DIE_CRK_DET_EN_DIE_CRK_DET_EN_SHIFT                       0x07
+#define WCD939X_DIE_CRK_DET_EN_SEL_CURR_INJCT_PT_MRING_SHIFT              0x06
+
+/* WCD939X_DIE_CRK_DET_OUT Fields: */
+#define WCD939X_DIE_CRK_DET_OUT_DIE_CRK_DET_OUT_SHIFT                     0x07
+
+
+/* WCD939X_RDAC_GAIN_CTL Fields: */
+#define WCD939X_RDAC_GAIN_CTL_SPARE_BITS_SHIFT                            0x00
+
+/* WCD939X_PA_GAIN_CTL_L Fields: */
+#define WCD939X_PA_GAIN_CTL_L_EN_HPHPA_2VPK_SHIFT                         0x07
+#define WCD939X_PA_GAIN_CTL_L_RX_SUPPLY_LEVEL_SHIFT                       0x06
+#define WCD939X_PA_GAIN_CTL_L_DAC_DR_BOOST_SHIFT                          0x05
+#define WCD939X_PA_GAIN_CTL_L_PA_GAIN_L_SHIFT                             0x00
+
+/* WCD939X_RDAC_VREF_CTL Fields: */
+#define WCD939X_RDAC_VREF_CTL_DAC_REF_EFUSE_TUNE_EN_SHIFT                 0x07
+#define WCD939X_RDAC_VREF_CTL_DAC_VREFN_TUNE_SHIFT                        0x04
+#define WCD939X_RDAC_VREF_CTL_REFCURRENT_2UA_SHIFT                        0x03
+#define WCD939X_RDAC_VREF_CTL_DAC_VREFP_TUNE_SHIFT                        0x00
+
+/* WCD939X_RDAC_OVERRIDE_CTL Fields: */
+#define WCD939X_RDAC_OVERRIDE_CTL_VDDRX_LDO_LIFT_BYPASS_SHIFT             0x07
+#define WCD939X_RDAC_OVERRIDE_CTL_REFBUF_IREF_OVRIDE_SHIFT                0x06
+#define WCD939X_RDAC_OVERRIDE_CTL_SPARE_BITS1_SHIFT                       0x04
+#define WCD939X_RDAC_OVERRIDE_CTL_RDAC_IDLE_DETECT_OVERRIDE_SHIFT         0x03
+#define WCD939X_RDAC_OVERRIDE_CTL_SPARE_BITS2_SHIFT                       0x00
+
+/* WCD939X_PA_GAIN_CTL_R Fields: */
+#define WCD939X_PA_GAIN_CTL_R_D_RCO_CLK_EN_SHIFT                          0x07
+#define WCD939X_PA_GAIN_CTL_R_SPARE_BITS_SHIFT                            0x05
+#define WCD939X_PA_GAIN_CTL_R_PA_GAIN_R_SHIFT                             0x00
+
+/* WCD939X_PA_MISC1 Fields: */
+#define WCD939X_PA_MISC1_EN_AUTO_CMPDR_DETECTION_SHIFT                    0x07
+#define WCD939X_PA_MISC1_EN_PA_IDLE_DETECT_OVERRIDE_SHIFT                 0x06
+#define WCD939X_PA_MISC1_D_PZ_INF_EN_SHIFT                                0x05
+#define WCD939X_PA_MISC1_HPHPA_BW_PROG_SHIFT                              0x03
+#define WCD939X_PA_MISC1_PA_CHOP_EN_OVERRIDE_SHIFT                        0x02
+#define WCD939X_PA_MISC1_OCP_FSM_LOCK_EN_SHIFT                            0x01
+#define WCD939X_PA_MISC1_AUTOCHOP_PDN_SEQ_OVERRIDE_SHIFT                  0x00
+
+/* WCD939X_PA_MISC2 Fields: */
+#define WCD939X_PA_MISC2_HPHPA_HI_Z_SHIFT                                 0x07
+#define WCD939X_PA_MISC2_HPH_PSRR_ENH_SHIFT                               0x06
+#define WCD939X_PA_MISC2_FORCE_IQCTRL_SHIFT                               0x05
+#define WCD939X_PA_MISC2_FORCE_PSRREH_SHIFT                               0x04
+#define WCD939X_PA_MISC2_CHOP_CLKLAP_SEL_SHIFT                            0x03
+#define WCD939X_PA_MISC2_SPARE_BITS_SHIFT                                 0x02
+#define WCD939X_PA_MISC2_IDLE_DETECT_L_DTEST_ENABLE_SHIFT                 0x01
+#define WCD939X_PA_MISC2_IDLE_DETECT_R_DTEST_ENABLE_SHIFT                 0x00
+
+/* WCD939X_PA_RDAC_MISC Fields: */
+#define WCD939X_PA_RDAC_MISC_CNP_WG_FINE_TIME_LSB_CTL_SHIFT               0x04
+#define WCD939X_PA_RDAC_MISC_RDAC_NSW_REG_CTL_SHIFT                       0x03
+#define WCD939X_PA_RDAC_MISC_RDAC_PSW_NSW_CTL_OVERRIDE_SHIFT              0x02
+#define WCD939X_PA_RDAC_MISC_RDAC_PSW_NSW_REG_CTL_SHIFT                   0x00
+
+/* WCD939X_HPH_TIMER1 Fields: */
+#define WCD939X_HPH_TIMER1_CURR_IDIV_CTL_CMPDR_OFF_SHIFT                  0x05
+#define WCD939X_HPH_TIMER1_CURR_IDIV_CTL_AUTOCHOP_SHIFT                   0x02
+#define WCD939X_HPH_TIMER1_AUTOCHOP_TIMER_CTL_EN_SHIFT                    0x01
+#define WCD939X_HPH_TIMER1_SPARE_BITS_SHIFT                               0x00
+
+/* WCD939X_HPH_TIMER2 Fields: */
+#define WCD939X_HPH_TIMER2_VREF_TIMER_IDLESTATE_SHIFT                     0x05
+#define WCD939X_HPH_TIMER2_CNP_WG_FINE_TIME_LSB_CTL_IDLE_SHIFT            0x01
+#define WCD939X_HPH_TIMER2_SPARE_BITS_SHIFT                               0x00
+
+/* WCD939X_HPH_TIMER3 Fields: */
+#define WCD939X_HPH_TIMER3_WG_FINE_TIMER_CMPDR_OFF_SHIFT                  0x00
+
+/* WCD939X_HPH_TIMER4 Fields: */
+#define WCD939X_HPH_TIMER4_WG_FINE_TIMER_AUTOCHOP_SHIFT                   0x00
+
+/* WCD939X_PA_RDAC_MISC2 Fields: */
+#define WCD939X_PA_RDAC_MISC2_SPARE_BITS_SHIFT                            0x05
+#define WCD939X_PA_RDAC_MISC2_RDAC_DNW_RES_FORCE_BYPASS_SHIFT             0x04
+#define WCD939X_PA_RDAC_MISC2_SCLPF_BYPASS_TIMER_STG1_SHIFT               0x02
+#define WCD939X_PA_RDAC_MISC2_SCLPF_BYPASS_TIMER_STG2_SHIFT               0x00
+
+/* WCD939X_PA_RDAC_MISC3 Fields: */
+#define WCD939X_PA_RDAC_MISC3_SPARE_BITS_SHIFT                            0x00
+
+/* WCD939X_RDAC_HD2_CTL_L Fields: */
+#define WCD939X_RDAC_HD2_CTL_L_EN_HD2_RES_DIV_L_SHIFT                     0x07
+#define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_PULLGND_L_SHIFT                0x06
+#define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_SHIFT                    0x00
+
+/* WCD939X_RDAC_HD2_CTL_R Fields: */
+#define WCD939X_RDAC_HD2_CTL_R_EN_HD2_RES_DIV_R_SHIFT                     0x07
+#define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_PULLGND_L_SHIFT                0x06
+#define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_SHIFT                    0x00
+
+
+/* WCD939X_HPH_RDAC_BIAS_LOHIFI Fields: */
+#define WCD939X_HPH_RDAC_BIAS_LOHIFI_HPHPA_BIAS_LOHIFI_SHIFT              0x04
+#define WCD939X_HPH_RDAC_BIAS_LOHIFI_HPHRDAC_BIAS_LOHIFI_SHIFT            0x00
+
+/* WCD939X_HPH_RDAC_BIAS_ULP Fields: */
+#define WCD939X_HPH_RDAC_BIAS_ULP_SLEEPBG_PWR_SEL_SHIFT                   0x07
+#define WCD939X_HPH_RDAC_BIAS_ULP_SLEEPBG_PWR_SEL_OVERRIDE_SHIFT          0x06
+#define WCD939X_HPH_RDAC_BIAS_ULP_CDC_3P5MM_LEGACY_IN_SHIFT               0x05
+#define WCD939X_HPH_RDAC_BIAS_ULP_SPARE_BITS1_SHIFT                       0x04
+#define WCD939X_HPH_RDAC_BIAS_ULP_HPHRDAC_BIAS_ULP_SHIFT                  0x00
+
+/* WCD939X_HPH_RDAC_LDO_LP Fields: */
+#define WCD939X_HPH_RDAC_LDO_LP_HPHRDAC_1P6VLDO_BIAS_LP_SHIFT             0x04
+#define WCD939X_HPH_RDAC_LDO_LP_HPHRDAC_N1P6VLDO_BIAS_LP_SHIFT            0x00
+
+
+/* WCD939X_MOISTURE_DET_DC_CTRL Fields: */
+#define WCD939X_MOISTURE_DET_DC_CTRL_ONCOUNT_SHIFT                        0x05
+#define WCD939X_MOISTURE_DET_DC_CTRL_OFFCOUNT_SHIFT                       0x00
+
+/* WCD939X_MOISTURE_DET_POLLING_CTRL Fields: */
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_HPHL_PA_EN_SHIFT                0x06
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_DTEST_EN_SHIFT                  0x04
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOISTURE_OVRD_POLLING_SHIFT     0x03
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOISTURE_EN_POLLING_SHIFT       0x02
+#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOISTURE_DBNC_TIME_SHIFT        0x00
+
+/* WCD939X_MECH_DET_CURRENT Fields: */
+#define WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL_SHIFT                   0x00
+
+/* WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW Fields: */
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_SPARE_BITS_7_SHIFT          0x07
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_ZDET_CLK_SEL_SHIFT          0x06
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_ZDET_SUBSEL_OV_SHIFT        0x05
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_ZDET_CLK_EN_CTL_SHIFT       0x04
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_MOIS_CURRENT_CTL_SEL_SHIFT  0x03
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_MOIS_CURRENT_ADD_SHIFT      0x02
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW_MECH_REF_SEL_SHIFT          0x00
+
+
+/* WCD939X_EAR_CHOPPER_CON Fields: */
+#define WCD939X_EAR_CHOPPER_CON_EAR_CHOPPER_EN_SHIFT                      0x07
+#define WCD939X_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_DIV_SHIFT                 0x03
+#define WCD939X_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_INV_SHIFT                 0x02
+#define WCD939X_EAR_CHOPPER_CON_EAR_CHOPPER_CLK_OVERLAP_SHIFT             0x01
+#define WCD939X_EAR_CHOPPER_CON_SCD_SHTDWN_FAST_PATH_DIS_SHIFT            0x00
+
+/* WCD939X_CNP_VCM_CON1 Fields: */
+#define WCD939X_CNP_VCM_CON1_SCD_EN_TIME_SEL_SHIFT                        0x07
+#define WCD939X_CNP_VCM_CON1_NO_DYN_BIAS_DURING_STARTUP_SHIFT             0x06
+#define WCD939X_CNP_VCM_CON1_CNP_VCM_GEN_START_SHIFT                      0x00
+
+/* WCD939X_CNP_VCM_CON2 Fields: */
+#define WCD939X_CNP_VCM_CON2_DTEST_SEL_SHIFT                              0x06
+#define WCD939X_CNP_VCM_CON2_CNP_VCM_GEN_STOP_SHIFT                       0x00
+
+/* WCD939X_EAR_DYNAMIC_BIAS Fields: */
+#define WCD939X_EAR_DYNAMIC_BIAS_EAR_DYN_BIAS_SEL_SHIFT                   0x05
+#define WCD939X_EAR_DYNAMIC_BIAS_EAR_BIAS_CURR_SHIFT                      0x00
+
+
+/* WCD939X_WATCHDOG_CTL_1 Fields: */
+#define WCD939X_WATCHDOG_CTL_1_VREF_HI_CTL_SHIFT                          0x00
+
+/* WCD939X_WATCHDOG_CTL_2 Fields: */
+#define WCD939X_WATCHDOG_CTL_2_VREF_LO_CTL_SHIFT                          0x00
+
+
+/* WCD939X_DIE_CRK_DET_INT1 Fields: */
+#define WCD939X_DIE_CRK_DET_INT1_SEL_EDGE_DET_SHIFT                       0x06
+#define WCD939X_DIE_CRK_DET_INT1_EN_RINGM_ATEST_SHIFT                     0x05
+#define WCD939X_DIE_CRK_DET_INT1_EN_RINGP_ATEST_SHIFT                     0x04
+#define WCD939X_DIE_CRK_DET_INT1_RING_CURR_SEL_SHIFT                      0x01
+#define WCD939X_DIE_CRK_DET_INT1_EN_VREF_ATEST_SHIFT                      0x00
+
+/* WCD939X_DIE_CRK_DET_INT2 Fields: */
+#define WCD939X_DIE_CRK_DET_INT2_REF_CURR_SEL_SHIFT                       0x05
+#define WCD939X_DIE_CRK_DET_INT2_COMP_STG1_IBIAS_SHIFT                    0x03
+#define WCD939X_DIE_CRK_DET_INT2_COMP_STG2_IBIAS_SHIFT                    0x01
+#define WCD939X_DIE_CRK_DET_INT2_EN_ATEST_SHIFT                           0x00
+
+
+/* WCD939X_TXFE_DIVSTOP_L2 Fields: */
+#define WCD939X_TXFE_DIVSTOP_L2_DIV_L2_SHIFT                              0x00
+
+/* WCD939X_TXFE_DIVSTOP_L1 Fields: */
+#define WCD939X_TXFE_DIVSTOP_L1_DIV_L1_SHIFT                              0x00
+
+/* WCD939X_TXFE_DIVSTOP_L0 Fields: */
+#define WCD939X_TXFE_DIVSTOP_L0_DIV_L0_SHIFT                              0x00
+
+/* WCD939X_TXFE_DIVSTOP_ULP1P2M Fields: */
+#define WCD939X_TXFE_DIVSTOP_ULP1P2M_DIV_ULP1P2M_SHIFT                    0x00
+
+/* WCD939X_TXFE_DIVSTOP_ULP0P6M Fields: */
+#define WCD939X_TXFE_DIVSTOP_ULP0P6M_DIV_ULP0P6M_SHIFT                    0x00
+
+/* WCD939X_TXFE_ICTRL_STG1_L2L1 Fields: */
+#define WCD939X_TXFE_ICTRL_STG1_L2L1_NINIT_L2_SHIFT                       0x06
+#define WCD939X_TXFE_ICTRL_STG1_L2L1_ICTRL_STG1_L2L1_SHIFT                0x00
+
+/* WCD939X_TXFE_ICTRL_STG1_L0 Fields: */
+#define WCD939X_TXFE_ICTRL_STG1_L0_NINIT_L1_SHIFT                         0x06
+#define WCD939X_TXFE_ICTRL_STG1_L0_ICTRL_STG1_L0_SHIFT                    0x00
+
+/* WCD939X_TXFE_ICTRL_STG1_ULP Fields: */
+#define WCD939X_TXFE_ICTRL_STG1_ULP_NINIT_L0_SHIFT                        0x06
+#define WCD939X_TXFE_ICTRL_STG1_ULP_ICTRL_STG1_ULP_SHIFT                  0x00
+
+/* WCD939X_TXFE_ICTRL_STG2MAIN_L2L1 Fields: */
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L2L1_NINIT_ULP1P2M_SHIFT              0x06
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L2L1_ICTRL_STG2MAIN_L2L1_SHIFT        0x00
+
+/* WCD939X_TXFE_ICTRL_STG2MAIN_L0 Fields: */
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L0_NINIT_ULP0P6M_SHIFT                0x06
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L0_ADCREF_ULPIBIAS_EN_SHIFT           0x05
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L0_ICTRL_STG2MAIN_L0_SHIFT            0x00
+
+/* WCD939X_TXFE_ICTRL_STG2MAIN_ULP Fields: */
+#define WCD939X_TXFE_ICTRL_STG2MAIN_ULP_ICTRL_STG2MAIN_ULP_SHIFT          0x00
+
+/* WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0 Fields: */
+#define WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0_ICTRL_STG2CASC_L2L1_SHIFT      0x04
+#define WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0_ICTRL_STG2CASC_L0_SHIFT        0x00
+
+/* WCD939X_TXFE_ICTRL_STG2CASC_ULP Fields: */
+#define WCD939X_TXFE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M_SHIFT        0x04
+#define WCD939X_TXFE_ICTRL_STG2CASC_ULP_ICTRL_STG2CASC_ULP_SHIFT          0x00
+
+/* WCD939X_TXADC_SCBIAS_L2L1 Fields: */
+#define WCD939X_TXADC_SCBIAS_L2L1_ICTRL_SCBIAS_L2_SHIFT                   0x04
+#define WCD939X_TXADC_SCBIAS_L2L1_ICTRL_SCBIAS_L1_SHIFT                   0x00
+
+/* WCD939X_TXADC_SCBIAS_L0ULP Fields: */
+#define WCD939X_TXADC_SCBIAS_L0ULP_ICTRL_SCBIAS_L0_SHIFT                  0x04
+#define WCD939X_TXADC_SCBIAS_L0ULP_ICTRL_SCBIAS_ULP1P2M_SHIFT             0x00
+
+/* WCD939X_TXADC_INT_L2 Fields: */
+#define WCD939X_TXADC_INT_L2_INT1_L2_SHIFT                                0x04
+#define WCD939X_TXADC_INT_L2_INT2_L2_SHIFT                                0x00
+
+/* WCD939X_TXADC_INT_L1 Fields: */
+#define WCD939X_TXADC_INT_L1_INT1_L1_SHIFT                                0x04
+#define WCD939X_TXADC_INT_L1_INT2_L1_SHIFT                                0x00
+
+/* WCD939X_TXADC_INT_L0 Fields: */
+#define WCD939X_TXADC_INT_L0_INT1_L0_SHIFT                                0x04
+#define WCD939X_TXADC_INT_L0_INT2_L0_SHIFT                                0x00
+
+/* WCD939X_TXADC_INT_ULP Fields: */
+#define WCD939X_TXADC_INT_ULP_INT1_ULP_SHIFT                              0x04
+#define WCD939X_TXADC_INT_ULP_INT2_ULP_SHIFT                              0x00
+
+
+/* WCD939X_DIGITAL_PAGE Fields: */
+#define WCD939X_DIGITAL_PAGE_PAG_REG_SHIFT                                0x00
+
+/* WCD939X_CHIP_ID0 Fields: */
+#define WCD939X_CHIP_ID0_BYTE_0_SHIFT                                     0x00
+
+/* WCD939X_CHIP_ID1 Fields: */
+#define WCD939X_CHIP_ID1_BYTE_1_SHIFT                                     0x00
+
+/* WCD939X_CHIP_ID2 Fields: */
+#define WCD939X_CHIP_ID2_BYTE_2_SHIFT                                     0x00
+
+/* WCD939X_CHIP_ID3 Fields: */
+#define WCD939X_CHIP_ID3_BYTE_3_SHIFT                                     0x00
+
+/* WCD939X_SWR_TX_CLK_RATE Fields: */
+#define WCD939X_SWR_TX_CLK_RATE_CLK_RATE_BK_1_SHIFT                       0x04
+#define WCD939X_SWR_TX_CLK_RATE_CLK_RATE_BK_0_SHIFT                       0x00
+
+/* WCD939X_CDC_RST_CTL Fields: */
+#define WCD939X_CDC_RST_CTL_ANA_SW_RST_N_SHIFT                            0x01
+#define WCD939X_CDC_RST_CTL_DIG_SW_RST_N_SHIFT                            0x00
+
+/* WCD939X_TOP_CLK_CFG Fields: */
+#define WCD939X_TOP_CLK_CFG_RX_CLK_CFG_SHIFT                              0x01
+#define WCD939X_TOP_CLK_CFG_TX_CLK_CFG_SHIFT                              0x00
+
+/* WCD939X_CDC_ANA_CLK_CTL Fields: */
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV4_CLK_EN_SHIFT                  0x05
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN_SHIFT                  0x04
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN_SHIFT                       0x03
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN_SHIFT                  0x02
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN_SHIFT                  0x01
+#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN_SHIFT                       0x00
+
+/* WCD939X_CDC_DIG_CLK_CTL Fields: */
+#define WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN_SHIFT                         0x07
+#define WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN_SHIFT                         0x06
+#define WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN_SHIFT                         0x05
+#define WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN_SHIFT                         0x04
+#define WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN_SHIFT                         0x02
+#define WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN_SHIFT                         0x01
+#define WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN_SHIFT                         0x00
+
+/* WCD939X_SWR_RST_EN Fields: */
+#define WCD939X_SWR_RST_EN_RX_RESET_SYNC_LOST_EN_SHIFT                    0x05
+#define WCD939X_SWR_RST_EN_RX_RESET_SWR_BUS_EN_SHIFT                      0x04
+#define WCD939X_SWR_RST_EN_RX_RESET_SWR_REG_EN_SHIFT                      0x03
+#define WCD939X_SWR_RST_EN_TX_RESET_SYNC_LOST_EN_SHIFT                    0x02
+#define WCD939X_SWR_RST_EN_TX_RESET_SWR_BUS_EN_SHIFT                      0x01
+#define WCD939X_SWR_RST_EN_TX_RESET_SWR_REG_EN_SHIFT                      0x00
+
+/* WCD939X_CDC_PATH_MODE Fields: */
+#define WCD939X_CDC_PATH_MODE_EAR_MODE_SHIFT                              0x06
+#define WCD939X_CDC_PATH_MODE_TXD2_MODE_SHIFT                             0x04
+#define WCD939X_CDC_PATH_MODE_TXD1_MODE_SHIFT                             0x02
+#define WCD939X_CDC_PATH_MODE_TXD0_MODE_SHIFT                             0x00
+
+/* WCD939X_CDC_RX_RST Fields: */
+#define WCD939X_CDC_RX_RST_RX2_SOFT_RST_SHIFT                             0x02
+#define WCD939X_CDC_RX_RST_RX1_SOFT_RST_SHIFT                             0x01
+#define WCD939X_CDC_RX_RST_RX0_SOFT_RST_SHIFT                             0x00
+
+/* WCD939X_CDC_RX0_CTL Fields: */
+#define WCD939X_CDC_RX0_CTL_DSM_DITHER_ENABLE_SHIFT                       0x07
+#define WCD939X_CDC_RX0_CTL_DEM_DITHER_ENABLE_SHIFT                       0x06
+#define WCD939X_CDC_RX0_CTL_DEM_MID_ENABLE_SHIFT                          0x05
+#define WCD939X_CDC_RX0_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_SHIFT          0x04
+#define WCD939X_CDC_RX0_CTL_DEM_SWITCHING_BLOCK_ENABLE_SHIFT              0x03
+#define WCD939X_CDC_RX0_CTL_DEM_SEGMENTING_BLOCK_ENABLE_SHIFT             0x02
+#define WCD939X_CDC_RX0_CTL_DEM_BYPASS_SHIFT                              0x01
+
+/* WCD939X_CDC_RX1_CTL Fields: */
+#define WCD939X_CDC_RX1_CTL_DSM_DITHER_ENABLE_SHIFT                       0x07
+#define WCD939X_CDC_RX1_CTL_DEM_DITHER_ENABLE_SHIFT                       0x06
+#define WCD939X_CDC_RX1_CTL_DEM_MID_ENABLE_SHIFT                          0x05
+#define WCD939X_CDC_RX1_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_SHIFT          0x04
+#define WCD939X_CDC_RX1_CTL_DEM_SWITCHING_BLOCK_ENABLE_SHIFT              0x03
+#define WCD939X_CDC_RX1_CTL_DEM_SEGMENTING_BLOCK_ENABLE_SHIFT             0x02
+#define WCD939X_CDC_RX1_CTL_DEM_BYPASS_SHIFT                              0x01
+
+/* WCD939X_CDC_RX2_CTL Fields: */
+#define WCD939X_CDC_RX2_CTL_DSM_DITHER_ENABLE_SHIFT                       0x07
+#define WCD939X_CDC_RX2_CTL_DEM_DITHER_ENABLE_SHIFT                       0x06
+#define WCD939X_CDC_RX2_CTL_DEM_MID_ENABLE_SHIFT                          0x05
+#define WCD939X_CDC_RX2_CTL_DEM_MOD_SWITCHING_BLOCK_ENABLE_SHIFT          0x04
+#define WCD939X_CDC_RX2_CTL_DEM_SWITCHING_BLOCK_ENABLE_SHIFT              0x03
+#define WCD939X_CDC_RX2_CTL_DEM_SEGMENTING_BLOCK_ENABLE_SHIFT             0x02
+#define WCD939X_CDC_RX2_CTL_DEM_BYPASS_SHIFT                              0x01
+
+/* WCD939X_CDC_TX_ANA_MODE_0_1 Fields: */
+#define WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE_SHIFT                       0x04
+#define WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE_SHIFT                       0x00
+
+/* WCD939X_CDC_TX_ANA_MODE_2_3 Fields: */
+#define WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE_SHIFT                       0x04
+#define WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE_SHIFT                       0x00
+
+/* WCD939X_CDC_COMP_CTL_0 Fields: */
+#define WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN_SHIFT                         0x01
+#define WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN_SHIFT                         0x00
+
+/* WCD939X_CDC_ANA_TX_CLK_CTL Fields: */
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_MBHC_1P2M_CLK_EN_SHIFT             0x05
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX3_ADC_CLK_EN_SHIFT               0x04
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX2_ADC_CLK_EN_SHIFT               0x03
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX1_ADC_CLK_EN_SHIFT               0x02
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX0_ADC_CLK_EN_SHIFT               0x01
+#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN_SHIFT              0x00
+
+/* WCD939X_CDC_HPH_DSM_A1_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A1_0_COEF_A1_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A1_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A1_1_COEF_A1_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A2_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A2_0_COEF_A2_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A2_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A2_1_COEF_A2_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A3_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A3_0_COEF_A3_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A3_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A3_1_COEF_A3_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A4_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A4_0_COEF_A4_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A4_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A4_1_COEF_A4_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A5_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A5_0_COEF_A5_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A5_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_A5_1_COEF_A5_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A6_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A6_0_COEF_A6_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_A7_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_A7_0_COEF_A7_SHIFT                            0x00
+
+/* WCD939X_CDC_HPH_DSM_C_0 Fields: */
+#define WCD939X_CDC_HPH_DSM_C_0_COEF_C3_SHIFT                             0x04
+#define WCD939X_CDC_HPH_DSM_C_0_COEF_C2_SHIFT                             0x00
+
+/* WCD939X_CDC_HPH_DSM_C_1 Fields: */
+#define WCD939X_CDC_HPH_DSM_C_1_COEF_C5_SHIFT                             0x04
+#define WCD939X_CDC_HPH_DSM_C_1_COEF_C4_SHIFT                             0x00
+
+/* WCD939X_CDC_HPH_DSM_C_2 Fields: */
+#define WCD939X_CDC_HPH_DSM_C_2_COEF_C7_SHIFT                             0x04
+#define WCD939X_CDC_HPH_DSM_C_2_COEF_C6_SHIFT                             0x00
+
+/* WCD939X_CDC_HPH_DSM_C_3 Fields: */
+#define WCD939X_CDC_HPH_DSM_C_3_COEF_C7_SHIFT                             0x00
+
+/* WCD939X_CDC_HPH_DSM_R1 Fields: */
+#define WCD939X_CDC_HPH_DSM_R1_SAT_LIMIT_R1_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_DSM_R2 Fields: */
+#define WCD939X_CDC_HPH_DSM_R2_SAT_LIMIT_R2_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_DSM_R3 Fields: */
+#define WCD939X_CDC_HPH_DSM_R3_SAT_LIMIT_R3_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_DSM_R4 Fields: */
+#define WCD939X_CDC_HPH_DSM_R4_SAT_LIMIT_R4_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_DSM_R5 Fields: */
+#define WCD939X_CDC_HPH_DSM_R5_SAT_LIMIT_R5_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_DSM_R6 Fields: */
+#define WCD939X_CDC_HPH_DSM_R6_SAT_LIMIT_R6_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_DSM_R7 Fields: */
+#define WCD939X_CDC_HPH_DSM_R7_SAT_LIMIT_R7_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_DSM_A1_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A1_0_COEF_A1_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A1_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A1_1_COEF_A1_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A2_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A2_0_COEF_A2_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A2_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A2_1_COEF_A2_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A3_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A3_0_COEF_A3_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A3_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A3_1_COEF_A3_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A4_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A4_0_COEF_A4_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A4_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A4_1_COEF_A4_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A5_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A5_0_COEF_A5_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A5_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_A5_1_COEF_A5_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A6_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A6_0_COEF_A6_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_A7_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_A7_0_COEF_A7_SHIFT                            0x00
+
+/* WCD939X_CDC_EAR_DSM_C_0 Fields: */
+#define WCD939X_CDC_EAR_DSM_C_0_COEF_C3_SHIFT                             0x04
+#define WCD939X_CDC_EAR_DSM_C_0_COEF_C2_SHIFT                             0x00
+
+/* WCD939X_CDC_EAR_DSM_C_1 Fields: */
+#define WCD939X_CDC_EAR_DSM_C_1_COEF_C5_SHIFT                             0x04
+#define WCD939X_CDC_EAR_DSM_C_1_COEF_C4_SHIFT                             0x00
+
+/* WCD939X_CDC_EAR_DSM_C_2 Fields: */
+#define WCD939X_CDC_EAR_DSM_C_2_COEF_C7_SHIFT                             0x04
+#define WCD939X_CDC_EAR_DSM_C_2_COEF_C6_SHIFT                             0x00
+
+/* WCD939X_CDC_EAR_DSM_C_3 Fields: */
+#define WCD939X_CDC_EAR_DSM_C_3_COEF_C7_SHIFT                             0x00
+
+/* WCD939X_CDC_EAR_DSM_R1 Fields: */
+#define WCD939X_CDC_EAR_DSM_R1_SAT_LIMIT_R1_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_DSM_R2 Fields: */
+#define WCD939X_CDC_EAR_DSM_R2_SAT_LIMIT_R2_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_DSM_R3 Fields: */
+#define WCD939X_CDC_EAR_DSM_R3_SAT_LIMIT_R3_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_DSM_R4 Fields: */
+#define WCD939X_CDC_EAR_DSM_R4_SAT_LIMIT_R4_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_DSM_R5 Fields: */
+#define WCD939X_CDC_EAR_DSM_R5_SAT_LIMIT_R5_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_DSM_R6 Fields: */
+#define WCD939X_CDC_EAR_DSM_R6_SAT_LIMIT_R6_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_DSM_R7 Fields: */
+#define WCD939X_CDC_EAR_DSM_R7_SAT_LIMIT_R7_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_GAIN_RX_0 Fields: */
+#define WCD939X_CDC_HPH_GAIN_RX_0_GAIN_RX_SHIFT                           0x00
+
+/* WCD939X_CDC_HPH_GAIN_RX_1 Fields: */
+#define WCD939X_CDC_HPH_GAIN_RX_1_GAIN_RX_SHIFT                           0x00
+
+/* WCD939X_CDC_HPH_GAIN_DSD_0 Fields: */
+#define WCD939X_CDC_HPH_GAIN_DSD_0_GAIN_DSD_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_GAIN_DSD_1 Fields: */
+#define WCD939X_CDC_HPH_GAIN_DSD_1_GAIN_DSD_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_GAIN_DSD_2 Fields: */
+#define WCD939X_CDC_HPH_GAIN_DSD_2_GAIN_LATCH_SHIFT                       0x01
+#define WCD939X_CDC_HPH_GAIN_DSD_2_GAIN_DSD_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_GAIN_DSD_0 Fields: */
+#define WCD939X_CDC_EAR_GAIN_DSD_0_GAIN_DSD_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_GAIN_DSD_1 Fields: */
+#define WCD939X_CDC_EAR_GAIN_DSD_1_GAIN_DSD_SHIFT                         0x00
+
+/* WCD939X_CDC_EAR_GAIN_DSD_2 Fields: */
+#define WCD939X_CDC_EAR_GAIN_DSD_2_GAIN_LATCH_SHIFT                       0x01
+#define WCD939X_CDC_EAR_GAIN_DSD_2_GAIN_DSD_SHIFT                         0x00
+
+/* WCD939X_CDC_HPH_GAIN_CTL Fields: */
+#define WCD939X_CDC_HPH_GAIN_CTL_HPH_STEREO_EN_SHIFT                      0x04
+#define WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT                         0x03
+#define WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT                         0x02
+#define WCD939X_CDC_HPH_GAIN_CTL_HPHR_DSD_EN_SHIFT                        0x01
+#define WCD939X_CDC_HPH_GAIN_CTL_HPHL_DSD_EN_SHIFT                        0x00
+
+/* WCD939X_CDC_EAR_GAIN_CTL Fields: */
+#define WCD939X_CDC_EAR_GAIN_CTL_EAR_EN_SHIFT                             0x00
+
+/* WCD939X_CDC_EAR_PATH_CTL Fields: */
+#define WCD939X_CDC_EAR_PATH_CTL_EAR_GAIN_CTL_SHIFT                       0x01
+#define WCD939X_CDC_EAR_PATH_CTL_EAR_MUX_SEL_SHIFT                        0x00
+
+/* WCD939X_CDC_SWR_CLH Fields: */
+#define WCD939X_CDC_SWR_CLH_CLH_CTL_SHIFT                                 0x00
+
+/* WCD939X_SWR_CLH_BYP Fields: */
+#define WCD939X_SWR_CLH_BYP_SWR_CLH_BYP_SHIFT                             0x00
+
+/* WCD939X_CDC_TX0_CTL Fields: */
+#define WCD939X_CDC_TX0_CTL_REQ_FB_SEL_SHIFT                              0x06
+#define WCD939X_CDC_TX0_CTL_TX_DITHER_EN_SHIFT                            0x05
+#define WCD939X_CDC_TX0_CTL_RANDOM_REGION_SHIFT                           0x00
+
+/* WCD939X_CDC_TX1_CTL Fields: */
+#define WCD939X_CDC_TX1_CTL_REQ_FB_SEL_SHIFT                              0x06
+#define WCD939X_CDC_TX1_CTL_TX_DITHER_EN_SHIFT                            0x05
+#define WCD939X_CDC_TX1_CTL_RANDOM_REGION_SHIFT                           0x00
+
+/* WCD939X_CDC_TX2_CTL Fields: */
+#define WCD939X_CDC_TX2_CTL_REQ_FB_SEL_SHIFT                              0x06
+#define WCD939X_CDC_TX2_CTL_TX_DITHER_EN_SHIFT                            0x05
+#define WCD939X_CDC_TX2_CTL_RANDOM_REGION_SHIFT                           0x00
+
+/* WCD939X_CDC_TX_RST Fields: */
+#define WCD939X_CDC_TX_RST_TX3_SOFT_RST_SHIFT                             0x03
+#define WCD939X_CDC_TX_RST_TX2_SOFT_RST_SHIFT                             0x02
+#define WCD939X_CDC_TX_RST_TX1_SOFT_RST_SHIFT                             0x01
+#define WCD939X_CDC_TX_RST_TX0_SOFT_RST_SHIFT                             0x00
+
+/* WCD939X_CDC_REQ_CTL Fields: */
+#define WCD939X_CDC_REQ_CTL_TX3_WIDE_BAND_SHIFT                           0x05
+#define WCD939X_CDC_REQ_CTL_TX2_WIDE_BAND_SHIFT                           0x04
+#define WCD939X_CDC_REQ_CTL_TX1_WIDE_BAND_SHIFT                           0x03
+#define WCD939X_CDC_REQ_CTL_TX0_WIDE_BAND_SHIFT                           0x02
+#define WCD939X_CDC_REQ_CTL_FS_RATE_4P8_SHIFT                             0x01
+#define WCD939X_CDC_REQ_CTL_NO_NOTCH_SHIFT                                0x00
+
+/* WCD939X_CDC_RST Fields: */
+#define WCD939X_CDC_RST_TX_SOFT_RST_SHIFT                                 0x01
+#define WCD939X_CDC_RST_RX_SOFT_RST_SHIFT                                 0x00
+
+/* WCD939X_CDC_AMIC_CTL Fields: */
+#define WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL_SHIFT                           0x03
+#define WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL_SHIFT                           0x02
+#define WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL_SHIFT                           0x01
+#define WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL_SHIFT                           0x00
+
+/* WCD939X_CDC_DMIC_CTL Fields: */
+#define WCD939X_CDC_DMIC_CTL_DMIC_LEGACY_SW_MODE_SHIFT                    0x03
+#define WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN_SHIFT                        0x02
+#define WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN_SHIFT                           0x01
+#define WCD939X_CDC_DMIC_CTL_SOFT_RESET_SHIFT                             0x00
+
+/* WCD939X_CDC_DMIC1_CTL Fields: */
+#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SCALE_SEL_SHIFT                    0x04
+#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN_SHIFT                           0x03
+#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SEL_SHIFT                          0x00
+
+/* WCD939X_CDC_DMIC2_CTL Fields: */
+#define WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN_SHIFT                          0x07
+#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SCALE_SEL_SHIFT                    0x04
+#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN_SHIFT                           0x03
+#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SEL_SHIFT                          0x00
+
+/* WCD939X_CDC_DMIC3_CTL Fields: */
+#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SCALE_SEL_SHIFT                    0x04
+#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN_SHIFT                           0x03
+#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SEL_SHIFT                          0x00
+
+/* WCD939X_CDC_DMIC4_CTL Fields: */
+#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SCALE_SEL_SHIFT                    0x04
+#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN_SHIFT                           0x03
+#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SEL_SHIFT                          0x00
+
+/* WCD939X_EFUSE_PRG_CTL Fields: */
+#define WCD939X_EFUSE_PRG_CTL_PRG_ADDR_SHIFT                              0x00
+
+/* WCD939X_EFUSE_CTL Fields: */
+#define WCD939X_EFUSE_CTL_EFUSE_ST_CNT_SHIFT                              0x02
+#define WCD939X_EFUSE_CTL_EFUSE_SOFT_RST_N_SHIFT                          0x01
+#define WCD939X_EFUSE_CTL_EFUSE_EN_SHIFT                                  0x00
+
+/* WCD939X_CDC_DMIC_RATE_1_2 Fields: */
+#define WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE_SHIFT                        0x04
+#define WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE_SHIFT                        0x00
+
+/* WCD939X_CDC_DMIC_RATE_3_4 Fields: */
+#define WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE_SHIFT                        0x04
+#define WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE_SHIFT                        0x00
+
+/* WCD939X_PDM_WD_CTL0 Fields: */
+#define WCD939X_PDM_WD_CTL0_HOLD_OFF_SHIFT                                0x04
+#define WCD939X_PDM_WD_CTL0_TIME_OUT_SEL_SHIFT                            0x03
+#define WCD939X_PDM_WD_CTL0_PDM_WD_EN_SHIFT                               0x00
+
+/* WCD939X_PDM_WD_CTL1 Fields: */
+#define WCD939X_PDM_WD_CTL1_HOLD_OFF_SHIFT                                0x04
+#define WCD939X_PDM_WD_CTL1_TIME_OUT_SEL_SHIFT                            0x03
+#define WCD939X_PDM_WD_CTL1_PDM_WD_EN_SHIFT                               0x00
+
+/* WCD939X_PDM_WD_CTL2 Fields: */
+#define WCD939X_PDM_WD_CTL2_HOLD_OFF_SHIFT                                0x02
+#define WCD939X_PDM_WD_CTL2_TIME_OUT_SEL_SHIFT                            0x01
+#define WCD939X_PDM_WD_CTL2_PDM_WD_EN_SHIFT                               0x00
+
+/* WCD939X_INTR_MODE Fields: */
+#define WCD939X_INTR_MODE_SWR_PULSE_CLR_SHIFT                             0x05
+#define WCD939X_INTR_MODE_SWR_RX_INT_OUT_EN_SHIFT                         0x04
+#define WCD939X_INTR_MODE_SWR_INTR_LEVEL_SHIFT                            0x01
+#define WCD939X_INTR_MODE_INT_POLARITY_SHIFT                              0x00
+
+/* WCD939X_INTR_MASK_0 Fields: */
+#define WCD939X_INTR_MASK_0_HPHL_OCP_INT_SHIFT                            0x07
+#define WCD939X_INTR_MASK_0_HPHR_CNP_INT_SHIFT                            0x06
+#define WCD939X_INTR_MASK_0_HPHR_OCP_INT_SHIFT                            0x05
+#define WCD939X_INTR_MASK_0_MBHC_SW_INT_SHIFT                             0x04
+#define WCD939X_INTR_MASK_0_MBHC_ELECT_INS_REM_LEG_INT_SHIFT              0x03
+#define WCD939X_INTR_MASK_0_MBHC_ELECT_INS_REM_INT_SHIFT                  0x02
+#define WCD939X_INTR_MASK_0_MBHC_BTN_RELEASE_INT_SHIFT                    0x01
+#define WCD939X_INTR_MASK_0_MBHC_BTN_PRESS_INT_SHIFT                      0x00
+
+/* WCD939X_INTR_MASK_1 Fields: */
+#define WCD939X_INTR_MASK_1_EAR_PDM_WD_INT_SHIFT                          0x07
+#define WCD939X_INTR_MASK_1_HPHR_PDM_WD_INT_SHIFT                         0x06
+#define WCD939X_INTR_MASK_1_HPHL_PDM_WD_INT_SHIFT                         0x05
+#define WCD939X_INTR_MASK_1_EAR_SCD_INT_SHIFT                             0x02
+#define WCD939X_INTR_MASK_1_EAR_CNP_INT_SHIFT                             0x01
+#define WCD939X_INTR_MASK_1_HPHL_CNP_INT_SHIFT                            0x00
+
+/* WCD939X_INTR_MASK_2 Fields: */
+#define WCD939X_INTR_MASK_2_HPHL_SURGE_DET_INT_SHIFT                      0x03
+#define WCD939X_INTR_MASK_2_HPHR_SURGE_DET_INT_SHIFT                      0x02
+#define WCD939X_INTR_MASK_2_MBHC_MOISTRUE_INT_SHIFT                       0x01
+
+/* WCD939X_INTR_STATUS_0 Fields: */
+#define WCD939X_INTR_STATUS_0_HPHL_OCP_INT_SHIFT                          0x07
+#define WCD939X_INTR_STATUS_0_HPHR_CNP_INT_SHIFT                          0x06
+#define WCD939X_INTR_STATUS_0_HPHR_OCP_INT_SHIFT                          0x05
+#define WCD939X_INTR_STATUS_0_MBHC_SW_INT_SHIFT                           0x04
+#define WCD939X_INTR_STATUS_0_MBHC_ELECT_INS_REM_LEG_INT_SHIFT            0x03
+#define WCD939X_INTR_STATUS_0_MBHC_ELECT_INS_REM_INT_SHIFT                0x02
+#define WCD939X_INTR_STATUS_0_MBHC_BTN_RELEASE_INT_SHIFT                  0x01
+#define WCD939X_INTR_STATUS_0_MBHC_BTN_PRESS_INT_SHIFT                    0x00
+
+/* WCD939X_INTR_STATUS_1 Fields: */
+#define WCD939X_INTR_STATUS_1_EAR_PDM_WD_INT_SHIFT                        0x07
+#define WCD939X_INTR_STATUS_1_HPHR_PDM_WD_INT_SHIFT                       0x06
+#define WCD939X_INTR_STATUS_1_HPHL_PDM_WD_INT_SHIFT                       0x05
+#define WCD939X_INTR_STATUS_1_EAR_SCD_INT_SHIFT                           0x02
+#define WCD939X_INTR_STATUS_1_EAR_CNP_INT_SHIFT                           0x01
+#define WCD939X_INTR_STATUS_1_HPHL_CNP_INT_SHIFT                          0x00
+
+/* WCD939X_INTR_STATUS_2 Fields: */
+#define WCD939X_INTR_STATUS_2_HPHL_SURGE_DET_INT_SHIFT                    0x03
+#define WCD939X_INTR_STATUS_2_HPHR_SURGE_DET_INT_SHIFT                    0x02
+#define WCD939X_INTR_STATUS_2_MBHC_MOISTRUE_INT_SHIFT                     0x01
+
+/* WCD939X_INTR_CLEAR_0 Fields: */
+#define WCD939X_INTR_CLEAR_0_HPHL_OCP_INT_SHIFT                           0x07
+#define WCD939X_INTR_CLEAR_0_HPHR_CNP_INT_SHIFT                           0x06
+#define WCD939X_INTR_CLEAR_0_HPHR_OCP_INT_SHIFT                           0x05
+#define WCD939X_INTR_CLEAR_0_MBHC_SW_INT_SHIFT                            0x04
+#define WCD939X_INTR_CLEAR_0_MBHC_ELECT_INS_REM_LEG_INT_SHIFT             0x03
+#define WCD939X_INTR_CLEAR_0_MBHC_ELECT_INS_REM_INT_SHIFT                 0x02
+#define WCD939X_INTR_CLEAR_0_MBHC_BTN_RELEASE_INT_SHIFT                   0x01
+#define WCD939X_INTR_CLEAR_0_MBHC_BTN_PRESS_INT_SHIFT                     0x00
+
+/* WCD939X_INTR_CLEAR_1 Fields: */
+#define WCD939X_INTR_CLEAR_1_EAR_PDM_WD_INT_SHIFT                         0x07
+#define WCD939X_INTR_CLEAR_1_HPHR_PDM_WD_INT_SHIFT                        0x06
+#define WCD939X_INTR_CLEAR_1_HPHL_PDM_WD_INT_SHIFT                        0x05
+#define WCD939X_INTR_CLEAR_1_EAR_SCD_INT_SHIFT                            0x02
+#define WCD939X_INTR_CLEAR_1_EAR_CNP_INT_SHIFT                            0x01
+#define WCD939X_INTR_CLEAR_1_HPHL_CNP_INT_SHIFT                           0x00
+
+/* WCD939X_INTR_CLEAR_2 Fields: */
+#define WCD939X_INTR_CLEAR_2_HPHL_SURGE_DET_INT_SHIFT                     0x03
+#define WCD939X_INTR_CLEAR_2_HPHR_SURGE_DET_INT_SHIFT                     0x02
+#define WCD939X_INTR_CLEAR_2_MBHC_MOISTRUE_INT_SHIFT                      0x01
+
+/* WCD939X_INTR_LEVEL_0 Fields: */
+#define WCD939X_INTR_LEVEL_0_HPHL_OCP_INT_SHIFT                           0x07
+#define WCD939X_INTR_LEVEL_0_HPHR_CNP_INT_SHIFT                           0x06
+#define WCD939X_INTR_LEVEL_0_HPHR_OCP_INT_SHIFT                           0x05
+#define WCD939X_INTR_LEVEL_0_MBHC_SW_INT_SHIFT                            0x04
+#define WCD939X_INTR_LEVEL_0_MBHC_ELECT_INS_REM_LEG_INT_SHIFT             0x03
+#define WCD939X_INTR_LEVEL_0_MBHC_ELECT_INS_REM_INT_SHIFT                 0x02
+#define WCD939X_INTR_LEVEL_0_MBHC_BTN_RELEASE_INT_SHIFT                   0x01
+#define WCD939X_INTR_LEVEL_0_MBHC_BTN_PRESS_INT_SHIFT                     0x00
+
+/* WCD939X_INTR_LEVEL_1 Fields: */
+#define WCD939X_INTR_LEVEL_1_EAR_PDM_WD_INT_SHIFT                         0x07
+#define WCD939X_INTR_LEVEL_1_HPHR_PDM_WD_INT_SHIFT                        0x06
+#define WCD939X_INTR_LEVEL_1_HPHL_PDM_WD_INT_SHIFT                        0x05
+#define WCD939X_INTR_LEVEL_1_EAR_SCD_INT_SHIFT                            0x02
+#define WCD939X_INTR_LEVEL_1_EAR_CNP_INT_SHIFT                            0x01
+#define WCD939X_INTR_LEVEL_1_HPHL_CNP_INT_SHIFT                           0x00
+
+/* WCD939X_INTR_LEVEL_2 Fields: */
+#define WCD939X_INTR_LEVEL_2_HPHL_SURGE_DET_INT_SHIFT                     0x03
+#define WCD939X_INTR_LEVEL_2_HPHR_SURGE_DET_INT_SHIFT                     0x02
+#define WCD939X_INTR_LEVEL_2_MBHC_MOISTRUE_INT_SHIFT                      0x01
+
+/* WCD939X_INTR_SET_0 Fields: */
+#define WCD939X_INTR_SET_0_HPHL_OCP_INT_SHIFT                             0x07
+#define WCD939X_INTR_SET_0_HPHR_CNP_INT_SHIFT                             0x06
+#define WCD939X_INTR_SET_0_HPHR_OCP_INT_SHIFT                             0x05
+#define WCD939X_INTR_SET_0_MBHC_SW_INT_SHIFT                              0x04
+#define WCD939X_INTR_SET_0_MBHC_ELECT_INS_REM_LEG_INT_SHIFT               0x03
+#define WCD939X_INTR_SET_0_MBHC_ELECT_INS_REM_INT_SHIFT                   0x02
+#define WCD939X_INTR_SET_0_MBHC_BTN_RELEASE_INT_SHIFT                     0x01
+#define WCD939X_INTR_SET_0_MBHC_BTN_PRESS_INT_SHIFT                       0x00
+
+/* WCD939X_INTR_SET_1 Fields: */
+#define WCD939X_INTR_SET_1_EAR_PDM_WD_INT_SHIFT                           0x07
+#define WCD939X_INTR_SET_1_HPHR_PDM_WD_INT_SHIFT                          0x06
+#define WCD939X_INTR_SET_1_HPHL_PDM_WD_INT_SHIFT                          0x05
+#define WCD939X_INTR_SET_1_EAR_SCD_INT_SHIFT                              0x02
+#define WCD939X_INTR_SET_1_EAR_CNP_INT_SHIFT                              0x01
+#define WCD939X_INTR_SET_1_HPHL_CNP_INT_SHIFT                             0x00
+
+/* WCD939X_INTR_SET_2 Fields: */
+#define WCD939X_INTR_SET_2_HPHL_SURGE_DET_INT_SHIFT                       0x03
+#define WCD939X_INTR_SET_2_HPHR_SURGE_DET_INT_SHIFT                       0x02
+#define WCD939X_INTR_SET_2_MBHC_MOISTRUE_INT_SHIFT                        0x01
+
+/* WCD939X_INTR_TEST_0 Fields: */
+#define WCD939X_INTR_TEST_0_HPHL_OCP_INT_SHIFT                            0x07
+#define WCD939X_INTR_TEST_0_HPHR_CNP_INT_SHIFT                            0x06
+#define WCD939X_INTR_TEST_0_HPHR_OCP_INT_SHIFT                            0x05
+#define WCD939X_INTR_TEST_0_MBHC_SW_INT_SHIFT                             0x04
+#define WCD939X_INTR_TEST_0_MBHC_ELECT_INS_REM_LEG_INT_SHIFT              0x03
+#define WCD939X_INTR_TEST_0_MBHC_ELECT_INS_REM_INT_SHIFT                  0x02
+#define WCD939X_INTR_TEST_0_MBHC_BTN_RELEASE_INT_SHIFT                    0x01
+#define WCD939X_INTR_TEST_0_MBHC_BTN_PRESS_INT_SHIFT                      0x00
+
+/* WCD939X_INTR_TEST_1 Fields: */
+#define WCD939X_INTR_TEST_1_EAR_PDM_WD_INT_SHIFT                          0x07
+#define WCD939X_INTR_TEST_1_HPHR_PDM_WD_INT_SHIFT                         0x06
+#define WCD939X_INTR_TEST_1_HPHL_PDM_WD_INT_SHIFT                         0x05
+#define WCD939X_INTR_TEST_1_EAR_SCD_INT_SHIFT                             0x02
+#define WCD939X_INTR_TEST_1_EAR_CNP_INT_SHIFT                             0x01
+#define WCD939X_INTR_TEST_1_HPHL_CNP_INT_SHIFT                            0x00
+
+/* WCD939X_INTR_TEST_2 Fields: */
+#define WCD939X_INTR_TEST_2_HPHL_SURGE_DET_INT_SHIFT                      0x03
+#define WCD939X_INTR_TEST_2_HPHR_SURGE_DET_INT_SHIFT                      0x02
+#define WCD939X_INTR_TEST_2_MBHC_MOISTRUE_INT_SHIFT                       0x01
+
+/* WCD939X_TX_MODE_DBG_EN Fields: */
+#define WCD939X_TX_MODE_DBG_EN_TXD3_MODE_DBG_EN_SHIFT                     0x03
+#define WCD939X_TX_MODE_DBG_EN_TXD2_MODE_DBG_EN_SHIFT                     0x02
+#define WCD939X_TX_MODE_DBG_EN_TXD1_MODE_DBG_EN_SHIFT                     0x01
+#define WCD939X_TX_MODE_DBG_EN_TXD0_MODE_DBG_EN_SHIFT                     0x00
+
+/* WCD939X_TX_MODE_DBG_0_1 Fields: */
+#define WCD939X_TX_MODE_DBG_0_1_TXD1_MODE_DBG_SHIFT                       0x04
+#define WCD939X_TX_MODE_DBG_0_1_TXD0_MODE_DBG_SHIFT                       0x00
+
+/* WCD939X_TX_MODE_DBG_2_3 Fields: */
+#define WCD939X_TX_MODE_DBG_2_3_TXD3_MODE_DBG_SHIFT                       0x04
+#define WCD939X_TX_MODE_DBG_2_3_TXD2_MODE_DBG_SHIFT                       0x00
+
+/* WCD939X_LB_IN_SEL_CTL Fields: */
+#define WCD939X_LB_IN_SEL_CTL_EAR_LB_IN_SEL_SHIFT                         0x02
+#define WCD939X_LB_IN_SEL_CTL_HPH_LB_IN_SEL_SHIFT                         0x00
+
+/* WCD939X_LOOP_BACK_MODE Fields: */
+#define WCD939X_LOOP_BACK_MODE_TX_DATA_EDGE_SHIFT                         0x04
+#define WCD939X_LOOP_BACK_MODE_RX_DATA_EDGE_SHIFT                         0x03
+#define WCD939X_LOOP_BACK_MODE_LOOPBACK_MODE_SHIFT                        0x00
+
+/* WCD939X_SWR_DAC_TEST Fields: */
+#define WCD939X_SWR_DAC_TEST_SWR_DAC_TEST_SHIFT                           0x00
+
+/* WCD939X_SWR_HM_TEST_RX_0 Fields: */
+#define WCD939X_SWR_HM_TEST_RX_0_ALT_MODE_SHIFT                           0x07
+#define WCD939X_SWR_HM_TEST_RX_0_IO_MODE_SHIFT                            0x06
+#define WCD939X_SWR_HM_TEST_RX_0_LN2_T_DATA_OE_SHIFT                      0x05
+#define WCD939X_SWR_HM_TEST_RX_0_LN2_T_DATA_OUT_SHIFT                     0x04
+#define WCD939X_SWR_HM_TEST_RX_0_LN2_T_KEEPER_EN_SHIFT                    0x03
+#define WCD939X_SWR_HM_TEST_RX_0_LN1_T_DATA_OE_SHIFT                      0x02
+#define WCD939X_SWR_HM_TEST_RX_0_LN1_T_DATA_OUT_SHIFT                     0x01
+#define WCD939X_SWR_HM_TEST_RX_0_LN1_T_KEEPER_EN_SHIFT                    0x00
+
+/* WCD939X_SWR_HM_TEST_TX_0 Fields: */
+#define WCD939X_SWR_HM_TEST_TX_0_ALT_MODE_SHIFT                           0x07
+#define WCD939X_SWR_HM_TEST_TX_0_IO_MODE_SHIFT                            0x06
+#define WCD939X_SWR_HM_TEST_TX_0_LN2_T_DATA_OE_SHIFT                      0x05
+#define WCD939X_SWR_HM_TEST_TX_0_LN2_T_DATA_OUT_SHIFT                     0x04
+#define WCD939X_SWR_HM_TEST_TX_0_LN2_T_KEEPER_EN_SHIFT                    0x03
+#define WCD939X_SWR_HM_TEST_TX_0_LN1_T_DATA_OE_SHIFT                      0x02
+#define WCD939X_SWR_HM_TEST_TX_0_LN1_T_DATA_OUT_SHIFT                     0x01
+#define WCD939X_SWR_HM_TEST_TX_0_LN1_T_KEEPER_EN_SHIFT                    0x00
+
+/* WCD939X_SWR_HM_TEST_RX_1 Fields: */
+#define WCD939X_SWR_HM_TEST_RX_1_DTEST_SEL_SHIFT                          0x02
+#define WCD939X_SWR_HM_TEST_RX_1_LN2_DLY_CELL_TEST_EN_SHIFT               0x01
+#define WCD939X_SWR_HM_TEST_RX_1_LN1_DLY_CELL_TEST_EN_SHIFT               0x00
+
+/* WCD939X_SWR_HM_TEST_TX_1 Fields: */
+#define WCD939X_SWR_HM_TEST_TX_1_DTEST_SEL_SHIFT                          0x03
+#define WCD939X_SWR_HM_TEST_TX_1_LN3_DLY_CELL_TEST_EN_SHIFT               0x02
+#define WCD939X_SWR_HM_TEST_TX_1_LN2_DLY_CELL_TEST_EN_SHIFT               0x01
+#define WCD939X_SWR_HM_TEST_TX_1_LN1_DLY_CELL_TEST_EN_SHIFT               0x00
+
+/* WCD939X_SWR_HM_TEST_TX_2 Fields: */
+#define WCD939X_SWR_HM_TEST_TX_2_LN3_T_DATA_OE_SHIFT                      0x02
+#define WCD939X_SWR_HM_TEST_TX_2_LN3_T_DATA_OUT_SHIFT                     0x01
+#define WCD939X_SWR_HM_TEST_TX_2_LN3_T_KEEPER_EN_SHIFT                    0x00
+
+/* WCD939X_SWR_HM_TEST_0 Fields: */
+#define WCD939X_SWR_HM_TEST_0_TX_LN2_T_DATA_IN_SHIFT                      0x07
+#define WCD939X_SWR_HM_TEST_0_TX_LN2_T_CLK_IN_SHIFT                       0x06
+#define WCD939X_SWR_HM_TEST_0_TX_LN1_T_DATA_IN_SHIFT                      0x05
+#define WCD939X_SWR_HM_TEST_0_TX_LN1_T_CLK_IN_SHIFT                       0x04
+#define WCD939X_SWR_HM_TEST_0_RX_LN2_T_DATA_IN_SHIFT                      0x03
+#define WCD939X_SWR_HM_TEST_0_RX_LN2_T_CLK_IN_SHIFT                       0x02
+#define WCD939X_SWR_HM_TEST_0_RX_LN1_T_DATA_IN_SHIFT                      0x01
+#define WCD939X_SWR_HM_TEST_0_RX_LN1_T_CLK_IN_SHIFT                       0x00
+
+/* WCD939X_SWR_HM_TEST_1 Fields: */
+#define WCD939X_SWR_HM_TEST_1_TX_LN3_T_DATA_IN_SHIFT                      0x01
+#define WCD939X_SWR_HM_TEST_1_TX_LN3_T_CLK_IN_SHIFT                       0x00
+
+/* WCD939X_PAD_CTL_SWR_0 Fields: */
+#define WCD939X_PAD_CTL_SWR_0_SWR_SLEW_PRG_SHIFT                          0x04
+#define WCD939X_PAD_CTL_SWR_0_SWR_DRIVE_PRG_SHIFT                         0x00
+
+/* WCD939X_PAD_CTL_SWR_1 Fields: */
+#define WCD939X_PAD_CTL_SWR_1_SWR_TDZ_PRG_SHIFT                           0x00
+
+/* WCD939X_I2C_CTL Fields: */
+#define WCD939X_I2C_CTL_ACTIVE_MODE_SHIFT                                 0x00
+
+/* WCD939X_CDC_TX_TANGGU_SW_MODE Fields: */
+#define WCD939X_CDC_TX_TANGGU_SW_MODE_LEGACY_SW_MODE_SHIFT                0x00
+
+/* WCD939X_EFUSE_TEST_CTL_0 Fields: */
+#define WCD939X_EFUSE_TEST_CTL_0_EFUSE_TEST_CTL_LSB_SHIFT                 0x00
+
+/* WCD939X_EFUSE_TEST_CTL_1 Fields: */
+#define WCD939X_EFUSE_TEST_CTL_1_EFUSE_TEST_CTL_MSB_SHIFT                 0x00
+
+/* WCD939X_EFUSE_T_DATA_0 Fields: */
+#define WCD939X_EFUSE_T_DATA_0_EFUSE_DATA_SHIFT                           0x00
+
+/* WCD939X_EFUSE_T_DATA_1 Fields: */
+#define WCD939X_EFUSE_T_DATA_1_EFUSE_DATA_SHIFT                           0x00
+
+/* WCD939X_PAD_CTL_PDM_RX0 Fields: */
+#define WCD939X_PAD_CTL_PDM_RX0_PDM_SLEW_PRG_SHIFT                        0x04
+#define WCD939X_PAD_CTL_PDM_RX0_PDM_DRIVE_PRG_SHIFT                       0x00
+
+/* WCD939X_PAD_CTL_PDM_RX1 Fields: */
+#define WCD939X_PAD_CTL_PDM_RX1_PDM_SLEW_PRG_SHIFT                        0x04
+#define WCD939X_PAD_CTL_PDM_RX1_PDM_DRIVE_PRG_SHIFT                       0x00
+
+/* WCD939X_PAD_CTL_PDM_TX0 Fields: */
+#define WCD939X_PAD_CTL_PDM_TX0_PDM_SLEW_PRG_SHIFT                        0x04
+#define WCD939X_PAD_CTL_PDM_TX0_PDM_DRIVE_PRG_SHIFT                       0x00
+
+/* WCD939X_PAD_CTL_PDM_TX1 Fields: */
+#define WCD939X_PAD_CTL_PDM_TX1_PDM_SLEW_PRG_SHIFT                        0x04
+#define WCD939X_PAD_CTL_PDM_TX1_PDM_DRIVE_PRG_SHIFT                       0x00
+
+/* WCD939X_PAD_CTL_PDM_TX2 Fields: */
+#define WCD939X_PAD_CTL_PDM_TX2_PDM_SLEW_PRG_SHIFT                        0x04
+#define WCD939X_PAD_CTL_PDM_TX2_PDM_DRIVE_PRG_SHIFT                       0x00
+
+/* WCD939X_PAD_INP_DIS_0 Fields: */
+#define WCD939X_PAD_INP_DIS_0_DMIC3_CLK_SHIFT                             0x05
+#define WCD939X_PAD_INP_DIS_0_DMIC3_DATA_SHIFT                            0x04
+#define WCD939X_PAD_INP_DIS_0_DMIC2_CLK_SHIFT                             0x03
+#define WCD939X_PAD_INP_DIS_0_DMIC2_DATA_SHIFT                            0x02
+#define WCD939X_PAD_INP_DIS_0_DMIC1_CLK_SHIFT                             0x01
+#define WCD939X_PAD_INP_DIS_0_DMIC1_DATA_SHIFT                            0x00
+
+/* WCD939X_PAD_INP_DIS_1 Fields: */
+#define WCD939X_PAD_INP_DIS_1_DMIC4_CLK_SHIFT                             0x04
+#define WCD939X_PAD_INP_DIS_1_DMIC4_DATA_SHIFT                            0x03
+
+/* WCD939X_DRIVE_STRENGTH_0 Fields: */
+#define WCD939X_DRIVE_STRENGTH_0_DS_DMIC2_CLK_SHIFT                       0x06
+#define WCD939X_DRIVE_STRENGTH_0_DS_DMIC2_DATA_SHIFT                      0x04
+#define WCD939X_DRIVE_STRENGTH_0_DS_DMIC1_CLK_SHIFT                       0x02
+#define WCD939X_DRIVE_STRENGTH_0_DS_DMIC1_DATA_SHIFT                      0x00
+
+/* WCD939X_DRIVE_STRENGTH_1 Fields: */
+#define WCD939X_DRIVE_STRENGTH_1_DS_DMIC3_CLK_SHIFT                       0x02
+#define WCD939X_DRIVE_STRENGTH_1_DS_DMIC3_DATA_SHIFT                      0x00
+
+/* WCD939X_DRIVE_STRENGTH_2 Fields: */
+#define WCD939X_DRIVE_STRENGTH_2_DS_DMIC4_CLK_SHIFT                       0x06
+#define WCD939X_DRIVE_STRENGTH_2_DS_DMIC4_DATA_SHIFT                      0x04
+
+/* WCD939X_RX_DATA_EDGE_CTL Fields: */
+#define WCD939X_RX_DATA_EDGE_CTL_HPH_CLH_EDGE_SHIFT                       0x05
+#define WCD939X_RX_DATA_EDGE_CTL_EAR_DOUT_EDGE_SHIFT                      0x04
+#define WCD939X_RX_DATA_EDGE_CTL_HPHR_DOUT_EDGE_SHIFT                     0x03
+#define WCD939X_RX_DATA_EDGE_CTL_HPHL_DOUT_EDGE_SHIFT                     0x02
+#define WCD939X_RX_DATA_EDGE_CTL_HPHR_GAIN_EDGE_SHIFT                     0x01
+#define WCD939X_RX_DATA_EDGE_CTL_HPHL_GAIN_EDGE_SHIFT                     0x00
+
+/* WCD939X_TX_DATA_EDGE_CTL Fields: */
+#define WCD939X_TX_DATA_EDGE_CTL_TX_WE_DLY_SHIFT                          0x06
+#define WCD939X_TX_DATA_EDGE_CTL_TX3_DIN_EDGE_SHIFT                       0x03
+#define WCD939X_TX_DATA_EDGE_CTL_TX2_DIN_EDGE_SHIFT                       0x02
+#define WCD939X_TX_DATA_EDGE_CTL_TX1_DIN_EDGE_SHIFT                       0x01
+#define WCD939X_TX_DATA_EDGE_CTL_TX0_DIN_EDGE_SHIFT                       0x00
+
+/* WCD939X_GPIO_MODE Fields: */
+#define WCD939X_GPIO_MODE_GPIO_3_EN_SHIFT                                 0x02
+#define WCD939X_GPIO_MODE_GPIO_2_EN_SHIFT                                 0x01
+#define WCD939X_GPIO_MODE_TEST_MODE_SHIFT                                 0x00
+
+/* WCD939X_PIN_CTL_OE Fields: */
+#define WCD939X_PIN_CTL_OE_TEST_PIN_CTL_OE_SHIFT                          0x04
+#define WCD939X_PIN_CTL_OE_GPIO_3_PIN_CTL_OE_SHIFT                        0x03
+#define WCD939X_PIN_CTL_OE_GPIO_2_PIN_CTL_OE_SHIFT                        0x02
+
+/* WCD939X_PIN_CTL_DATA_0 Fields: */
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC3_CLK_SHIFT                        0x05
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC3_DATA_SHIFT                       0x04
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC2_CLK_SHIFT                        0x03
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC2_DATA_SHIFT                       0x02
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC1_CLK_SHIFT                        0x01
+#define WCD939X_PIN_CTL_DATA_0_PAD_DMIC1_DATA_SHIFT                       0x00
+
+/* WCD939X_PIN_CTL_DATA_1 Fields: */
+#define WCD939X_PIN_CTL_DATA_1_PAD_DMIC4_CLK_SHIFT                        0x03
+#define WCD939X_PIN_CTL_DATA_1_PAD_DMIC4_DATA_SHIFT                       0x02
+
+/* WCD939X_PIN_STATUS_0 Fields: */
+#define WCD939X_PIN_STATUS_0_PAD_DMIC3_CLK_SHIFT                          0x05
+#define WCD939X_PIN_STATUS_0_PAD_DMIC3_DATA_SHIFT                         0x04
+#define WCD939X_PIN_STATUS_0_PAD_DMIC2_CLK_SHIFT                          0x03
+#define WCD939X_PIN_STATUS_0_PAD_DMIC2_DATA_SHIFT                         0x02
+#define WCD939X_PIN_STATUS_0_PAD_DMIC1_CLK_SHIFT                          0x01
+#define WCD939X_PIN_STATUS_0_PAD_DMIC1_DATA_SHIFT                         0x00
+
+/* WCD939X_PIN_STATUS_1 Fields: */
+#define WCD939X_PIN_STATUS_1_PAD_DMIC4_CLK_SHIFT                          0x03
+#define WCD939X_PIN_STATUS_1_PAD_DMIC4_DATA_SHIFT                         0x02
+
+/* WCD939X_DIG_DEBUG_CTL Fields: */
+#define WCD939X_DIG_DEBUG_CTL_DIG_DEBUG_CTL_SHIFT                         0x00
+
+/* WCD939X_DIG_DEBUG_EN Fields: */
+#define WCD939X_DIG_DEBUG_EN_TX_DBG_MODE_SHIFT                            0x02
+#define WCD939X_DIG_DEBUG_EN_RX_DBG_MODE_1_SHIFT                          0x01
+#define WCD939X_DIG_DEBUG_EN_RX_DBG_MODE_0_SHIFT                          0x00
+
+/* WCD939X_ANA_CSR_DBG_ADD Fields: */
+#define WCD939X_ANA_CSR_DBG_ADD_ADD_SHIFT                                 0x00
+
+/* WCD939X_ANA_CSR_DBG_CTL Fields: */
+#define WCD939X_ANA_CSR_DBG_CTL_WR_VALUE_SHIFT                            0x06
+#define WCD939X_ANA_CSR_DBG_CTL_RD_VALUE_SHIFT                            0x03
+#define WCD939X_ANA_CSR_DBG_CTL_DBG_PAGE_SEL_SHIFT                        0x01
+#define WCD939X_ANA_CSR_DBG_CTL_DBG_EN_SHIFT                              0x00
+
+/* WCD939X_SSP_DBG Fields: */
+#define WCD939X_SSP_DBG_RX_SSP_DBG_SHIFT                                  0x01
+#define WCD939X_SSP_DBG_TX_SSP_DBG_SHIFT                                  0x00
+
+/* WCD939X_MODE_STATUS_0 Fields: */
+#define WCD939X_MODE_STATUS_0_ATE_7_SHIFT                                 0x07
+#define WCD939X_MODE_STATUS_0_ATE_6_SHIFT                                 0x06
+#define WCD939X_MODE_STATUS_0_ATE_5_SHIFT                                 0x05
+#define WCD939X_MODE_STATUS_0_ATE_4_SHIFT                                 0x04
+#define WCD939X_MODE_STATUS_0_ATE_3_SHIFT                                 0x03
+#define WCD939X_MODE_STATUS_0_ATE_2_SHIFT                                 0x02
+#define WCD939X_MODE_STATUS_0_ATE_1_SHIFT                                 0x01
+#define WCD939X_MODE_STATUS_0_SWR_TEST_SHIFT                              0x00
+
+/* WCD939X_MODE_STATUS_1 Fields: */
+#define WCD939X_MODE_STATUS_1_SWR_PAD_TEST_SHIFT                          0x01
+#define WCD939X_MODE_STATUS_1_EFUSE_MODE_SHIFT                            0x00
+
+/* WCD939X_SPARE_0 Fields: */
+#define WCD939X_SPARE_0_SPARE_REG_0_SHIFT                                 0x00
+
+/* WCD939X_SPARE_1 Fields: */
+#define WCD939X_SPARE_1_SPARE_REG_1_SHIFT                                 0x00
+
+/* WCD939X_SPARE_2 Fields: */
+#define WCD939X_SPARE_2_SPARE_REG_2_SHIFT                                 0x00
+
+/* WCD939X_EFUSE_REG_0 Fields: */
+#define WCD939X_EFUSE_REG_0_SPARE_BITS_SHIFT                              0x05
+#define WCD939X_EFUSE_REG_0_WCD939X_ID_SHIFT                              0x01
+#define WCD939X_EFUSE_REG_0_EFUSE_BLOWN_SHIFT                             0x00
+
+/* WCD939X_EFUSE_REG_1 Fields: */
+#define WCD939X_EFUSE_REG_1_LOT_ID_0_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_2 Fields: */
+#define WCD939X_EFUSE_REG_2_LOT_ID_1_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_3 Fields: */
+#define WCD939X_EFUSE_REG_3_LOT_ID_2_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_4 Fields: */
+#define WCD939X_EFUSE_REG_4_LOT_ID_3_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_5 Fields: */
+#define WCD939X_EFUSE_REG_5_LOT_ID_4_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_6 Fields: */
+#define WCD939X_EFUSE_REG_6_LOT_ID_5_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_7 Fields: */
+#define WCD939X_EFUSE_REG_7_LOT_ID_6_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_8 Fields: */
+#define WCD939X_EFUSE_REG_8_LOT_ID_7_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_9 Fields: */
+#define WCD939X_EFUSE_REG_9_LOT_ID_8_SHIFT                                0x00
+
+/* WCD939X_EFUSE_REG_10 Fields: */
+#define WCD939X_EFUSE_REG_10_LOT_ID_9_SHIFT                               0x00
+
+/* WCD939X_EFUSE_REG_11 Fields: */
+#define WCD939X_EFUSE_REG_11_LOT_ID_10_SHIFT                              0x00
+
+/* WCD939X_EFUSE_REG_12 Fields: */
+#define WCD939X_EFUSE_REG_12_LOT_ID_11_SHIFT                              0x00
+
+/* WCD939X_EFUSE_REG_13 Fields: */
+#define WCD939X_EFUSE_REG_13_WAFER_ID_SHIFT                               0x00
+
+/* WCD939X_EFUSE_REG_14 Fields: */
+#define WCD939X_EFUSE_REG_14_X_DIE_LOCATION_SHIFT                         0x00
+
+/* WCD939X_EFUSE_REG_15 Fields: */
+#define WCD939X_EFUSE_REG_15_Y_DIE_LOCATION_SHIFT                         0x00
+
+/* WCD939X_EFUSE_REG_16 Fields: */
+#define WCD939X_EFUSE_REG_16_FAB_ID_SHIFT                                 0x00
+
+/* WCD939X_EFUSE_REG_17 Fields: */
+#define WCD939X_EFUSE_REG_17_TEST_PROGRAM_REV_SHIFT                       0x00
+
+/* WCD939X_EFUSE_REG_18 Fields: */
+#define WCD939X_EFUSE_REG_18_DIE_REVISION_SHIFT                           0x00
+
+/* WCD939X_EFUSE_REG_19 Fields: */
+#define WCD939X_EFUSE_REG_19_MFG_ID_SPARE_SHIFT                           0x00
+
+/* WCD939X_EFUSE_REG_20 Fields: */
+#define WCD939X_EFUSE_REG_20_I2C_SLV_ID_BLOWN_SHIFT                       0x07
+#define WCD939X_EFUSE_REG_20_I2C_SLAVE_ID_SHIFT                           0x00
+
+/* WCD939X_EFUSE_REG_21 Fields: */
+#define WCD939X_EFUSE_REG_21_MBHC_IMP_DET_0_SHIFT                         0x00
+
+/* WCD939X_EFUSE_REG_22 Fields: */
+#define WCD939X_EFUSE_REG_22_MBHC_IMP_DET_1_SHIFT                         0x00
+
+/* WCD939X_EFUSE_REG_23 Fields: */
+#define WCD939X_EFUSE_REG_23_SWR_PAD_DRIVE_PRG_1P2V_SHIFT                 0x04
+#define WCD939X_EFUSE_REG_23_SWR_SLEW_PRG_1P2V_SHIFT                      0x00
+
+/* WCD939X_EFUSE_REG_24 Fields: */
+#define WCD939X_EFUSE_REG_24_SPARE_BITS_SHIFT                             0x05
+#define WCD939X_EFUSE_REG_24_SWR_PAD_BLOWN_SHIFT                          0x04
+#define WCD939X_EFUSE_REG_24_SWR_TDZ_DELAY_PRG_1P2V_SHIFT                 0x00
+
+/* WCD939X_EFUSE_REG_25 Fields: */
+#define WCD939X_EFUSE_REG_25_MBHC_IMP_DET_2_SHIFT                         0x00
+
+/* WCD939X_EFUSE_REG_26 Fields: */
+#define WCD939X_EFUSE_REG_26_MBHC_IMP_DET_3_SHIFT                         0x00
+
+/* WCD939X_EFUSE_REG_27 Fields: */
+#define WCD939X_EFUSE_REG_27_HPH_DSD_DIS_SHIFT                            0x07
+#define WCD939X_EFUSE_REG_27_BG_TUNE_BLOWN_SHIFT                          0x06
+#define WCD939X_EFUSE_REG_27_BG_TUNE_SHIFT                                0x04
+#define WCD939X_EFUSE_REG_27_EFUSE_HPH_SHIFT                              0x00
+
+/* WCD939X_EFUSE_REG_28 Fields: */
+#define WCD939X_EFUSE_REG_28_HPH_CLH_DIS_SHIFT                            0x07
+#define WCD939X_EFUSE_REG_28_HPH_LOHIFI_DIS_SHIFT                         0x06
+#define WCD939X_EFUSE_REG_28_HPH_HIFI_DIS_SHIFT                           0x05
+#define WCD939X_EFUSE_REG_28_EAR_CLH_DIS_SHIFT                            0x04
+#define WCD939X_EFUSE_REG_28_DMIC_DIS_SHIFT                               0x03
+#define WCD939X_EFUSE_REG_28_TX_LP_DIS_SHIFT                              0x02
+#define WCD939X_EFUSE_REG_28_TX_HP_DIS_SHIFT                              0x01
+#define WCD939X_EFUSE_REG_28_SPARE_BITS_SHIFT                             0x00
+
+/* WCD939X_EFUSE_REG_29 Fields: */
+#define WCD939X_EFUSE_REG_29_TX_ULP1_DIS_SHIFT                            0x07
+#define WCD939X_EFUSE_REG_29_TX_ULP2_DIS_SHIFT                            0x06
+#define WCD939X_EFUSE_REG_29_SPARE_BITS_SHIFT                             0x04
+#define WCD939X_EFUSE_REG_29_SWR_PAD_DRIVE_PRG_1P8V_SHIFT                 0x00
+
+/* WCD939X_EFUSE_REG_30 Fields: */
+#define WCD939X_EFUSE_REG_30_SWR_SLEW_PRG_1P8V_SHIFT                      0x04
+#define WCD939X_EFUSE_REG_30_SWR_TDZ_DELAY_PRG_1P8V_SHIFT                 0x00
+
+/* WCD939X_EFUSE_REG_31 Fields: */
+#define WCD939X_EFUSE_REG_31_SPARE_EFUSE_ANA_SHIFT                        0x00
+
+/* WCD939X_TX_REQ_FB_CTL_0 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_0_ULP2_FB_T2_SHIFT                          0x04
+#define WCD939X_TX_REQ_FB_CTL_0_ULP2_FB_T1_SHIFT                          0x00
+
+/* WCD939X_TX_REQ_FB_CTL_1 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_1_ULP1_FB_T2_SHIFT                          0x04
+#define WCD939X_TX_REQ_FB_CTL_1_ULP1_FB_T1_SHIFT                          0x00
+
+/* WCD939X_TX_REQ_FB_CTL_2 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_2_L0_FB_T2_SHIFT                            0x04
+#define WCD939X_TX_REQ_FB_CTL_2_L0_FB_T1_SHIFT                            0x00
+
+/* WCD939X_TX_REQ_FB_CTL_3 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_3_L1_FB_T2_SHIFT                            0x04
+#define WCD939X_TX_REQ_FB_CTL_3_L1_FB_T1_SHIFT                            0x00
+
+/* WCD939X_TX_REQ_FB_CTL_4 Fields: */
+#define WCD939X_TX_REQ_FB_CTL_4_L2_FB_T2_SHIFT                            0x04
+#define WCD939X_TX_REQ_FB_CTL_4_L2_FB_T1_SHIFT                            0x00
+
+/* WCD939X_DEM_BYPASS_DATA0 Fields: */
+#define WCD939X_DEM_BYPASS_DATA0_DEM_BYPASS_DATA0_SHIFT                   0x00
+
+/* WCD939X_DEM_BYPASS_DATA1 Fields: */
+#define WCD939X_DEM_BYPASS_DATA1_DEM_BYPASS_DATA1_SHIFT                   0x00
+
+/* WCD939X_DEM_BYPASS_DATA2 Fields: */
+#define WCD939X_DEM_BYPASS_DATA2_DEM_BYPASS_DATA2_SHIFT                   0x00
+
+/* WCD939X_DEM_BYPASS_DATA3 Fields: */
+#define WCD939X_DEM_BYPASS_DATA3_DEM_BYPASS_DATA3_SHIFT                   0x00
+
+/* WCD939X_DEM_SECOND_ORDER Fields: */
+#define WCD939X_DEM_SECOND_ORDER_DEM_1_2ND_ORDER_EN_SHIFT                 0x01
+#define WCD939X_DEM_SECOND_ORDER_DEM_0_2ND_ORDER_EN_SHIFT                 0x00
+
+/* WCD939X_DSM_CTRL Fields: */
+#define WCD939X_DSM_CTRL_DSM_1_STATIC_EN_SHIFT                            0x01
+#define WCD939X_DSM_CTRL_DSM_0_STATIC_EN_SHIFT                            0x00
+
+/* WCD939X_DSM_0_STATIC_DATA_0 Fields: */
+#define WCD939X_DSM_0_STATIC_DATA_0_DSM_0_STATIC_DATA0_SHIFT              0x00
+
+/* WCD939X_DSM_0_STATIC_DATA_1 Fields: */
+#define WCD939X_DSM_0_STATIC_DATA_1_DSM_0_STATIC_DATA1_SHIFT              0x00
+
+/* WCD939X_DSM_0_STATIC_DATA_2 Fields: */
+#define WCD939X_DSM_0_STATIC_DATA_2_DSM_0_STATIC_DATA2_SHIFT              0x00
+
+/* WCD939X_DSM_0_STATIC_DATA_3 Fields: */
+#define WCD939X_DSM_0_STATIC_DATA_3_DSM_0_STATIC_DATA3_SHIFT              0x00
+
+/* WCD939X_DSM_1_STATIC_DATA_0 Fields: */
+#define WCD939X_DSM_1_STATIC_DATA_0_DSM_1_STATIC_DATA0_SHIFT              0x00
+
+/* WCD939X_DSM_1_STATIC_DATA_1 Fields: */
+#define WCD939X_DSM_1_STATIC_DATA_1_DSM_1_STATIC_DATA1_SHIFT              0x00
+
+/* WCD939X_DSM_1_STATIC_DATA_2 Fields: */
+#define WCD939X_DSM_1_STATIC_DATA_2_DSM_1_STATIC_DATA2_SHIFT              0x00
+
+/* WCD939X_DSM_1_STATIC_DATA_3 Fields: */
+#define WCD939X_DSM_1_STATIC_DATA_3_DSM_1_STATIC_DATA3_SHIFT              0x00
+
+
+/* WCD939X_RX_PAGE Fields: */
+#define WCD939X_RX_PAGE_PAG_REG_SHIFT                                     0x00
+
+/* WCD939X_TOP_CFG0 Fields: */
+#define WCD939X_TOP_CFG0_HPH_DAC_RATE_SEL_SHIFT                           0x01
+#define WCD939X_TOP_CFG0_PGA_UPDATE_SHIFT                                 0x00
+
+/* WCD939X_HPHL_COMP_WR_LSB Fields: */
+#define WCD939X_HPHL_COMP_WR_LSB_COEFF_SHIFT                              0x00
+
+/* WCD939X_HPHL_COMP_WR_MSB Fields: */
+#define WCD939X_HPHL_COMP_WR_MSB_COEFF_SHIFT                              0x00
+
+/* WCD939X_HPHL_COMP_LUT Fields: */
+#define WCD939X_HPHL_COMP_LUT_BYPASS_SHIFT                                0x07
+#define WCD939X_HPHL_COMP_LUT_MANUAL_RD_SHIFT                             0x06
+#define WCD939X_HPHL_COMP_LUT_MANUAL_WR_SHIFT                             0x05
+#define WCD939X_HPHL_COMP_LUT_ADDR_SHIFT                                  0x00
+
+/* WCD939X_HPHL_COMP_RD_LSB Fields: */
+#define WCD939X_HPHL_COMP_RD_LSB_COEFF_SHIFT                              0x00
+
+/* WCD939X_HPHL_COMP_RD_MSB Fields: */
+#define WCD939X_HPHL_COMP_RD_MSB_COEFF_SHIFT                              0x00
+
+/* WCD939X_HPHR_COMP_WR_LSB Fields: */
+#define WCD939X_HPHR_COMP_WR_LSB_COEFF_SHIFT                              0x00
+
+/* WCD939X_HPHR_COMP_WR_MSB Fields: */
+#define WCD939X_HPHR_COMP_WR_MSB_COEFF_SHIFT                              0x00
+
+/* WCD939X_HPHR_COMP_LUT Fields: */
+#define WCD939X_HPHR_COMP_LUT_BYPASS_SHIFT                                0x07
+#define WCD939X_HPHR_COMP_LUT_MANUAL_RD_SHIFT                             0x06
+#define WCD939X_HPHR_COMP_LUT_MANUAL_WR_SHIFT                             0x05
+#define WCD939X_HPHR_COMP_LUT_ADDR_SHIFT                                  0x00
+
+/* WCD939X_HPHR_COMP_RD_LSB Fields: */
+#define WCD939X_HPHR_COMP_RD_LSB_COEFF_SHIFT                              0x00
+
+/* WCD939X_HPHR_COMP_RD_MSB Fields: */
+#define WCD939X_HPHR_COMP_RD_MSB_COEFF_SHIFT                              0x00
+
+/* WCD939X_DSD0_DEBUG_CFG1 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG1_DSD_UNPACKING_ORDER_SHIFT                 0x03
+#define WCD939X_DSD0_DEBUG_CFG1_DSD_DC_DET_EN_SHIFT                       0x02
+#define WCD939X_DSD0_DEBUG_CFG1_DSD_MUTE_DET_EN_SHIFT                     0x00
+
+/* WCD939X_DSD0_DEBUG_CFG2 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG2_MUTE_INI_VAL_SHIFT                        0x04
+#define WCD939X_DSD0_DEBUG_CFG2_DC_INTR_THRESHOLD_SHIFT                   0x02
+#define WCD939X_DSD0_DEBUG_CFG2_DC_DET_THRESHOLD_SHIFT                    0x00
+
+/* WCD939X_DSD0_DEBUG_CFG3 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG3_DSD_POST_GAIN_SHIFT                       0x03
+#define WCD939X_DSD0_DEBUG_CFG3_DSD_GAIN_ADJ_SHIFT                        0x00
+
+/* WCD939X_DSD0_DEBUG_CFG4 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG4_DSD_INPUT_ZOH_SHIFT                       0x00
+
+/* WCD939X_DSD0_DEBUG_CFG5 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG5_DSD_DC_DET_SHIFT                          0x07
+#define WCD939X_DSD0_DEBUG_CFG5_DSD_PGA_GAIN_UPD_STATUS_SHIFT             0x06
+#define WCD939X_DSD0_DEBUG_CFG5_DSD_DC_SAMPLE_NUM_MSB_SHIFT               0x00
+
+/* WCD939X_DSD0_DEBUG_CFG6 Fields: */
+#define WCD939X_DSD0_DEBUG_CFG6_DSD_DC_SAMPLE_NUM_LSB_SHIFT               0x00
+
+/* WCD939X_DSD1_DEBUG_CFG1 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG1_DSD_UNPACKING_ORDER_SHIFT                 0x02
+#define WCD939X_DSD1_DEBUG_CFG1_DSD_DC_DET_EN_SHIFT                       0x01
+#define WCD939X_DSD1_DEBUG_CFG1_DSD_MUTE_DET_EN_SHIFT                     0x00
+
+/* WCD939X_DSD1_DEBUG_CFG2 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG2_MUTE_INI_VAL_SHIFT                        0x04
+#define WCD939X_DSD1_DEBUG_CFG2_DC_INTR_THRESHOLD_SHIFT                   0x02
+#define WCD939X_DSD1_DEBUG_CFG2_DC_DET_THRESHOLD_SHIFT                    0x00
+
+/* WCD939X_DSD1_DEBUG_CFG3 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG3_DSD_POST_GAIN_SHIFT                       0x03
+#define WCD939X_DSD1_DEBUG_CFG3_DSD_GAIN_ADJ_SHIFT                        0x00
+
+/* WCD939X_DSD1_DEBUG_CFG4 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG4_DSD_INPUT_ZOH_SHIFT                       0x00
+
+/* WCD939X_DSD1_DEBUG_CFG5 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG5_DSD_DC_DET_SHIFT                          0x07
+#define WCD939X_DSD1_DEBUG_CFG5_DSD_PGA_GAIN_UPD_STATUS_SHIFT             0x06
+#define WCD939X_DSD1_DEBUG_CFG5_DSD_DC_SAMPLE_NUM_MSB_SHIFT               0x00
+
+/* WCD939X_DSD1_DEBUG_CFG6 Fields: */
+#define WCD939X_DSD1_DEBUG_CFG6_DSD_DC_SAMPLE_NUM_LSB_SHIFT               0x00
+
+/* WCD939X_HPHL_RX_PATH_CFG0 Fields: */
+#define WCD939X_HPHL_RX_PATH_CFG0_INT_EN_SHIFT                            0x01
+#define WCD939X_HPHL_RX_PATH_CFG0_DLY_ZN_EN_SHIFT                         0x00
+
+/* WCD939X_HPHL_RX_PATH_CFG1 Fields: */
+#define WCD939X_HPHL_RX_PATH_CFG1_DSM_SOFT_RST_SHIFT                      0x05
+#define WCD939X_HPHL_RX_PATH_CFG1_INT_SOFT_RST_SHIFT                      0x04
+#define WCD939X_HPHL_RX_PATH_CFG1_FMT_CONV_SHIFT                          0x03
+#define WCD939X_HPHL_RX_PATH_CFG1_IDLE_OVRD_EN_SHIFT                      0x02
+#define WCD939X_HPHL_RX_PATH_CFG1_RX_DC_DROOP_COEFF_SEL_SHIFT             0x00
+
+/* WCD939X_HPHR_RX_PATH_CFG0 Fields: */
+#define WCD939X_HPHR_RX_PATH_CFG0_INT_EN_SHIFT                            0x02
+#define WCD939X_HPHR_RX_PATH_CFG0_DLY_ZN_EN_SHIFT                         0x01
+
+/* WCD939X_HPHR_RX_PATH_CFG1 Fields: */
+#define WCD939X_HPHR_RX_PATH_CFG1_DSM_SOFT_RST_SHIFT                      0x05
+#define WCD939X_HPHR_RX_PATH_CFG1_INT_SOFT_RST_SHIFT                      0x04
+#define WCD939X_HPHR_RX_PATH_CFG1_FMT_CONV_SHIFT                          0x03
+#define WCD939X_HPHR_RX_PATH_CFG1_IDLE_OVRD_EN_SHIFT                      0x02
+#define WCD939X_HPHR_RX_PATH_CFG1_RX_DC_DROOP_COEFF_SEL_SHIFT             0x00
+
+/* WCD939X_RX_PATH_CFG2 Fields: */
+#define WCD939X_RX_PATH_CFG2_COMP_XTALK_EN_SHIFT                          0x03
+#define WCD939X_RX_PATH_CFG2_XTALK_NLIN_EN_SHIFT                          0x02
+#define WCD939X_RX_PATH_CFG2_XTALK_LIN_EN_SHIFT                           0x01
+#define WCD939X_RX_PATH_CFG2_XTALK_EN_SHIFT                               0x00
+
+/* WCD939X_HPHL_RX_PATH_SEC0 Fields: */
+#define WCD939X_HPHL_RX_PATH_SEC0_LIN_XTALK_POLARITY_SHIFT                0x05
+#define WCD939X_HPHL_RX_PATH_SEC0_LIN_XTALK_SCALE_SHIFT                   0x00
+
+/* WCD939X_HPHL_RX_PATH_SEC1 Fields: */
+#define WCD939X_HPHL_RX_PATH_SEC1_LIN_XTALK_ALPHA_SHIFT                   0x00
+
+/* WCD939X_HPHL_RX_PATH_SEC2 Fields: */
+#define WCD939X_HPHL_RX_PATH_SEC2_NLIN_XTALK_POLARITY_SHIFT               0x06
+#define WCD939X_HPHL_RX_PATH_SEC2_NLIN_XTALK_BYPASS_SHIFT                 0x05
+#define WCD939X_HPHL_RX_PATH_SEC2_NLIN_XTALK_SCALE_SHIFT                  0x00
+
+/* WCD939X_HPHL_RX_PATH_SEC3 Fields: */
+#define WCD939X_HPHL_RX_PATH_SEC3_NLIN_XTALK_ALPHA_SHIFT                  0x00
+
+/* WCD939X_HPHR_RX_PATH_SEC0 Fields: */
+#define WCD939X_HPHR_RX_PATH_SEC0_LIN_XTALK_POLARITY_SHIFT                0x05
+#define WCD939X_HPHR_RX_PATH_SEC0_LIN_XTALK_SCALE_SHIFT                   0x00
+
+/* WCD939X_HPHR_RX_PATH_SEC1 Fields: */
+#define WCD939X_HPHR_RX_PATH_SEC1_LIN_XTALK_ALPHA_SHIFT                   0x00
+
+/* WCD939X_HPHR_RX_PATH_SEC2 Fields: */
+#define WCD939X_HPHR_RX_PATH_SEC2_NLIN_XTALK_POLARITY_SHIFT               0x06
+#define WCD939X_HPHR_RX_PATH_SEC2_NLIN_XTALK_BYPASS_SHIFT                 0x05
+#define WCD939X_HPHR_RX_PATH_SEC2_NLIN_XTALK_SCALE_SHIFT                  0x00
+
+/* WCD939X_HPHR_RX_PATH_SEC3 Fields: */
+#define WCD939X_HPHR_RX_PATH_SEC3_NLIN_XTALK_ALPHA_SHIFT                  0x00
+
+/* WCD939X_RX_PATH_SEC4 Fields: */
+#define WCD939X_RX_PATH_SEC4_NLIN_CMB_POLARITY_SHIFT                      0x05
+#define WCD939X_RX_PATH_SEC4_NLIN_CMB_SCALE_SHIFT                         0x00
+
+/* WCD939X_RX_PATH_SEC5 Fields: */
+#define WCD939X_RX_PATH_SEC5_NLIN_CMB_ALPHA_SHIFT                         0x00
+
+
+/* WCD939X_CTL0 Fields: */
+#define WCD939X_CTL0_SHUTDWN_TOUT_SHIFT                                   0x04
+#define WCD939X_CTL0_DROPOUT_EN_SHIFT                                     0x03
+#define WCD939X_CTL0_COMP_HALT_SHIFT                                      0x02
+#define WCD939X_CTL0_SOFT_RST_SHIFT                                       0x01
+#define WCD939X_CTL0_CLK_EN_SHIFT                                         0x00
+
+/* WCD939X_CTL1 Fields: */
+#define WCD939X_CTL1_LEVEL_METER_DIV_FACTOR_SHIFT                         0x04
+#define WCD939X_CTL1_PEAK_METER_TOUT_SHIFT                                0x00
+
+/* WCD939X_CTL2 Fields: */
+#define WCD939X_CTL2_LEVEL_METER_RESAMPLE_RATE_SHIFT                      0x00
+
+/* WCD939X_CTL3 Fields: */
+#define WCD939X_CTL3_STATIC_GAIN_OFFSET_SHIFT                             0x07
+#define WCD939X_CTL3_ZONE_SELECT_SHIFT_SHIFT                              0x04
+#define WCD939X_CTL3_ZONE_SELECT_ENTRY_SHIFT                              0x00
+
+/* WCD939X_CTL4 Fields: */
+#define WCD939X_CTL4_DET_WINDOW_SHIFT                                     0x00
+
+/* WCD939X_CTL5 Fields: */
+#define WCD939X_CTL5_GAIN_MAX_THOLD_SHIFT                                 0x03
+#define WCD939X_CTL5_DET_WINDOW_SHIFT                                     0x00
+
+/* WCD939X_CTL6 Fields: */
+#define WCD939X_CTL6_STATUS_SHIFT                                         0x00
+
+/* WCD939X_CTL7 Fields: */
+#define WCD939X_CTL7_DIS_SCD_SHIFT                                        0x06
+#define WCD939X_CTL7_AGAIN_DELAY_SHIFT                                    0x01
+
+/* WCD939X_CTL8 Fields: */
+#define WCD939X_CTL8_PEAK_TO_FLAG_DIS_SHIFT                               0x01
+#define WCD939X_CTL8_GAIN_STEP_SELECT_SHIFT                               0x00
+
+/* WCD939X_CTL9 Fields: */
+#define WCD939X_CTL9_ZONE0_RMS_SHIFT                                      0x00
+
+/* WCD939X_CTL10 Fields: */
+#define WCD939X_CTL10_ZONE1_RMS_SHIFT                                     0x00
+
+/* WCD939X_CTL11 Fields: */
+#define WCD939X_CTL11_ZONE2_RMS_SHIFT                                     0x00
+
+/* WCD939X_CTL12 Fields: */
+#define WCD939X_CTL12_ZONE3_RMS_SHIFT                                     0x00
+
+/* WCD939X_CTL13 Fields: */
+#define WCD939X_CTL13_ZONE4_RMS_SHIFT                                     0x00
+
+/* WCD939X_CTL14 Fields: */
+#define WCD939X_CTL14_ZONE5_RMS_SHIFT                                     0x00
+
+/* WCD939X_CTL15 Fields: */
+#define WCD939X_CTL15_ZONE6_RMS_SHIFT                                     0x00
+
+/* WCD939X_CTL16 Fields: */
+#define WCD939X_CTL16_MAX_ATTN_SHIFT                                      0x00
+
+/* WCD939X_CTL17 Fields: */
+#define WCD939X_CTL17_PATH_GAIN_SHIFT                                     0x00
+
+/* WCD939X_CTL18 Fields: */
+#define WCD939X_CTL18_ANA_ADDR_MAP_SHIFT                                  0x00
+
+/* WCD939X_CTL19 Fields: */
+#define WCD939X_CTL19_RMS_TOUT_SHIFT                                      0x01
+#define WCD939X_CTL19_RMS_TOUT_OVERRIDE_SHIFT                             0x00
+
+
+/* WCD939X_R_CTL0 Fields: */
+#define WCD939X_R_CTL0_SHUTDWN_TOUT_SHIFT                                 0x04
+#define WCD939X_R_CTL0_DROPOUT_EN_SHIFT                                   0x03
+#define WCD939X_R_CTL0_COMP_HALT_SHIFT                                    0x02
+#define WCD939X_R_CTL0_SOFT_RST_SHIFT                                     0x01
+#define WCD939X_R_CTL0_CLK_EN_SHIFT                                       0x00
+
+/* WCD939X_R_CTL1 Fields: */
+#define WCD939X_R_CTL1_LEVEL_METER_DIV_FACTOR_SHIFT                       0x04
+#define WCD939X_R_CTL1_PEAK_METER_TOUT_SHIFT                              0x00
+
+/* WCD939X_R_CTL2 Fields: */
+#define WCD939X_R_CTL2_LEVEL_METER_RESAMPLE_RATE_SHIFT                    0x00
+
+/* WCD939X_R_CTL3 Fields: */
+#define WCD939X_R_CTL3_STATIC_GAIN_OFFSET_SHIFT                           0x07
+#define WCD939X_R_CTL3_ZONE_SELECT_SHIFT_SHIFT                            0x04
+#define WCD939X_R_CTL3_ZONE_SELECT_ENTRY_SHIFT                            0x00
+
+/* WCD939X_R_CTL4 Fields: */
+#define WCD939X_R_CTL4_DET_WINDOW_SHIFT                                   0x00
+
+/* WCD939X_R_CTL5 Fields: */
+#define WCD939X_R_CTL5_GAIN_MAX_THOLD_SHIFT                               0x03
+#define WCD939X_R_CTL5_DET_WINDOW_SHIFT                                   0x00
+
+/* WCD939X_R_CTL6 Fields: */
+#define WCD939X_R_CTL6_STATUS_SHIFT                                       0x00
+
+/* WCD939X_R_CTL7 Fields: */
+#define WCD939X_R_CTL7_DIS_SCD_SHIFT                                      0x06
+#define WCD939X_R_CTL7_AGAIN_DELAY_SHIFT                                  0x01
+
+/* WCD939X_R_CTL8 Fields: */
+#define WCD939X_R_CTL8_PEAK_TO_FLAG_DIS_SHIFT                             0x01
+#define WCD939X_R_CTL8_GAIN_STEP_SELECT_SHIFT                             0x00
+
+/* WCD939X_R_CTL9 Fields: */
+#define WCD939X_R_CTL9_ZONE0_RMS_SHIFT                                    0x00
+
+/* WCD939X_R_CTL10 Fields: */
+#define WCD939X_R_CTL10_ZONE1_RMS_SHIFT                                   0x00
+
+/* WCD939X_R_CTL11 Fields: */
+#define WCD939X_R_CTL11_ZONE2_RMS_SHIFT                                   0x00
+
+/* WCD939X_R_CTL12 Fields: */
+#define WCD939X_R_CTL12_ZONE3_RMS_SHIFT                                   0x00
+
+/* WCD939X_R_CTL13 Fields: */
+#define WCD939X_R_CTL13_ZONE4_RMS_SHIFT                                   0x00
+
+/* WCD939X_R_CTL14 Fields: */
+#define WCD939X_R_CTL14_ZONE5_RMS_SHIFT                                   0x00
+
+/* WCD939X_R_CTL15 Fields: */
+#define WCD939X_R_CTL15_ZONE6_RMS_SHIFT                                   0x00
+
+/* WCD939X_R_CTL16 Fields: */
+#define WCD939X_R_CTL16_MAX_ATTN_SHIFT                                    0x00
+
+/* WCD939X_R_CTL17 Fields: */
+#define WCD939X_R_CTL17_PATH_GAIN_SHIFT                                   0x00
+
+/* WCD939X_R_CTL18 Fields: */
+#define WCD939X_R_CTL18_ANA_ADDR_MAP_SHIFT                                0x00
+
+/* WCD939X_R_CTL19 Fields: */
+#define WCD939X_R_CTL19_RMS_TOUT_SHIFT                                    0x01
+#define WCD939X_R_CTL19_RMS_TOUT_OVERRIDE_SHIFT                           0x00
+
+
+/* WCD939X_PATH_CTL Fields: */
+#define WCD939X_PATH_CTL_RESET_RIGHT_SHIFT                                0x03
+#define WCD939X_PATH_CTL_RESET_LEFT_SHIFT                                 0x02
+#define WCD939X_PATH_CTL_CLK_EN_RIGHT_SHIFT                               0x01
+#define WCD939X_PATH_CTL_CLK_EN_LEFT_SHIFT                                0x00
+
+/* WCD939X_CFG0 Fields: */
+#define WCD939X_CFG0_AUTO_DISABLE_ANC_SHIFT                               0x02
+#define WCD939X_CFG0_AUTO_DISABLE_DSD_SHIFT                               0x01
+#define WCD939X_CFG0_IDLE_STEREO_SHIFT                                    0x00
+
+/* WCD939X_CFG1 Fields: */
+#define WCD939X_CFG1_IDLE_N_HOLDOFF_LSB_SHIFT                             0x00
+
+/* WCD939X_CFG2 Fields: */
+#define WCD939X_CFG2_IDLE_N_HOLDOFF_MSB_SHIFT                             0x00
+
+/* WCD939X_CFG3 Fields: */
+#define WCD939X_CFG3_IDLE_THRESHOLD_SHIFT                                 0x00
+
+
+/* WCD939X_DSD_HPHL_PATH_CTL Fields: */
+#define WCD939X_DSD_HPHL_PATH_CTL_RESET_SHIFT                             0x01
+#define WCD939X_DSD_HPHL_PATH_CTL_CLK_EN_SHIFT                            0x00
+
+/* WCD939X_DSD_HPHL_CFG0 Fields: */
+#define WCD939X_DSD_HPHL_CFG0_INP_SEL_SHIFT                               0x00
+
+/* WCD939X_DSD_HPHL_CFG1 Fields: */
+#define WCD939X_DSD_HPHL_CFG1_PGA_GAIN_SHIFT                              0x00
+
+/* WCD939X_DSD_HPHL_CFG2 Fields: */
+#define WCD939X_DSD_HPHL_CFG2_PGA_TIMER_MSB_EXT_SHIFT                     0x03
+#define WCD939X_DSD_HPHL_CFG2_PGA_MUTE_EN_SHIFT                           0x02
+#define WCD939X_DSD_HPHL_CFG2_PGA_MODE_SHIFT                              0x01
+#define WCD939X_DSD_HPHL_CFG2_PGA_HALF_DB_SHIFT                           0x00
+
+/* WCD939X_DSD_HPHL_CFG3 Fields: */
+#define WCD939X_DSD_HPHL_CFG3_PGA_TIMER_SHIFT                             0x00
+
+/* WCD939X_CFG4 Fields: */
+#define WCD939X_CFG4_TOGGLE_THRESHOLD_SHIFT                               0x03
+#define WCD939X_CFG4_MUTE_THRESHOLD_SHIFT                                 0x00
+
+/* WCD939X_CFG5 Fields: */
+#define WCD939X_CFG5_DATA_BIT_POLARITY_SHIFT                              0x01
+#define WCD939X_CFG5_INP_BIT_POLARITY_SHIFT                               0x00
+
+
+/* WCD939X_DSD_HPHR_PATH_CTL Fields: */
+#define WCD939X_DSD_HPHR_PATH_CTL_RESET_SHIFT                             0x01
+#define WCD939X_DSD_HPHR_PATH_CTL_CLK_EN_SHIFT                            0x00
+
+/* WCD939X_DSD_HPHR_CFG0 Fields: */
+#define WCD939X_DSD_HPHR_CFG0_INP_SEL_SHIFT                               0x00
+
+/* WCD939X_DSD_HPHR_CFG1 Fields: */
+#define WCD939X_DSD_HPHR_CFG1_PGA_GAIN_SHIFT                              0x00
+
+/* WCD939X_DSD_HPHR_CFG2 Fields: */
+#define WCD939X_DSD_HPHR_CFG2_PGA_TIMER_MSB_EXT_SHIFT                     0x03
+#define WCD939X_DSD_HPHR_CFG2_PGA_MUTE_EN_SHIFT                           0x02
+#define WCD939X_DSD_HPHR_CFG2_PGA_MODE_SHIFT                              0x01
+#define WCD939X_DSD_HPHR_CFG2_PGA_HALF_DB_SHIFT                           0x00
+
+/* WCD939X_DSD_HPHR_CFG3 Fields: */
+#define WCD939X_DSD_HPHR_CFG3_PGA_TIMER_SHIFT                             0x00
+
+/* WCD939X_DSD_HPHR_CFG4 Fields: */
+#define WCD939X_DSD_HPHR_CFG4_TOGGLE_THRESHOLD_SHIFT                      0x03
+#define WCD939X_DSD_HPHR_CFG4_MUTE_THRESHOLD_SHIFT                        0x00
+
+/* WCD939X_DSD_HPHR_CFG5 Fields: */
+#define WCD939X_DSD_HPHR_CFG5_DATA_BIT_POLARITY_SHIFT                     0x01
+#define WCD939X_DSD_HPHR_CFG5_INP_BIT_POLARITY_SHIFT                      0x00
+
+
+#endif /* WCD939X_REG_SHIFTS_H */

asoc/codecs/wcd939x/wcd939x-registers.h

@@ -0,0 +1,655 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef WCD939X_REGISTERS_H
+#define WCD939X_REGISTERS_H
+
+#define WCD939X_BASE 0x2fff
+#define WCD939X_REG(reg)  (reg - WCD939X_BASE - 1)
+
+enum {
+       REG_NO_ACCESS,
+       RD_REG,
+       WR_REG,
+       RD_WR_REG
+};
+
+
+#define WCD939X_ANA_BASE                       (WCD939X_BASE+0x01)
+#define WCD939X_ANA_PAGE                       (WCD939X_ANA_BASE+0x00)
+#define WCD939X_BIAS                           (WCD939X_ANA_BASE+0x01)
+#define WCD939X_RX_SUPPLIES                    (WCD939X_ANA_BASE+0x08)
+#define WCD939X_HPH                            (WCD939X_ANA_BASE+0x09)
+#define WCD939X_EAR                            (WCD939X_ANA_BASE+0x0a)
+#define WCD939X_EAR_COMPANDER_CTL              (WCD939X_ANA_BASE+0x0b)
+#define WCD939X_TX_CH1                         (WCD939X_ANA_BASE+0x0e)
+#define WCD939X_TX_CH2                         (WCD939X_ANA_BASE+0x0f)
+#define WCD939X_TX_CH3                         (WCD939X_ANA_BASE+0x10)
+#define WCD939X_TX_CH4                         (WCD939X_ANA_BASE+0x11)
+#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC       (WCD939X_ANA_BASE+0x12)
+#define WCD939X_MICB3_DSP_EN_LOGIC             (WCD939X_ANA_BASE+0x13)
+#define WCD939X_MBHC_MECH                      (WCD939X_ANA_BASE+0x14)
+#define WCD939X_MBHC_ELECT                     (WCD939X_ANA_BASE+0x15)
+#define WCD939X_MBHC_ZDET                      (WCD939X_ANA_BASE+0x16)
+#define WCD939X_MBHC_RESULT_1                  (WCD939X_ANA_BASE+0x17)
+#define WCD939X_MBHC_RESULT_2                  (WCD939X_ANA_BASE+0x18)
+#define WCD939X_MBHC_RESULT_3                  (WCD939X_ANA_BASE+0x19)
+#define WCD939X_MBHC_BTN0                      (WCD939X_ANA_BASE+0x1a)
+#define WCD939X_MBHC_BTN1                      (WCD939X_ANA_BASE+0x1b)
+#define WCD939X_MBHC_BTN2                      (WCD939X_ANA_BASE+0x1c)
+#define WCD939X_MBHC_BTN3                      (WCD939X_ANA_BASE+0x1d)
+#define WCD939X_MBHC_BTN4                      (WCD939X_ANA_BASE+0x1e)
+#define WCD939X_MBHC_BTN5                      (WCD939X_ANA_BASE+0x1f)
+#define WCD939X_MBHC_BTN6                      (WCD939X_ANA_BASE+0x20)
+#define WCD939X_MBHC_BTN7                      (WCD939X_ANA_BASE+0x21)
+#define WCD939X_MICB1                          (WCD939X_ANA_BASE+0x22)
+#define WCD939X_MICB2                          (WCD939X_ANA_BASE+0x23)
+#define WCD939X_MICB2_RAMP                     (WCD939X_ANA_BASE+0x24)
+#define WCD939X_MICB3                          (WCD939X_ANA_BASE+0x25)
+#define WCD939X_MICB4                          (WCD939X_ANA_BASE+0x26)
+
+#define WCD939X_BIAS_BASE                      (WCD939X_BASE+0x29)
+#define WCD939X_CTL                            (WCD939X_BIAS_BASE+0x00)
+#define WCD939X_VBG_FINE_ADJ                   (WCD939X_BIAS_BASE+0x01)
+
+#define WCD939X_LDOL_BASE                      (WCD939X_BASE+0x41)
+#define WCD939X_VDDCX_ADJUST                   (WCD939X_LDOL_BASE+0x00)
+#define WCD939X_DISABLE_LDOL                   (WCD939X_LDOL_BASE+0x01)
+
+#define WCD939X_MBHC_BASE                      (WCD939X_BASE+0x57)
+#define WCD939X_CTL_CLK                        (WCD939X_MBHC_BASE+0x00)
+#define WCD939X_CTL_ANA                        (WCD939X_MBHC_BASE+0x01)
+#define WCD939X_ZDET_VNEG_CTL                  (WCD939X_MBHC_BASE+0x02)
+#define WCD939X_ZDET_BIAS_CTL                  (WCD939X_MBHC_BASE+0x03)
+#define WCD939X_CTL_BCS                        (WCD939X_MBHC_BASE+0x04)
+#define WCD939X_MOISTURE_DET_FSM_STATUS        (WCD939X_MBHC_BASE+0x05)
+#define WCD939X_TEST_CTL                       (WCD939X_MBHC_BASE+0x06)
+
+#define WCD939X_LDOH_BASE                      (WCD939X_BASE+0x68)
+#define WCD939X_MODE                           (WCD939X_LDOH_BASE+0x00)
+#define WCD939X_LDOH_BIAS                      (WCD939X_LDOH_BASE+0x01)
+#define WCD939X_STB_LOADS                      (WCD939X_LDOH_BASE+0x02)
+#define WCD939X_SLOWRAMP                       (WCD939X_LDOH_BASE+0x03)
+
+#define WCD939X_MICB1_BASE                     (WCD939X_BASE+0x6c)
+#define WCD939X_TEST_CTL_1                     (WCD939X_MICB1_BASE+0x00)
+#define WCD939X_TEST_CTL_2                     (WCD939X_MICB1_BASE+0x01)
+#define WCD939X_TEST_CTL_3                     (WCD939X_MICB1_BASE+0x02)
+
+#define WCD939X_MICB2_BASE                     (WCD939X_BASE+0x6f)
+#define WCD939X_MICB2_TEST_CTL_1               (WCD939X_MICB2_BASE+0x00)
+#define WCD939X_MICB2_TEST_CTL_2               (WCD939X_MICB2_BASE+0x01)
+#define WCD939X_MICB2_TEST_CTL_3               (WCD939X_MICB2_BASE+0x02)
+
+#define WCD939X_MICB3_BASE                     (WCD939X_BASE+0x72)
+#define WCD939X_MICB3_TEST_CTL_1               (WCD939X_MICB3_BASE+0x00)
+#define WCD939X_MICB3_TEST_CTL_2               (WCD939X_MICB3_BASE+0x01)
+#define WCD939X_MICB3_TEST_CTL_3               (WCD939X_MICB3_BASE+0x02)
+
+#define WCD939X_MICB4_BASE                     (WCD939X_BASE+0x75)
+#define WCD939X_MICB4_TEST_CTL_1               (WCD939X_MICB4_BASE+0x00)
+#define WCD939X_MICB4_TEST_CTL_2               (WCD939X_MICB4_BASE+0x01)
+#define WCD939X_MICB4_TEST_CTL_3               (WCD939X_MICB4_BASE+0x02)
+
+#define WCD939X_TX_COM_BASE                    (WCD939X_BASE+0x78)
+#define WCD939X_ADC_VCM                        (WCD939X_TX_COM_BASE+0x00)
+#define WCD939X_BIAS_ATEST                     (WCD939X_TX_COM_BASE+0x01)
+#define WCD939X_SPARE1                         (WCD939X_TX_COM_BASE+0x02)
+#define WCD939X_SPARE2                         (WCD939X_TX_COM_BASE+0x03)
+#define WCD939X_TXFE_DIV_CTL                   (WCD939X_TX_COM_BASE+0x04)
+#define WCD939X_TXFE_DIV_START                 (WCD939X_TX_COM_BASE+0x05)
+#define WCD939X_SPARE3                         (WCD939X_TX_COM_BASE+0x06)
+#define WCD939X_SPARE4                         (WCD939X_TX_COM_BASE+0x07)
+
+#define WCD939X_TX_1_2_BASE                    (WCD939X_BASE+0x80)
+#define WCD939X_TEST_EN                        (WCD939X_TX_1_2_BASE+0x00)
+#define WCD939X_ADC_IB                         (WCD939X_TX_1_2_BASE+0x01)
+#define WCD939X_ATEST_REFCTL                   (WCD939X_TX_1_2_BASE+0x02)
+#define WCD939X_TX_1_2_TEST_CTL                (WCD939X_TX_1_2_BASE+0x03)
+#define WCD939X_TEST_BLK_EN1                   (WCD939X_TX_1_2_BASE+0x04)
+#define WCD939X_TXFE1_CLKDIV                   (WCD939X_TX_1_2_BASE+0x05)
+#define WCD939X_SAR2_ERR                       (WCD939X_TX_1_2_BASE+0x06)
+#define WCD939X_SAR1_ERR                       (WCD939X_TX_1_2_BASE+0x07)
+
+#define WCD939X_TX_3_4_BASE                    (WCD939X_BASE+0x88)
+#define WCD939X_TX_3_4_TEST_EN                 (WCD939X_TX_3_4_BASE+0x00)
+#define WCD939X_TX_3_4_ADC_IB                  (WCD939X_TX_3_4_BASE+0x01)
+#define WCD939X_TX_3_4_ATEST_REFCTL            (WCD939X_TX_3_4_BASE+0x02)
+#define WCD939X_TX_3_4_TEST_CTL                (WCD939X_TX_3_4_BASE+0x03)
+#define WCD939X_TEST_BLK_EN3                   (WCD939X_TX_3_4_BASE+0x04)
+#define WCD939X_TXFE3_CLKDIV                   (WCD939X_TX_3_4_BASE+0x05)
+#define WCD939X_SAR4_ERR                       (WCD939X_TX_3_4_BASE+0x06)
+#define WCD939X_SAR3_ERR                       (WCD939X_TX_3_4_BASE+0x07)
+#define WCD939X_TEST_BLK_EN2                   (WCD939X_TX_3_4_BASE+0x08)
+#define WCD939X_TXFE2_CLKDIV                   (WCD939X_TX_3_4_BASE+0x09)
+#define WCD939X_TX_3_4_SPARE1                  (WCD939X_TX_3_4_BASE+0x0a)
+#define WCD939X_TEST_BLK_EN4                   (WCD939X_TX_3_4_BASE+0x0b)
+#define WCD939X_TXFE4_CLKDIV                   (WCD939X_TX_3_4_BASE+0x0c)
+#define WCD939X_TX_3_4_SPARE2                  (WCD939X_TX_3_4_BASE+0x0d)
+
+#define WCD939X_CLASSH_BASE                    (WCD939X_BASE+0x98)
+#define WCD939X_MODE_1                         (WCD939X_CLASSH_BASE+0x00)
+#define WCD939X_MODE_2                         (WCD939X_CLASSH_BASE+0x01)
+#define WCD939X_MODE_3                         (WCD939X_CLASSH_BASE+0x02)
+#define WCD939X_CTRL_VCL_1                     (WCD939X_CLASSH_BASE+0x03)
+#define WCD939X_CTRL_VCL_2                     (WCD939X_CLASSH_BASE+0x04)
+#define WCD939X_CTRL_CCL_1                     (WCD939X_CLASSH_BASE+0x05)
+#define WCD939X_CTRL_CCL_2                     (WCD939X_CLASSH_BASE+0x06)
+#define WCD939X_CTRL_CCL_3                     (WCD939X_CLASSH_BASE+0x07)
+#define WCD939X_CTRL_CCL_4                     (WCD939X_CLASSH_BASE+0x08)
+#define WCD939X_CTRL_CCL_5                     (WCD939X_CLASSH_BASE+0x09)
+#define WCD939X_BUCK_TMUX_A_D                  (WCD939X_CLASSH_BASE+0x0a)
+#define WCD939X_BUCK_SW_DRV_CNTL               (WCD939X_CLASSH_BASE+0x0b)
+#define WCD939X_SPARE                          (WCD939X_CLASSH_BASE+0x0c)
+
+#define WCD939X_FLYBACK_BASE                   (WCD939X_BASE+0xa5)
+#define WCD939X_EN                             (WCD939X_FLYBACK_BASE+0x00)
+#define WCD939X_VNEG_CTRL_1                    (WCD939X_FLYBACK_BASE+0x01)
+#define WCD939X_VNEG_CTRL_2                    (WCD939X_FLYBACK_BASE+0x02)
+#define WCD939X_VNEG_CTRL_3                    (WCD939X_FLYBACK_BASE+0x03)
+#define WCD939X_VNEG_CTRL_4                    (WCD939X_FLYBACK_BASE+0x04)
+#define WCD939X_VNEG_CTRL_5                    (WCD939X_FLYBACK_BASE+0x05)
+#define WCD939X_VNEG_CTRL_6                    (WCD939X_FLYBACK_BASE+0x06)
+#define WCD939X_VNEG_CTRL_7                    (WCD939X_FLYBACK_BASE+0x07)
+#define WCD939X_VNEG_CTRL_8                    (WCD939X_FLYBACK_BASE+0x08)
+#define WCD939X_VNEG_CTRL_9                    (WCD939X_FLYBACK_BASE+0x09)
+#define WCD939X_VNEGDAC_CTRL_1                 (WCD939X_FLYBACK_BASE+0x0a)
+#define WCD939X_VNEGDAC_CTRL_2                 (WCD939X_FLYBACK_BASE+0x0b)
+#define WCD939X_VNEGDAC_CTRL_3                 (WCD939X_FLYBACK_BASE+0x0c)
+#define WCD939X_CTRL_1                         (WCD939X_FLYBACK_BASE+0x0d)
+#define WCD939X_FLYBACK_TEST_CTL               (WCD939X_FLYBACK_BASE+0x0e)
+
+#define WCD939X_RX_BASE                        (WCD939X_BASE+0xb4)
+#define WCD939X_AUX_SW_CTL                     (WCD939X_RX_BASE+0x00)
+#define WCD939X_PA_AUX_IN_CONN                 (WCD939X_RX_BASE+0x01)
+#define WCD939X_TIMER_DIV                      (WCD939X_RX_BASE+0x02)
+#define WCD939X_OCP_CTL                        (WCD939X_RX_BASE+0x03)
+#define WCD939X_OCP_COUNT                      (WCD939X_RX_BASE+0x04)
+#define WCD939X_BIAS_EAR_DAC                   (WCD939X_RX_BASE+0x05)
+#define WCD939X_BIAS_EAR_AMP                   (WCD939X_RX_BASE+0x06)
+#define WCD939X_BIAS_HPH_LDO                   (WCD939X_RX_BASE+0x07)
+#define WCD939X_BIAS_HPH_PA                    (WCD939X_RX_BASE+0x08)
+#define WCD939X_BIAS_HPH_RDACBUFF_CNP2         (WCD939X_RX_BASE+0x09)
+#define WCD939X_BIAS_HPH_RDAC_LDO              (WCD939X_RX_BASE+0x0a)
+#define WCD939X_BIAS_HPH_CNP1                  (WCD939X_RX_BASE+0x0b)
+#define WCD939X_BIAS_HPH_LOWPOWER              (WCD939X_RX_BASE+0x0c)
+#define WCD939X_BIAS_AUX_DAC                   (WCD939X_RX_BASE+0x0d)
+#define WCD939X_BIAS_AUX_AMP                   (WCD939X_RX_BASE+0x0e)
+#define WCD939X_BIAS_VNEGDAC_BLEEDER           (WCD939X_RX_BASE+0x0f)
+#define WCD939X_BIAS_MISC                      (WCD939X_RX_BASE+0x10)
+#define WCD939X_BIAS_BUCK_RST                  (WCD939X_RX_BASE+0x11)
+#define WCD939X_BIAS_BUCK_VREF_ERRAMP          (WCD939X_RX_BASE+0x12)
+#define WCD939X_BIAS_FLYB_ERRAMP               (WCD939X_RX_BASE+0x13)
+#define WCD939X_BIAS_FLYB_BUFF                 (WCD939X_RX_BASE+0x14)
+#define WCD939X_BIAS_FLYB_MID_RST              (WCD939X_RX_BASE+0x15)
+
+#define WCD939X_HPH_BASE                       (WCD939X_BASE+0xca)
+#define WCD939X_L_STATUS                       (WCD939X_HPH_BASE+0x00)
+#define WCD939X_R_STATUS                       (WCD939X_HPH_BASE+0x01)
+#define WCD939X_CNP_EN                         (WCD939X_HPH_BASE+0x02)
+#define WCD939X_CNP_WG_CTL                     (WCD939X_HPH_BASE+0x03)
+#define WCD939X_CNP_WG_TIME                    (WCD939X_HPH_BASE+0x04)
+#define WCD939X_HPH_OCP_CTL                    (WCD939X_HPH_BASE+0x05)
+#define WCD939X_AUTO_CHOP                      (WCD939X_HPH_BASE+0x06)
+#define WCD939X_CHOP_CTL                       (WCD939X_HPH_BASE+0x07)
+#define WCD939X_PA_CTL1                        (WCD939X_HPH_BASE+0x08)
+#define WCD939X_PA_CTL2                        (WCD939X_HPH_BASE+0x09)
+#define WCD939X_L_EN                           (WCD939X_HPH_BASE+0x0a)
+#define WCD939X_L_TEST                         (WCD939X_HPH_BASE+0x0b)
+#define WCD939X_L_ATEST                        (WCD939X_HPH_BASE+0x0c)
+#define WCD939X_R_EN                           (WCD939X_HPH_BASE+0x0d)
+#define WCD939X_R_TEST                         (WCD939X_HPH_BASE+0x0e)
+#define WCD939X_R_ATEST                        (WCD939X_HPH_BASE+0x0f)
+#define WCD939X_RDAC_CLK_CTL1                  (WCD939X_HPH_BASE+0x10)
+#define WCD939X_RDAC_CLK_CTL2                  (WCD939X_HPH_BASE+0x11)
+#define WCD939X_RDAC_LDO_CTL                   (WCD939X_HPH_BASE+0x12)
+#define WCD939X_RDAC_CHOP_CLK_LP_CTL           (WCD939X_HPH_BASE+0x13)
+#define WCD939X_REFBUFF_UHQA_CTL               (WCD939X_HPH_BASE+0x14)
+#define WCD939X_REFBUFF_LP_CTL                 (WCD939X_HPH_BASE+0x15)
+#define WCD939X_L_DAC_CTL                      (WCD939X_HPH_BASE+0x16)
+#define WCD939X_R_DAC_CTL                      (WCD939X_HPH_BASE+0x17)
+
+#define WCD939X_HPH_SURGE_BASE                 (WCD939X_BASE+0xe2)
+#define WCD939X_HPHLR_SURGE_COMP_SEL           (WCD939X_HPH_SURGE_BASE+0x00)
+#define WCD939X_HPHLR_SURGE_EN                 (WCD939X_HPH_SURGE_BASE+0x01)
+#define WCD939X_HPHLR_SURGE_MISC1              (WCD939X_HPH_SURGE_BASE+0x02)
+#define WCD939X_HPHLR_SURGE_STATUS             (WCD939X_HPH_SURGE_BASE+0x03)
+
+#define WCD939X_EAR_BASE                       (WCD939X_BASE+0xea)
+#define WCD939X_EAR_EN_REG                     (WCD939X_EAR_BASE+0x00)
+#define WCD939X_EAR_PA_CON                     (WCD939X_EAR_BASE+0x01)
+#define WCD939X_EAR_SP_CON                     (WCD939X_EAR_BASE+0x02)
+#define WCD939X_EAR_DAC_CON                    (WCD939X_EAR_BASE+0x03)
+#define WCD939X_EAR_CNP_FSM_CON                (WCD939X_EAR_BASE+0x04)
+#define WCD939X_EAR_TEST_CTL                   (WCD939X_EAR_BASE+0x05)
+#define WCD939X_STATUS_REG_1                   (WCD939X_EAR_BASE+0x06)
+#define WCD939X_STATUS_REG_2                   (WCD939X_EAR_BASE+0x07)
+
+#define WCD939X_ANA_NEW_BASE                   (WCD939X_BASE+0x101)
+#define WCD939X_ANA_NEW_PAGE                   (WCD939X_ANA_NEW_BASE+0x00)
+
+#define WCD939X_HPH_NEW_BASE                   (WCD939X_BASE+0x102)
+#define WCD939X_ANA_HPH2                       (WCD939X_HPH_NEW_BASE+0x00)
+#define WCD939X_ANA_HPH3                       (WCD939X_HPH_NEW_BASE+0x01)
+
+#define WCD939X_SLEEP_BASE                     (WCD939X_BASE+0x104)
+#define WCD939X_SLEEP_CTL                      (WCD939X_SLEEP_BASE+0x00)
+#define WCD939X_WATCHDOG_CTL                   (WCD939X_SLEEP_BASE+0x01)
+
+#define WCD939X_MBHC_NEW_BASE                  (WCD939X_BASE+0x120)
+#define WCD939X_ELECT_REM_CLAMP_CTL            (WCD939X_MBHC_NEW_BASE+0x00)
+#define WCD939X_CTL_1                          (WCD939X_MBHC_NEW_BASE+0x01)
+#define WCD939X_CTL_2                          (WCD939X_MBHC_NEW_BASE+0x02)
+#define WCD939X_PLUG_DETECT_CTL                (WCD939X_MBHC_NEW_BASE+0x03)
+#define WCD939X_ZDET_ANA_CTL                   (WCD939X_MBHC_NEW_BASE+0x04)
+#define WCD939X_ZDET_RAMP_CTL                  (WCD939X_MBHC_NEW_BASE+0x05)
+#define WCD939X_FSM_STATUS                     (WCD939X_MBHC_NEW_BASE+0x06)
+#define WCD939X_ADC_RESULT                     (WCD939X_MBHC_NEW_BASE+0x07)
+
+#define WCD939X_TX_NEW_BASE                    (WCD939X_BASE+0x128)
+#define WCD939X_TX_CH12_MUX                    (WCD939X_TX_NEW_BASE+0x00)
+#define WCD939X_TX_CH34_MUX                    (WCD939X_TX_NEW_BASE+0x01)
+
+#define WCD939X_DIE_CRACK_BASE                 (WCD939X_BASE+0x12d)
+#define WCD939X_DIE_CRK_DET_EN                 (WCD939X_DIE_CRACK_BASE+0x00)
+#define WCD939X_DIE_CRK_DET_OUT                (WCD939X_DIE_CRACK_BASE+0x01)
+
+#define WCD939X_HPH_NEW_INT_BASE               (WCD939X_BASE+0x133)
+#define WCD939X_RDAC_GAIN_CTL                  (WCD939X_HPH_NEW_INT_BASE+0x00)
+#define WCD939X_PA_GAIN_CTL_L                  (WCD939X_HPH_NEW_INT_BASE+0x01)
+#define WCD939X_RDAC_VREF_CTL                  (WCD939X_HPH_NEW_INT_BASE+0x02)
+#define WCD939X_RDAC_OVERRIDE_CTL              (WCD939X_HPH_NEW_INT_BASE+0x03)
+#define WCD939X_PA_GAIN_CTL_R                  (WCD939X_HPH_NEW_INT_BASE+0x04)
+#define WCD939X_PA_MISC1                       (WCD939X_HPH_NEW_INT_BASE+0x05)
+#define WCD939X_PA_MISC2                       (WCD939X_HPH_NEW_INT_BASE+0x06)
+#define WCD939X_PA_RDAC_MISC                   (WCD939X_HPH_NEW_INT_BASE+0x07)
+#define WCD939X_HPH_TIMER1                     (WCD939X_HPH_NEW_INT_BASE+0x08)
+#define WCD939X_HPH_TIMER2                     (WCD939X_HPH_NEW_INT_BASE+0x09)
+#define WCD939X_HPH_TIMER3                     (WCD939X_HPH_NEW_INT_BASE+0x0a)
+#define WCD939X_HPH_TIMER4                     (WCD939X_HPH_NEW_INT_BASE+0x0b)
+#define WCD939X_PA_RDAC_MISC2                  (WCD939X_HPH_NEW_INT_BASE+0x0c)
+#define WCD939X_PA_RDAC_MISC3                  (WCD939X_HPH_NEW_INT_BASE+0x0d)
+#define WCD939X_RDAC_HD2_CTL_L                 (WCD939X_HPH_NEW_INT_BASE+0x0e)
+#define WCD939X_RDAC_HD2_CTL_R                 (WCD939X_HPH_NEW_INT_BASE+0x0f)
+
+#define WCD939X_RX_NEW_INT_BASE                (WCD939X_BASE+0x146)
+#define WCD939X_HPH_RDAC_BIAS_LOHIFI           (WCD939X_RX_NEW_INT_BASE+0x00)
+#define WCD939X_HPH_RDAC_BIAS_ULP              (WCD939X_RX_NEW_INT_BASE+0x01)
+#define WCD939X_HPH_RDAC_LDO_LP                (WCD939X_RX_NEW_INT_BASE+0x02)
+
+#define WCD939X_MBHC_NEW_INT_BASE              (WCD939X_BASE+0x1b0)
+#define WCD939X_MOISTURE_DET_DC_CTRL           (WCD939X_MBHC_NEW_INT_BASE+0x00)
+#define WCD939X_MOISTURE_DET_POLLING_CTRL      (WCD939X_MBHC_NEW_INT_BASE+0x01)
+#define WCD939X_MECH_DET_CURRENT               (WCD939X_MBHC_NEW_INT_BASE+0x02)
+#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW  (WCD939X_MBHC_NEW_INT_BASE+0x03)
+
+#define WCD939X_EAR_INT_NEW_BASE               (WCD939X_BASE+0x1b8)
+#define WCD939X_EAR_CHOPPER_CON                (WCD939X_EAR_INT_NEW_BASE+0x00)
+#define WCD939X_CNP_VCM_CON1                   (WCD939X_EAR_INT_NEW_BASE+0x01)
+#define WCD939X_CNP_VCM_CON2                   (WCD939X_EAR_INT_NEW_BASE+0x02)
+#define WCD939X_EAR_DYNAMIC_BIAS               (WCD939X_EAR_INT_NEW_BASE+0x03)
+
+#define WCD939X_SLEEP_INT_BASE                 (WCD939X_BASE+0x1d1)
+#define WCD939X_WATCHDOG_CTL_1                 (WCD939X_SLEEP_INT_BASE+0x00)
+#define WCD939X_WATCHDOG_CTL_2                 (WCD939X_SLEEP_INT_BASE+0x01)
+
+#define WCD939X_DIE_CRACK_INT_BASE             (WCD939X_BASE+0x1d4)
+#define WCD939X_DIE_CRK_DET_INT1               (WCD939X_DIE_CRACK_INT_BASE+0x00)
+#define WCD939X_DIE_CRK_DET_INT2               (WCD939X_DIE_CRACK_INT_BASE+0x01)
+
+#define WCD939X_TX_COM_NEW_INT_BASE            (WCD939X_BASE+0x1d6)
+#define WCD939X_TXFE_DIVSTOP_L2                (WCD939X_TX_COM_NEW_INT_BASE+0x00)
+#define WCD939X_TXFE_DIVSTOP_L1                (WCD939X_TX_COM_NEW_INT_BASE+0x01)
+#define WCD939X_TXFE_DIVSTOP_L0                (WCD939X_TX_COM_NEW_INT_BASE+0x02)
+#define WCD939X_TXFE_DIVSTOP_ULP1P2M           (WCD939X_TX_COM_NEW_INT_BASE+0x03)
+#define WCD939X_TXFE_DIVSTOP_ULP0P6M           (WCD939X_TX_COM_NEW_INT_BASE+0x04)
+#define WCD939X_TXFE_ICTRL_STG1_L2L1           (WCD939X_TX_COM_NEW_INT_BASE+0x05)
+#define WCD939X_TXFE_ICTRL_STG1_L0             (WCD939X_TX_COM_NEW_INT_BASE+0x06)
+#define WCD939X_TXFE_ICTRL_STG1_ULP            (WCD939X_TX_COM_NEW_INT_BASE+0x07)
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L2L1       (WCD939X_TX_COM_NEW_INT_BASE+0x08)
+#define WCD939X_TXFE_ICTRL_STG2MAIN_L0         (WCD939X_TX_COM_NEW_INT_BASE+0x09)
+#define WCD939X_TXFE_ICTRL_STG2MAIN_ULP        (WCD939X_TX_COM_NEW_INT_BASE+0x0a)
+#define WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0     (WCD939X_TX_COM_NEW_INT_BASE+0x0b)
+#define WCD939X_TXFE_ICTRL_STG2CASC_ULP        (WCD939X_TX_COM_NEW_INT_BASE+0x0c)
+#define WCD939X_TXADC_SCBIAS_L2L1              (WCD939X_TX_COM_NEW_INT_BASE+0x0d)
+#define WCD939X_TXADC_SCBIAS_L0ULP             (WCD939X_TX_COM_NEW_INT_BASE+0x0e)
+#define WCD939X_TXADC_INT_L2                   (WCD939X_TX_COM_NEW_INT_BASE+0x0f)
+#define WCD939X_TXADC_INT_L1                   (WCD939X_TX_COM_NEW_INT_BASE+0x10)
+#define WCD939X_TXADC_INT_L0                   (WCD939X_TX_COM_NEW_INT_BASE+0x11)
+#define WCD939X_TXADC_INT_ULP                  (WCD939X_TX_COM_NEW_INT_BASE+0x12)
+
+#define WCD939X_DIGITAL_BASE                   (WCD939X_BASE+0x401)
+#define WCD939X_DIGITAL_PAGE                   (WCD939X_DIGITAL_BASE+0x00)
+#define WCD939X_CHIP_ID0                       (WCD939X_DIGITAL_BASE+0x01)
+#define WCD939X_CHIP_ID1                       (WCD939X_DIGITAL_BASE+0x02)
+#define WCD939X_CHIP_ID2                       (WCD939X_DIGITAL_BASE+0x03)
+#define WCD939X_CHIP_ID3                       (WCD939X_DIGITAL_BASE+0x04)
+#define WCD939X_SWR_TX_CLK_RATE                (WCD939X_DIGITAL_BASE+0x05)
+#define WCD939X_CDC_RST_CTL                    (WCD939X_DIGITAL_BASE+0x06)
+#define WCD939X_TOP_CLK_CFG                    (WCD939X_DIGITAL_BASE+0x07)
+#define WCD939X_CDC_ANA_CLK_CTL                (WCD939X_DIGITAL_BASE+0x08)
+#define WCD939X_CDC_DIG_CLK_CTL                (WCD939X_DIGITAL_BASE+0x09)
+#define WCD939X_SWR_RST_EN                     (WCD939X_DIGITAL_BASE+0x0a)
+#define WCD939X_CDC_PATH_MODE                  (WCD939X_DIGITAL_BASE+0x0b)
+#define WCD939X_CDC_RX_RST                     (WCD939X_DIGITAL_BASE+0x0c)
+#define WCD939X_CDC_RX0_CTL                    (WCD939X_DIGITAL_BASE+0x0d)
+#define WCD939X_CDC_RX1_CTL                    (WCD939X_DIGITAL_BASE+0x0e)
+#define WCD939X_CDC_RX2_CTL                    (WCD939X_DIGITAL_BASE+0x0f)
+#define WCD939X_CDC_TX_ANA_MODE_0_1            (WCD939X_DIGITAL_BASE+0x10)
+#define WCD939X_CDC_TX_ANA_MODE_2_3            (WCD939X_DIGITAL_BASE+0x11)
+#define WCD939X_CDC_COMP_CTL_0                 (WCD939X_DIGITAL_BASE+0x14)
+#define WCD939X_CDC_ANA_TX_CLK_CTL             (WCD939X_DIGITAL_BASE+0x17)
+#define WCD939X_CDC_HPH_DSM_A1_0               (WCD939X_DIGITAL_BASE+0x18)
+#define WCD939X_CDC_HPH_DSM_A1_1               (WCD939X_DIGITAL_BASE+0x19)
+#define WCD939X_CDC_HPH_DSM_A2_0               (WCD939X_DIGITAL_BASE+0x1a)
+#define WCD939X_CDC_HPH_DSM_A2_1               (WCD939X_DIGITAL_BASE+0x1b)
+#define WCD939X_CDC_HPH_DSM_A3_0               (WCD939X_DIGITAL_BASE+0x1c)
+#define WCD939X_CDC_HPH_DSM_A3_1               (WCD939X_DIGITAL_BASE+0x1d)
+#define WCD939X_CDC_HPH_DSM_A4_0               (WCD939X_DIGITAL_BASE+0x1e)
+#define WCD939X_CDC_HPH_DSM_A4_1               (WCD939X_DIGITAL_BASE+0x1f)
+#define WCD939X_CDC_HPH_DSM_A5_0               (WCD939X_DIGITAL_BASE+0x20)
+#define WCD939X_CDC_HPH_DSM_A5_1               (WCD939X_DIGITAL_BASE+0x21)
+#define WCD939X_CDC_HPH_DSM_A6_0               (WCD939X_DIGITAL_BASE+0x22)
+#define WCD939X_CDC_HPH_DSM_A7_0               (WCD939X_DIGITAL_BASE+0x23)
+#define WCD939X_CDC_HPH_DSM_C_0                (WCD939X_DIGITAL_BASE+0x24)
+#define WCD939X_CDC_HPH_DSM_C_1                (WCD939X_DIGITAL_BASE+0x25)
+#define WCD939X_CDC_HPH_DSM_C_2                (WCD939X_DIGITAL_BASE+0x26)
+#define WCD939X_CDC_HPH_DSM_C_3                (WCD939X_DIGITAL_BASE+0x27)
+#define WCD939X_CDC_HPH_DSM_R1                 (WCD939X_DIGITAL_BASE+0x28)
+#define WCD939X_CDC_HPH_DSM_R2                 (WCD939X_DIGITAL_BASE+0x29)
+#define WCD939X_CDC_HPH_DSM_R3                 (WCD939X_DIGITAL_BASE+0x2a)
+#define WCD939X_CDC_HPH_DSM_R4                 (WCD939X_DIGITAL_BASE+0x2b)
+#define WCD939X_CDC_HPH_DSM_R5                 (WCD939X_DIGITAL_BASE+0x2c)
+#define WCD939X_CDC_HPH_DSM_R6                 (WCD939X_DIGITAL_BASE+0x2d)
+#define WCD939X_CDC_HPH_DSM_R7                 (WCD939X_DIGITAL_BASE+0x2e)
+#define WCD939X_CDC_EAR_DSM_A1_0               (WCD939X_DIGITAL_BASE+0x2f)
+#define WCD939X_CDC_EAR_DSM_A1_1               (WCD939X_DIGITAL_BASE+0x30)
+#define WCD939X_CDC_EAR_DSM_A2_0               (WCD939X_DIGITAL_BASE+0x31)
+#define WCD939X_CDC_EAR_DSM_A2_1               (WCD939X_DIGITAL_BASE+0x32)
+#define WCD939X_CDC_EAR_DSM_A3_0               (WCD939X_DIGITAL_BASE+0x33)
+#define WCD939X_CDC_EAR_DSM_A3_1               (WCD939X_DIGITAL_BASE+0x34)
+#define WCD939X_CDC_EAR_DSM_A4_0               (WCD939X_DIGITAL_BASE+0x35)
+#define WCD939X_CDC_EAR_DSM_A4_1               (WCD939X_DIGITAL_BASE+0x36)
+#define WCD939X_CDC_EAR_DSM_A5_0               (WCD939X_DIGITAL_BASE+0x37)
+#define WCD939X_CDC_EAR_DSM_A5_1               (WCD939X_DIGITAL_BASE+0x38)
+#define WCD939X_CDC_EAR_DSM_A6_0               (WCD939X_DIGITAL_BASE+0x39)
+#define WCD939X_CDC_EAR_DSM_A7_0               (WCD939X_DIGITAL_BASE+0x3a)
+#define WCD939X_CDC_EAR_DSM_C_0                (WCD939X_DIGITAL_BASE+0x3b)
+#define WCD939X_CDC_EAR_DSM_C_1                (WCD939X_DIGITAL_BASE+0x3c)
+#define WCD939X_CDC_EAR_DSM_C_2                (WCD939X_DIGITAL_BASE+0x3d)
+#define WCD939X_CDC_EAR_DSM_C_3                (WCD939X_DIGITAL_BASE+0x3e)
+#define WCD939X_CDC_EAR_DSM_R1                 (WCD939X_DIGITAL_BASE+0x3f)
+#define WCD939X_CDC_EAR_DSM_R2                 (WCD939X_DIGITAL_BASE+0x40)
+#define WCD939X_CDC_EAR_DSM_R3                 (WCD939X_DIGITAL_BASE+0x41)
+#define WCD939X_CDC_EAR_DSM_R4                 (WCD939X_DIGITAL_BASE+0x42)
+#define WCD939X_CDC_EAR_DSM_R5                 (WCD939X_DIGITAL_BASE+0x43)
+#define WCD939X_CDC_EAR_DSM_R6                 (WCD939X_DIGITAL_BASE+0x44)
+#define WCD939X_CDC_EAR_DSM_R7                 (WCD939X_DIGITAL_BASE+0x45)
+#define WCD939X_CDC_HPH_GAIN_RX_0              (WCD939X_DIGITAL_BASE+0x46)
+#define WCD939X_CDC_HPH_GAIN_RX_1              (WCD939X_DIGITAL_BASE+0x47)
+#define WCD939X_CDC_HPH_GAIN_DSD_0             (WCD939X_DIGITAL_BASE+0x48)
+#define WCD939X_CDC_HPH_GAIN_DSD_1             (WCD939X_DIGITAL_BASE+0x49)
+#define WCD939X_CDC_HPH_GAIN_DSD_2             (WCD939X_DIGITAL_BASE+0x4a)
+#define WCD939X_CDC_EAR_GAIN_DSD_0             (WCD939X_DIGITAL_BASE+0x4b)
+#define WCD939X_CDC_EAR_GAIN_DSD_1             (WCD939X_DIGITAL_BASE+0x4c)
+#define WCD939X_CDC_EAR_GAIN_DSD_2             (WCD939X_DIGITAL_BASE+0x4d)
+#define WCD939X_CDC_HPH_GAIN_CTL               (WCD939X_DIGITAL_BASE+0x4e)
+#define WCD939X_CDC_EAR_GAIN_CTL               (WCD939X_DIGITAL_BASE+0x4f)
+#define WCD939X_CDC_EAR_PATH_CTL               (WCD939X_DIGITAL_BASE+0x50)
+#define WCD939X_CDC_SWR_CLH                    (WCD939X_DIGITAL_BASE+0x51)
+#define WCD939X_SWR_CLH_BYP                    (WCD939X_DIGITAL_BASE+0x52)
+#define WCD939X_CDC_TX0_CTL                    (WCD939X_DIGITAL_BASE+0x53)
+#define WCD939X_CDC_TX1_CTL                    (WCD939X_DIGITAL_BASE+0x54)
+#define WCD939X_CDC_TX2_CTL                    (WCD939X_DIGITAL_BASE+0x55)
+#define WCD939X_CDC_TX_RST                     (WCD939X_DIGITAL_BASE+0x56)
+#define WCD939X_CDC_REQ_CTL                    (WCD939X_DIGITAL_BASE+0x57)
+#define WCD939X_CDC_RST                        (WCD939X_DIGITAL_BASE+0x58)
+#define WCD939X_CDC_AMIC_CTL                   (WCD939X_DIGITAL_BASE+0x5a)
+#define WCD939X_CDC_DMIC_CTL                   (WCD939X_DIGITAL_BASE+0x5b)
+#define WCD939X_CDC_DMIC1_CTL                  (WCD939X_DIGITAL_BASE+0x5c)
+#define WCD939X_CDC_DMIC2_CTL                  (WCD939X_DIGITAL_BASE+0x5d)
+#define WCD939X_CDC_DMIC3_CTL                  (WCD939X_DIGITAL_BASE+0x5e)
+#define WCD939X_CDC_DMIC4_CTL                  (WCD939X_DIGITAL_BASE+0x5f)
+#define WCD939X_EFUSE_PRG_CTL                  (WCD939X_DIGITAL_BASE+0x60)
+#define WCD939X_EFUSE_CTL                      (WCD939X_DIGITAL_BASE+0x61)
+#define WCD939X_CDC_DMIC_RATE_1_2              (WCD939X_DIGITAL_BASE+0x62)
+#define WCD939X_CDC_DMIC_RATE_3_4              (WCD939X_DIGITAL_BASE+0x63)
+#define WCD939X_PDM_WD_CTL0                    (WCD939X_DIGITAL_BASE+0x65)
+#define WCD939X_PDM_WD_CTL1                    (WCD939X_DIGITAL_BASE+0x66)
+#define WCD939X_PDM_WD_CTL2                    (WCD939X_DIGITAL_BASE+0x67)
+#define WCD939X_INTR_MODE                      (WCD939X_DIGITAL_BASE+0x6a)
+#define WCD939X_INTR_MASK_0                    (WCD939X_DIGITAL_BASE+0x6b)
+#define WCD939X_INTR_MASK_1                    (WCD939X_DIGITAL_BASE+0x6c)
+#define WCD939X_INTR_MASK_2                    (WCD939X_DIGITAL_BASE+0x6d)
+#define WCD939X_INTR_STATUS_0                  (WCD939X_DIGITAL_BASE+0x6e)
+#define WCD939X_INTR_STATUS_1                  (WCD939X_DIGITAL_BASE+0x6f)
+#define WCD939X_INTR_STATUS_2                  (WCD939X_DIGITAL_BASE+0x70)
+#define WCD939X_INTR_CLEAR_0                   (WCD939X_DIGITAL_BASE+0x71)
+#define WCD939X_INTR_CLEAR_1                   (WCD939X_DIGITAL_BASE+0x72)
+#define WCD939X_INTR_CLEAR_2                   (WCD939X_DIGITAL_BASE+0x73)
+#define WCD939X_INTR_LEVEL_0                   (WCD939X_DIGITAL_BASE+0x74)
+#define WCD939X_INTR_LEVEL_1                   (WCD939X_DIGITAL_BASE+0x75)
+#define WCD939X_INTR_LEVEL_2                   (WCD939X_DIGITAL_BASE+0x76)
+#define WCD939X_INTR_SET_0                     (WCD939X_DIGITAL_BASE+0x77)
+#define WCD939X_INTR_SET_1                     (WCD939X_DIGITAL_BASE+0x78)
+#define WCD939X_INTR_SET_2                     (WCD939X_DIGITAL_BASE+0x79)
+#define WCD939X_INTR_TEST_0                    (WCD939X_DIGITAL_BASE+0x7a)
+#define WCD939X_INTR_TEST_1                    (WCD939X_DIGITAL_BASE+0x7b)
+#define WCD939X_INTR_TEST_2                    (WCD939X_DIGITAL_BASE+0x7c)
+#define WCD939X_TX_MODE_DBG_EN                 (WCD939X_DIGITAL_BASE+0x7f)
+#define WCD939X_TX_MODE_DBG_0_1                (WCD939X_DIGITAL_BASE+0x80)
+#define WCD939X_TX_MODE_DBG_2_3                (WCD939X_DIGITAL_BASE+0x81)
+#define WCD939X_LB_IN_SEL_CTL                  (WCD939X_DIGITAL_BASE+0x82)
+#define WCD939X_LOOP_BACK_MODE                 (WCD939X_DIGITAL_BASE+0x83)
+#define WCD939X_SWR_DAC_TEST                   (WCD939X_DIGITAL_BASE+0x84)
+#define WCD939X_SWR_HM_TEST_RX_0               (WCD939X_DIGITAL_BASE+0x85)
+#define WCD939X_SWR_HM_TEST_TX_0               (WCD939X_DIGITAL_BASE+0x86)
+#define WCD939X_SWR_HM_TEST_RX_1               (WCD939X_DIGITAL_BASE+0x87)
+#define WCD939X_SWR_HM_TEST_TX_1               (WCD939X_DIGITAL_BASE+0x88)
+#define WCD939X_SWR_HM_TEST_TX_2               (WCD939X_DIGITAL_BASE+0x89)
+#define WCD939X_SWR_HM_TEST_0                  (WCD939X_DIGITAL_BASE+0x8a)
+#define WCD939X_SWR_HM_TEST_1                  (WCD939X_DIGITAL_BASE+0x8b)
+#define WCD939X_PAD_CTL_SWR_0                  (WCD939X_DIGITAL_BASE+0x8c)
+#define WCD939X_PAD_CTL_SWR_1                  (WCD939X_DIGITAL_BASE+0x8d)
+#define WCD939X_I2C_CTL                        (WCD939X_DIGITAL_BASE+0x8e)
+#define WCD939X_CDC_TX_TANGGU_SW_MODE          (WCD939X_DIGITAL_BASE+0x8f)
+#define WCD939X_EFUSE_TEST_CTL_0               (WCD939X_DIGITAL_BASE+0x90)
+#define WCD939X_EFUSE_TEST_CTL_1               (WCD939X_DIGITAL_BASE+0x91)
+#define WCD939X_EFUSE_T_DATA_0                 (WCD939X_DIGITAL_BASE+0x92)
+#define WCD939X_EFUSE_T_DATA_1                 (WCD939X_DIGITAL_BASE+0x93)
+#define WCD939X_PAD_CTL_PDM_RX0                (WCD939X_DIGITAL_BASE+0x94)
+#define WCD939X_PAD_CTL_PDM_RX1                (WCD939X_DIGITAL_BASE+0x95)
+#define WCD939X_PAD_CTL_PDM_TX0                (WCD939X_DIGITAL_BASE+0x96)
+#define WCD939X_PAD_CTL_PDM_TX1                (WCD939X_DIGITAL_BASE+0x97)
+#define WCD939X_PAD_CTL_PDM_TX2                (WCD939X_DIGITAL_BASE+0x98)
+#define WCD939X_PAD_INP_DIS_0                  (WCD939X_DIGITAL_BASE+0x99)
+#define WCD939X_PAD_INP_DIS_1                  (WCD939X_DIGITAL_BASE+0x9a)
+#define WCD939X_DRIVE_STRENGTH_0               (WCD939X_DIGITAL_BASE+0x9b)
+#define WCD939X_DRIVE_STRENGTH_1               (WCD939X_DIGITAL_BASE+0x9c)
+#define WCD939X_DRIVE_STRENGTH_2               (WCD939X_DIGITAL_BASE+0x9d)
+#define WCD939X_RX_DATA_EDGE_CTL               (WCD939X_DIGITAL_BASE+0x9e)
+#define WCD939X_TX_DATA_EDGE_CTL               (WCD939X_DIGITAL_BASE+0x9f)
+#define WCD939X_GPIO_MODE                      (WCD939X_DIGITAL_BASE+0xa0)
+#define WCD939X_PIN_CTL_OE                     (WCD939X_DIGITAL_BASE+0xa1)
+#define WCD939X_PIN_CTL_DATA_0                 (WCD939X_DIGITAL_BASE+0xa2)
+#define WCD939X_PIN_CTL_DATA_1                 (WCD939X_DIGITAL_BASE+0xa3)
+#define WCD939X_PIN_STATUS_0                   (WCD939X_DIGITAL_BASE+0xa4)
+#define WCD939X_PIN_STATUS_1                   (WCD939X_DIGITAL_BASE+0xa5)
+#define WCD939X_DIG_DEBUG_CTL                  (WCD939X_DIGITAL_BASE+0xa6)
+#define WCD939X_DIG_DEBUG_EN                   (WCD939X_DIGITAL_BASE+0xa7)
+#define WCD939X_ANA_CSR_DBG_ADD                (WCD939X_DIGITAL_BASE+0xa8)
+#define WCD939X_ANA_CSR_DBG_CTL                (WCD939X_DIGITAL_BASE+0xa9)
+#define WCD939X_SSP_DBG                        (WCD939X_DIGITAL_BASE+0xaa)
+#define WCD939X_MODE_STATUS_0                  (WCD939X_DIGITAL_BASE+0xab)
+#define WCD939X_MODE_STATUS_1                  (WCD939X_DIGITAL_BASE+0xac)
+#define WCD939X_SPARE_0                        (WCD939X_DIGITAL_BASE+0xad)
+#define WCD939X_SPARE_1                        (WCD939X_DIGITAL_BASE+0xae)
+#define WCD939X_SPARE_2                        (WCD939X_DIGITAL_BASE+0xaf)
+#define WCD939X_EFUSE_REG_0                    (WCD939X_DIGITAL_BASE+0xb0)
+#define WCD939X_EFUSE_REG_1                    (WCD939X_DIGITAL_BASE+0xb1)
+#define WCD939X_EFUSE_REG_2                    (WCD939X_DIGITAL_BASE+0xb2)
+#define WCD939X_EFUSE_REG_3                    (WCD939X_DIGITAL_BASE+0xb3)
+#define WCD939X_EFUSE_REG_4                    (WCD939X_DIGITAL_BASE+0xb4)
+#define WCD939X_EFUSE_REG_5                    (WCD939X_DIGITAL_BASE+0xb5)
+#define WCD939X_EFUSE_REG_6                    (WCD939X_DIGITAL_BASE+0xb6)
+#define WCD939X_EFUSE_REG_7                    (WCD939X_DIGITAL_BASE+0xb7)
+#define WCD939X_EFUSE_REG_8                    (WCD939X_DIGITAL_BASE+0xb8)
+#define WCD939X_EFUSE_REG_9                    (WCD939X_DIGITAL_BASE+0xb9)
+#define WCD939X_EFUSE_REG_10                   (WCD939X_DIGITAL_BASE+0xba)
+#define WCD939X_EFUSE_REG_11                   (WCD939X_DIGITAL_BASE+0xbb)
+#define WCD939X_EFUSE_REG_12                   (WCD939X_DIGITAL_BASE+0xbc)
+#define WCD939X_EFUSE_REG_13                   (WCD939X_DIGITAL_BASE+0xbd)
+#define WCD939X_EFUSE_REG_14                   (WCD939X_DIGITAL_BASE+0xbe)
+#define WCD939X_EFUSE_REG_15                   (WCD939X_DIGITAL_BASE+0xbf)
+#define WCD939X_EFUSE_REG_16                   (WCD939X_DIGITAL_BASE+0xc0)
+#define WCD939X_EFUSE_REG_17                   (WCD939X_DIGITAL_BASE+0xc1)
+#define WCD939X_EFUSE_REG_18                   (WCD939X_DIGITAL_BASE+0xc2)
+#define WCD939X_EFUSE_REG_19                   (WCD939X_DIGITAL_BASE+0xc3)
+#define WCD939X_EFUSE_REG_20                   (WCD939X_DIGITAL_BASE+0xc4)
+#define WCD939X_EFUSE_REG_21                   (WCD939X_DIGITAL_BASE+0xc5)
+#define WCD939X_EFUSE_REG_22                   (WCD939X_DIGITAL_BASE+0xc6)
+#define WCD939X_EFUSE_REG_23                   (WCD939X_DIGITAL_BASE+0xc7)
+#define WCD939X_EFUSE_REG_24                   (WCD939X_DIGITAL_BASE+0xc8)
+#define WCD939X_EFUSE_REG_25                   (WCD939X_DIGITAL_BASE+0xc9)
+#define WCD939X_EFUSE_REG_26                   (WCD939X_DIGITAL_BASE+0xca)
+#define WCD939X_EFUSE_REG_27                   (WCD939X_DIGITAL_BASE+0xcb)
+#define WCD939X_EFUSE_REG_28                   (WCD939X_DIGITAL_BASE+0xcc)
+#define WCD939X_EFUSE_REG_29                   (WCD939X_DIGITAL_BASE+0xcd)
+#define WCD939X_EFUSE_REG_30                   (WCD939X_DIGITAL_BASE+0xce)
+#define WCD939X_EFUSE_REG_31                   (WCD939X_DIGITAL_BASE+0xcf)
+#define WCD939X_TX_REQ_FB_CTL_0                (WCD939X_DIGITAL_BASE+0xd0)
+#define WCD939X_TX_REQ_FB_CTL_1                (WCD939X_DIGITAL_BASE+0xd1)
+#define WCD939X_TX_REQ_FB_CTL_2                (WCD939X_DIGITAL_BASE+0xd2)
+#define WCD939X_TX_REQ_FB_CTL_3                (WCD939X_DIGITAL_BASE+0xd3)
+#define WCD939X_TX_REQ_FB_CTL_4                (WCD939X_DIGITAL_BASE+0xd4)
+#define WCD939X_DEM_BYPASS_DATA0               (WCD939X_DIGITAL_BASE+0xd5)
+#define WCD939X_DEM_BYPASS_DATA1               (WCD939X_DIGITAL_BASE+0xd6)
+#define WCD939X_DEM_BYPASS_DATA2               (WCD939X_DIGITAL_BASE+0xd7)
+#define WCD939X_DEM_BYPASS_DATA3               (WCD939X_DIGITAL_BASE+0xd8)
+#define WCD939X_DEM_SECOND_ORDER               (WCD939X_DIGITAL_BASE+0xd9)
+#define WCD939X_DSM_CTRL                       (WCD939X_DIGITAL_BASE+0xda)
+#define WCD939X_DSM_0_STATIC_DATA_0            (WCD939X_DIGITAL_BASE+0xdb)
+#define WCD939X_DSM_0_STATIC_DATA_1            (WCD939X_DIGITAL_BASE+0xdc)
+#define WCD939X_DSM_0_STATIC_DATA_2            (WCD939X_DIGITAL_BASE+0xdd)
+#define WCD939X_DSM_0_STATIC_DATA_3            (WCD939X_DIGITAL_BASE+0xde)
+#define WCD939X_DSM_1_STATIC_DATA_0            (WCD939X_DIGITAL_BASE+0xdf)
+#define WCD939X_DSM_1_STATIC_DATA_1            (WCD939X_DIGITAL_BASE+0xe0)
+#define WCD939X_DSM_1_STATIC_DATA_2            (WCD939X_DIGITAL_BASE+0xe1)
+#define WCD939X_DSM_1_STATIC_DATA_3            (WCD939X_DIGITAL_BASE+0xe2)
+
+#define WCD939X_RX_PAGE                        (WCD939X_RX_BASE+0x00)
+#define WCD939X_TOP_CFG0                       (WCD939X_RX_BASE+0x01)
+#define WCD939X_HPHL_COMP_WR_LSB               (WCD939X_RX_BASE+0x02)
+#define WCD939X_HPHL_COMP_WR_MSB               (WCD939X_RX_BASE+0x03)
+#define WCD939X_HPHL_COMP_LUT                  (WCD939X_RX_BASE+0x04)
+#define WCD939X_HPHL_COMP_RD_LSB               (WCD939X_RX_BASE+0x05)
+#define WCD939X_HPHL_COMP_RD_MSB               (WCD939X_RX_BASE+0x06)
+#define WCD939X_HPHR_COMP_WR_LSB               (WCD939X_RX_BASE+0x07)
+#define WCD939X_HPHR_COMP_WR_MSB               (WCD939X_RX_BASE+0x08)
+#define WCD939X_HPHR_COMP_LUT                  (WCD939X_RX_BASE+0x09)
+#define WCD939X_HPHR_COMP_RD_LSB               (WCD939X_RX_BASE+0x0a)
+#define WCD939X_HPHR_COMP_RD_MSB               (WCD939X_RX_BASE+0x0b)
+#define WCD939X_DSD0_DEBUG_CFG1                (WCD939X_RX_BASE+0x0c)
+#define WCD939X_DSD0_DEBUG_CFG2                (WCD939X_RX_BASE+0x0d)
+#define WCD939X_DSD0_DEBUG_CFG3                (WCD939X_RX_BASE+0x0e)
+#define WCD939X_DSD0_DEBUG_CFG4                (WCD939X_RX_BASE+0x0f)
+#define WCD939X_DSD0_DEBUG_CFG5                (WCD939X_RX_BASE+0x10)
+#define WCD939X_DSD0_DEBUG_CFG6                (WCD939X_RX_BASE+0x11)
+#define WCD939X_DSD1_DEBUG_CFG1                (WCD939X_RX_BASE+0x12)
+#define WCD939X_DSD1_DEBUG_CFG2                (WCD939X_RX_BASE+0x13)
+#define WCD939X_DSD1_DEBUG_CFG3                (WCD939X_RX_BASE+0x14)
+#define WCD939X_DSD1_DEBUG_CFG4                (WCD939X_RX_BASE+0x15)
+#define WCD939X_DSD1_DEBUG_CFG5                (WCD939X_RX_BASE+0x16)
+#define WCD939X_DSD1_DEBUG_CFG6                (WCD939X_RX_BASE+0x17)
+#define WCD939X_HPHL_RX_PATH_CFG0              (WCD939X_RX_BASE+0x1c)
+#define WCD939X_HPHL_RX_PATH_CFG1              (WCD939X_RX_BASE+0x1d)
+#define WCD939X_HPHR_RX_PATH_CFG0              (WCD939X_RX_BASE+0x1e)
+#define WCD939X_HPHR_RX_PATH_CFG1              (WCD939X_RX_BASE+0x1f)
+#define WCD939X_RX_PATH_CFG2                   (WCD939X_RX_BASE+0x20)
+#define WCD939X_HPHL_RX_PATH_SEC0              (WCD939X_RX_BASE+0x21)
+#define WCD939X_HPHL_RX_PATH_SEC1              (WCD939X_RX_BASE+0x22)
+#define WCD939X_HPHL_RX_PATH_SEC2              (WCD939X_RX_BASE+0x23)
+#define WCD939X_HPHL_RX_PATH_SEC3              (WCD939X_RX_BASE+0x24)
+#define WCD939X_HPHR_RX_PATH_SEC0              (WCD939X_RX_BASE+0x25)
+#define WCD939X_HPHR_RX_PATH_SEC1              (WCD939X_RX_BASE+0x26)
+#define WCD939X_HPHR_RX_PATH_SEC2              (WCD939X_RX_BASE+0x27)
+#define WCD939X_HPHR_RX_PATH_SEC3              (WCD939X_RX_BASE+0x28)
+#define WCD939X_RX_PATH_SEC4                   (WCD939X_RX_BASE+0x29)
+#define WCD939X_RX_PATH_SEC5                   (WCD939X_RX_BASE+0x2a)
+
+#define WCD939X_COMPANDER_HPHL_BASE            (WCD939X_BASE+0x541)
+#define WCD939X_CTL0                           (WCD939X_COMPANDER_HPHL_BASE+0x00)
+#define WCD939X_CTL1                           (WCD939X_COMPANDER_HPHL_BASE+0x01)
+#define WCD939X_CTL2                           (WCD939X_COMPANDER_HPHL_BASE+0x02)
+#define WCD939X_CTL3                           (WCD939X_COMPANDER_HPHL_BASE+0x03)
+#define WCD939X_CTL4                           (WCD939X_COMPANDER_HPHL_BASE+0x04)
+#define WCD939X_CTL5                           (WCD939X_COMPANDER_HPHL_BASE+0x05)
+#define WCD939X_CTL6                           (WCD939X_COMPANDER_HPHL_BASE+0x06)
+#define WCD939X_CTL7                           (WCD939X_COMPANDER_HPHL_BASE+0x07)
+#define WCD939X_CTL8                           (WCD939X_COMPANDER_HPHL_BASE+0x08)
+#define WCD939X_CTL9                           (WCD939X_COMPANDER_HPHL_BASE+0x09)
+#define WCD939X_CTL10                          (WCD939X_COMPANDER_HPHL_BASE+0x0a)
+#define WCD939X_CTL11                          (WCD939X_COMPANDER_HPHL_BASE+0x0b)
+#define WCD939X_CTL12                          (WCD939X_COMPANDER_HPHL_BASE+0x0c)
+#define WCD939X_CTL13                          (WCD939X_COMPANDER_HPHL_BASE+0x0d)
+#define WCD939X_CTL14                          (WCD939X_COMPANDER_HPHL_BASE+0x0e)
+#define WCD939X_CTL15                          (WCD939X_COMPANDER_HPHL_BASE+0x0f)
+#define WCD939X_CTL16                          (WCD939X_COMPANDER_HPHL_BASE+0x10)
+#define WCD939X_CTL17                          (WCD939X_COMPANDER_HPHL_BASE+0x11)
+#define WCD939X_CTL18                          (WCD939X_COMPANDER_HPHL_BASE+0x12)
+#define WCD939X_CTL19                          (WCD939X_COMPANDER_HPHL_BASE+0x13)
+
+#define WCD939X_R_BASE                         (WCD939X_BASE+0x561)
+#define WCD939X_R_CTL0                         (WCD939X_R_BASE+0x00)
+#define WCD939X_R_CTL1                         (WCD939X_R_BASE+0x01)
+#define WCD939X_R_CTL2                         (WCD939X_R_BASE+0x02)
+#define WCD939X_R_CTL3                         (WCD939X_R_BASE+0x03)
+#define WCD939X_R_CTL4                         (WCD939X_R_BASE+0x04)
+#define WCD939X_R_CTL5                         (WCD939X_R_BASE+0x05)
+#define WCD939X_R_CTL6                         (WCD939X_R_BASE+0x06)
+#define WCD939X_R_CTL7                         (WCD939X_R_BASE+0x07)
+#define WCD939X_R_CTL8                         (WCD939X_R_BASE+0x08)
+#define WCD939X_R_CTL9                         (WCD939X_R_BASE+0x09)
+#define WCD939X_R_CTL10                        (WCD939X_R_BASE+0x0a)
+#define WCD939X_R_CTL11                        (WCD939X_R_BASE+0x0b)
+#define WCD939X_R_CTL12                        (WCD939X_R_BASE+0x0c)
+#define WCD939X_R_CTL13                        (WCD939X_R_BASE+0x0d)
+#define WCD939X_R_CTL14                        (WCD939X_R_BASE+0x0e)
+#define WCD939X_R_CTL15                        (WCD939X_R_BASE+0x0f)
+#define WCD939X_R_CTL16                        (WCD939X_R_BASE+0x10)
+#define WCD939X_R_CTL17                        (WCD939X_R_BASE+0x11)
+#define WCD939X_R_CTL18                        (WCD939X_R_BASE+0x12)
+#define WCD939X_R_CTL19                        (WCD939X_R_BASE+0x13)
+
+#define WCD939X_E_BASE                         (WCD939X_BASE+0x581)
+#define WCD939X_PATH_CTL                       (WCD939X_E_BASE+0x00)
+#define WCD939X_CFG0                           (WCD939X_E_BASE+0x01)
+#define WCD939X_CFG1                           (WCD939X_E_BASE+0x02)
+#define WCD939X_CFG2                           (WCD939X_E_BASE+0x03)
+#define WCD939X_CFG3                           (WCD939X_E_BASE+0x04)
+
+#define WCD939X_DSD_HPHL_BASE                  (WCD939X_BASE+0x591)
+#define WCD939X_DSD_HPHL_PATH_CTL              (WCD939X_DSD_HPHL_BASE+0x00)
+#define WCD939X_DSD_HPHL_CFG0                  (WCD939X_DSD_HPHL_BASE+0x01)
+#define WCD939X_DSD_HPHL_CFG1                  (WCD939X_DSD_HPHL_BASE+0x02)
+#define WCD939X_DSD_HPHL_CFG2                  (WCD939X_DSD_HPHL_BASE+0x03)
+#define WCD939X_DSD_HPHL_CFG3                  (WCD939X_DSD_HPHL_BASE+0x04)
+#define WCD939X_CFG4                           (WCD939X_DSD_HPHL_BASE+0x05)
+#define WCD939X_CFG5                           (WCD939X_DSD_HPHL_BASE+0x06)
+
+#define WCD939X_DSD_HPHR_BASE                  (WCD939X_BASE+0x5a1)
+#define WCD939X_DSD_HPHR_PATH_CTL              (WCD939X_DSD_HPHR_BASE+0x00)
+#define WCD939X_DSD_HPHR_CFG0                  (WCD939X_DSD_HPHR_BASE+0x01)
+#define WCD939X_DSD_HPHR_CFG1                  (WCD939X_DSD_HPHR_BASE+0x02)
+#define WCD939X_DSD_HPHR_CFG2                  (WCD939X_DSD_HPHR_BASE+0x03)
+#define WCD939X_DSD_HPHR_CFG3                  (WCD939X_DSD_HPHR_BASE+0x04)
+#define WCD939X_DSD_HPHR_CFG4                  (WCD939X_DSD_HPHR_BASE+0x05)
+#define WCD939X_DSD_HPHR_CFG5                  (WCD939X_DSD_HPHR_BASE+0x06)
+
+#define WCD939X_NUM_REGISTERS                  (WCD939X_DSD_HPHR_CFG5+1)
+#define WCD939X_MAX_REGISTER                   (WCD939X_NUM_REGISTERS-1)
+
+#endif /* WCD939X_REGISTERS_H */

asoc/codecs/wcd939x/wcd939x-regmap.c

@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2019, 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd939x-registers.h"
+
+extern const u8 wcd939x_reg_access[WCD939X_NUM_REGISTERS];
+
+static struct reg_default wcd939x_defaults[] = {
+	{WCD939X_ANA_PAGE,                       0x00},
+	{WCD939X_BIAS,                           0x00},
+	{WCD939X_RX_SUPPLIES,                    0x00},
+	{WCD939X_HPH,                            0x0c},
+	{WCD939X_EAR,                            0x00},
+	{WCD939X_EAR_COMPANDER_CTL,              0x02},
+	{WCD939X_TX_CH1,                         0x20},
+	{WCD939X_TX_CH2,                         0x00},
+	{WCD939X_TX_CH3,                         0x20},
+	{WCD939X_TX_CH4,                         0x00},
+	{WCD939X_MICB1_MICB2_DSP_EN_LOGIC,       0x00},
+	{WCD939X_MICB3_DSP_EN_LOGIC,             0x00},
+	{WCD939X_MBHC_MECH,                      0x39},
+	{WCD939X_MBHC_ELECT,                     0x08},
+	{WCD939X_MBHC_ZDET,                      0x00},
+	{WCD939X_MBHC_RESULT_1,                  0x00},
+	{WCD939X_MBHC_RESULT_2,                  0x00},
+	{WCD939X_MBHC_RESULT_3,                  0x00},
+	{WCD939X_MBHC_BTN0,                      0x00},
+	{WCD939X_MBHC_BTN1,                      0x10},
+	{WCD939X_MBHC_BTN2,                      0x20},
+	{WCD939X_MBHC_BTN3,                      0x30},
+	{WCD939X_MBHC_BTN4,                      0x40},
+	{WCD939X_MBHC_BTN5,                      0x50},
+	{WCD939X_MBHC_BTN6,                      0x60},
+	{WCD939X_MBHC_BTN7,                      0x70},
+	{WCD939X_MICB1,                          0x10},
+	{WCD939X_MICB2,                          0x10},
+	{WCD939X_MICB2_RAMP,                     0x00},
+	{WCD939X_MICB3,                          0x00},
+	{WCD939X_MICB4,                          0x00},
+	{WCD939X_CTL,                            0x2a},
+	{WCD939X_VBG_FINE_ADJ,                   0x55},
+	{WCD939X_VDDCX_ADJUST,                   0x01},
+	{WCD939X_DISABLE_LDOL,                   0x00},
+	{WCD939X_CTL_CLK,                        0x00},
+	{WCD939X_CTL_ANA,                        0x00},
+	{WCD939X_ZDET_VNEG_CTL,                  0x00},
+	{WCD939X_ZDET_BIAS_CTL,                  0x46},
+	{WCD939X_CTL_BCS,                        0x00},
+	{WCD939X_MOISTURE_DET_FSM_STATUS,        0x00},
+	{WCD939X_TEST_CTL,                       0x00},
+	{WCD939X_MODE,                           0x2b},
+	{WCD939X_LDOH_BIAS,                      0x68},
+	{WCD939X_STB_LOADS,                      0x00},
+	{WCD939X_SLOWRAMP,                       0x50},
+	{WCD939X_TEST_CTL_1,                     0x1a},
+	{WCD939X_TEST_CTL_2,                     0x00},
+	{WCD939X_TEST_CTL_3,                     0xa4},
+	{WCD939X_MICB2_TEST_CTL_1,               0x1a},
+	{WCD939X_MICB2_TEST_CTL_2,               0x00},
+	{WCD939X_MICB2_TEST_CTL_3,               0x24},
+	{WCD939X_MICB3_TEST_CTL_1,               0x1a},
+	{WCD939X_MICB3_TEST_CTL_2,               0x00},
+	{WCD939X_MICB3_TEST_CTL_3,               0xa4},
+	{WCD939X_MICB4_TEST_CTL_1,               0x1a},
+	{WCD939X_MICB4_TEST_CTL_2,               0x00},
+	{WCD939X_MICB4_TEST_CTL_3,               0xa4},
+	{WCD939X_ADC_VCM,                        0x39},
+	{WCD939X_BIAS_ATEST,                     0xe0},
+	{WCD939X_SPARE1,                         0x00},
+	{WCD939X_SPARE2,                         0x00},
+	{WCD939X_TXFE_DIV_CTL,                   0x22},
+	{WCD939X_TXFE_DIV_START,                 0x00},
+	{WCD939X_SPARE3,                         0x00},
+	{WCD939X_SPARE4,                         0x00},
+	{WCD939X_TEST_EN,                        0xcc},
+	{WCD939X_ADC_IB,                         0xe9},
+	{WCD939X_ATEST_REFCTL,                   0x0b},
+	{WCD939X_TX_1_2_TEST_CTL,                0x38},
+	{WCD939X_TEST_BLK_EN1,                   0xff},
+	{WCD939X_TXFE1_CLKDIV,                   0x00},
+	{WCD939X_SAR2_ERR,                       0x00},
+	{WCD939X_SAR1_ERR,                       0x00},
+	{WCD939X_TX_3_4_TEST_EN,                 0xcc},
+	{WCD939X_TX_3_4_ADC_IB,                  0xe9},
+	{WCD939X_TX_3_4_ATEST_REFCTL,            0x0b},
+	{WCD939X_TX_3_4_TEST_CTL,                0x38},
+	{WCD939X_TEST_BLK_EN3,                   0xff},
+	{WCD939X_TXFE3_CLKDIV,                   0x00},
+	{WCD939X_SAR4_ERR,                       0x00},
+	{WCD939X_SAR3_ERR,                       0x00},
+	{WCD939X_TEST_BLK_EN2,                   0xfb},
+	{WCD939X_TXFE2_CLKDIV,                   0x00},
+	{WCD939X_TX_3_4_SPARE1,                  0x00},
+	{WCD939X_TEST_BLK_EN4,                   0xfb},
+	{WCD939X_TXFE4_CLKDIV,                   0x00},
+	{WCD939X_TX_3_4_SPARE2,                  0x00},
+	{WCD939X_MODE_1,                         0x40},
+	{WCD939X_MODE_2,                         0x3a},
+	{WCD939X_MODE_3,                         0xf0},
+	{WCD939X_CTRL_VCL_1,                     0x7c},
+	{WCD939X_CTRL_VCL_2,                     0x82},
+	{WCD939X_CTRL_CCL_1,                     0x31},
+	{WCD939X_CTRL_CCL_2,                     0x80},
+	{WCD939X_CTRL_CCL_3,                     0x80},
+	{WCD939X_CTRL_CCL_4,                     0x51},
+	{WCD939X_CTRL_CCL_5,                     0x00},
+	{WCD939X_BUCK_TMUX_A_D,                  0x00},
+	{WCD939X_BUCK_SW_DRV_CNTL,               0x77},
+	{WCD939X_SPARE,                          0x80},
+	{WCD939X_EN,                             0x4e},
+	{WCD939X_VNEG_CTRL_1,                    0x0b},
+	{WCD939X_VNEG_CTRL_2,                    0x45},
+	{WCD939X_VNEG_CTRL_3,                    0x14},
+	{WCD939X_VNEG_CTRL_4,                    0xdb},
+	{WCD939X_VNEG_CTRL_5,                    0x83},
+	{WCD939X_VNEG_CTRL_6,                    0x98},
+	{WCD939X_VNEG_CTRL_7,                    0xa9},
+	{WCD939X_VNEG_CTRL_8,                    0x68},
+	{WCD939X_VNEG_CTRL_9,                    0x66},
+	{WCD939X_VNEGDAC_CTRL_1,                 0xed},
+	{WCD939X_VNEGDAC_CTRL_2,                 0xf8},
+	{WCD939X_VNEGDAC_CTRL_3,                 0xa6},
+	{WCD939X_CTRL_1,                         0x65},
+	{WCD939X_FLYBACK_TEST_CTL,               0x02},
+	{WCD939X_AUX_SW_CTL,                     0x00},
+	{WCD939X_PA_AUX_IN_CONN,                 0x01},
+	{WCD939X_TIMER_DIV,                      0x32},
+	{WCD939X_OCP_CTL,                        0x1f},
+	{WCD939X_OCP_COUNT,                      0x77},
+	{WCD939X_BIAS_EAR_DAC,                   0xa0},
+	{WCD939X_BIAS_EAR_AMP,                   0xaa},
+	{WCD939X_BIAS_HPH_LDO,                   0xa9},
+	{WCD939X_BIAS_HPH_PA,                    0xaa},
+	{WCD939X_BIAS_HPH_RDACBUFF_CNP2,         0xca},
+	{WCD939X_BIAS_HPH_RDAC_LDO,              0x88},
+	{WCD939X_BIAS_HPH_CNP1,                  0x82},
+	{WCD939X_BIAS_HPH_LOWPOWER,              0x82},
+	{WCD939X_BIAS_AUX_DAC,                   0xa0},
+	{WCD939X_BIAS_AUX_AMP,                   0xaa},
+	{WCD939X_BIAS_VNEGDAC_BLEEDER,           0x50},
+	{WCD939X_BIAS_MISC,                      0x00},
+	{WCD939X_BIAS_BUCK_RST,                  0x08},
+	{WCD939X_BIAS_BUCK_VREF_ERRAMP,          0x44},
+	{WCD939X_BIAS_FLYB_ERRAMP,               0x40},
+	{WCD939X_BIAS_FLYB_BUFF,                 0xaa},
+	{WCD939X_BIAS_FLYB_MID_RST,              0x14},
+	{WCD939X_L_STATUS,                       0x04},
+	{WCD939X_R_STATUS,                       0x04},
+	{WCD939X_CNP_EN,                         0x80},
+	{WCD939X_CNP_WG_CTL,                     0x9a},
+	{WCD939X_CNP_WG_TIME,                    0x14},
+	{WCD939X_HPH_OCP_CTL,                    0x28},
+	{WCD939X_AUTO_CHOP,                      0x56},
+	{WCD939X_CHOP_CTL,                       0x83},
+	{WCD939X_PA_CTL1,                        0x46},
+	{WCD939X_PA_CTL2,                        0x50},
+	{WCD939X_L_EN,                           0x80},
+	{WCD939X_L_TEST,                         0xe0},
+	{WCD939X_L_ATEST,                        0x50},
+	{WCD939X_R_EN,                           0x80},
+	{WCD939X_R_TEST,                         0xe0},
+	{WCD939X_R_ATEST,                        0x50},
+	{WCD939X_RDAC_CLK_CTL1,                  0x80},
+	{WCD939X_RDAC_CLK_CTL2,                  0x0b},
+	{WCD939X_RDAC_LDO_CTL,                   0x33},
+	{WCD939X_RDAC_CHOP_CLK_LP_CTL,           0x00},
+	{WCD939X_REFBUFF_UHQA_CTL,               0x00},
+	{WCD939X_REFBUFF_LP_CTL,                 0x8e},
+	{WCD939X_L_DAC_CTL,                      0x20},
+	{WCD939X_R_DAC_CTL,                      0x20},
+	{WCD939X_HPHLR_SURGE_COMP_SEL,           0x55},
+	{WCD939X_HPHLR_SURGE_EN,                 0x19},
+	{WCD939X_HPHLR_SURGE_MISC1,              0xa0},
+	{WCD939X_HPHLR_SURGE_STATUS,             0x00},
+	{WCD939X_EAR_EN_REG,                     0x22},
+	{WCD939X_EAR_PA_CON,                     0x44},
+	{WCD939X_EAR_SP_CON,                     0xdb},
+	{WCD939X_EAR_DAC_CON,                    0x80},
+	{WCD939X_EAR_CNP_FSM_CON,                0xb2},
+	{WCD939X_EAR_TEST_CTL,                   0x00},
+	{WCD939X_STATUS_REG_1,                   0x00},
+	{WCD939X_STATUS_REG_2,                   0x08},
+	{WCD939X_ANA_NEW_PAGE,                   0x00},
+	{WCD939X_ANA_HPH2,                       0x00},
+	{WCD939X_ANA_HPH3,                       0x00},
+	{WCD939X_SLEEP_CTL,                      0x18},
+	{WCD939X_WATCHDOG_CTL,                   0x00},
+	{WCD939X_ELECT_REM_CLAMP_CTL,            0x00},
+	{WCD939X_CTL_1,                          0x02},
+	{WCD939X_CTL_2,                          0x05},
+	{WCD939X_PLUG_DETECT_CTL,                0xe9},
+	{WCD939X_ZDET_ANA_CTL,                   0x0f},
+	{WCD939X_ZDET_RAMP_CTL,                  0x00},
+	{WCD939X_FSM_STATUS,                     0x00},
+	{WCD939X_ADC_RESULT,                     0x00},
+	{WCD939X_TX_CH12_MUX,                    0x11},
+	{WCD939X_TX_CH34_MUX,                    0x23},
+	{WCD939X_DIE_CRK_DET_EN,                 0x00},
+	{WCD939X_DIE_CRK_DET_OUT,                0x00},
+	{WCD939X_RDAC_GAIN_CTL,                  0x00},
+	{WCD939X_PA_GAIN_CTL_L,                  0x00},
+	{WCD939X_RDAC_VREF_CTL,                  0x08},
+	{WCD939X_RDAC_OVERRIDE_CTL,              0x00},
+	{WCD939X_PA_GAIN_CTL_R,                  0x00},
+	{WCD939X_PA_MISC1,                       0x32},
+	{WCD939X_PA_MISC2,                       0x00},
+	{WCD939X_PA_RDAC_MISC,                   0x00},
+	{WCD939X_HPH_TIMER1,                     0xfe},
+	{WCD939X_HPH_TIMER2,                     0x02},
+	{WCD939X_HPH_TIMER3,                     0x4e},
+	{WCD939X_HPH_TIMER4,                     0x54},
+	{WCD939X_PA_RDAC_MISC2,                  0x0b},
+	{WCD939X_PA_RDAC_MISC3,                  0x00},
+	{WCD939X_RDAC_HD2_CTL_L,                 0xa0},
+	{WCD939X_RDAC_HD2_CTL_R,                 0xa0},
+	{WCD939X_HPH_RDAC_BIAS_LOHIFI,           0x64},
+	{WCD939X_HPH_RDAC_BIAS_ULP,              0x01},
+	{WCD939X_HPH_RDAC_LDO_LP,                0x11},
+	{WCD939X_MOISTURE_DET_DC_CTRL,           0x57},
+	{WCD939X_MOISTURE_DET_POLLING_CTRL,      0x01},
+	{WCD939X_MECH_DET_CURRENT,               0x00},
+	{WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW,  0x47},
+	{WCD939X_EAR_CHOPPER_CON,                0xa8},
+	{WCD939X_CNP_VCM_CON1,                   0x42},
+	{WCD939X_CNP_VCM_CON2,                   0x22},
+	{WCD939X_EAR_DYNAMIC_BIAS,               0x00},
+	{WCD939X_WATCHDOG_CTL_1,                 0x0a},
+	{WCD939X_WATCHDOG_CTL_2,                 0x0a},
+	{WCD939X_DIE_CRK_DET_INT1,               0x02},
+	{WCD939X_DIE_CRK_DET_INT2,               0x60},
+	{WCD939X_TXFE_DIVSTOP_L2,                0xff},
+	{WCD939X_TXFE_DIVSTOP_L1,                0x7f},
+	{WCD939X_TXFE_DIVSTOP_L0,                0x3f},
+	{WCD939X_TXFE_DIVSTOP_ULP1P2M,           0x1f},
+	{WCD939X_TXFE_DIVSTOP_ULP0P6M,           0x0f},
+	{WCD939X_TXFE_ICTRL_STG1_L2L1,           0xd7},
+	{WCD939X_TXFE_ICTRL_STG1_L0,             0xc8},
+	{WCD939X_TXFE_ICTRL_STG1_ULP,            0xc6},
+	{WCD939X_TXFE_ICTRL_STG2MAIN_L2L1,       0x95},
+	{WCD939X_TXFE_ICTRL_STG2MAIN_L0,         0x6a},
+	{WCD939X_TXFE_ICTRL_STG2MAIN_ULP,        0x05},
+	{WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0,     0xa5},
+	{WCD939X_TXFE_ICTRL_STG2CASC_ULP,        0x13},
+	{WCD939X_TXADC_SCBIAS_L2L1,              0x88},
+	{WCD939X_TXADC_SCBIAS_L0ULP,             0x42},
+	{WCD939X_TXADC_INT_L2,                   0xff},
+	{WCD939X_TXADC_INT_L1,                   0x64},
+	{WCD939X_TXADC_INT_L0,                   0x64},
+	{WCD939X_TXADC_INT_ULP,                  0x77},
+	{WCD939X_DIGITAL_PAGE,                   0x00},
+	{WCD939X_CHIP_ID0,                       0x00},
+	{WCD939X_CHIP_ID1,                       0x00},
+	{WCD939X_CHIP_ID2,                       0x0e},
+	{WCD939X_CHIP_ID3,                       0x01},
+	{WCD939X_SWR_TX_CLK_RATE,                0x00},
+	{WCD939X_CDC_RST_CTL,                    0x03},
+	{WCD939X_TOP_CLK_CFG,                    0x00},
+	{WCD939X_CDC_ANA_CLK_CTL,                0x00},
+	{WCD939X_CDC_DIG_CLK_CTL,                0xf0},
+	{WCD939X_SWR_RST_EN,                     0x00},
+	{WCD939X_CDC_PATH_MODE,                  0x55},
+	{WCD939X_CDC_RX_RST,                     0x00},
+	{WCD939X_CDC_RX0_CTL,                    0xfc},
+	{WCD939X_CDC_RX1_CTL,                    0xfc},
+	{WCD939X_CDC_RX2_CTL,                    0xfc},
+	{WCD939X_CDC_TX_ANA_MODE_0_1,            0x00},
+	{WCD939X_CDC_TX_ANA_MODE_2_3,            0x00},
+	{WCD939X_CDC_COMP_CTL_0,                 0x00},
+	{WCD939X_CDC_ANA_TX_CLK_CTL,             0x1e},
+	{WCD939X_CDC_HPH_DSM_A1_0,               0x00},
+	{WCD939X_CDC_HPH_DSM_A1_1,               0x01},
+	{WCD939X_CDC_HPH_DSM_A2_0,               0x63},
+	{WCD939X_CDC_HPH_DSM_A2_1,               0x04},
+	{WCD939X_CDC_HPH_DSM_A3_0,               0xac},
+	{WCD939X_CDC_HPH_DSM_A3_1,               0x04},
+	{WCD939X_CDC_HPH_DSM_A4_0,               0x1a},
+	{WCD939X_CDC_HPH_DSM_A4_1,               0x03},
+	{WCD939X_CDC_HPH_DSM_A5_0,               0xbc},
+	{WCD939X_CDC_HPH_DSM_A5_1,               0x02},
+	{WCD939X_CDC_HPH_DSM_A6_0,               0xc7},
+	{WCD939X_CDC_HPH_DSM_A7_0,               0xf8},
+	{WCD939X_CDC_HPH_DSM_C_0,                0x47},
+	{WCD939X_CDC_HPH_DSM_C_1,                0x43},
+	{WCD939X_CDC_HPH_DSM_C_2,                0xb1},
+	{WCD939X_CDC_HPH_DSM_C_3,                0x17},
+	{WCD939X_CDC_HPH_DSM_R1,                 0x4d},
+	{WCD939X_CDC_HPH_DSM_R2,                 0x29},
+	{WCD939X_CDC_HPH_DSM_R3,                 0x34},
+	{WCD939X_CDC_HPH_DSM_R4,                 0x59},
+	{WCD939X_CDC_HPH_DSM_R5,                 0x66},
+	{WCD939X_CDC_HPH_DSM_R6,                 0x87},
+	{WCD939X_CDC_HPH_DSM_R7,                 0x64},
+	{WCD939X_CDC_EAR_DSM_A1_0,               0x00},
+	{WCD939X_CDC_EAR_DSM_A1_1,               0x01},
+	{WCD939X_CDC_EAR_DSM_A2_0,               0x96},
+	{WCD939X_CDC_EAR_DSM_A2_1,               0x09},
+	{WCD939X_CDC_EAR_DSM_A3_0,               0xab},
+	{WCD939X_CDC_EAR_DSM_A3_1,               0x05},
+	{WCD939X_CDC_EAR_DSM_A4_0,               0x1c},
+	{WCD939X_CDC_EAR_DSM_A4_1,               0x02},
+	{WCD939X_CDC_EAR_DSM_A5_0,               0x17},
+	{WCD939X_CDC_EAR_DSM_A5_1,               0x02},
+	{WCD939X_CDC_EAR_DSM_A6_0,               0xaa},
+	{WCD939X_CDC_EAR_DSM_A7_0,               0xe3},
+	{WCD939X_CDC_EAR_DSM_C_0,                0x69},
+	{WCD939X_CDC_EAR_DSM_C_1,                0x54},
+	{WCD939X_CDC_EAR_DSM_C_2,                0x02},
+	{WCD939X_CDC_EAR_DSM_C_3,                0x15},
+	{WCD939X_CDC_EAR_DSM_R1,                 0xa4},
+	{WCD939X_CDC_EAR_DSM_R2,                 0xb5},
+	{WCD939X_CDC_EAR_DSM_R3,                 0x86},
+	{WCD939X_CDC_EAR_DSM_R4,                 0x85},
+	{WCD939X_CDC_EAR_DSM_R5,                 0xaa},
+	{WCD939X_CDC_EAR_DSM_R6,                 0xe2},
+	{WCD939X_CDC_EAR_DSM_R7,                 0x62},
+	{WCD939X_CDC_HPH_GAIN_RX_0,              0x55},
+	{WCD939X_CDC_HPH_GAIN_RX_1,              0xa9},
+	{WCD939X_CDC_HPH_GAIN_DSD_0,             0x3d},
+	{WCD939X_CDC_HPH_GAIN_DSD_1,             0x2e},
+	{WCD939X_CDC_HPH_GAIN_DSD_2,             0x01},
+	{WCD939X_CDC_EAR_GAIN_DSD_0,             0x00},
+	{WCD939X_CDC_EAR_GAIN_DSD_1,             0xfc},
+	{WCD939X_CDC_EAR_GAIN_DSD_2,             0x01},
+	{WCD939X_CDC_HPH_GAIN_CTL,               0x00},
+	{WCD939X_CDC_EAR_GAIN_CTL,               0x00},
+	{WCD939X_CDC_EAR_PATH_CTL,               0x00},
+	{WCD939X_CDC_SWR_CLH,                    0x00},
+	{WCD939X_SWR_CLH_BYP,                    0x00},
+	{WCD939X_CDC_TX0_CTL,                    0x68},
+	{WCD939X_CDC_TX1_CTL,                    0x68},
+	{WCD939X_CDC_TX2_CTL,                    0x68},
+	{WCD939X_CDC_TX_RST,                     0x00},
+	{WCD939X_CDC_REQ_CTL,                    0x01},
+	{WCD939X_CDC_RST,                        0x00},
+	{WCD939X_CDC_AMIC_CTL,                   0x0f},
+	{WCD939X_CDC_DMIC_CTL,                   0x04},
+	{WCD939X_CDC_DMIC1_CTL,                  0x01},
+	{WCD939X_CDC_DMIC2_CTL,                  0x01},
+	{WCD939X_CDC_DMIC3_CTL,                  0x01},
+	{WCD939X_CDC_DMIC4_CTL,                  0x01},
+	{WCD939X_EFUSE_PRG_CTL,                  0x00},
+	{WCD939X_EFUSE_CTL,                      0x2b},
+	{WCD939X_CDC_DMIC_RATE_1_2,              0x11},
+	{WCD939X_CDC_DMIC_RATE_3_4,              0x11},
+	{WCD939X_PDM_WD_CTL0,                    0x00},
+	{WCD939X_PDM_WD_CTL1,                    0x00},
+	{WCD939X_PDM_WD_CTL2,                    0x00},
+	{WCD939X_INTR_MODE,                      0x00},
+	{WCD939X_INTR_MASK_0,                    0xff},
+	{WCD939X_INTR_MASK_1,                    0xe7},
+	{WCD939X_INTR_MASK_2,                    0x0e},
+	{WCD939X_INTR_STATUS_0,                  0x00},
+	{WCD939X_INTR_STATUS_1,                  0x00},
+	{WCD939X_INTR_STATUS_2,                  0x00},
+	{WCD939X_INTR_CLEAR_0,                   0x00},
+	{WCD939X_INTR_CLEAR_1,                   0x00},
+	{WCD939X_INTR_CLEAR_2,                   0x00},
+	{WCD939X_INTR_LEVEL_0,                   0x00},
+	{WCD939X_INTR_LEVEL_1,                   0x00},
+	{WCD939X_INTR_LEVEL_2,                   0x00},
+	{WCD939X_INTR_SET_0,                     0x00},
+	{WCD939X_INTR_SET_1,                     0x00},
+	{WCD939X_INTR_SET_2,                     0x00},
+	{WCD939X_INTR_TEST_0,                    0x00},
+	{WCD939X_INTR_TEST_1,                    0x00},
+	{WCD939X_INTR_TEST_2,                    0x00},
+	{WCD939X_TX_MODE_DBG_EN,                 0x00},
+	{WCD939X_TX_MODE_DBG_0_1,                0x00},
+	{WCD939X_TX_MODE_DBG_2_3,                0x00},
+	{WCD939X_LB_IN_SEL_CTL,                  0x00},
+	{WCD939X_LOOP_BACK_MODE,                 0x00},
+	{WCD939X_SWR_DAC_TEST,                   0x00},
+	{WCD939X_SWR_HM_TEST_RX_0,               0x40},
+	{WCD939X_SWR_HM_TEST_TX_0,               0x40},
+	{WCD939X_SWR_HM_TEST_RX_1,               0x00},
+	{WCD939X_SWR_HM_TEST_TX_1,               0x00},
+	{WCD939X_SWR_HM_TEST_TX_2,               0x00},
+	{WCD939X_SWR_HM_TEST_0,                  0x00},
+	{WCD939X_SWR_HM_TEST_1,                  0x00},
+	{WCD939X_PAD_CTL_SWR_0,                  0x8f},
+	{WCD939X_PAD_CTL_SWR_1,                  0x06},
+	{WCD939X_I2C_CTL,                        0x00},
+	{WCD939X_CDC_TX_TANGGU_SW_MODE,          0x00},
+	{WCD939X_EFUSE_TEST_CTL_0,               0x00},
+	{WCD939X_EFUSE_TEST_CTL_1,               0x00},
+	{WCD939X_EFUSE_T_DATA_0,                 0x00},
+	{WCD939X_EFUSE_T_DATA_1,                 0x00},
+	{WCD939X_PAD_CTL_PDM_RX0,                0xf1},
+	{WCD939X_PAD_CTL_PDM_RX1,                0xf1},
+	{WCD939X_PAD_CTL_PDM_TX0,                0xf1},
+	{WCD939X_PAD_CTL_PDM_TX1,                0xf1},
+	{WCD939X_PAD_CTL_PDM_TX2,                0xf1},
+	{WCD939X_PAD_INP_DIS_0,                  0x00},
+	{WCD939X_PAD_INP_DIS_1,                  0x00},
+	{WCD939X_DRIVE_STRENGTH_0,               0x00},
+	{WCD939X_DRIVE_STRENGTH_1,               0x00},
+	{WCD939X_DRIVE_STRENGTH_2,               0x00},
+	{WCD939X_RX_DATA_EDGE_CTL,               0x1f},
+	{WCD939X_TX_DATA_EDGE_CTL,               0x80},
+	{WCD939X_GPIO_MODE,                      0x00},
+	{WCD939X_PIN_CTL_OE,                     0x00},
+	{WCD939X_PIN_CTL_DATA_0,                 0x00},
+	{WCD939X_PIN_CTL_DATA_1,                 0x00},
+	{WCD939X_PIN_STATUS_0,                   0x00},
+	{WCD939X_PIN_STATUS_1,                   0x00},
+	{WCD939X_DIG_DEBUG_CTL,                  0x00},
+	{WCD939X_DIG_DEBUG_EN,                   0x00},
+	{WCD939X_ANA_CSR_DBG_ADD,                0x00},
+	{WCD939X_ANA_CSR_DBG_CTL,                0x48},
+	{WCD939X_SSP_DBG,                        0x00},
+	{WCD939X_MODE_STATUS_0,                  0x00},
+	{WCD939X_MODE_STATUS_1,                  0x00},
+	{WCD939X_SPARE_0,                        0x00},
+	{WCD939X_SPARE_1,                        0x00},
+	{WCD939X_SPARE_2,                        0x00},
+	{WCD939X_EFUSE_REG_0,                    0x00},
+	{WCD939X_EFUSE_REG_1,                    0xff},
+	{WCD939X_EFUSE_REG_2,                    0xff},
+	{WCD939X_EFUSE_REG_3,                    0xff},
+	{WCD939X_EFUSE_REG_4,                    0xff},
+	{WCD939X_EFUSE_REG_5,                    0xff},
+	{WCD939X_EFUSE_REG_6,                    0xff},
+	{WCD939X_EFUSE_REG_7,                    0xff},
+	{WCD939X_EFUSE_REG_8,                    0xff},
+	{WCD939X_EFUSE_REG_9,                    0xff},
+	{WCD939X_EFUSE_REG_10,                   0xff},
+	{WCD939X_EFUSE_REG_11,                   0xff},
+	{WCD939X_EFUSE_REG_12,                   0xff},
+	{WCD939X_EFUSE_REG_13,                   0xff},
+	{WCD939X_EFUSE_REG_14,                   0xff},
+	{WCD939X_EFUSE_REG_15,                   0xff},
+	{WCD939X_EFUSE_REG_16,                   0xff},
+	{WCD939X_EFUSE_REG_17,                   0xff},
+	{WCD939X_EFUSE_REG_18,                   0xff},
+	{WCD939X_EFUSE_REG_19,                   0xff},
+	{WCD939X_EFUSE_REG_20,                   0x0e},
+	{WCD939X_EFUSE_REG_21,                   0x00},
+	{WCD939X_EFUSE_REG_22,                   0x00},
+	{WCD939X_EFUSE_REG_23,                   0xf6},
+	{WCD939X_EFUSE_REG_24,                   0x18},
+	{WCD939X_EFUSE_REG_25,                   0x00},
+	{WCD939X_EFUSE_REG_26,                   0x00},
+	{WCD939X_EFUSE_REG_27,                   0x00},
+	{WCD939X_EFUSE_REG_28,                   0x00},
+	{WCD939X_EFUSE_REG_29,                   0x0f},
+	{WCD939X_EFUSE_REG_30,                   0x49},
+	{WCD939X_EFUSE_REG_31,                   0x00},
+	{WCD939X_TX_REQ_FB_CTL_0,                0x88},
+	{WCD939X_TX_REQ_FB_CTL_1,                0x88},
+	{WCD939X_TX_REQ_FB_CTL_2,                0x88},
+	{WCD939X_TX_REQ_FB_CTL_3,                0x88},
+	{WCD939X_TX_REQ_FB_CTL_4,                0x88},
+	{WCD939X_DEM_BYPASS_DATA0,               0x55},
+	{WCD939X_DEM_BYPASS_DATA1,               0x55},
+	{WCD939X_DEM_BYPASS_DATA2,               0x55},
+	{WCD939X_DEM_BYPASS_DATA3,               0x01},
+	{WCD939X_DEM_SECOND_ORDER,               0x03},
+	{WCD939X_DSM_CTRL,                       0x00},
+	{WCD939X_DSM_0_STATIC_DATA_0,            0x00},
+	{WCD939X_DSM_0_STATIC_DATA_1,            0x00},
+	{WCD939X_DSM_0_STATIC_DATA_2,            0x00},
+	{WCD939X_DSM_0_STATIC_DATA_3,            0x00},
+	{WCD939X_DSM_1_STATIC_DATA_0,            0x00},
+	{WCD939X_DSM_1_STATIC_DATA_1,            0x00},
+	{WCD939X_DSM_1_STATIC_DATA_2,            0x00},
+	{WCD939X_DSM_1_STATIC_DATA_3,            0x00},
+	{WCD939X_RX_PAGE,                        0x00},
+	{WCD939X_TOP_CFG0,                       0x00},
+	{WCD939X_HPHL_COMP_WR_LSB,               0x00},
+	{WCD939X_HPHL_COMP_WR_MSB,               0x00},
+	{WCD939X_HPHL_COMP_LUT,                  0x00},
+	{WCD939X_HPHL_COMP_RD_LSB,               0x00},
+	{WCD939X_HPHL_COMP_RD_MSB,               0x00},
+	{WCD939X_HPHR_COMP_WR_LSB,               0x00},
+	{WCD939X_HPHR_COMP_WR_MSB,               0x00},
+	{WCD939X_HPHR_COMP_LUT,                  0x00},
+	{WCD939X_HPHR_COMP_RD_LSB,               0x00},
+	{WCD939X_HPHR_COMP_RD_MSB,               0x00},
+	{WCD939X_DSD0_DEBUG_CFG1,                0x05},
+	{WCD939X_DSD0_DEBUG_CFG2,                0x08},
+	{WCD939X_DSD0_DEBUG_CFG3,                0x00},
+	{WCD939X_DSD0_DEBUG_CFG4,                0x00},
+	{WCD939X_DSD0_DEBUG_CFG5,                0x00},
+	{WCD939X_DSD0_DEBUG_CFG6,                0x00},
+	{WCD939X_DSD1_DEBUG_CFG1,                0x03},
+	{WCD939X_DSD1_DEBUG_CFG2,                0x08},
+	{WCD939X_DSD1_DEBUG_CFG3,                0x00},
+	{WCD939X_DSD1_DEBUG_CFG4,                0x00},
+	{WCD939X_DSD1_DEBUG_CFG5,                0x00},
+	{WCD939X_DSD1_DEBUG_CFG6,                0x00},
+	{WCD939X_HPHL_RX_PATH_CFG0,              0x00},
+	{WCD939X_HPHL_RX_PATH_CFG1,              0x00},
+	{WCD939X_HPHR_RX_PATH_CFG0,              0x00},
+	{WCD939X_HPHR_RX_PATH_CFG1,              0x00},
+	{WCD939X_RX_PATH_CFG2,                   0x00},
+	{WCD939X_HPHL_RX_PATH_SEC0,              0x00},
+	{WCD939X_HPHL_RX_PATH_SEC1,              0x00},
+	{WCD939X_HPHL_RX_PATH_SEC2,              0x00},
+	{WCD939X_HPHL_RX_PATH_SEC3,              0x00},
+	{WCD939X_HPHR_RX_PATH_SEC0,              0x00},
+	{WCD939X_HPHR_RX_PATH_SEC1,              0x00},
+	{WCD939X_HPHR_RX_PATH_SEC2,              0x00},
+	{WCD939X_HPHR_RX_PATH_SEC3,              0x00},
+	{WCD939X_RX_PATH_SEC4,                   0x00},
+	{WCD939X_RX_PATH_SEC5,                   0x00},
+	{WCD939X_CTL0,                           0x60},
+	{WCD939X_CTL1,                           0xdb},
+	{WCD939X_CTL2,                           0xff},
+	{WCD939X_CTL3,                           0x35},
+	{WCD939X_CTL4,                           0xff},
+	{WCD939X_CTL5,                           0x00},
+	{WCD939X_CTL6,                           0x01},
+	{WCD939X_CTL7,                           0x08},
+	{WCD939X_CTL8,                           0x00},
+	{WCD939X_CTL9,                           0x00},
+	{WCD939X_CTL10,                          0x06},
+	{WCD939X_CTL11,                          0x12},
+	{WCD939X_CTL12,                          0x1e},
+	{WCD939X_CTL13,                          0x2a},
+	{WCD939X_CTL14,                          0x36},
+	{WCD939X_CTL15,                          0x3c},
+	{WCD939X_CTL16,                          0xc4},
+	{WCD939X_CTL17,                          0x00},
+	{WCD939X_CTL18,                          0x0c},
+	{WCD939X_CTL19,                          0x16},
+	{WCD939X_R_CTL0,                         0x60},
+	{WCD939X_R_CTL1,                         0xdb},
+	{WCD939X_R_CTL2,                         0xff},
+	{WCD939X_R_CTL3,                         0x35},
+	{WCD939X_R_CTL4,                         0xff},
+	{WCD939X_R_CTL5,                         0x00},
+	{WCD939X_R_CTL6,                         0x01},
+	{WCD939X_R_CTL7,                         0x08},
+	{WCD939X_R_CTL8,                         0x00},
+	{WCD939X_R_CTL9,                         0x00},
+	{WCD939X_R_CTL10,                        0x06},
+	{WCD939X_R_CTL11,                        0x12},
+	{WCD939X_R_CTL12,                        0x1e},
+	{WCD939X_R_CTL13,                        0x2a},
+	{WCD939X_R_CTL14,                        0x36},
+	{WCD939X_R_CTL15,                        0x3c},
+	{WCD939X_R_CTL16,                        0xc4},
+	{WCD939X_R_CTL17,                        0x00},
+	{WCD939X_R_CTL18,                        0x0c},
+	{WCD939X_R_CTL19,                        0x16},
+	{WCD939X_PATH_CTL,                       0x00},
+	{WCD939X_CFG0,                           0x07},
+	{WCD939X_CFG1,                           0x3c},
+	{WCD939X_CFG2,                           0x00},
+	{WCD939X_CFG3,                           0x00},
+	{WCD939X_DSD_HPHL_PATH_CTL,              0x00},
+	{WCD939X_DSD_HPHL_CFG0,                  0x00},
+	{WCD939X_DSD_HPHL_CFG1,                  0x00},
+	{WCD939X_DSD_HPHL_CFG2,                  0x22},
+	{WCD939X_DSD_HPHL_CFG3,                  0x00},
+	{WCD939X_CFG4,                           0x1a},
+	{WCD939X_CFG5,                           0x00},
+	{WCD939X_DSD_HPHR_PATH_CTL,              0x00},
+	{WCD939X_DSD_HPHR_CFG0,                  0x00},
+	{WCD939X_DSD_HPHR_CFG1,                  0x00},
+	{WCD939X_DSD_HPHR_CFG2,                  0x22},
+	{WCD939X_DSD_HPHR_CFG3,                  0x00},
+	{WCD939X_DSD_HPHR_CFG4,                  0x1a},
+	{WCD939X_DSD_HPHR_CFG5,                  0x00},
+};
+
+static bool wcd939x_readable_register(struct device *dev, unsigned int reg)
+{
+	if (reg <= WCD939X_BASE + 1)
+		return 0;
+
+	return wcd939x_reg_access[WCD939X_REG(reg)] & RD_REG;
+}
+
+static bool wcd939x_writeable_register(struct device *dev, unsigned int reg)
+{
+	if (reg <= WCD939X_BASE + 1)
+		return 0;
+
+	return wcd939x_reg_access[WCD939X_REG(reg)] & WR_REG;
+}
+
+static bool wcd939x_volatile_register(struct device *dev, unsigned int reg)
+{
+	if (reg <= WCD939X_BASE + 1)
+		return 0;
+
+	return ((wcd939x_reg_access[WCD939X_REG(reg)] & RD_REG) &&
+		!(wcd939x_reg_access[WCD939X_REG(reg)] & WR_REG));
+}
+
+struct regmap_config wcd939x_regmap_config = {
+	.reg_bits = 16,
+	.val_bits = 8,
+	.cache_type = REGCACHE_RBTREE,
+	.reg_defaults = wcd939x_defaults,
+	.num_reg_defaults = ARRAY_SIZE(wcd939x_defaults),
+	.max_register = WCD939X_MAX_REGISTER,
+	.volatile_reg = wcd939x_volatile_register,
+	.readable_reg = wcd939x_readable_register,
+	.writeable_reg = wcd939x_writeable_register,
+	.reg_format_endian = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian = REGMAP_ENDIAN_NATIVE,
+	.can_multi_write = true,
+	.use_single_read = true,
+};

asoc/codecs/wcd939x/wcd939x-slave.c

@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/component.h>
+#include <soc/soundwire.h>
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+
+#define SWR_SLV_MAX_REG_ADDR    0x2009
+#define SWR_SLV_START_REG_ADDR  0x40
+#define SWR_SLV_MAX_BUF_LEN     20
+#define BYTES_PER_LINE          12
+#define SWR_SLV_RD_BUF_LEN      8
+#define SWR_SLV_WR_BUF_LEN      32
+#define SWR_SLV_MAX_DEVICES     2
+#endif /* CONFIG_DEBUG_FS */
+
+#define SWR_MAX_RETRY    5
+
+struct wcd939x_slave_priv {
+	struct swr_device *swr_slave;
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *debugfs_wcd939x_dent;
+	struct dentry *debugfs_peek;
+	struct dentry *debugfs_poke;
+	struct dentry *debugfs_reg_dump;
+	unsigned int read_data;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_FS
+static int codec_debug_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static int get_parameters(char *buf, u32 *param1, int num_of_par)
+{
+	char *token = NULL;
+	int base = 0, cnt = 0;
+
+	token = strsep(&buf, " ");
+	for (cnt = 0; cnt < num_of_par; cnt++) {
+		if (token) {
+			if ((token[1] == 'x') || (token[1] == 'X'))
+				base = 16;
+			else
+				base = 10;
+
+			if (kstrtou32(token, base, &param1[cnt]) != 0)
+				return -EINVAL;
+
+			token = strsep(&buf, " ");
+		} else {
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+static bool is_swr_slv_reg_readable(int reg)
+{
+	int ret = true;
+
+	if (((reg > 0x46) && (reg < 0x4A)) ||
+	    ((reg > 0x4A) && (reg < 0x50)) ||
+	    ((reg > 0x55) && (reg < 0xD0)) ||
+	    ((reg > 0xD0) && (reg < 0xE0)) ||
+	    ((reg > 0xE0) && (reg < 0xF0)) ||
+	    ((reg > 0xF0) && (reg < 0x100)) ||
+	    ((reg > 0x105) && (reg < 0x120)) ||
+	    ((reg > 0x205) && (reg < 0x220)) ||
+	    ((reg > 0x305) && (reg < 0x320)) ||
+	    ((reg > 0x405) && (reg < 0x420)) ||
+	    ((reg > 0x128) && (reg < 0x130)) ||
+	    ((reg > 0x228) && (reg < 0x230)) ||
+	    ((reg > 0x328) && (reg < 0x330)) ||
+	    ((reg > 0x428) && (reg < 0x430)) ||
+	    ((reg > 0x138) && (reg < 0x205)) ||
+	    ((reg > 0x238) && (reg < 0x305)) ||
+	    ((reg > 0x338) && (reg < 0x405)) ||
+	    ((reg > 0x405) && (reg < 0xF00)) ||
+	    ((reg > 0xF05) && (reg < 0xF20)) ||
+	    ((reg > 0xF25) && (reg < 0xF30)) ||
+	    ((reg > 0xF35) && (reg < 0x2000)))
+		ret = false;
+
+	return ret;
+}
+
+static ssize_t wcd939x_swrslave_reg_show(struct swr_device *pdev,
+					char __user *ubuf,
+					size_t count, loff_t *ppos)
+{
+	int i, reg_val, len;
+	ssize_t total = 0;
+	char tmp_buf[SWR_SLV_MAX_BUF_LEN];
+
+	if (!ubuf || !ppos)
+		return 0;
+
+	for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
+		i <= SWR_SLV_MAX_REG_ADDR; i++) {
+		if (!is_swr_slv_reg_readable(i))
+			continue;
+		swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
+		len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
+			       (reg_val & 0xFF));
+		if (((total + len) >= count - 1) || (len < 0))
+			break;
+		if (copy_to_user((ubuf + total), tmp_buf, len)) {
+			pr_err_ratelimited("%s: fail to copy reg dump\n", __func__);
+			total = -EFAULT;
+			goto copy_err;
+		}
+		total += len;
+		*ppos += len;
+	}
+
+copy_err:
+	*ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
+	return total;
+}
+
+static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
+				size_t count, loff_t *ppos)
+{
+	struct swr_device *pdev;
+
+	if (!count || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	return wcd939x_swrslave_reg_show(pdev, ubuf, count, ppos);
+}
+
+static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
+				size_t count, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_RD_BUF_LEN];
+	struct swr_device *pdev = NULL;
+	struct wcd939x_slave_priv *wcd939x_slave = NULL;
+
+	if (!count || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	wcd939x_slave = swr_get_dev_data(pdev);
+	if (!wcd939x_slave)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	snprintf(lbuf, sizeof(lbuf), "0x%x\n",
+			(wcd939x_slave->read_data & 0xFF));
+
+	return simple_read_from_buffer(ubuf, count, ppos, lbuf,
+					       strnlen(lbuf, 7));
+}
+
+static ssize_t codec_debug_peek_write(struct file *file,
+	const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_WR_BUF_LEN];
+	int rc = 0;
+	u32 param[5];
+	struct swr_device *pdev = NULL;
+	struct wcd939x_slave_priv *wcd939x_slave = NULL;
+
+	if (!cnt || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	wcd939x_slave = swr_get_dev_data(pdev);
+	if (!wcd939x_slave)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	if (cnt > sizeof(lbuf) - 1)
+		return -EINVAL;
+
+	rc = copy_from_user(lbuf, ubuf, cnt);
+	if (rc)
+		return -EFAULT;
+
+	lbuf[cnt] = '\0';
+	rc = get_parameters(lbuf, param, 1);
+	if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
+		return -EINVAL;
+	swr_read(pdev, pdev->dev_num, param[0], &wcd939x_slave->read_data, 1);
+	if (rc == 0)
+		rc = cnt;
+	else
+		pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
+
+	return rc;
+}
+
+static ssize_t codec_debug_write(struct file *file,
+	const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_WR_BUF_LEN];
+	int rc = 0;
+	u32 param[5];
+	struct swr_device *pdev;
+
+	if (!file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	if (cnt > sizeof(lbuf) - 1)
+		return -EINVAL;
+
+	rc = copy_from_user(lbuf, ubuf, cnt);
+	if (rc)
+		return -EFAULT;
+
+	lbuf[cnt] = '\0';
+	rc = get_parameters(lbuf, param, 2);
+	if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
+		(param[1] <= 0xFF) && (rc == 0)))
+		return -EINVAL;
+	swr_write(pdev, pdev->dev_num, param[0], &param[1]);
+	if (rc == 0)
+		rc = cnt;
+	else
+		pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
+
+	return rc;
+}
+
+static const struct file_operations codec_debug_write_ops = {
+	.open = codec_debug_open,
+	.write = codec_debug_write,
+};
+
+static const struct file_operations codec_debug_read_ops = {
+	.open = codec_debug_open,
+	.read = codec_debug_read,
+	.write = codec_debug_peek_write,
+};
+
+static const struct file_operations codec_debug_dump_ops = {
+	.open = codec_debug_open,
+	.read = codec_debug_dump,
+};
+#endif
+
+static int wcd939x_slave_bind(struct device *dev,
+				struct device *master, void *data)
+{
+	int ret = 0;
+	uint8_t devnum = 0;
+	struct swr_device *pdev = to_swr_device(dev);
+	int retry = SWR_MAX_RETRY;
+
+	if (!pdev) {
+		pr_err_ratelimited("%s: invalid swr device handle\n", __func__);
+		return -EINVAL;
+	}
+
+	do {
+		/* Add delay for soundwire enumeration */
+		usleep_range(100, 110);
+		ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
+	} while (ret && --retry);
+
+	if (ret) {
+		dev_dbg(&pdev->dev,
+			"%s get devnum %d for dev addr %llx failed\n",
+			__func__, devnum, pdev->addr);
+		ret = -EPROBE_DEFER;
+		return ret;
+	}
+	pdev->dev_num = devnum;
+
+	return ret;
+}
+
+static void wcd939x_slave_unbind(struct device *dev,
+				struct device *master, void *data)
+{
+	struct wcd939x_slave_priv *wcd939x_slave = NULL;
+	struct swr_device *pdev = to_swr_device(dev);
+
+	wcd939x_slave = swr_get_dev_data(pdev);
+	if (!wcd939x_slave) {
+		dev_err_ratelimited(&pdev->dev, "%s: wcd939x_slave is NULL\n", __func__);
+		return;
+	}
+}
+
+static const struct swr_device_id wcd939x_swr_id[] = {
+	{"wcd939x-slave", 0},
+	{}
+};
+
+static const struct of_device_id wcd939x_swr_dt_match[] = {
+	{
+		.compatible = "qcom,wcd939x-slave",
+	},
+	{}
+};
+
+static const struct component_ops wcd939x_slave_comp_ops = {
+	.bind   = wcd939x_slave_bind,
+	.unbind = wcd939x_slave_unbind,
+};
+
+static int wcd939x_swr_probe(struct swr_device *pdev)
+{
+	struct wcd939x_slave_priv *wcd939x_slave = NULL;
+
+	wcd939x_slave = devm_kzalloc(&pdev->dev,
+				sizeof(struct wcd939x_slave_priv), GFP_KERNEL);
+	if (!wcd939x_slave)
+		return -ENOMEM;
+
+	swr_set_dev_data(pdev, wcd939x_slave);
+
+	wcd939x_slave->swr_slave = pdev;
+
+#ifdef CONFIG_DEBUG_FS
+	if (!wcd939x_slave->debugfs_wcd939x_dent) {
+		wcd939x_slave->debugfs_wcd939x_dent = debugfs_create_dir(
+						dev_name(&pdev->dev), 0);
+		if (!IS_ERR(wcd939x_slave->debugfs_wcd939x_dent)) {
+			wcd939x_slave->debugfs_peek =
+					debugfs_create_file("swrslave_peek",
+					S_IFREG | 0444,
+					wcd939x_slave->debugfs_wcd939x_dent,
+					(void *) pdev,
+					&codec_debug_read_ops);
+
+			wcd939x_slave->debugfs_poke =
+					debugfs_create_file("swrslave_poke",
+					S_IFREG | 0444,
+					wcd939x_slave->debugfs_wcd939x_dent,
+					(void *) pdev,
+					&codec_debug_write_ops);
+
+			wcd939x_slave->debugfs_reg_dump =
+					debugfs_create_file(
+					"swrslave_reg_dump",
+					S_IFREG | 0444,
+					wcd939x_slave->debugfs_wcd939x_dent,
+					(void *) pdev,
+					&codec_debug_dump_ops);
+                }
+        }
+#endif
+
+	return component_add(&pdev->dev, &wcd939x_slave_comp_ops);
+}
+
+static int wcd939x_swr_remove(struct swr_device *pdev)
+{
+#ifdef CONFIG_DEBUG_FS
+	struct wcd939x_slave_priv *wcd939x_slave = swr_get_dev_data(pdev);
+
+	if (wcd939x_slave) {
+		debugfs_remove_recursive(wcd939x_slave->debugfs_wcd939x_dent);
+		wcd939x_slave->debugfs_wcd939x_dent = NULL;
+	}
+#endif
+	component_del(&pdev->dev, &wcd939x_slave_comp_ops);
+	swr_set_dev_data(pdev, NULL);
+	swr_remove_device(pdev);
+
+	return 0;
+}
+
+static struct swr_driver wcd939x_slave_driver = {
+	.driver = {
+		.name = "wcd939x-slave",
+		.owner = THIS_MODULE,
+		.of_match_table = wcd939x_swr_dt_match,
+	},
+	.probe = wcd939x_swr_probe,
+	.remove = wcd939x_swr_remove,
+	.id_table = wcd939x_swr_id,
+};
+
+static int __init wcd939x_slave_init(void)
+{
+	return swr_driver_register(&wcd939x_slave_driver);
+}
+
+static void __exit wcd939x_slave_exit(void)
+{
+	swr_driver_unregister(&wcd939x_slave_driver);
+}
+
+module_init(wcd939x_slave_init);
+module_exit(wcd939x_slave_exit);
+
+MODULE_DESCRIPTION("WCD939X Swr Slave driver");
+MODULE_LICENSE("GPL v2");

asoc/codecs/wcd939x/wcd939x-tables.c

@@ -0,0 +1,568 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd939x-registers.h"
+
+const u8 wcd939x_reg_access[WCD939X_NUM_REGISTERS] = {
+	[WCD939X_REG(WCD939X_ANA_PAGE)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RX_SUPPLIES)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH)]                            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR)]                            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR_COMPANDER_CTL)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_CH1)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_CH2)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_CH3)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_CH4)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB1_MICB2_DSP_EN_LOGIC)]       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB3_DSP_EN_LOGIC)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_MECH)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_ELECT)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_ZDET)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_RESULT_1)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_MBHC_RESULT_2)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_MBHC_RESULT_3)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_MBHC_BTN0)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_BTN1)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_BTN2)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_BTN3)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_BTN4)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_BTN5)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_BTN6)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MBHC_BTN7)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB1)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB2)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB2_RAMP)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB3)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB4)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL)]                            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VBG_FINE_ADJ)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VDDCX_ADJUST)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DISABLE_LDOL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL_CLK)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL_ANA)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ZDET_VNEG_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ZDET_BIAS_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL_BCS)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MOISTURE_DET_FSM_STATUS)]        = RD_REG,
+	[WCD939X_REG(WCD939X_TEST_CTL)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MODE)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_LDOH_BIAS)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_STB_LOADS)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SLOWRAMP)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TEST_CTL_1)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TEST_CTL_2)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TEST_CTL_3)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB2_TEST_CTL_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB2_TEST_CTL_2)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB2_TEST_CTL_3)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB3_TEST_CTL_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB3_TEST_CTL_2)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB3_TEST_CTL_3)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB4_TEST_CTL_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB4_TEST_CTL_2)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MICB4_TEST_CTL_3)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ADC_VCM)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_ATEST)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SPARE1)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SPARE2)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_DIV_CTL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_DIV_START)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SPARE3)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SPARE4)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TEST_EN)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ADC_IB)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ATEST_REFCTL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_1_2_TEST_CTL)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TEST_BLK_EN1)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE1_CLKDIV)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SAR2_ERR)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_SAR1_ERR)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_TX_3_4_TEST_EN)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_3_4_ADC_IB)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_3_4_ATEST_REFCTL)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_3_4_TEST_CTL)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TEST_BLK_EN3)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE3_CLKDIV)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SAR4_ERR)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_SAR3_ERR)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_TEST_BLK_EN2)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE2_CLKDIV)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_3_4_SPARE1)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TEST_BLK_EN4)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE4_CLKDIV)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_3_4_SPARE2)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MODE_1)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MODE_2)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MODE_3)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTRL_VCL_1)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTRL_VCL_2)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTRL_CCL_1)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTRL_CCL_2)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTRL_CCL_3)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTRL_CCL_4)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTRL_CCL_5)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BUCK_TMUX_A_D)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BUCK_SW_DRV_CNTL)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SPARE)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EN)]                             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_1)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_2)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_3)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_4)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_5)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_6)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_7)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_8)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEG_CTRL_9)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEGDAC_CTRL_1)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEGDAC_CTRL_2)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_VNEGDAC_CTRL_3)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTRL_1)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_FLYBACK_TEST_CTL)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_AUX_SW_CTL)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_AUX_IN_CONN)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TIMER_DIV)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_OCP_CTL)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_OCP_COUNT)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_EAR_DAC)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_EAR_AMP)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_HPH_LDO)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_HPH_PA)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_HPH_RDACBUFF_CNP2)]         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_HPH_RDAC_LDO)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_HPH_CNP1)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_HPH_LOWPOWER)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_AUX_DAC)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_AUX_AMP)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_VNEGDAC_BLEEDER)]           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_MISC)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_BUCK_RST)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_BUCK_VREF_ERRAMP)]          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_FLYB_ERRAMP)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_FLYB_BUFF)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_BIAS_FLYB_MID_RST)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_L_STATUS)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_R_STATUS)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_CNP_EN)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CNP_WG_CTL)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CNP_WG_TIME)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH_OCP_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_AUTO_CHOP)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CHOP_CTL)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_CTL1)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_CTL2)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_L_EN)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_L_TEST)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_L_ATEST)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_EN)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_TEST)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_ATEST)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RDAC_CLK_CTL1)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RDAC_CLK_CTL2)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RDAC_LDO_CTL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RDAC_CHOP_CLK_LP_CTL)]           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_REFBUFF_UHQA_CTL)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_REFBUFF_LP_CTL)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_L_DAC_CTL)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_DAC_CTL)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHLR_SURGE_COMP_SEL)]           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHLR_SURGE_EN)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHLR_SURGE_MISC1)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHLR_SURGE_STATUS)]             = RD_REG,
+	[WCD939X_REG(WCD939X_EAR_EN_REG)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR_PA_CON)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR_SP_CON)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR_DAC_CON)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR_CNP_FSM_CON)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR_TEST_CTL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_STATUS_REG_1)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_STATUS_REG_2)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_ANA_NEW_PAGE)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ANA_HPH2)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ANA_HPH3)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SLEEP_CTL)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_WATCHDOG_CTL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ELECT_REM_CLAMP_CTL)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL_1)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL_2)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PLUG_DETECT_CTL)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ZDET_ANA_CTL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ZDET_RAMP_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_FSM_STATUS)]                     = RD_REG,
+	[WCD939X_REG(WCD939X_ADC_RESULT)]                     = RD_REG,
+	[WCD939X_REG(WCD939X_TX_CH12_MUX)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_CH34_MUX)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DIE_CRK_DET_EN)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DIE_CRK_DET_OUT)]                = RD_REG,
+	[WCD939X_REG(WCD939X_RDAC_GAIN_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_GAIN_CTL_L)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RDAC_VREF_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RDAC_OVERRIDE_CTL)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_GAIN_CTL_R)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_MISC1)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_MISC2)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_RDAC_MISC)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH_TIMER1)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH_TIMER2)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH_TIMER3)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH_TIMER4)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_RDAC_MISC2)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PA_RDAC_MISC3)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RDAC_HD2_CTL_L)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RDAC_HD2_CTL_R)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH_RDAC_BIAS_LOHIFI)]           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH_RDAC_BIAS_ULP)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPH_RDAC_LDO_LP)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MOISTURE_DET_DC_CTRL)]           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MOISTURE_DET_POLLING_CTRL)]      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MECH_DET_CURRENT)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW)]  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR_CHOPPER_CON)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CNP_VCM_CON1)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CNP_VCM_CON2)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EAR_DYNAMIC_BIAS)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_WATCHDOG_CTL_1)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_WATCHDOG_CTL_2)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DIE_CRK_DET_INT1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DIE_CRK_DET_INT2)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_DIVSTOP_L2)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_DIVSTOP_L1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_DIVSTOP_L0)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_DIVSTOP_ULP1P2M)]           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_DIVSTOP_ULP0P6M)]           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_ICTRL_STG1_L2L1)]           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_ICTRL_STG1_L0)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_ICTRL_STG1_ULP)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2MAIN_L2L1)]       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2MAIN_L0)]         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2MAIN_ULP)]        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0)]     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2CASC_ULP)]        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXADC_SCBIAS_L2L1)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXADC_SCBIAS_L0ULP)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXADC_INT_L2)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXADC_INT_L1)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXADC_INT_L0)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TXADC_INT_ULP)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DIGITAL_PAGE)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CHIP_ID0)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_CHIP_ID1)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_CHIP_ID2)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_CHIP_ID3)]                       = RD_REG,
+	[WCD939X_REG(WCD939X_SWR_TX_CLK_RATE)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_RST_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TOP_CLK_CFG)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_ANA_CLK_CTL)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_DIG_CLK_CTL)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_RST_EN)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_PATH_MODE)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_RX_RST)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_RX0_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_RX1_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_RX2_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_TX_ANA_MODE_0_1)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_TX_ANA_MODE_2_3)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_COMP_CTL_0)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_ANA_TX_CLK_CTL)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A1_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A1_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A2_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A2_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A3_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A3_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A4_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A4_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A5_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A5_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A6_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_A7_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_C_0)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_C_1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_C_2)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_C_3)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_R1)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_R2)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_R3)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_R4)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_R5)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_R6)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_DSM_R7)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A1_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A1_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A2_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A2_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A3_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A3_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A4_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A4_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A5_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A5_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A6_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_A7_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_C_0)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_C_1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_C_2)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_C_3)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_R1)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_R2)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_R3)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_R4)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_R5)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_R6)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_DSM_R7)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_GAIN_RX_0)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_GAIN_RX_1)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_GAIN_DSD_0)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_GAIN_DSD_1)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_GAIN_DSD_2)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_GAIN_DSD_0)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_GAIN_DSD_1)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_GAIN_DSD_2)]             = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_HPH_GAIN_CTL)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_GAIN_CTL)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_EAR_PATH_CTL)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_SWR_CLH)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_CLH_BYP)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_TX0_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_TX1_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_TX2_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_TX_RST)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_REQ_CTL)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_RST)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_AMIC_CTL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_DMIC_CTL)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_DMIC1_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_DMIC2_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_DMIC3_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_DMIC4_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EFUSE_PRG_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EFUSE_CTL)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_DMIC_RATE_1_2)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_DMIC_RATE_3_4)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PDM_WD_CTL0)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PDM_WD_CTL1)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PDM_WD_CTL2)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_MODE)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_MASK_0)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_MASK_1)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_MASK_2)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_STATUS_0)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_INTR_STATUS_1)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_INTR_STATUS_2)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_INTR_CLEAR_0)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_CLEAR_1)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_CLEAR_2)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_LEVEL_0)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_LEVEL_1)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_LEVEL_2)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_SET_0)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_SET_1)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_SET_2)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_TEST_0)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_TEST_1)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_INTR_TEST_2)]                    = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_MODE_DBG_EN)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_MODE_DBG_0_1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_MODE_DBG_2_3)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_LB_IN_SEL_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_LOOP_BACK_MODE)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_DAC_TEST)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_HM_TEST_RX_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_HM_TEST_TX_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_HM_TEST_RX_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_HM_TEST_TX_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_HM_TEST_TX_2)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SWR_HM_TEST_0)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_SWR_HM_TEST_1)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_PAD_CTL_SWR_0)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PAD_CTL_SWR_1)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_I2C_CTL)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CDC_TX_TANGGU_SW_MODE)]          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EFUSE_TEST_CTL_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EFUSE_TEST_CTL_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EFUSE_T_DATA_0)]                 = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_T_DATA_1)]                 = RD_REG,
+	[WCD939X_REG(WCD939X_PAD_CTL_PDM_RX0)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PAD_CTL_PDM_RX1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PAD_CTL_PDM_TX0)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PAD_CTL_PDM_TX1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PAD_CTL_PDM_TX2)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PAD_INP_DIS_0)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PAD_INP_DIS_1)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DRIVE_STRENGTH_0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DRIVE_STRENGTH_1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DRIVE_STRENGTH_2)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RX_DATA_EDGE_CTL)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_DATA_EDGE_CTL)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_GPIO_MODE)]                      = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PIN_CTL_OE)]                     = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PIN_CTL_DATA_0)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PIN_CTL_DATA_1)]                 = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PIN_STATUS_0)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_PIN_STATUS_1)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_DIG_DEBUG_CTL)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DIG_DEBUG_EN)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ANA_CSR_DBG_ADD)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_ANA_CSR_DBG_CTL)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SSP_DBG)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_MODE_STATUS_0)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_MODE_STATUS_1)]                  = RD_REG,
+	[WCD939X_REG(WCD939X_SPARE_0)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SPARE_1)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_SPARE_2)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_0)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_1)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_2)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_3)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_4)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_5)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_6)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_7)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_8)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_9)]                    = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_10)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_11)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_12)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_13)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_14)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_15)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_16)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_17)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_18)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_19)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_20)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_21)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_22)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_23)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_24)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_25)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_26)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_27)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_28)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_29)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_30)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_EFUSE_REG_31)]                   = RD_REG,
+	[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_0)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_2)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_3)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_4)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DEM_BYPASS_DATA0)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DEM_BYPASS_DATA1)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DEM_BYPASS_DATA2)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DEM_BYPASS_DATA3)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DEM_SECOND_ORDER)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_CTRL)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_0_STATIC_DATA_0)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_0_STATIC_DATA_1)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_0_STATIC_DATA_2)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_0_STATIC_DATA_3)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_1_STATIC_DATA_0)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_1_STATIC_DATA_1)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_1_STATIC_DATA_2)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSM_1_STATIC_DATA_3)]            = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RX_PAGE)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_TOP_CFG0)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_COMP_WR_LSB)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_COMP_WR_MSB)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_COMP_LUT)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_COMP_RD_LSB)]               = RD_REG,
+	[WCD939X_REG(WCD939X_HPHL_COMP_RD_MSB)]               = RD_REG,
+	[WCD939X_REG(WCD939X_HPHR_COMP_WR_LSB)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_COMP_WR_MSB)]               = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_COMP_LUT)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_COMP_RD_LSB)]               = RD_REG,
+	[WCD939X_REG(WCD939X_HPHR_COMP_RD_MSB)]               = RD_REG,
+	[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG2)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG3)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG4)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG5)]                = RD_REG,
+	[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG6)]                = RD_REG,
+	[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG1)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG2)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG3)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG4)]                = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG5)]                = RD_REG,
+	[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG6)]                = RD_REG,
+	[WCD939X_REG(WCD939X_HPHL_RX_PATH_CFG0)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_RX_PATH_CFG1)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_RX_PATH_CFG0)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_RX_PATH_CFG1)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RX_PATH_CFG2)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_RX_PATH_SEC0)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_RX_PATH_SEC1)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_RX_PATH_SEC2)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHL_RX_PATH_SEC3)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_RX_PATH_SEC0)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_RX_PATH_SEC1)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_RX_PATH_SEC2)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_HPHR_RX_PATH_SEC3)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RX_PATH_SEC4)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_RX_PATH_SEC5)]                   = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL0)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL1)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL2)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL3)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL4)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL5)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL6)]                           = RD_REG,
+	[WCD939X_REG(WCD939X_CTL7)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL8)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL9)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL10)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL11)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL12)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL13)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL14)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL15)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL16)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL17)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL18)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CTL19)]                          = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL0)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL1)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL2)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL3)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL4)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL5)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL6)]                         = RD_REG,
+	[WCD939X_REG(WCD939X_R_CTL7)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL8)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL9)]                         = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL10)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL11)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL12)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL13)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL14)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL15)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL16)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL17)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL18)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_R_CTL19)]                        = RD_WR_REG,
+	[WCD939X_REG(WCD939X_PATH_CTL)]                       = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CFG0)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CFG1)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CFG2)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CFG3)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHL_PATH_CTL)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHL_CFG0)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHL_CFG1)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHL_CFG2)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHL_CFG3)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CFG4)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_CFG5)]                           = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHR_PATH_CTL)]              = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHR_CFG0)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHR_CFG1)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHR_CFG2)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHR_CFG3)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHR_CFG4)]                  = RD_WR_REG,
+	[WCD939X_REG(WCD939X_DSD_HPHR_CFG5)]                  = RD_WR_REG,
+};

asoc/codecs/wcd939x/wcd939x.c

@@ -0,0 +1,4494 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/component.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+#include <soc/soundwire.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <asoc/wcdcal-hwdep.h>
+#include <asoc/msm-cdc-pinctrl.h>
+#include <asoc/msm-cdc-supply.h>
+#include <bindings/audio-codec-port-types.h>
+#include <linux/qti-regmap-debugfs.h>
+
+#include "wcd939x-registers.h"
+#include "wcd939x.h"
+#include "internal.h"
+#include "asoc/bolero-slave-internal.h"
+#include "wcd939x-reg-masks.h"
+#include "wcd939x-reg-shifts.h"
+
+
+#define NUM_SWRS_DT_PARAMS 5
+#define WCD939X_VARIANT_ENTRY_SIZE 32
+
+#define WCD939X_VERSION_1_0 1
+#define WCD939X_VERSION_ENTRY_SIZE 32
+
+#define ADC_MODE_VAL_HIFI     0x01
+#define ADC_MODE_VAL_LO_HIF   0x02
+#define ADC_MODE_VAL_NORMAL   0x03
+#define ADC_MODE_VAL_LP       0x05
+#define ADC_MODE_VAL_ULP1     0x09
+#define ADC_MODE_VAL_ULP2     0x0B
+
+#define NUM_ATTEMPTS 5
+
+#define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
+#define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
+#define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
+#define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
+
+#define WCD939X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
+			SNDRV_PCM_RATE_384000)
+/* Fractional Rates */
+#define WCD939X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
+				SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
+
+#define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+		SNDRV_PCM_FMTBIT_S24_LE |\
+		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+#define REG_FIELD_VALUE(register_name, field_name, value) \
+WCD939X_##register_name, FIELD_MASK(register_name, field_name), \
+value << FIELD_SHIFT(register_name, field_name)
+enum {
+	CODEC_TX = 0,
+	CODEC_RX,
+};
+
+enum {
+	WCD_ADC1 = 0,
+	WCD_ADC2,
+	WCD_ADC3,
+	WCD_ADC4,
+	ALLOW_BUCK_DISABLE,
+	HPH_COMP_DELAY,
+	HPH_PA_DELAY,
+	AMIC2_BCS_ENABLE,
+	WCD_SUPPLIES_LPM_MODE,
+	WCD_ADC1_MODE,
+	WCD_ADC2_MODE,
+	WCD_ADC3_MODE,
+	WCD_ADC4_MODE,
+};
+
+enum {
+	ADC_MODE_INVALID = 0,
+	ADC_MODE_HIFI,
+	ADC_MODE_LO_HIF,
+	ADC_MODE_NORMAL,
+	ADC_MODE_LP,
+	ADC_MODE_ULP1,
+	ADC_MODE_ULP2,
+};
+
+static u8 tx_mode_bit[] = {
+	[ADC_MODE_INVALID] = 0x00,
+	[ADC_MODE_HIFI] = 0x01,
+	[ADC_MODE_LO_HIF] = 0x02,
+	[ADC_MODE_NORMAL] = 0x04,
+	[ADC_MODE_LP] = 0x08,
+	[ADC_MODE_ULP1] = 0x10,
+	[ADC_MODE_ULP2] = 0x20,
+};
+
+static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
+static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
+
+static int wcd939x_handle_post_irq(void *data);
+static int wcd939x_reset(struct device *dev);
+static int wcd939x_reset_low(struct device *dev);
+static int wcd939x_get_adc_mode(int val);
+
+static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
+	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
+	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
+	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
+	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
+	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
+	REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
+	REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
+	REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
+	REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
+	REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
+	REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
+	REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
+	REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
+	REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
+	REGMAP_IRQ_REG(WCD939X_IRQ_LDORT_SCD_INT, 2, 0x01),
+	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
+	REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
+	REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
+};
+
+static struct regmap_irq_chip wcd939x_regmap_irq_chip = {
+	.name = "wcd939x",
+	.irqs = wcd939x_irqs,
+	.num_irqs = ARRAY_SIZE(wcd939x_irqs),
+	.num_regs = 3,
+	.status_base = WCD939X_INTR_STATUS_0,
+	.mask_base = WCD939X_INTR_MASK_0,
+	.type_base = WCD939X_INTR_LEVEL_0,
+	.ack_base = WCD939X_INTR_CLEAR_0,
+	.use_ack = 1,
+	.runtime_pm = false,
+	.handle_post_irq = wcd939x_handle_post_irq,
+	.irq_drv_data = NULL,
+};
+
+static int wcd939x_handle_post_irq(void *data)
+{
+	struct wcd939x_priv *wcd939x = data;
+	u32 sts1 = 0, sts2 = 0, sts3 = 0;
+
+	regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_0, &sts1);
+	regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_1, &sts2);
+	regmap_read(wcd939x->regmap, WCD939X_INTR_STATUS_2, &sts3);
+
+	wcd939x->tx_swr_dev->slave_irq_pending =
+			((sts1 || sts2 || sts3) ? true : false);
+
+	return IRQ_HANDLED;
+}
+
+static int wcd939x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
+{
+	int ret = 0;
+	int bank = 0;
+
+	ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
+	if (ret)
+		return -EINVAL;
+
+	return ((bank & 0x40) ? 1: 0);
+}
+
+static int wcd939x_get_clk_rate(int mode)
+{
+	int rate;
+
+	switch (mode) {
+	case ADC_MODE_ULP2:
+		rate = SWR_CLK_RATE_0P6MHZ;
+		break;
+	case ADC_MODE_ULP1:
+		rate = SWR_CLK_RATE_1P2MHZ;
+		break;
+	case ADC_MODE_LP:
+		rate = SWR_CLK_RATE_4P8MHZ;
+		break;
+	case ADC_MODE_NORMAL:
+	case ADC_MODE_LO_HIF:
+	case ADC_MODE_HIFI:
+	case ADC_MODE_INVALID:
+	default:
+		rate = SWR_CLK_RATE_9P6MHZ;
+		break;
+	}
+
+	return rate;
+}
+
+static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component,
+					int rate, int bank)
+{
+	u8 mask = (bank ? 0xF0 : 0x0F);
+	u8 val = 0;
+
+	switch (rate) {
+	case SWR_CLK_RATE_0P6MHZ:
+		val = (bank ? 0x60 : 0x06);
+		break;
+	case SWR_CLK_RATE_1P2MHZ:
+		val = (bank ? 0x50 : 0x05);
+		break;
+	case SWR_CLK_RATE_2P4MHZ:
+		val = (bank ? 0x30 : 0x03);
+		break;
+	case SWR_CLK_RATE_4P8MHZ:
+		val = (bank ? 0x10 : 0x01);
+		break;
+	case SWR_CLK_RATE_9P6MHZ:
+	default:
+		val = 0x00;
+		break;
+	}
+	snd_soc_component_update_bits(component,
+				      WCD939X_SWR_TX_CLK_RATE,
+				      mask, val);
+
+	return 0;
+}
+
+static int wcd939x_init_reg(struct snd_soc_component *component)
+{
+
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(VBG_FINE_ADJ, VBG_FINE_ADJ, 0x04));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(BIAS, ANALOG_BIAS_EN, 0x01));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x01));
+
+	/* 10 msec delay as per HW requirement */
+	usleep_range(10000, 10010);
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(BIAS, PRECHRG_EN, 0x00));
+
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x15));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x15));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(REFBUFF_UHQA_CTL, SPARE_BITS, 0x02));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
+
+	snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_SCBIAS_ULP0P6M, 0x1));
+	snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(TXFE_ICTRL_STG2CASC_ULP, ICTRL_STG2CASC_ULP, 0x4));
+
+	snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(TXFE_ICTRL_STG2MAIN_ULP, ICTRL_STG2MAIN_ULP, 0x08));
+
+
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(MICB2_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(MICB3_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(MICB4_TEST_CTL_1, NOISE_FILT_RES_VAL, 0x07));
+	snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(TEST_BLK_EN2, TXFE2_MBHC_CLKRST_EN, 0x00));
+
+	snd_soc_component_update_bits(component,
+			REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHL, 0x01));
+	snd_soc_component_update_bits(component,
+			REG_FIELD_VALUE(HPHLR_SURGE_EN, EN_SURGE_PROTECTION_HPHR, 0x01));
+
+	return 0;
+}
+
+static int wcd939x_set_port_params(struct snd_soc_component *component,
+			u8 slv_prt_type, u8 *port_id, u8 *num_ch,
+			u8 *ch_mask, u32 *ch_rate,
+			u8 *port_type, u8 path)
+{
+	int i, j;
+	u8 num_ports = 0;
+	struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	switch (path) {
+	case CODEC_RX:
+		map = &wcd939x->rx_port_mapping;
+		num_ports = wcd939x->num_rx_ports;
+		break;
+	case CODEC_TX:
+		map = &wcd939x->tx_port_mapping;
+		num_ports = wcd939x->num_tx_ports;
+		break;
+	default:
+		dev_err_ratelimited(component->dev, "%s Invalid path selected %u\n",
+					__func__, path);
+		return -EINVAL;
+	}
+
+	for (i = 0; i <= num_ports; i++) {
+		for (j = 0; j < MAX_CH_PER_PORT; j++) {
+			if ((*map)[i][j].slave_port_type == slv_prt_type)
+				goto found;
+		}
+	}
+found:
+	if (i > num_ports || j == MAX_CH_PER_PORT) {
+		dev_err_ratelimited(component->dev, "%s Failed to find slave port for type %u\n",
+						__func__, slv_prt_type);
+		return -EINVAL;
+	}
+	*port_id = i;
+	*num_ch = (*map)[i][j].num_ch;
+	*ch_mask = (*map)[i][j].ch_mask;
+	*ch_rate = (*map)[i][j].ch_rate;
+	*port_type = (*map)[i][j].master_port_type;
+
+	return 0;
+}
+
+
+/* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
+			<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
+			<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
+			<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
+static int wcd939x_parse_port_params(struct device *dev,
+			char *prop, u8 path)
+{
+	u32 *dt_array, map_size, max_uc;
+	int ret = 0;
+	u32 cnt = 0;
+	u32 i, j;
+	struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
+	struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
+
+	switch (path) {
+	case CODEC_TX:
+		map = &wcd939x->tx_port_params;
+		map_uc = &wcd939x->swr_tx_port_params;
+		break;
+	default:
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+
+	if (!of_find_property(dev->of_node, prop,
+				&map_size)) {
+		dev_err(dev, "missing port mapping prop %s\n", prop);
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+
+	max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
+
+	if (max_uc != SWR_UC_MAX) {
+		dev_err(dev, "%s: port params not provided for all usecases\n",
+			__func__);
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+	dt_array = kzalloc(map_size, GFP_KERNEL);
+
+	if (!dt_array) {
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+	ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
+				SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
+	if (ret) {
+		dev_err(dev, "%s: Failed to read  port mapping from prop %s\n",
+					__func__, prop);
+		goto err_pdata_fail;
+	}
+
+	for (i = 0; i < max_uc; i++) {
+		for (j = 0; j < SWR_NUM_PORTS; j++) {
+			cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
+			(*map)[i][j].offset1 = dt_array[cnt];
+			(*map)[i][j].lane_ctrl = dt_array[cnt + 1];
+		}
+		(*map_uc)[i].pp = &(*map)[i][0];
+	}
+	kfree(dt_array);
+	return 0;
+
+err_pdata_fail:
+	kfree(dt_array);
+err_alloc:
+err_port_map:
+	return ret;
+}
+
+static int wcd939x_parse_port_mapping(struct device *dev,
+			char *prop, u8 path)
+{
+	u32 *dt_array, map_size, map_length;
+	u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
+	u32 slave_port_type, master_port_type;
+	u32 i, ch_iter = 0;
+	int ret = 0;
+	u8 *num_ports = NULL;
+	struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
+
+	switch (path) {
+	case CODEC_RX:
+		map = &wcd939x->rx_port_mapping;
+		num_ports = &wcd939x->num_rx_ports;
+		break;
+	case CODEC_TX:
+		map = &wcd939x->tx_port_mapping;
+		num_ports = &wcd939x->num_tx_ports;
+		break;
+	default:
+		dev_err(dev, "%s Invalid path selected %u\n",
+			      __func__, path);
+		return -EINVAL;
+	}
+
+	if (!of_find_property(dev->of_node, prop,
+				&map_size)) {
+		dev_err(dev, "missing port mapping prop %s\n", prop);
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+
+	map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
+
+	dt_array = kzalloc(map_size, GFP_KERNEL);
+
+	if (!dt_array) {
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+	ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
+				NUM_SWRS_DT_PARAMS * map_length);
+	if (ret) {
+		dev_err(dev, "%s: Failed to read  port mapping from prop %s\n",
+					__func__, prop);
+		goto err_pdata_fail;
+	}
+
+	for (i = 0; i < map_length; i++) {
+		port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
+		slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
+		ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
+		ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
+		master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
+
+		if (port_num != old_port_num)
+			ch_iter = 0;
+
+		(*map)[port_num][ch_iter].slave_port_type = slave_port_type;
+		(*map)[port_num][ch_iter].ch_mask = ch_mask;
+		(*map)[port_num][ch_iter].master_port_type = master_port_type;
+		(*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
+		(*map)[port_num][ch_iter++].ch_rate = ch_rate;
+		old_port_num = port_num;
+	}
+	*num_ports = port_num;
+	kfree(dt_array);
+	return 0;
+
+err_pdata_fail:
+	kfree(dt_array);
+err_alloc:
+err_port_map:
+	return ret;
+}
+
+static int wcd939x_tx_connect_port(struct snd_soc_component *component,
+					u8 slv_port_type, int clk_rate,
+					u8 enable)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	u8 port_id, num_ch, ch_mask;
+	u8 ch_type = 0;
+	u32 ch_rate;
+	int slave_ch_idx;
+	u8 num_port = 1;
+	int ret = 0;
+
+	ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
+				&num_ch, &ch_mask, &ch_rate,
+				&ch_type, CODEC_TX);
+	if (ret)
+		return ret;
+
+	if (clk_rate)
+		ch_rate = clk_rate;
+
+	slave_ch_idx = wcd939x_slave_get_slave_ch_val(slv_port_type);
+	if (slave_ch_idx != -EINVAL)
+		ch_type = wcd939x->tx_master_ch_map[slave_ch_idx];
+
+	dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
+		__func__, slave_ch_idx, ch_type);
+
+	if (enable)
+		ret = swr_connect_port(wcd939x->tx_swr_dev, &port_id,
+					num_port, &ch_mask, &ch_rate,
+					 &num_ch, &ch_type);
+	else
+		ret = swr_disconnect_port(wcd939x->tx_swr_dev, &port_id,
+					num_port, &ch_mask, &ch_type);
+	return ret;
+
+}
+static int wcd939x_rx_connect_port(struct snd_soc_component *component,
+					u8 slv_port_type, u8 enable)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	u8 port_id, num_ch, ch_mask, port_type;
+	u32 ch_rate;
+	u8 num_port = 1;
+	int ret = 0;
+
+	ret = wcd939x_set_port_params(component, slv_port_type, &port_id,
+				&num_ch, &ch_mask, &ch_rate,
+				&port_type, CODEC_RX);
+
+	if (ret)
+		return ret;
+
+	if (enable)
+		ret = swr_connect_port(wcd939x->rx_swr_dev, &port_id,
+					num_port, &ch_mask, &ch_rate,
+					&num_ch, &port_type);
+	else
+		ret = swr_disconnect_port(wcd939x->rx_swr_dev, &port_id,
+					num_port, &ch_mask, &port_type);
+	return ret;
+}
+
+static int wcd939x_rx_clk_enable(struct snd_soc_component *component)
+{
+
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	if (wcd939x->rx_clk_cnt == 0) {
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_RX0_CTL, DEM_DITHER_ENABLE, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_RX1_CTL, DEM_DITHER_ENABLE, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_RX2_CTL, DEM_DITHER_ENABLE, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x01));
+	}
+	wcd939x->rx_clk_cnt++;
+
+	return 0;
+}
+
+static int wcd939x_rx_clk_disable(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	wcd939x->rx_clk_cnt--;
+	if (wcd939x->rx_clk_cnt == 0) {
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RX_SUPPLIES, VNEG_EN, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RX_SUPPLIES, VPOS_EN, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RX_SUPPLIES, RX_BIAS_ENABLE, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_DIV2_CLK_EN, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_RX_CLK_EN, 0x00));
+	}
+	return 0;
+}
+
+/*
+ * wcd939x_soc_get_mbhc: get wcd939x_mbhc handle of corresponding component
+ * @component: handle to snd_soc_component *
+ *
+ * return wcd939x_mbhc handle or error code in case of failure
+ */
+struct wcd939x_mbhc *wcd939x_soc_get_mbhc(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x;
+
+	if (!component) {
+		pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
+		return NULL;
+	}
+	wcd939x = snd_soc_component_get_drvdata(component);
+
+	if (!wcd939x) {
+		pr_err_ratelimited("%s: wcd939x is NULL\n", __func__);
+		return NULL;
+	}
+
+	return wcd939x->mbhc;
+}
+EXPORT_SYMBOL(wcd939x_soc_get_mbhc);
+
+static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_rx_clk_enable(component);
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHL_RX_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RDAC_HD2_CTL_L, HD2_RES_DIV_CTL_L, 0x0f));
+		if (wcd939x->comp1_enable) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
+
+			/* 5msec compander delay as per HW requirement */
+			if (!wcd939x->comp2_enable ||
+				(snd_soc_component_read(component,
+					WCD939X_CDC_COMP_CTL_0) & 0x01))
+			usleep_range(5000, 5010);
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
+		} else {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x00));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(L_EN, GAIN_SOURCE_SEL, 0x01));
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		snd_soc_component_update_bits(component,
+			REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x01));
+		break;
+	}
+
+	return 0;
+}
+
+static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_rx_clk_enable(component);
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_HPH_GAIN_CTL, HPHR_RX_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RDAC_CLK_CTL1, OPAMP_CHOP_CLK_EN, 0x00));
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x02));
+		if (wcd939x->comp2_enable) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x01));
+			/* 5msec compander delay as per HW requirement */
+			if (!wcd939x->comp1_enable ||
+				(snd_soc_component_read(component,
+					WCD939X_CDC_COMP_CTL_0) & 0x02))
+				usleep_range(5000, 5010);
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x00));
+		} else {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHR_COMP_EN, 0x00));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(R_EN, GAIN_SOURCE_SEL, 0x01));
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		snd_soc_component_update_bits(component,
+			REG_FIELD_VALUE(RDAC_HD2_CTL_R, HD2_RES_DIV_CTL_R, 0x01));
+		break;
+	}
+
+	return 0;
+}
+
+static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_rx_clk_enable(component);
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_EAR_GAIN_CTL, EAR_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x01));
+		if (wcd939x->comp1_enable)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
+
+		/* 5 msec delay as per HW requirement */
+		usleep_range(5000, 5010);
+		if (wcd939x->flyback_cur_det_disable == 0)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(EN, EN_CUR_DET, 0x00));
+
+		wcd939x->flyback_cur_det_disable++;
+		wcd_cls_h_fsm(component, &wcd939x->clsh_info,
+			     WCD_CLSH_EVENT_PRE_DAC,
+			     WCD_CLSH_STATE_EAR,
+			     wcd939x->hph_mode);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x00));
+		if (wcd939x->comp1_enable)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_COMP_CTL_0, HPHL_COMP_EN, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(EAR_DAC_CON, DAC_SAMPLE_EDGE_SEL, 0x01));
+		break;
+	};
+	return 0;
+
+}
+
+static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int ret = 0;
+	int hph_mode = wcd939x->hph_mode;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (wcd939x->ldoh)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
+		if (wcd939x->update_wcd_event)
+			wcd939x->update_wcd_event(wcd939x->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX2 << 0x10 | 0x1));
+		ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
+				    wcd939x->rx_swr_dev->dev_num,
+				    true);
+		wcd_cls_h_fsm(component, &wcd939x->clsh_info,
+			     WCD_CLSH_EVENT_PRE_DAC,
+			     WCD_CLSH_STATE_HPHR,
+			     hph_mode);
+		wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
+		if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
+		    hph_mode == CLS_H_ULP) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
+		}
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x01));
+		wcd_clsh_set_hph_mode(component, hph_mode);
+		/* 100 usec delay as per HW requirement */
+		usleep_range(100, 110);
+		set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x03));
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		/*
+		 * 7ms sleep is required if compander is enabled as per
+		 * HW requirement. If compander is disabled, then
+		 * 20ms delay is required.
+		 */
+		if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
+			if (!wcd939x->comp2_enable)
+				usleep_range(20000, 20100);
+			else
+				usleep_range(7000, 7100);
+			if (hph_mode == CLS_H_LP ||
+			    hph_mode == CLS_H_LOHIFI ||
+			    hph_mode == CLS_H_ULP)
+				snd_soc_component_update_bits(component,
+						REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
+			clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
+		}
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
+		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
+			hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
+		if (wcd939x->update_wcd_event)
+			wcd939x->update_wcd_event(wcd939x->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX2 << 0x10));
+		wcd_enable_irq(&wcd939x->irq_info,
+					WCD939X_IRQ_HPHR_PDM_WD_INT);
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		if (wcd939x->update_wcd_event)
+			wcd939x->update_wcd_event(wcd939x->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX2 << 0x10 | 0x1));
+		wcd_disable_irq(&wcd939x->irq_info,
+					WCD939X_IRQ_HPHR_PDM_WD_INT);
+		if (wcd939x->update_wcd_event && wcd939x->comp2_enable)
+			wcd939x->update_wcd_event(wcd939x->handle,
+					SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
+					(WCD_RX2 << 0x10));
+		/*
+		 * 7ms sleep is required if compander is enabled as per
+		 * HW requirement. If compander is disabled, then
+		 * 20ms delay is required.
+		 */
+		if (!wcd939x->comp2_enable)
+			usleep_range(20000, 20100);
+		else
+			usleep_range(7000, 7100);
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH, HPHR_ENABLE, 0x00));
+
+		blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
+					     WCD_EVENT_PRE_HPHR_PA_OFF,
+					     &wcd939x->mbhc->wcd_mbhc);
+		set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/*
+		 * 7ms sleep is required if compander is enabled as per
+		 * HW requirement. If compander is disabled, then
+		 * 20ms delay is required.
+		 */
+		if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
+			if (!wcd939x->comp2_enable)
+				usleep_range(20000, 20100);
+			else
+				usleep_range(7000, 7100);
+			clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
+		}
+		blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
+					     WCD_EVENT_POST_HPHR_PA_OFF,
+					     &wcd939x->mbhc->wcd_mbhc);
+
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH, HPHR_REF_ENABLE, 0x00));
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(PDM_WD_CTL1, PDM_WD_EN, 0x00));
+		wcd_cls_h_fsm(component, &wcd939x->clsh_info,
+			     WCD_CLSH_EVENT_POST_PA,
+			     WCD_CLSH_STATE_HPHR,
+			     hph_mode);
+		if (wcd939x->ldoh)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
+		break;
+	};
+	return ret;
+}
+
+static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int ret = 0;
+	int hph_mode = wcd939x->hph_mode;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (wcd939x->ldoh)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(MODE, LDOH_EN, 0x01));
+		if (wcd939x->update_wcd_event)
+			wcd939x->update_wcd_event(wcd939x->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10 | 0x01));
+		ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
+				    wcd939x->rx_swr_dev->dev_num,
+				    true);
+		wcd_cls_h_fsm(component, &wcd939x->clsh_info,
+			     WCD_CLSH_EVENT_PRE_DAC,
+			     WCD_CLSH_STATE_HPHL,
+			     hph_mode);
+		wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
+		if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
+		    hph_mode == CLS_H_ULP) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x01));
+		}
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x01));
+		wcd_clsh_set_hph_mode(component, hph_mode);
+		/* 100 usec delay as per HW requirement */
+		usleep_range(100, 110);
+		set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		/*
+		 * 7ms sleep is required if compander is enabled as per
+		 * HW requirement. If compander is disabled, then
+		 * 20ms delay is required.
+		 */
+		if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
+			if (!wcd939x->comp1_enable)
+				usleep_range(20000, 20100);
+			else
+				usleep_range(7000, 7100);
+			if (hph_mode == CLS_H_LP ||
+			    hph_mode == CLS_H_LOHIFI ||
+			    hph_mode == CLS_H_ULP)
+				snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(REFBUFF_LP_CTL, PREREF_FILT_BYPASS, 0x00));
+			clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
+		}
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH_TIMER1, AUTOCHOP_TIMER_CTL_EN, 0x01));
+		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
+			hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
+		if (wcd939x->update_wcd_event)
+			wcd939x->update_wcd_event(wcd939x->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10));
+		wcd_enable_irq(&wcd939x->irq_info,
+					WCD939X_IRQ_HPHL_PDM_WD_INT);
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		if (wcd939x->update_wcd_event)
+			wcd939x->update_wcd_event(wcd939x->handle,
+						SLV_BOLERO_EVT_RX_MUTE,
+						(WCD_RX1 << 0x10 | 0x1));
+		wcd_disable_irq(&wcd939x->irq_info,
+					WCD939X_IRQ_HPHL_PDM_WD_INT);
+		if (wcd939x->update_wcd_event && wcd939x->comp1_enable)
+			wcd939x->update_wcd_event(wcd939x->handle,
+					SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
+					(WCD_RX1 << 0x10));
+		/*
+		 * 7ms sleep is required if compander is enabled as per
+		 * HW requirement. If compander is disabled, then
+		 * 20ms delay is required.
+		 */
+		if (!wcd939x->comp1_enable)
+			usleep_range(20000, 20100);
+		else
+			usleep_range(7000, 7100);
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
+		blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
+					     WCD_EVENT_PRE_HPHL_PA_OFF,
+					     &wcd939x->mbhc->wcd_mbhc);
+		set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/*
+		 * 7ms sleep is required if compander is enabled as per
+		 * HW requirement. If compander is disabled, then
+		 * 20ms delay is required.
+		 */
+		if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
+			if (!wcd939x->comp1_enable)
+				usleep_range(21000, 21100);
+			else
+				usleep_range(7000, 7100);
+			clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
+		}
+		blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
+					     WCD_EVENT_POST_HPHL_PA_OFF,
+					     &wcd939x->mbhc->wcd_mbhc);
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH, HPHL_REF_ENABLE, 0x00));
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
+
+		wcd_cls_h_fsm(component, &wcd939x->clsh_info,
+			     WCD_CLSH_EVENT_POST_PA,
+			     WCD_CLSH_STATE_HPHL,
+			     hph_mode);
+		if (wcd939x->ldoh)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(MODE, LDOH_EN, 0x00));
+
+		break;
+	};
+	return ret;
+}
+
+static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
+				       struct snd_kcontrol *kcontrol,
+				       int event)
+{
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int hph_mode = wcd939x->hph_mode;
+	int ret = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		ret = swr_slvdev_datapath_control(wcd939x->rx_swr_dev,
+			    wcd939x->rx_swr_dev->dev_num,
+			    true);
+		/*
+		 * Enable watchdog interrupt for HPHL
+		 */
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x03));
+		if (!wcd939x->comp1_enable)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x01));
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		/* 6 msec delay as per HW requirement */
+		usleep_range(6000, 6010);
+		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
+			hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(RX_SUPPLIES, REGULATOR_MODE, 0x01));
+		if (wcd939x->update_wcd_event)
+			wcd939x->update_wcd_event(wcd939x->handle,
+					SLV_BOLERO_EVT_RX_MUTE,
+					(WCD_RX1 << 0x10));
+		wcd_enable_irq(&wcd939x->irq_info,
+				WCD939X_IRQ_EAR_PDM_WD_INT);
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		wcd_disable_irq(&wcd939x->irq_info,
+				WCD939X_IRQ_EAR_PDM_WD_INT);
+		if (wcd939x->update_wcd_event)
+			wcd939x->update_wcd_event(wcd939x->handle,
+					SLV_BOLERO_EVT_RX_MUTE,
+					(WCD_RX1 << 0x10 | 0x1));
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (!wcd939x->comp1_enable)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(EAR_COMPANDER_CTL, GAIN_OVRD_REG, 0x00));
+		/* 7 msec delay as per HW requirement */
+		usleep_range(7000, 7010);
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(PDM_WD_CTL0, PDM_WD_EN, 0x00));
+		wcd_cls_h_fsm(component, &wcd939x->clsh_info,
+			     WCD_CLSH_EVENT_POST_PA,
+			     WCD_CLSH_STATE_EAR,
+			     hph_mode);
+
+		wcd939x->flyback_cur_det_disable--;
+		if (wcd939x->flyback_cur_det_disable == 0)
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(EN, EN_CUR_DET, 0x01));
+		break;
+	};
+	return ret;
+}
+
+static int wcd939x_enable_clsh(struct snd_soc_dapm_widget *w,
+			       struct snd_kcontrol *kcontrol,
+			       int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int mode = wcd939x->hph_mode;
+	int ret = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
+		mode == CLS_H_HIFI || mode == CLS_H_LP) {
+		wcd939x_rx_connect_port(component, CLSH,
+				SND_SOC_DAPM_EVENT_ON(event));
+	}
+	if (SND_SOC_DAPM_EVENT_OFF(event))
+		ret = swr_slvdev_datapath_control(
+				wcd939x->rx_swr_dev,
+				wcd939x->rx_swr_dev->dev_num,
+				false);
+	return ret;
+}
+
+static int wcd939x_enable_rx1(struct snd_soc_dapm_widget *w,
+			      struct snd_kcontrol *kcontrol,
+			      int event)
+{
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_rx_connect_port(component, HPH_L, true);
+		if (wcd939x->comp1_enable)
+			wcd939x_rx_connect_port(component, COMP_L, true);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x_rx_connect_port(component, HPH_L, false);
+		if (wcd939x->comp1_enable)
+			wcd939x_rx_connect_port(component, COMP_L, false);
+		wcd939x_rx_clk_disable(component);
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD0_CLK_EN, 0x00));
+		break;
+	};
+
+	return 0;
+}
+
+static int wcd939x_enable_rx2(struct snd_soc_dapm_widget *w,
+			      struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_rx_connect_port(component, HPH_R, true);
+		if (wcd939x->comp2_enable)
+			wcd939x_rx_connect_port(component, COMP_R, true);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x_rx_connect_port(component, HPH_R, false);
+		if (wcd939x->comp2_enable)
+			wcd939x_rx_connect_port(component, COMP_R, false);
+		wcd939x_rx_clk_disable(component);
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD1_CLK_EN, 0x00));
+		break;
+	};
+
+	return 0;
+}
+
+static int wcd939x_enable_rx3(struct snd_soc_dapm_widget *w,
+			      struct snd_kcontrol *kcontrol,
+			      int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_rx_connect_port(component, LO, true);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x_rx_connect_port(component, LO, false);
+		/* 6 msec delay as per HW requirement */
+		usleep_range(6000, 6010);
+		wcd939x_rx_clk_disable(component);
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, RXD2_CLK_EN, 0x00));
+		break;
+	}
+
+	return 0;
+}
+
+static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
+				     struct snd_kcontrol *kcontrol,
+				     int event)
+{
+	struct snd_soc_component *component =
+				snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	u16 dmic_clk_reg, dmic_clk_en_reg;
+	s32 *dmic_clk_cnt;
+	u8 dmic_ctl_shift = 0;
+	u8 dmic_clk_shift = 0;
+	u8 dmic_clk_mask = 0;
+	u16 dmic2_left_en = 0;
+	int ret = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (w->shift) {
+	case 0:
+	case 1:
+		dmic_clk_cnt = &(wcd939x->dmic_0_1_clk_cnt);
+		dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
+		dmic_clk_en_reg = WCD939X_CDC_DMIC1_CTL;
+		dmic_clk_mask = 0x0F;
+		dmic_clk_shift = 0x00;
+		dmic_ctl_shift = 0x00;
+		break;
+	case 2:
+		dmic2_left_en = WCD939X_CDC_DMIC2_CTL;
+		fallthrough;
+	case 3:
+		dmic_clk_cnt = &(wcd939x->dmic_2_3_clk_cnt);
+		dmic_clk_reg = WCD939X_CDC_DMIC_RATE_1_2;
+		dmic_clk_en_reg = WCD939X_CDC_DMIC2_CTL;
+		dmic_clk_mask = 0xF0;
+		dmic_clk_shift = 0x04;
+		dmic_ctl_shift = 0x01;
+		break;
+	case 4:
+	case 5:
+		dmic_clk_cnt = &(wcd939x->dmic_4_5_clk_cnt);
+		dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
+		dmic_clk_en_reg = WCD939X_CDC_DMIC3_CTL;
+		dmic_clk_mask = 0x0F;
+		dmic_clk_shift = 0x00;
+		dmic_ctl_shift = 0x02;
+		break;
+	case 6:
+	case 7:
+		dmic_clk_cnt = &(wcd939x->dmic_6_7_clk_cnt);
+		dmic_clk_reg = WCD939X_CDC_DMIC_RATE_3_4;
+		dmic_clk_en_reg = WCD939X_CDC_DMIC4_CTL;
+		dmic_clk_mask = 0xF0;
+		dmic_clk_shift = 0x04;
+		dmic_ctl_shift = 0x03;
+		break;
+	default:
+		dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
+			__func__);
+		return -EINVAL;
+	};
+	dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
+			__func__, event,  (w->shift +1), *dmic_clk_cnt);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_component_update_bits(component,
+				WCD939X_CDC_AMIC_CTL,
+				(0x01 << dmic_ctl_shift), 0x00);
+		/* 250us sleep as per HW requirement */
+		usleep_range(250, 260);
+		if (dmic2_left_en)
+			snd_soc_component_update_bits(component,
+				dmic2_left_en, 0x80, 0x80);
+		/* Setting DMIC clock rate to 2.4MHz */
+		snd_soc_component_update_bits(component,
+					      dmic_clk_reg, dmic_clk_mask,
+					      (0x03 << dmic_clk_shift));
+		snd_soc_component_update_bits(component,
+					      dmic_clk_en_reg, 0x08, 0x08);
+		/* enable clock scaling */
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DMIC_CTL, CLK_SCALE_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DMIC_CTL, DMIC_DIV_BAK_EN, 0x01));
+		ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
+				wcd939x->tx_swr_dev->dev_num,
+				true);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x_tx_connect_port(component, DMIC0 + (w->shift), 0,
+				false);
+		snd_soc_component_update_bits(component,
+				WCD939X_CDC_AMIC_CTL,
+				(0x01 << dmic_ctl_shift),
+				(0x01 << dmic_ctl_shift));
+		if (dmic2_left_en)
+			snd_soc_component_update_bits(component,
+				dmic2_left_en, 0x80, 0x00);
+		snd_soc_component_update_bits(component,
+					      dmic_clk_en_reg, 0x08, 0x00);
+		break;
+	};
+	return ret;
+}
+
+/*
+ * wcd939x_get_micb_vout_ctl_val: converts micbias from volts to register value
+ * @micb_mv: micbias in mv
+ *
+ * return register value converted
+ */
+int wcd939x_get_micb_vout_ctl_val(u32 micb_mv)
+{
+	/* min micbias voltage is 1V and maximum is 2.85V */
+	if (micb_mv < 1000 || micb_mv > 2850) {
+		pr_err_ratelimited("%s: unsupported micbias voltage\n", __func__);
+		return -EINVAL;
+	}
+
+	return (micb_mv - 1000) / 50;
+}
+EXPORT_SYMBOL(wcd939x_get_micb_vout_ctl_val);
+
+/*
+ * wcd939x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
+ * @component: handle to snd_soc_component *
+ * @req_volt: micbias voltage to be set
+ * @micb_num: micbias to be set, e.g. micbias1 or micbias2
+ *
+ * return 0 if adjustment is success or error code in case of failure
+ */
+int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
+				   int req_volt, int micb_num)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int cur_vout_ctl, req_vout_ctl;
+	int micb_reg, micb_val, micb_en;
+	int ret = 0;
+
+	switch (micb_num) {
+	case MIC_BIAS_1:
+		micb_reg = WCD939X_MICB1;
+		break;
+	case MIC_BIAS_2:
+		micb_reg = WCD939X_MICB2;
+		break;
+	case MIC_BIAS_3:
+		micb_reg = WCD939X_MICB3;
+		break;
+	case MIC_BIAS_4:
+		micb_reg = WCD939X_MICB4;
+		break;
+	default:
+		return -EINVAL;
+	}
+	mutex_lock(&wcd939x->micb_lock);
+
+	/*
+	 * If requested micbias voltage is same as current micbias
+	 * voltage, then just return. Otherwise, adjust voltage as
+	 * per requested value. If micbias is already enabled, then
+	 * to avoid slow micbias ramp-up or down enable pull-up
+	 * momentarily, change the micbias value and then re-enable
+	 * micbias.
+	 */
+	micb_val = snd_soc_component_read(component, micb_reg);
+	micb_en = (micb_val & 0xC0) >> 6;
+	cur_vout_ctl = micb_val & 0x3F;
+
+	req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt);
+	if (req_vout_ctl < 0) {
+		ret = -EINVAL;
+		goto exit;
+	}
+	if (cur_vout_ctl == req_vout_ctl) {
+		ret = 0;
+		goto exit;
+	}
+
+	dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
+		 __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
+		 req_volt, micb_en);
+
+	if (micb_en == 0x1)
+		snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
+
+	snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
+
+	if (micb_en == 0x1) {
+		snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
+		/*
+		 * Add 2ms delay as per HW requirement after enabling
+		 * micbias
+		 */
+		usleep_range(2000, 2100);
+	}
+exit:
+	mutex_unlock(&wcd939x->micb_lock);
+	return ret;
+}
+EXPORT_SYMBOL(wcd939x_mbhc_micb_adjust_voltage);
+
+static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
+				    struct snd_kcontrol *kcontrol,
+				    int event)
+{
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int ret = 0;
+	int bank = 0;
+	u8 mode = 0;
+	int i = 0;
+	int rate = 0;
+
+	bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
+					wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
+
+	/* power mode is applicable only to analog mics */
+	if (strnstr(w->name, "ADC", sizeof("ADC"))) {
+		/* Get channel rate */
+		rate = wcd939x_get_clk_rate(wcd939x->tx_mode[w->shift - ADC1]);
+	}
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		/* Check AMIC2 is connected to ADC2 to take an action on BCS */
+		if (w->shift == ADC2 &&
+			(((snd_soc_component_read(component, WCD939X_TX_CH12_MUX) &
+				   0x38) >> 3)  == 0x2)) {
+			if (!wcd939x->bcs_dis) {
+				wcd939x_tx_connect_port(component, MBHC,
+					SWR_CLK_RATE_4P8MHZ, true);
+				set_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
+			}
+		}
+		if (strnstr(w->name, "ADC", sizeof("ADC"))) {
+			set_bit(w->shift - ADC1, &wcd939x->status_mask);
+			wcd939x_tx_connect_port(component, w->shift, rate,
+					true);
+		} else {
+			wcd939x_tx_connect_port(component, w->shift,
+					SWR_CLK_RATE_2P4MHZ, true);
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		if (strnstr(w->name, "ADC", sizeof("ADC"))) {
+			if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
+				clear_bit(WCD_ADC1, &wcd939x->status_mask);
+				clear_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
+			} else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
+				clear_bit(WCD_ADC2, &wcd939x->status_mask);
+				clear_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
+			} else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
+				clear_bit(WCD_ADC3, &wcd939x->status_mask);
+				clear_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
+			} else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
+				clear_bit(WCD_ADC4, &wcd939x->status_mask);
+				clear_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
+			}
+		}
+		if (strnstr(w->name, "ADC", sizeof("ADC"))) {
+			if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
+				test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
+				mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
+			if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
+				test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
+				mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
+			if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
+				test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
+				mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
+			if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
+				test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
+				mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
+
+			if (mode != 0) {
+				for (i = 0; i < ADC_MODE_ULP2; i++) {
+					if (mode & (1 << i)) {
+						i++;
+						break;
+					}
+				}
+			}
+			rate = wcd939x_get_clk_rate(i);
+			if (wcd939x->adc_count) {
+				rate =  (wcd939x->adc_count * rate);
+				if (rate > SWR_CLK_RATE_9P6MHZ)
+					rate = SWR_CLK_RATE_9P6MHZ;
+			}
+			wcd939x_set_swr_clk_rate(component, rate, bank);
+		}
+		ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
+				wcd939x->tx_swr_dev->dev_num,
+				false);
+
+		if (strnstr(w->name, "ADC", sizeof("ADC")))
+			wcd939x_set_swr_clk_rate(component, rate, !bank);
+		break;
+	};
+
+	return ret;
+}
+
+static int wcd939x_get_adc_mode(int val)
+{
+	int ret = 0;
+
+	switch (val) {
+	case ADC_MODE_INVALID:
+		ret = ADC_MODE_VAL_NORMAL;
+		break;
+	case ADC_MODE_HIFI:
+		ret = ADC_MODE_VAL_HIFI;
+		break;
+	case ADC_MODE_LO_HIF:
+		ret = ADC_MODE_VAL_LO_HIF;
+		break;
+	case ADC_MODE_NORMAL:
+		ret = ADC_MODE_VAL_NORMAL;
+		break;
+	case ADC_MODE_LP:
+		ret = ADC_MODE_VAL_LP;
+		break;
+	case ADC_MODE_ULP1:
+		ret = ADC_MODE_VAL_ULP1;
+		break;
+	case ADC_MODE_ULP2:
+		ret = ADC_MODE_VAL_ULP2;
+		break;
+	default:
+		ret = -EINVAL;
+		pr_err_ratelimited("%s: invalid ADC mode value %d\n", __func__, val);
+		break;
+	}
+	return ret;
+}
+
+int wcd939x_tx_channel_config(struct snd_soc_component *component,
+			      int channel, int mode)
+{
+	int reg = WCD939X_TX_CH2, mask = 0, val = 0;
+	int ret = 0;
+
+	switch (channel) {
+	case 0:
+		reg = WCD939X_TX_CH2;
+		mask = 0x40;
+		break;
+	case 1:
+		reg = WCD939X_TX_CH2;
+		mask = 0x20;
+		break;
+	case 2:
+		reg = WCD939X_TX_CH4;
+		mask = 0x40;
+		break;
+	case 3:
+		reg = WCD939X_TX_CH4;
+		mask = 0x20;
+		break;
+	default:
+		pr_err_ratelimited("%s: Invalid channel num %d\n", __func__, channel);
+		ret = -EINVAL;
+		break;
+	}
+
+	if (!mode)
+		val = 0x00;
+	else
+		val = mask;
+
+	if (!ret)
+		snd_soc_component_update_bits(component, reg, mask, val);
+
+	return ret;
+}
+
+static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
+				    struct snd_kcontrol *kcontrol,
+				    int event){
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int clk_rate = 0, ret = 0;
+	int mode = 0, i = 0, bank = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+	bank = (wcd939x_swr_slv_get_current_bank(wcd939x->tx_swr_dev,
+		wcd939x->tx_swr_dev->dev_num) ? 0 : 1);
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x->adc_count++;
+		if (test_bit(WCD_ADC1, &wcd939x->status_mask) ||
+			test_bit(WCD_ADC1_MODE, &wcd939x->status_mask))
+			mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
+		if (test_bit(WCD_ADC2, &wcd939x->status_mask) ||
+			test_bit(WCD_ADC2_MODE, &wcd939x->status_mask))
+			mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
+		if (test_bit(WCD_ADC3, &wcd939x->status_mask) ||
+			test_bit(WCD_ADC3_MODE, &wcd939x->status_mask))
+			mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
+		if (test_bit(WCD_ADC4, &wcd939x->status_mask) ||
+			test_bit(WCD_ADC4_MODE, &wcd939x->status_mask))
+			mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
+
+		if (mode != 0) {
+			for (i = 0; i < ADC_MODE_ULP2; i++) {
+				if (mode & (1 << i)) {
+					i++;
+					break;
+				}
+			}
+		}
+		clk_rate = wcd939x_get_clk_rate(i);
+
+		/* clk_rate depends on number of paths getting enabled */
+		clk_rate =  (wcd939x->adc_count * clk_rate);
+		if (clk_rate > SWR_CLK_RATE_9P6MHZ)
+			clk_rate = SWR_CLK_RATE_9P6MHZ;
+		wcd939x_set_swr_clk_rate(component, clk_rate, bank);
+		ret = swr_slvdev_datapath_control(wcd939x->tx_swr_dev,
+				 wcd939x->tx_swr_dev->dev_num,
+				 true);
+		wcd939x_set_swr_clk_rate(component, clk_rate, !bank);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x->adc_count--;
+		if (wcd939x->adc_count < 0)
+			wcd939x->adc_count = 0;
+
+		wcd939x_tx_connect_port(component, ADC1 + w->shift, 0, false);
+		if (w->shift + ADC1 == ADC2 &&
+			test_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask)) {
+			wcd939x_tx_connect_port(component, MBHC, 0,
+					false);
+			clear_bit(AMIC2_BCS_ENABLE, &wcd939x->status_mask);
+		}
+		break;
+	};
+
+	return ret;
+}
+
+void wcd939x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
+					    bool bcs_disable)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	if (wcd939x->update_wcd_event) {
+		if (bcs_disable)
+			wcd939x->update_wcd_event(wcd939x->handle,
+						SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
+		else
+			wcd939x->update_wcd_event(wcd939x->handle,
+						SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
+	}
+}
+
+static int wcd939x_enable_req(struct snd_soc_dapm_widget *w,
+			      struct snd_kcontrol *kcontrol, int event)
+{
+	struct snd_soc_component *component =
+					snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x =
+					snd_soc_component_get_drvdata(component);
+	int ret = 0;
+	u8 mode = 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_REQ_CTL, FS_RATE_4P8, 0x01));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_REQ_CTL, NO_NOTCH, 0x00));
+
+		ret = wcd939x_tx_channel_config(component, w->shift, 1);
+		mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
+		if (mode < 0) {
+			dev_info_ratelimited(component->dev,
+				 "%s: invalid mode, setting to normal mode\n",
+				 __func__);
+			mode = ADC_MODE_VAL_NORMAL;
+		}
+		switch (w->shift) {
+		case 0:
+			snd_soc_component_update_bits(component,
+				WCD939X_CDC_TX_ANA_MODE_0_1, 0x0F,
+				mode);
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x01));
+			break;
+		case 1:
+			snd_soc_component_update_bits(component,
+				WCD939X_CDC_TX_ANA_MODE_0_1, 0xF0,
+				mode << 4);
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x01));
+			break;
+		case 2:
+			snd_soc_component_update_bits(component,
+				WCD939X_CDC_TX_ANA_MODE_2_3, 0x0F,
+				mode);
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x01));
+			break;
+		case 3:
+			snd_soc_component_update_bits(component,
+				WCD939X_CDC_TX_ANA_MODE_2_3, 0xF0,
+				mode << 4);
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x01));
+			break;
+		default:
+			break;
+		}
+		ret |= wcd939x_tx_channel_config(component, w->shift, 0);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		switch (w->shift) {
+		case 0:
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD0_MODE, 0x00));
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD0_CLK_EN, 0x00));
+			break;
+		case 1:
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_TX_ANA_MODE_0_1, TXD1_MODE, 0x00));
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD1_CLK_EN, 0x00));
+			break;
+		case 2:
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD2_MODE, 0x00));
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD2_CLK_EN, 0x00));
+			break;
+		case 3:
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_TX_ANA_MODE_2_3, TXD3_MODE, 0x00));
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(CDC_DIG_CLK_CTL, TXD3_CLK_EN, 0x00));
+			break;
+		default:
+			break;
+		}
+		if (wcd939x->adc_count == 0) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x00));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_CLK_EN, 0x00));
+		}
+		break;
+	};
+	return ret;
+}
+
+int wcd939x_micbias_control(struct snd_soc_component *component,
+				int micb_num, int req, bool is_dapm)
+{
+
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int micb_index = micb_num - 1;
+	u16 micb_reg;
+	int pre_off_event = 0, post_off_event = 0;
+	int post_on_event = 0, post_dapm_off = 0;
+	int post_dapm_on = 0;
+	int ret = 0;
+
+	if ((micb_index < 0) || (micb_index > WCD939X_MAX_MICBIAS - 1)) {
+		dev_err_ratelimited(component->dev,
+			"%s: Invalid micbias index, micb_ind:%d\n",
+			__func__, micb_index);
+		return -EINVAL;
+	}
+
+	if (NULL == wcd939x) {
+		dev_err_ratelimited(component->dev,
+			"%s: wcd939x private data is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	switch (micb_num) {
+	case MIC_BIAS_1:
+		micb_reg = WCD939X_MICB1;
+		break;
+	case MIC_BIAS_2:
+		micb_reg = WCD939X_MICB2;
+		pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
+		post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
+		post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
+		post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
+		post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
+		break;
+	case MIC_BIAS_3:
+		micb_reg = WCD939X_MICB3;
+		break;
+	case MIC_BIAS_4:
+		micb_reg = WCD939X_MICB4;
+		break;
+	default:
+		dev_err_ratelimited(component->dev, "%s: Invalid micbias number: %d\n",
+			__func__, micb_num);
+		return -EINVAL;
+	};
+	mutex_lock(&wcd939x->micb_lock);
+
+	switch (req) {
+	case MICB_PULLUP_ENABLE:
+		if (!wcd939x->dev_up) {
+			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
+				__func__, req);
+			ret = -ENODEV;
+			goto done;
+		}
+		wcd939x->pullup_ref[micb_index]++;
+		if ((wcd939x->pullup_ref[micb_index] == 1) &&
+		    (wcd939x->micb_ref[micb_index] == 0))
+			snd_soc_component_update_bits(component, micb_reg,
+							0xC0, 0x80);
+		break;
+	case MICB_PULLUP_DISABLE:
+		if (wcd939x->pullup_ref[micb_index] > 0)
+			wcd939x->pullup_ref[micb_index]--;
+		if (!wcd939x->dev_up) {
+			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
+				__func__, req);
+			ret = -ENODEV;
+			goto done;
+		}
+		if ((wcd939x->pullup_ref[micb_index] == 0) &&
+		    (wcd939x->micb_ref[micb_index] == 0))
+			snd_soc_component_update_bits(component, micb_reg,
+							0xC0, 0x00);
+		break;
+	case MICB_ENABLE:
+		if (!wcd939x->dev_up) {
+			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
+				__func__, req);
+			ret = -ENODEV;
+			goto done;
+		}
+		wcd939x->micb_ref[micb_index]++;
+		if (wcd939x->micb_ref[micb_index] == 1) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD3_CLK_EN, 0x01));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD2_CLK_EN, 0x01));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD1_CLK_EN, 0x01));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_DIG_CLK_CTL,TXD0_CLK_EN, 0x01));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_ANA_CLK_CTL, ANA_TX_DIV2_CLK_EN, 0x01));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(CDC_ANA_TX_CLK_CTL, ANA_TXSCBIAS_CLK_EN, 0x01));
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(MICB2_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(MICB3_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
+			snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(MICB4_TEST_CTL_2, IBIAS_LDO_DRIVER, 0x01));
+			snd_soc_component_update_bits(component,
+				micb_reg, 0xC0, 0x40);
+			if (post_on_event)
+				blocking_notifier_call_chain(
+						&wcd939x->mbhc->notifier,
+						post_on_event,
+						&wcd939x->mbhc->wcd_mbhc);
+		}
+		if (is_dapm && post_dapm_on && wcd939x->mbhc)
+			blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
+						     post_dapm_on,
+						     &wcd939x->mbhc->wcd_mbhc);
+		break;
+	case MICB_DISABLE:
+		if (wcd939x->micb_ref[micb_index] > 0)
+			wcd939x->micb_ref[micb_index]--;
+		if (!wcd939x->dev_up) {
+			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
+				__func__, req);
+			ret = -ENODEV;
+			goto done;
+		}
+		if ((wcd939x->micb_ref[micb_index] == 0) &&
+		    (wcd939x->pullup_ref[micb_index] > 0))
+			snd_soc_component_update_bits(component, micb_reg,
+							0xC0, 0x80);
+		else if ((wcd939x->micb_ref[micb_index] == 0) &&
+			 (wcd939x->pullup_ref[micb_index] == 0)) {
+			if (pre_off_event && wcd939x->mbhc)
+				blocking_notifier_call_chain(
+						&wcd939x->mbhc->notifier,
+						pre_off_event,
+						&wcd939x->mbhc->wcd_mbhc);
+			snd_soc_component_update_bits(component, micb_reg,
+							0xC0, 0x00);
+			if (post_off_event && wcd939x->mbhc)
+				blocking_notifier_call_chain(
+						&wcd939x->mbhc->notifier,
+						post_off_event,
+						&wcd939x->mbhc->wcd_mbhc);
+		}
+		if (is_dapm && post_dapm_off && wcd939x->mbhc)
+			blocking_notifier_call_chain(&wcd939x->mbhc->notifier,
+						post_dapm_off,
+						&wcd939x->mbhc->wcd_mbhc);
+		break;
+	};
+
+	dev_dbg(component->dev,
+		"%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
+		__func__, micb_num, wcd939x->micb_ref[micb_index],
+		wcd939x->pullup_ref[micb_index]);
+
+done:
+	mutex_unlock(&wcd939x->micb_lock);
+	return ret;
+}
+EXPORT_SYMBOL(wcd939x_micbias_control);
+
+static int wcd939x_get_logical_addr(struct swr_device *swr_dev)
+{
+	int ret = 0;
+	uint8_t devnum = 0;
+	int num_retry = NUM_ATTEMPTS;
+
+	do {
+		/* retry after 1ms */
+		usleep_range(1000, 1010);
+		ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
+	} while (ret && --num_retry);
+
+	if (ret)
+		dev_err_ratelimited(&swr_dev->dev,
+			"%s get devnum %d for dev addr %llx failed\n",
+			__func__, devnum, swr_dev->addr);
+
+	swr_dev->dev_num = devnum;
+	return 0;
+}
+
+static bool get_usbc_hs_status(struct snd_soc_component *component,
+			struct wcd_mbhc_config *mbhc_cfg)
+{
+	if (mbhc_cfg->enable_usbc_analog) {
+		if (!(snd_soc_component_read(component, WCD939X_MBHC_MECH)
+			& 0x20))
+			return true;
+	}
+	return false;
+}
+
+int wcd939x_swr_dmic_register_notifier(struct snd_soc_component *component,
+					struct notifier_block *nblock,
+					bool enable)
+{
+	struct wcd939x_priv *wcd939x_priv;
+	if(NULL == component) {
+		pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd939x_priv = snd_soc_component_get_drvdata(component);
+	wcd939x_priv->notify_swr_dmic = enable;
+	if (enable)
+		return blocking_notifier_chain_register(&wcd939x_priv->notifier,
+							nblock);
+	else
+		return blocking_notifier_chain_unregister(
+				&wcd939x_priv->notifier, nblock);
+}
+EXPORT_SYMBOL(wcd939x_swr_dmic_register_notifier);
+
+static int wcd939x_event_notify(struct notifier_block *block,
+				unsigned long val,
+				void *data)
+{
+	u16 event = (val & 0xffff);
+	int ret = 0;
+	struct wcd939x_priv *wcd939x = dev_get_drvdata((struct device *)data);
+	struct snd_soc_component *component = wcd939x->component;
+	struct wcd_mbhc *mbhc;
+
+	switch (event) {
+	case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
+		if (test_bit(WCD_ADC1, &wcd939x->status_mask)) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(TX_CH2, HPF1_INIT, 0x00));
+			set_bit(WCD_ADC1_MODE, &wcd939x->status_mask);
+			clear_bit(WCD_ADC1, &wcd939x->status_mask);
+		}
+		if (test_bit(WCD_ADC2, &wcd939x->status_mask)) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(TX_CH2, HPF2_INIT, 0x00));
+			set_bit(WCD_ADC2_MODE, &wcd939x->status_mask);
+			clear_bit(WCD_ADC2, &wcd939x->status_mask);
+		}
+		if (test_bit(WCD_ADC3, &wcd939x->status_mask)) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(TX_CH4, HPF3_INIT, 0x00));
+			set_bit(WCD_ADC3_MODE, &wcd939x->status_mask);
+			clear_bit(WCD_ADC3, &wcd939x->status_mask);
+		}
+		if (test_bit(WCD_ADC4, &wcd939x->status_mask)) {
+			snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(TX_CH4, HPF4_INIT, 0x00));
+			set_bit(WCD_ADC4_MODE, &wcd939x->status_mask);
+			clear_bit(WCD_ADC4, &wcd939x->status_mask);
+		}
+		break;
+	case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH, HPHL_ENABLE, 0x00));
+		snd_soc_component_update_bits(component,
+					REG_FIELD_VALUE(HPH, HPHR_ENABLE , 0x00));
+		snd_soc_component_update_bits(component,
+				REG_FIELD_VALUE(EAR, ENABLE, 0x00));
+		break;
+	case BOLERO_SLV_EVT_SSR_DOWN:
+		wcd939x->dev_up = false;
+		if(wcd939x->notify_swr_dmic)
+			blocking_notifier_call_chain(&wcd939x->notifier,
+						     WCD939X_EVT_SSR_DOWN,
+						     NULL);
+		wcd939x->mbhc->wcd_mbhc.deinit_in_progress = true;
+		mbhc = &wcd939x->mbhc->wcd_mbhc;
+		wcd939x->usbc_hs_status = get_usbc_hs_status(component,
+						mbhc->mbhc_cfg);
+		wcd939x_mbhc_ssr_down(wcd939x->mbhc, component);
+		wcd939x_reset_low(wcd939x->dev);
+		break;
+	case BOLERO_SLV_EVT_SSR_UP:
+		wcd939x_reset(wcd939x->dev);
+		/* allow reset to take effect */
+		usleep_range(10000, 10010);
+
+		wcd939x_get_logical_addr(wcd939x->tx_swr_dev);
+		wcd939x_get_logical_addr(wcd939x->rx_swr_dev);
+
+		wcd939x_init_reg(component);
+		regcache_mark_dirty(wcd939x->regmap);
+		regcache_sync(wcd939x->regmap);
+		/* Initialize MBHC module */
+		mbhc = &wcd939x->mbhc->wcd_mbhc;
+		ret = wcd939x_mbhc_post_ssr_init(wcd939x->mbhc, component);
+		if (ret) {
+			dev_err_ratelimited(component->dev, "%s: mbhc initialization failed\n",
+				__func__);
+		} else {
+			wcd939x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
+		}
+		wcd939x->mbhc->wcd_mbhc.deinit_in_progress = false;
+		wcd939x->dev_up = true;
+		if(wcd939x->notify_swr_dmic)
+			blocking_notifier_call_chain(&wcd939x->notifier,
+						     WCD939X_EVT_SSR_UP,
+						     NULL);
+		if (wcd939x->usbc_hs_status)
+			mdelay(500);
+		break;
+	case BOLERO_SLV_EVT_CLK_NOTIFY:
+		snd_soc_component_update_bits(component,
+				WCD939X_TOP_CLK_CFG, 0x06,
+				((val >> 0x10) << 0x01));
+		break;
+	default:
+		dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
+		break;
+	}
+	return 0;
+}
+
+static int __wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
+					  int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	int micb_num;
+
+	dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
+		__func__, w->name, event);
+
+	if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
+		micb_num = MIC_BIAS_1;
+	else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
+		micb_num = MIC_BIAS_2;
+	else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
+		micb_num = MIC_BIAS_3;
+	else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
+		micb_num = MIC_BIAS_4;
+	else
+		return -EINVAL;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_micbias_control(component, micb_num,
+						MICB_ENABLE, true);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		/* 1 msec delay as per HW requirement */
+		usleep_range(1000, 1100);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x_micbias_control(component, micb_num,
+						MICB_DISABLE, true);
+		break;
+	};
+
+	return 0;
+
+}
+
+static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
+					struct snd_kcontrol *kcontrol,
+					int event)
+{
+	return __wcd939x_codec_enable_micbias(w, event);
+}
+
+static int __wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
+						 int event)
+{
+	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	int micb_num;
+
+	dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
+		__func__, w->name, event);
+
+	if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
+		micb_num = MIC_BIAS_1;
+	else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
+		micb_num = MIC_BIAS_2;
+	else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
+		micb_num = MIC_BIAS_3;
+	else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
+		micb_num = MIC_BIAS_4;
+	else
+		return -EINVAL;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_micbias_control(component, micb_num,
+					MICB_PULLUP_ENABLE, true);
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		/* 1 msec delay as per HW requirement */
+		usleep_range(1000, 1100);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x_micbias_control(component, micb_num,
+					MICB_PULLUP_DISABLE, true);
+		break;
+	};
+
+	return 0;
+
+}
+
+static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
+					       struct snd_kcontrol *kcontrol,
+					       int event)
+{
+	return __wcd939x_codec_enable_micbias_pullup(w, event);
+}
+
+static int wcd939x_wakeup(void *handle, bool enable)
+{
+	struct wcd939x_priv *priv;
+	int ret = 0;
+
+	if (!handle) {
+		pr_err_ratelimited("%s: NULL handle\n", __func__);
+		return -EINVAL;
+	}
+	priv = (struct wcd939x_priv *)handle;
+	if (!priv->tx_swr_dev) {
+		pr_err_ratelimited("%s: tx swr dev is NULL\n", __func__);
+		return -EINVAL;
+	}
+	mutex_lock(&priv->wakeup_lock);
+	if (enable)
+		ret = swr_device_wakeup_vote(priv->tx_swr_dev);
+	else
+		ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
+	mutex_unlock(&priv->wakeup_lock);
+
+	return ret;
+}
+
+static int wcd939x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
+					    struct snd_kcontrol *kcontrol,
+					    int event)
+{
+	int ret = 0;
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_wakeup(wcd939x, true);
+		ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
+		wcd939x_wakeup(wcd939x, false);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x_wakeup(wcd939x, true);
+		ret = __wcd939x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
+		wcd939x_wakeup(wcd939x, false);
+		break;
+	}
+
+	return ret;
+}
+
+static int wcd939x_enable_micbias(struct wcd939x_priv *wcd939x,
+					int micb_num, int req)
+{
+	int micb_index = micb_num - 1;
+	u16 micb_reg;
+
+	if (NULL == wcd939x) {
+		pr_err_ratelimited("%s: wcd939x private data is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	switch (micb_num) {
+	case MIC_BIAS_1:
+		micb_reg = WCD939X_MICB1;
+		break;
+	case MIC_BIAS_2:
+		micb_reg = WCD939X_MICB2;
+		break;
+	case MIC_BIAS_3:
+		micb_reg = WCD939X_MICB3;
+		break;
+	case MIC_BIAS_4:
+		micb_reg = WCD939X_MICB4;
+		break;
+	default:
+		pr_err_ratelimited("%s: Invalid micbias number: %d\n", __func__, micb_num);
+		return -EINVAL;
+	};
+
+	pr_debug("%s: req: %d micb_num: %d  micb_ref: %d pullup_ref: %d\n",
+		__func__, req, micb_num, wcd939x->micb_ref[micb_index],
+		wcd939x->pullup_ref[micb_index]);
+	mutex_lock(&wcd939x->micb_lock);
+
+	switch (req) {
+	case MICB_ENABLE:
+		wcd939x->micb_ref[micb_index]++;
+		if (wcd939x->micb_ref[micb_index] == 1) {
+			regmap_update_bits(wcd939x->regmap,
+				WCD939X_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
+			regmap_update_bits(wcd939x->regmap,
+				WCD939X_CDC_ANA_CLK_CTL, 0x10, 0x10);
+			regmap_update_bits(wcd939x->regmap,
+			       WCD939X_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
+			regmap_update_bits(wcd939x->regmap,
+				WCD939X_TEST_CTL_2, 0x01, 0x01);
+			regmap_update_bits(wcd939x->regmap,
+				WCD939X_MICB2_TEST_CTL_2, 0x01, 0x01);
+			regmap_update_bits(wcd939x->regmap,
+				WCD939X_MICB3_TEST_CTL_2, 0x01, 0x01);
+			regmap_update_bits(wcd939x->regmap,
+				WCD939X_MICB4_TEST_CTL_2, 0x01, 0x01);
+			regmap_update_bits(wcd939x->regmap,
+				micb_reg, 0xC0, 0x40);
+			regmap_update_bits(wcd939x->regmap, micb_reg, 0x3F, 0x10);
+		}
+		break;
+	case MICB_PULLUP_ENABLE:
+		wcd939x->pullup_ref[micb_index]++;
+		if ((wcd939x->pullup_ref[micb_index] == 1) &&
+		    (wcd939x->micb_ref[micb_index] == 0))
+			regmap_update_bits(wcd939x->regmap, micb_reg,
+							0xC0, 0x80);
+		break;
+	case MICB_PULLUP_DISABLE:
+		if (wcd939x->pullup_ref[micb_index] > 0)
+			wcd939x->pullup_ref[micb_index]--;
+
+		if ((wcd939x->pullup_ref[micb_index] == 0) &&
+		    (wcd939x->micb_ref[micb_index] == 0))
+			regmap_update_bits(wcd939x->regmap, micb_reg,
+							0xC0, 0x00);
+		break;
+	case MICB_DISABLE:
+		if (wcd939x->micb_ref[micb_index] > 0)
+			wcd939x->micb_ref[micb_index]--;
+
+		if ((wcd939x->micb_ref[micb_index] == 0) &&
+		    (wcd939x->pullup_ref[micb_index] > 0))
+			regmap_update_bits(wcd939x->regmap, micb_reg,
+							0xC0, 0x80);
+		else if ((wcd939x->micb_ref[micb_index] == 0) &&
+			 (wcd939x->pullup_ref[micb_index] == 0))
+			regmap_update_bits(wcd939x->regmap, micb_reg,
+							0xC0, 0x00);
+		break;
+	};
+
+	mutex_unlock(&wcd939x->micb_lock);
+	return 0;
+}
+
+int wcd939x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
+					int event, int micb_num)
+{
+	struct wcd939x_priv *wcd939x_priv = NULL;
+	int ret = 0;
+	int micb_index = micb_num - 1;
+
+	if(NULL == component) {
+		pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
+		return -EINVAL;
+	}
+	if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
+		pr_err_ratelimited("%s: invalid event: %d\n", __func__, event);
+		return -EINVAL;
+	}
+	if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
+		pr_err_ratelimited("%s: invalid mic bias num: %d\n", __func__, micb_num);
+		return -EINVAL;
+	}
+
+	wcd939x_priv = snd_soc_component_get_drvdata(component);
+
+	if (!wcd939x_priv->dev_up) {
+		if ((wcd939x_priv->pullup_ref[micb_index] > 0) &&
+			(event == SND_SOC_DAPM_POST_PMD)) {
+			wcd939x_priv->pullup_ref[micb_index]--;
+			ret = -ENODEV;
+			goto done;
+		}
+	}
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		wcd939x_wakeup(wcd939x_priv, true);
+		wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_ENABLE);
+		wcd939x_wakeup(wcd939x_priv, false);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		wcd939x_wakeup(wcd939x_priv, true);
+		wcd939x_enable_micbias(wcd939x_priv, micb_num, MICB_PULLUP_DISABLE);
+		wcd939x_wakeup(wcd939x_priv, false);
+		break;
+	}
+
+done:
+	return ret;
+}
+EXPORT_SYMBOL(wcd939x_codec_force_enable_micbias_v2);
+
+static inline int wcd939x_tx_path_get(const char *wname,
+				      unsigned int *path_num)
+{
+	int ret = 0;
+	char *widget_name = NULL;
+	char *w_name = NULL;
+	char *path_num_char = NULL;
+	char *path_name = NULL;
+
+	widget_name = kstrndup(wname, 9, GFP_KERNEL);
+	if (!widget_name)
+		return -EINVAL;
+
+	w_name = widget_name;
+
+	path_name = strsep(&widget_name, " ");
+	if (!path_name) {
+		pr_err_ratelimited("%s: Invalid widget name = %s\n",
+			__func__, widget_name);
+		ret = -EINVAL;
+		goto err;
+	}
+	path_num_char = strpbrk(path_name, "0123");
+	if (!path_num_char) {
+		pr_err_ratelimited("%s: tx path index not found\n",
+			__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	ret = kstrtouint(path_num_char, 10, path_num);
+	if (ret < 0)
+		pr_err_ratelimited("%s: Invalid tx path = %s\n",
+			__func__, w_name);
+
+err:
+	kfree(w_name);
+	return ret;
+}
+
+static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = NULL;
+	int ret = 0;
+	unsigned int path = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd939x = snd_soc_component_get_drvdata(component);
+
+	if (!wcd939x)
+		return -EINVAL;
+
+	ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
+	if (ret < 0)
+		return ret;
+
+	ucontrol->value.integer.value[0] = wcd939x->tx_mode[path];
+
+	return 0;
+}
+
+static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = NULL;
+	u32 mode_val;
+	unsigned int path = 0;
+	int ret = 0;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd939x  = snd_soc_component_get_drvdata(component);
+
+	if (!wcd939x)
+		return -EINVAL;
+
+	ret = wcd939x_tx_path_get(kcontrol->id.name, &path);
+	if (ret)
+		return ret;
+
+	mode_val = ucontrol->value.enumerated.item[0];
+
+	dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
+
+	wcd939x->tx_mode[path] = mode_val;
+
+	return 0;
+}
+
+static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = wcd939x->hph_mode;
+	return 0;
+}
+
+static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	u32 mode_val;
+
+	mode_val = ucontrol->value.enumerated.item[0];
+
+	dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
+
+	if (wcd939x->variant == WCD9390) {
+		if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
+			dev_info_ratelimited(component->dev,
+				"%s:Invalid HPH Mode, default to CLS_H_ULP\n",
+				__func__);
+			mode_val = CLS_H_ULP;
+		}
+	}
+	if (mode_val == CLS_H_NORMAL) {
+		dev_info_ratelimited(component->dev,
+			"%s:Invalid HPH Mode, default to class_AB\n",
+			__func__);
+		mode_val = CLS_H_ULP;
+	}
+	wcd939x->hph_mode = mode_val;
+	return 0;
+}
+
+static int wcd939x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	u8 ear_pa_gain = 0;
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+
+	ear_pa_gain = snd_soc_component_read(component,
+				WCD939X_EAR_COMPANDER_CTL);
+
+	ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
+
+	ucontrol->value.integer.value[0] = ear_pa_gain;
+
+	dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
+		ear_pa_gain);
+
+	return 0;
+}
+
+static int wcd939x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	u8 ear_pa_gain = 0;
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0]  = %ld\n",
+			__func__, ucontrol->value.integer.value[0]);
+
+	ear_pa_gain =  ucontrol->value.integer.value[0] << 2;
+
+	if (!wcd939x->comp1_enable) {
+		snd_soc_component_update_bits(component,
+				WCD939X_EAR_COMPANDER_CTL,
+				0x7C, ear_pa_gain);
+	}
+
+	return 0;
+}
+
+/* wcd939x_codec_get_dev_num - returns swr device number
+ * @component: Codec instance
+ *
+ * Return: swr device number on success or negative error
+ * code on failure.
+ */
+int wcd939x_codec_get_dev_num(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x;
+
+	if (!component)
+		return -EINVAL;
+
+	wcd939x = snd_soc_component_get_drvdata(component);
+	if (!wcd939x || !wcd939x->rx_swr_dev) {
+		pr_err_ratelimited("%s: wcd939x component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	return wcd939x->rx_swr_dev->dev_num;
+}
+EXPORT_SYMBOL(wcd939x_codec_get_dev_num);
+
+static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	bool hphr;
+	struct soc_multi_mixer_control *mc;
+
+	mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
+	hphr = mc->shift;
+
+	ucontrol->value.integer.value[0] = hphr ? wcd939x->comp2_enable :
+						wcd939x->comp1_enable;
+	return 0;
+}
+
+static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	int value = ucontrol->value.integer.value[0];
+	bool hphr;
+	struct soc_multi_mixer_control *mc;
+
+	mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
+	hphr = mc->shift;
+	if (hphr)
+		wcd939x->comp2_enable = value;
+	else
+		wcd939x->comp1_enable = value;
+
+	return 0;
+}
+
+static int wcd939x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
+					 struct snd_kcontrol *kcontrol,
+					 int event)
+{
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	struct wcd939x_pdata *pdata = NULL;
+	int ret = 0;
+
+	pdata = dev_get_platdata(wcd939x->dev);
+
+	if (!pdata) {
+		dev_err_ratelimited(component->dev, "%s: pdata is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (!msm_cdc_is_ondemand_supply(wcd939x->dev,
+					wcd939x->supplies,
+					pdata->regulator,
+					pdata->num_supplies,
+					"cdc-vdd-buck"))
+		return 0;
+
+	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
+		w->name, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
+			dev_dbg(component->dev,
+				"%s: buck already in enabled state\n",
+				__func__);
+			clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
+			return 0;
+		}
+		ret = msm_cdc_enable_ondemand_supply(wcd939x->dev,
+						wcd939x->supplies,
+						pdata->regulator,
+						pdata->num_supplies,
+						"cdc-vdd-buck");
+		if (ret == -EINVAL) {
+			dev_err_ratelimited(component->dev, "%s: vdd buck is not enabled\n",
+				__func__);
+			return ret;
+		}
+		clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
+		/*
+		 * 200us sleep is required after LDO is enabled as per
+		 * HW requirement
+		 */
+		usleep_range(200, 250);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		set_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
+		break;
+	}
+	return 0;
+}
+
+
+static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = wcd939x->ldoh;
+
+	return 0;
+}
+
+static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	wcd939x->ldoh = ucontrol->value.integer.value[0];
+
+	return 0;
+}
+
+const char * const tx_master_ch_text[] = {
+	"ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
+	"SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
+	"SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
+	"SWRM_TX3_CH4", "SWRM_PCM_IN",
+};
+
+const struct soc_enum tx_master_ch_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
+					tx_master_ch_text);
+
+static void wcd939x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
+{
+	u8 ch_type = 0;
+
+	if (strnstr(wname, "ADC1", sizeof("ADC1")))
+		ch_type = ADC1;
+	else if (strnstr(wname, "ADC2", sizeof("ADC2")))
+		ch_type = ADC2;
+	else if (strnstr(wname, "ADC3", sizeof("ADC3")))
+		ch_type = ADC3;
+	else if (strnstr(wname, "ADC4", sizeof("ADC4")))
+		ch_type = ADC4;
+	else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
+		ch_type = DMIC0;
+	else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
+		ch_type = DMIC1;
+	else if (strnstr(wname, "MBHC", sizeof("MBHC")))
+		ch_type = MBHC;
+	else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
+		ch_type = DMIC2;
+	else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
+		ch_type = DMIC3;
+	else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
+		ch_type = DMIC4;
+	else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
+		ch_type = DMIC5;
+	else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
+		ch_type = DMIC6;
+	else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
+		ch_type = DMIC7;
+	else
+		pr_err_ratelimited("%s: port name: %s is not listed\n", __func__, wname);
+
+	if (ch_type)
+		*ch_idx = wcd939x_slave_get_slave_ch_val(ch_type);
+	else
+		*ch_idx = -EINVAL;
+}
+
+static int wcd939x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = NULL;
+	int slave_ch_idx = -EINVAL;
+
+	if (component == NULL)
+		return -EINVAL;
+
+	wcd939x = snd_soc_component_get_drvdata(component);
+	if (wcd939x == NULL)
+		return -EINVAL;
+
+	wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
+	if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
+		return -EINVAL;
+
+	ucontrol->value.integer.value[0] = wcd939x_slave_get_master_ch_val(
+			wcd939x->tx_master_ch_map[slave_ch_idx]);
+
+	return 0;
+}
+
+static int wcd939x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = NULL;
+	int slave_ch_idx = -EINVAL, idx = 0;
+
+	if (component == NULL)
+		return -EINVAL;
+
+	wcd939x = snd_soc_component_get_drvdata(component);
+	if (wcd939x == NULL)
+		return -EINVAL;
+
+	wcd939x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
+
+	if (slave_ch_idx < 0 || slave_ch_idx >= WCD939X_MAX_SLAVE_CH_TYPES)
+		return -EINVAL;
+
+	dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
+	dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
+			__func__, ucontrol->value.enumerated.item[0]);
+
+	idx = ucontrol->value.enumerated.item[0];
+	if (idx < 0 || idx >= ARRAY_SIZE(swr_master_ch_map))
+		return -EINVAL;
+
+	wcd939x->tx_master_ch_map[slave_ch_idx] = wcd939x_slave_get_master_ch(idx);
+	return 0;
+}
+
+static int wcd939x_bcs_get(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = wcd939x->bcs_dis;
+
+	return 0;
+}
+
+static int wcd939x_bcs_put(struct snd_kcontrol *kcontrol,
+				 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	wcd939x->bcs_dis = ucontrol->value.integer.value[0];
+
+	return 0;
+}
+
+static const char * const tx_mode_mux_text_wcd9390[] = {
+	"ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
+};
+
+static const struct soc_enum tx_mode_mux_enum_wcd9390 =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9390),
+			    tx_mode_mux_text_wcd9390);
+
+static const char * const tx_mode_mux_text[] = {
+	"ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
+	"ADC_ULP1", "ADC_ULP2",
+};
+
+static const struct soc_enum tx_mode_mux_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
+			    tx_mode_mux_text);
+
+static const char * const rx_hph_mode_mux_text_wcd9390[] = {
+	"CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
+	"CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
+	"CLS_AB_LOHIFI",
+};
+
+static const char * const wcd939x_ear_pa_gain_text[] = {
+	"G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
+	"G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
+	"G_M6_DB", "G_7P5_DB", "G_M9_DB",
+	"G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
+	"G_M15_DB", "G_M16P5_DB", "G_M18_DB",
+};
+
+static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
+			    rx_hph_mode_mux_text_wcd9390);
+
+static SOC_ENUM_SINGLE_EXT_DECL(wcd939x_ear_pa_gain_enum,
+				wcd939x_ear_pa_gain_text);
+
+static const char * const rx_hph_mode_mux_text[] = {
+	"CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
+	"CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
+};
+
+static const struct soc_enum rx_hph_mode_mux_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
+			    rx_hph_mode_mux_text);
+
+static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
+	SOC_ENUM_EXT("EAR PA GAIN", wcd939x_ear_pa_gain_enum,
+		wcd939x_ear_pa_gain_get, wcd939x_ear_pa_gain_put),
+
+	SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
+		wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
+
+	SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9390,
+			wcd939x_tx_mode_get, wcd939x_tx_mode_put),
+	SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9390,
+			wcd939x_tx_mode_get, wcd939x_tx_mode_put),
+	SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9390,
+			wcd939x_tx_mode_get, wcd939x_tx_mode_put),
+	SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9390,
+			wcd939x_tx_mode_get, wcd939x_tx_mode_put),
+};
+
+static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
+	SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
+		wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
+
+	SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
+			wcd939x_tx_mode_get, wcd939x_tx_mode_put),
+	SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
+			wcd939x_tx_mode_get, wcd939x_tx_mode_put),
+	SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
+			wcd939x_tx_mode_get, wcd939x_tx_mode_put),
+	SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
+			wcd939x_tx_mode_get, wcd939x_tx_mode_put),
+};
+
+static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
+	SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
+		wcd939x_get_compander, wcd939x_set_compander),
+	SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
+		wcd939x_get_compander, wcd939x_set_compander),
+	SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
+		wcd939x_ldoh_get, wcd939x_ldoh_put),
+
+	SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
+		wcd939x_bcs_get, wcd939x_bcs_put),
+
+	SOC_SINGLE_TLV("HPHL Volume", WCD939X_L_EN, 0, 20, 1, line_gain),
+	SOC_SINGLE_TLV("HPHR Volume", WCD939X_R_EN, 0, 20, 1, line_gain),
+	SOC_SINGLE_TLV("ADC1 Volume", WCD939X_TX_CH1, 0, 20, 0,
+			analog_gain),
+	SOC_SINGLE_TLV("ADC2 Volume", WCD939X_TX_CH2, 0, 20, 0,
+			analog_gain),
+	SOC_SINGLE_TLV("ADC3 Volume", WCD939X_TX_CH3, 0, 20, 0,
+			analog_gain),
+	SOC_SINGLE_TLV("ADC4 Volume", WCD939X_TX_CH4, 0, 20, 0,
+			analog_gain),
+
+	SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+	SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
+			wcd939x_tx_master_ch_get, wcd939x_tx_master_ch_put),
+};
+
+static const struct snd_kcontrol_new adc1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new adc2_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new adc3_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new adc4_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new amic1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new amic2_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new amic3_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new amic4_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new amic5_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new va_amic1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new va_amic2_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new va_amic3_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new va_amic4_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new va_amic5_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic1_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic2_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic3_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic4_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic5_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic6_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic7_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new dmic8_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new ear_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new hphl_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new hphr_rdac_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const char * const adc1_mux_text[] = {
+	"CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
+};
+
+static const struct soc_enum adc1_enum =
+	SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH1_SEL_SHIFT,
+		ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
+
+static const struct snd_kcontrol_new tx_adc1_mux =
+	SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
+
+static const char * const adc2_mux_text[] = {
+	"CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
+};
+
+static const struct soc_enum adc2_enum =
+	SOC_ENUM_SINGLE(WCD939X_TX_CH12_MUX, WCD939X_TX_CH12_MUX_CH2_SEL_SHIFT,
+		ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
+
+static const struct snd_kcontrol_new tx_adc2_mux =
+	SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
+
+static const char * const adc3_mux_text[] = {
+	"CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
+};
+
+static const struct soc_enum adc3_enum =
+	SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH3_SEL_SHIFT,
+		ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
+
+static const struct snd_kcontrol_new tx_adc3_mux =
+	SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
+
+static const char * const adc4_mux_text[] = {
+	"CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
+};
+
+static const struct soc_enum adc4_enum =
+	SOC_ENUM_SINGLE(WCD939X_TX_CH34_MUX, WCD939X_TX_CH34_MUX_CH4_SEL_SHIFT,
+		ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
+
+static const struct snd_kcontrol_new tx_adc4_mux =
+	SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
+
+static const char * const rdac3_mux_text[] = {
+	"RX1", "RX3"
+};
+
+
+static const struct soc_enum rdac3_enum =
+	SOC_ENUM_SINGLE(WCD939X_CDC_EAR_PATH_CTL, 0,
+		ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
+
+static const struct snd_kcontrol_new rx_rdac3_mux =
+	SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
+
+static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
+
+	/*input widgets*/
+	SND_SOC_DAPM_INPUT("AMIC1"),
+	SND_SOC_DAPM_INPUT("AMIC2"),
+	SND_SOC_DAPM_INPUT("AMIC3"),
+	SND_SOC_DAPM_INPUT("AMIC4"),
+	SND_SOC_DAPM_INPUT("AMIC5"),
+	SND_SOC_DAPM_INPUT("VA AMIC1"),
+	SND_SOC_DAPM_INPUT("VA AMIC2"),
+	SND_SOC_DAPM_INPUT("VA AMIC3"),
+	SND_SOC_DAPM_INPUT("VA AMIC4"),
+	SND_SOC_DAPM_INPUT("VA AMIC5"),
+
+	SND_SOC_DAPM_INPUT("IN1_HPHL"),
+	SND_SOC_DAPM_INPUT("IN2_HPHR"),
+	SND_SOC_DAPM_INPUT("IN3_EAR"),
+	/*
+	 * These dummy widgets are null connected to WCD939x dapm input and
+	 * output widgets which are not actual path endpoints. This ensures
+	 * dapm doesnt set these dapm input and output widgets as endpoints.
+	 */
+	SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
+	SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
+
+	/*tx widgets*/
+	SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_adc,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
+				wcd939x_codec_enable_adc,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
+				wcd939x_codec_enable_adc,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
+				wcd939x_codec_enable_adc,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
+				wcd939x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
+				wcd939x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
+				wcd939x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
+				wcd939x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
+				wcd939x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
+				wcd939x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
+				wcd939x_codec_enable_dmic,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
+				NULL, 0, wcd939x_enable_req,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
+				NULL, 0, wcd939x_enable_req,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
+				NULL, 0, wcd939x_enable_req,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
+				NULL, 0, wcd939x_enable_req,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
+				amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
+				amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
+				amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
+				amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
+				amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
+				va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
+				va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
+				va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
+				va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
+				va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
+				&tx_adc1_mux),
+	SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
+				&tx_adc2_mux),
+	SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
+				&tx_adc3_mux),
+	SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
+				&tx_adc4_mux),
+	/*tx mixers*/
+	SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
+				adc1_switch, ARRAY_SIZE(adc1_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
+				adc2_switch, ARRAY_SIZE(adc2_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
+				ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
+				ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
+				0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
+				0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
+				0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
+				0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
+				0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
+				0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
+				0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
+				0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
+				wcd939x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	/* micbias widgets*/
+	SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_micbias,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_micbias,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_micbias,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_micbias,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
+		wcd939x_codec_force_enable_micbias,
+		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
+		wcd939x_codec_force_enable_micbias,
+		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
+		wcd939x_codec_force_enable_micbias,
+		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
+		wcd939x_codec_force_enable_micbias,
+		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
+			     wcd939x_codec_enable_vdd_buck,
+			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
+			     wcd939x_enable_clsh,
+			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	/*rx widgets*/
+	SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_EAR, 7, 0, NULL, 0,
+				wcd939x_codec_enable_ear_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_HPH, 7, 0, NULL, 0,
+				wcd939x_codec_enable_hphl_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_HPH, 6, 0, NULL, 0,
+				wcd939x_codec_enable_hphr_pa,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_hphl_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_hphr_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_ear_dac_event,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
+
+	SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd939x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd939x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
+				wcd939x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
+				SND_SOC_DAPM_POST_PMD),
+
+	/* rx mixer widgets*/
+
+	SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
+			   ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
+	SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
+			   hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
+	SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
+			   hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
+
+	/*output widgets tx*/
+	SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
+
+	/*output widgets rx*/
+	SND_SOC_DAPM_OUTPUT("EAR"),
+	SND_SOC_DAPM_OUTPUT("HPHL"),
+	SND_SOC_DAPM_OUTPUT("HPHR"),
+
+	/* micbias pull up widgets*/
+	SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_micbias_pullup,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_micbias_pullup,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_micbias_pullup,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
+				wcd939x_codec_enable_micbias_pullup,
+				SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
+				SND_SOC_DAPM_POST_PMD),
+};
+
+static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
+
+/*ADC-1 (channel-1)*/
+	{"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
+	{"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
+	{"ADC1_MIXER", "Switch", "ADC1 REQ"},
+	{"ADC1 REQ", NULL, "ADC1"},
+	{"ADC1", NULL, "ADC1 MUX"},
+	{"ADC1 MUX", "CH1_AMIC1", "AMIC1_MIXER"},
+	{"ADC1 MUX", "CH1_AMIC2", "AMIC2_MIXER"},
+	{"ADC1 MUX", "CH1_AMIC3", "AMIC3_MIXER"},
+	{"ADC1 MUX", "CH1_AMIC4", "AMIC4_MIXER"},
+	{"ADC1 MUX", "CH1_AMIC5", "AMIC5_MIXER"},
+
+	{"AMIC1_MIXER", "Switch", "AMIC1"},
+	{"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
+	{"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
+
+	{"AMIC2_MIXER", "Switch", "AMIC2"},
+	{"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
+	{"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
+
+	{"AMIC3_MIXER", "Switch", "AMIC3"},
+	{"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
+	{"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
+
+	{"AMIC4_MIXER", "Switch", "AMIC4"},
+	{"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
+	{"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
+
+	{"AMIC5_MIXER", "Switch", "AMIC5"},
+	{"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
+	{"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
+
+/*ADC-2 (channel-2)*/
+	{"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
+	{"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
+	{"ADC2_MIXER", "Switch", "ADC2 REQ"},
+	{"ADC2 REQ", NULL, "ADC2"},
+	{"ADC2", NULL, "ADC2 MUX"},
+	{"ADC2 MUX", "CH2_AMIC1", "AMIC1_MIXER"},
+	{"ADC2 MUX", "CH2_AMIC2", "AMIC2_MIXER"},
+	{"ADC2 MUX", "CH2_AMIC3", "AMIC3_MIXER"},
+	{"ADC2 MUX", "CH2_AMIC4", "AMIC4_MIXER"},
+	{"ADC2 MUX", "CH2_AMIC5", "AMIC5_MIXER"},
+
+/*ADC-3 (channel-3)*/
+	{"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
+	{"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
+	{"ADC3_MIXER", "Switch", "ADC3 REQ"},
+	{"ADC3 REQ", NULL, "ADC3"},
+	{"ADC3", NULL, "ADC3 MUX"},
+	{"ADC3 MUX", "CH3_AMIC1", "AMIC1_MIXER"},
+	{"ADC3 MUX", "CH3_AMIC3", "AMIC3_MIXER"},
+	{"ADC3 MUX", "CH3_AMIC4", "AMIC4_MIXER"},
+	{"ADC3 MUX", "CH3_AMIC5", "AMIC5_MIXER"},
+
+/*ADC-4 (channel-4)*/
+	{"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
+	{"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
+	{"ADC4_MIXER", "Switch", "ADC4 REQ"},
+	{"ADC4 REQ", NULL, "ADC4"},
+	{"ADC4", NULL, "ADC4 MUX"},
+	{"ADC4 MUX", "CH4_AMIC1", "AMIC1_MIXER"},
+	{"ADC4 MUX", "CH4_AMIC3", "AMIC3_MIXER"},
+	{"ADC4 MUX", "CH4_AMIC4", "AMIC4_MIXER"},
+	{"ADC4 MUX", "CH4_AMIC5", "AMIC5_MIXER"},
+
+	{"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
+	{"DMIC1_MIXER", "Switch", "DMIC1"},
+
+	{"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
+	{"DMIC2_MIXER", "Switch", "DMIC2"},
+
+	{"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
+	{"DMIC3_MIXER", "Switch", "DMIC3"},
+
+	{"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
+	{"DMIC4_MIXER", "Switch", "DMIC4"},
+
+	{"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
+	{"DMIC5_MIXER", "Switch", "DMIC5"},
+
+	{"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
+	{"DMIC6_MIXER", "Switch", "DMIC6"},
+
+	{"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
+	{"DMIC7_MIXER", "Switch", "DMIC7"},
+
+	{"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
+	{"DMIC8_MIXER", "Switch", "DMIC8"},
+
+	{"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
+	{"IN1_HPHL", NULL, "VDD_BUCK"},
+	{"IN1_HPHL", NULL, "CLS_H_PORT"},
+	{"RX1", NULL, "IN1_HPHL"},
+	{"RDAC1", NULL, "RX1"},
+	{"HPHL_RDAC", "Switch", "RDAC1"},
+	{"HPHL PGA", NULL, "HPHL_RDAC"},
+	{"HPHL", NULL, "HPHL PGA"},
+
+	{"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
+	{"IN2_HPHR", NULL, "VDD_BUCK"},
+	{"IN2_HPHR", NULL, "CLS_H_PORT"},
+	{"RX2", NULL, "IN2_HPHR"},
+	{"RDAC2", NULL, "RX2"},
+	{"HPHR_RDAC", "Switch", "RDAC2"},
+	{"HPHR PGA", NULL, "HPHR_RDAC"},
+	{"HPHR", NULL, "HPHR PGA"},
+
+	{"IN3_EAR", NULL, "WCD_RX_DUMMY"},
+	{"IN3_EAR", NULL, "VDD_BUCK"},
+	{"IN3_EAR", NULL, "CLS_H_PORT"},
+	{"RX3", NULL, "IN3_EAR"},
+	{"RDAC3_MUX", "RX3", "RX3"},
+	{"RDAC3_MUX", "RX1", "RX1"},
+	{"RDAC3", NULL, "RDAC3_MUX"},
+	{"EAR_RDAC", "Switch", "RDAC3"},
+	{"EAR PGA", NULL, "EAR_RDAC"},
+	{"EAR", NULL, "EAR PGA"},
+};
+
+static ssize_t wcd939x_version_read(struct snd_info_entry *entry,
+				   void *file_private_data,
+				   struct file *file,
+				   char __user *buf, size_t count,
+				   loff_t pos)
+{
+	struct wcd939x_priv *priv;
+	char buffer[WCD939X_VERSION_ENTRY_SIZE];
+	int len = 0;
+
+	priv = (struct wcd939x_priv *) entry->private_data;
+	if (!priv) {
+		pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
+		return -EINVAL;
+	}
+
+	switch (priv->version) {
+	case WCD939X_VERSION_1_0:
+		len = snprintf(buffer, sizeof(buffer), "WCD939X_1_0\n");
+		break;
+	default:
+		len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
+	}
+
+	return simple_read_from_buffer(buf, count, &pos, buffer, len);
+}
+
+static struct snd_info_entry_ops wcd939x_info_ops = {
+	.read = wcd939x_version_read,
+};
+
+static ssize_t wcd939x_variant_read(struct snd_info_entry *entry,
+				    void *file_private_data,
+				    struct file *file,
+				    char __user *buf, size_t count,
+				    loff_t pos)
+{
+	struct wcd939x_priv *priv;
+	char buffer[WCD939X_VARIANT_ENTRY_SIZE];
+	int len = 0;
+
+	priv = (struct wcd939x_priv *) entry->private_data;
+	if (!priv) {
+		pr_err_ratelimited("%s: wcd939x priv is null\n", __func__);
+		return -EINVAL;
+	}
+
+	switch (priv->variant) {
+	case WCD9390:
+		len = snprintf(buffer, sizeof(buffer), "WCD9390\n");
+		break;
+	case WCD9395:
+		len = snprintf(buffer, sizeof(buffer), "WCD9395\n");
+		break;
+	default:
+		len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
+	}
+
+	return simple_read_from_buffer(buf, count, &pos, buffer, len);
+}
+
+static struct snd_info_entry_ops wcd939x_variant_ops = {
+	.read = wcd939x_variant_read,
+};
+
+/*
+ * wcd939x_get_codec_variant
+ * @component: component instance
+ *
+ * Return: codec variant or -EINVAL in error.
+ */
+int wcd939x_get_codec_variant(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *priv = NULL;
+
+	if (!component)
+		return -EINVAL;
+
+	priv = snd_soc_component_get_drvdata(component);
+	if (!priv) {
+		dev_err(component->dev,
+			"%s:wcd939x not probed\n", __func__);
+		return 0;
+	}
+
+	return priv->variant;
+}
+EXPORT_SYMBOL(wcd939x_get_codec_variant);
+
+/*
+ * wcd939x_info_create_codec_entry - creates wcd939x module
+ * @codec_root: The parent directory
+ * @component: component instance
+ *
+ * Creates wcd939x module, variant and version entry under the given
+ * parent directory.
+ *
+ * Return: 0 on success or negative error code on failure.
+ */
+int wcd939x_info_create_codec_entry(struct snd_info_entry *codec_root,
+				   struct snd_soc_component *component)
+{
+	struct snd_info_entry *version_entry;
+	struct snd_info_entry *variant_entry;
+	struct wcd939x_priv *priv;
+	struct snd_soc_card *card;
+
+	if (!codec_root || !component)
+		return -EINVAL;
+
+	priv = snd_soc_component_get_drvdata(component);
+	if (priv->entry) {
+		dev_dbg(priv->dev,
+			"%s:wcd939x module already created\n", __func__);
+		return 0;
+	}
+	card = component->card;
+
+	priv->entry = snd_info_create_module_entry(codec_root->module,
+					     "wcd939x", codec_root);
+	if (!priv->entry) {
+		dev_dbg(component->dev, "%s: failed to create wcd939x entry\n",
+			__func__);
+		return -ENOMEM;
+	}
+	priv->entry->mode = S_IFDIR | 0555;
+	if (snd_info_register(priv->entry) < 0) {
+		snd_info_free_entry(priv->entry);
+		return -ENOMEM;
+	}
+	version_entry = snd_info_create_card_entry(card->snd_card,
+						   "version",
+						   priv->entry);
+	if (!version_entry) {
+		dev_dbg(component->dev, "%s: failed to create wcd939x version entry\n",
+			__func__);
+		snd_info_free_entry(priv->entry);
+		return -ENOMEM;
+	}
+
+	version_entry->private_data = priv;
+	version_entry->size = WCD939X_VERSION_ENTRY_SIZE;
+	version_entry->content = SNDRV_INFO_CONTENT_DATA;
+	version_entry->c.ops = &wcd939x_info_ops;
+
+	if (snd_info_register(version_entry) < 0) {
+		snd_info_free_entry(version_entry);
+		snd_info_free_entry(priv->entry);
+		return -ENOMEM;
+	}
+	priv->version_entry = version_entry;
+
+	variant_entry = snd_info_create_card_entry(card->snd_card,
+						   "variant",
+						   priv->entry);
+	if (!variant_entry) {
+		dev_dbg(component->dev, "%s: failed to create wcd939x variant entry\n",
+			__func__);
+		snd_info_free_entry(version_entry);
+		snd_info_free_entry(priv->entry);
+		return -ENOMEM;
+	}
+
+	variant_entry->private_data = priv;
+	variant_entry->size = WCD939X_VARIANT_ENTRY_SIZE;
+	variant_entry->content = SNDRV_INFO_CONTENT_DATA;
+	variant_entry->c.ops = &wcd939x_variant_ops;
+
+	if (snd_info_register(variant_entry) < 0) {
+		snd_info_free_entry(variant_entry);
+		snd_info_free_entry(version_entry);
+		snd_info_free_entry(priv->entry);
+		return -ENOMEM;
+	}
+	priv->variant_entry = variant_entry;
+
+	return 0;
+}
+EXPORT_SYMBOL(wcd939x_info_create_codec_entry);
+
+static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x,
+			      struct wcd939x_pdata *pdata)
+{
+	int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
+	int rc = 0;
+
+	if (!pdata) {
+		dev_err(wcd939x->dev, "%s: NULL pdata\n", __func__);
+		return -ENODEV;
+	}
+
+	/* set micbias voltage */
+	vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
+	vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
+	vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
+	vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
+	if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
+	    vout_ctl_4 < 0) {
+		rc = -EINVAL;
+		goto done;
+	}
+	regmap_update_bits(wcd939x->regmap, WCD939X_MICB1, 0x3F,
+			   vout_ctl_1);
+	regmap_update_bits(wcd939x->regmap, WCD939X_MICB2, 0x3F,
+			   vout_ctl_2);
+	regmap_update_bits(wcd939x->regmap, WCD939X_MICB3, 0x3F,
+			   vout_ctl_3);
+	regmap_update_bits(wcd939x->regmap, WCD939X_MICB4, 0x3F,
+			   vout_ctl_4);
+
+done:
+	return rc;
+}
+
+static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+	struct snd_soc_dapm_context *dapm =
+			snd_soc_component_get_dapm(component);
+	int variant;
+	int ret = -EINVAL;
+
+	dev_info(component->dev, "%s()\n", __func__);
+	wcd939x = snd_soc_component_get_drvdata(component);
+
+	if (!wcd939x)
+		return -EINVAL;
+
+	wcd939x->component = component;
+	snd_soc_component_init_regmap(component, wcd939x->regmap);
+
+	devm_regmap_qti_debugfs_register(&wcd939x->tx_swr_dev->dev, wcd939x->regmap);
+
+	variant = (snd_soc_component_read(component,
+			WCD939X_EFUSE_REG_0) & 0x1E) >> 1;
+	wcd939x->variant = variant;
+
+	wcd939x->fw_data = devm_kzalloc(component->dev,
+					sizeof(*(wcd939x->fw_data)),
+					GFP_KERNEL);
+	if (!wcd939x->fw_data) {
+		dev_err(component->dev, "Failed to allocate fw_data\n");
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	set_bit(WCD9XXX_MBHC_CAL, wcd939x->fw_data->cal_bit);
+	ret = wcd_cal_create_hwdep(wcd939x->fw_data,
+				   WCD9XXX_CODEC_HWDEP_NODE, component);
+
+	if (ret < 0) {
+		dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
+		goto err_hwdep;
+	}
+
+	ret = wcd939x_mbhc_init(&wcd939x->mbhc, component, wcd939x->fw_data);
+	if (ret) {
+		pr_err("%s: mbhc initialization failed\n", __func__);
+		goto err_hwdep;
+	}
+
+	snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Playback");
+	snd_soc_dapm_ignore_suspend(dapm, "WCD939X_AIF Capture");
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
+	snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
+	snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
+	snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
+	snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
+	snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
+	snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
+	snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
+	snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
+	snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
+	snd_soc_dapm_ignore_suspend(dapm, "IN3_EAR");
+	snd_soc_dapm_ignore_suspend(dapm, "EAR");
+	snd_soc_dapm_ignore_suspend(dapm, "HPHL");
+	snd_soc_dapm_ignore_suspend(dapm, "HPHR");
+	snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
+	snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
+	snd_soc_dapm_sync(dapm);
+
+	wcd_cls_h_init(&wcd939x->clsh_info);
+	wcd939x_init_reg(component);
+
+	if (wcd939x->variant == WCD9390) {
+		ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
+					ARRAY_SIZE(wcd9390_snd_controls));
+		if (ret < 0) {
+			dev_err(component->dev,
+				"%s: Failed to add snd ctrls for variant: %d\n",
+				__func__, wcd939x->variant);
+			goto err_hwdep;
+		}
+	}
+	if (wcd939x->variant == WCD9395) {
+		ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
+					ARRAY_SIZE(wcd9395_snd_controls));
+		if (ret < 0) {
+			dev_err(component->dev,
+				"%s: Failed to add snd ctrls for variant: %d\n",
+				__func__, wcd939x->variant);
+			goto err_hwdep;
+		}
+	}
+	wcd939x->version = WCD939X_VERSION_1_0;
+       /* Register event notifier */
+	wcd939x->nblock.notifier_call = wcd939x_event_notify;
+	if (wcd939x->register_notifier) {
+		ret = wcd939x->register_notifier(wcd939x->handle,
+						&wcd939x->nblock,
+						true);
+		if (ret) {
+			dev_err(component->dev,
+				"%s: Failed to register notifier %d\n",
+				__func__, ret);
+			return ret;
+		}
+	}
+	return ret;
+
+err_hwdep:
+	wcd939x->fw_data = NULL;
+
+err:
+	return ret;
+}
+
+static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	if (!wcd939x) {
+		dev_err(component->dev, "%s: wcd939x is already NULL\n",
+			__func__);
+		return;
+	}
+	if (wcd939x->register_notifier)
+		wcd939x->register_notifier(wcd939x->handle,
+						&wcd939x->nblock,
+						false);
+}
+
+static int wcd939x_soc_codec_suspend(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	if (!wcd939x)
+		return 0;
+	wcd939x->dapm_bias_off = true;
+	return 0;
+}
+
+static int wcd939x_soc_codec_resume(struct snd_soc_component *component)
+{
+	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
+
+	if (!wcd939x)
+		return 0;
+	wcd939x->dapm_bias_off = false;
+	return 0;
+}
+
+static struct snd_soc_component_driver soc_codec_dev_wcd939x = {
+	.name = WCD939X_DRV_NAME,
+	.probe = wcd939x_soc_codec_probe,
+	.remove = wcd939x_soc_codec_remove,
+	.controls = wcd939x_snd_controls,
+	.num_controls = ARRAY_SIZE(wcd939x_snd_controls),
+	.dapm_widgets = wcd939x_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
+	.dapm_routes = wcd939x_audio_map,
+	.num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
+	.suspend =  wcd939x_soc_codec_suspend,
+	.resume = wcd939x_soc_codec_resume,
+};
+
+static int wcd939x_reset(struct device *dev)
+{
+	struct wcd939x_priv *wcd939x = NULL;
+	int rc = 0;
+	int value = 0;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd939x = dev_get_drvdata(dev);
+	if (!wcd939x)
+		return -EINVAL;
+
+	if (!wcd939x->rst_np) {
+		dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	value = msm_cdc_pinctrl_get_state(wcd939x->rst_np);
+	if (value > 0)
+		return 0;
+
+	rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
+	if (rc) {
+		dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
+				__func__);
+		return rc;
+	}
+	/* 20us sleep required after pulling the reset gpio to LOW */
+	usleep_range(20, 30);
+
+	rc = msm_cdc_pinctrl_select_active_state(wcd939x->rst_np);
+	if (rc) {
+		dev_err_ratelimited(dev, "%s: wcd active state request fail!\n",
+				__func__);
+		return rc;
+	}
+	/* 20us sleep required after pulling the reset gpio to HIGH */
+	usleep_range(20, 30);
+
+	return rc;
+}
+
+static int wcd939x_read_of_property_u32(struct device *dev, const char *name,
+					u32 *val)
+{
+	int rc = 0;
+
+	rc = of_property_read_u32(dev->of_node, name, val);
+	if (rc)
+		dev_err(dev, "%s: Looking up %s property in node %s failed\n",
+			__func__, name, dev->of_node->full_name);
+
+	return rc;
+}
+
+static void wcd939x_dt_parse_micbias_info(struct device *dev,
+					  struct wcd939x_micbias_setting *mb)
+{
+	u32 prop_val = 0;
+	int rc = 0;
+
+	/* MB1 */
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
+				    NULL)) {
+		rc = wcd939x_read_of_property_u32(dev,
+						  "qcom,cdc-micbias1-mv",
+						  &prop_val);
+		if (!rc)
+			mb->micb1_mv = prop_val;
+	} else {
+		dev_info(dev, "%s: Micbias1 DT property not found\n",
+			__func__);
+	}
+
+	/* MB2 */
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
+				    NULL)) {
+		rc = wcd939x_read_of_property_u32(dev,
+						  "qcom,cdc-micbias2-mv",
+						  &prop_val);
+		if (!rc)
+			mb->micb2_mv = prop_val;
+	} else {
+		dev_info(dev, "%s: Micbias2 DT property not found\n",
+			__func__);
+	}
+
+	/* MB3 */
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
+				    NULL)) {
+		rc = wcd939x_read_of_property_u32(dev,
+						  "qcom,cdc-micbias3-mv",
+						  &prop_val);
+		if (!rc)
+			mb->micb3_mv = prop_val;
+	} else {
+		dev_info(dev, "%s: Micbias3 DT property not found\n",
+			__func__);
+	}
+
+	/* MB4 */
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
+				    NULL)) {
+		rc = wcd939x_read_of_property_u32(dev,
+						  "qcom,cdc-micbias4-mv",
+						  &prop_val);
+		if (!rc)
+			mb->micb4_mv = prop_val;
+	} else {
+		dev_info(dev, "%s: Micbias4 DT property not found\n",
+			__func__);
+	}
+}
+
+static int wcd939x_reset_low(struct device *dev)
+{
+	struct wcd939x_priv *wcd939x = NULL;
+	int rc = 0;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd939x = dev_get_drvdata(dev);
+	if (!wcd939x)
+		return -EINVAL;
+
+	if (!wcd939x->rst_np) {
+		dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	rc = msm_cdc_pinctrl_select_sleep_state(wcd939x->rst_np);
+	if (rc) {
+		dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
+				__func__);
+		return rc;
+	}
+	/* 20us sleep required after pulling the reset gpio to LOW */
+	usleep_range(20, 30);
+
+	return rc;
+}
+
+struct wcd939x_pdata *wcd939x_populate_dt_data(struct device *dev)
+{
+	struct wcd939x_pdata *pdata = NULL;
+
+	pdata = devm_kzalloc(dev, sizeof(struct wcd939x_pdata),
+				GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	pdata->rst_np = of_parse_phandle(dev->of_node,
+			"qcom,wcd-rst-gpio-node", 0);
+
+	if (!pdata->rst_np) {
+		dev_err_ratelimited(dev, "%s: Looking up %s property in node %s failed\n",
+				__func__, "qcom,wcd-rst-gpio-node",
+				dev->of_node->full_name);
+		return NULL;
+	}
+
+	/* Parse power supplies */
+	msm_cdc_get_power_supplies(dev, &pdata->regulator,
+				   &pdata->num_supplies);
+	if (!pdata->regulator || (pdata->num_supplies <= 0)) {
+		dev_err_ratelimited(dev, "%s: no power supplies defined for codec\n",
+			__func__);
+		return NULL;
+	}
+
+	pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
+	pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
+
+	wcd939x_dt_parse_micbias_info(dev, &pdata->micbias);
+
+	return pdata;
+}
+
+static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
+{
+	pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
+			   __func__, irq);
+	return IRQ_HANDLED;
+}
+
+static struct snd_soc_dai_driver wcd939x_dai[] = {
+	{
+		.name = "wcd939x_cdc",
+		.playback = {
+			.stream_name = "WCD939X_AIF Playback",
+                        .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
+			.formats = WCD939X_FORMATS,
+			.rate_max = 384000,
+			.rate_min = 8000,
+			.channels_min = 1,
+			.channels_max = 4,
+		},
+		.capture = {
+			.stream_name = "WCD939X_AIF Capture",
+                        .rates = WCD939X_RATES | WCD939X_FRAC_RATES,
+			.formats = WCD939X_FORMATS,
+			.rate_max = 384000,
+			.rate_min = 8000,
+			.channels_min = 1,
+			.channels_max = 4,
+		},
+	},
+};
+
+static int wcd939x_bind(struct device *dev)
+{
+	int ret = 0, i = 0;
+	struct wcd939x_pdata *pdata = dev_get_platdata(dev);
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
+
+	/*
+	 * Add 5msec delay to provide sufficient time for
+	 * soundwire auto enumeration of slave devices as
+	 * as per HW requirement.
+	 */
+	usleep_range(5000, 5010);
+
+	ret = component_bind_all(dev, wcd939x);
+	if (ret) {
+		dev_err_ratelimited(dev, "%s: Slave bind failed, ret = %d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	wcd939x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
+	if (!wcd939x->rx_swr_dev) {
+		dev_err_ratelimited(dev, "%s: Could not find RX swr slave device\n",
+			 __func__);
+		ret = -ENODEV;
+		goto err;
+	}
+
+	wcd939x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
+	if (!wcd939x->tx_swr_dev) {
+		dev_err_ratelimited(dev, "%s: Could not find TX swr slave device\n",
+			__func__);
+		ret = -ENODEV;
+		goto err;
+	}
+	swr_init_port_params(wcd939x->tx_swr_dev, SWR_NUM_PORTS,
+			     wcd939x->swr_tx_port_params);
+
+	wcd939x->regmap = devm_regmap_init_swr(wcd939x->tx_swr_dev,
+					       &wcd939x_regmap_config);
+	if (!wcd939x->regmap) {
+		dev_err_ratelimited(dev, "%s: Regmap init failed\n",
+				__func__);
+		goto err;
+	}
+
+	/* Set all interupts as edge triggered */
+	for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
+		regmap_write(wcd939x->regmap,
+			     (WCD939X_INTR_LEVEL_0 + i), 0);
+
+	wcd939x_regmap_irq_chip.irq_drv_data = wcd939x;
+	wcd939x->irq_info.wcd_regmap_irq_chip = &wcd939x_regmap_irq_chip;
+	wcd939x->irq_info.codec_name = "WCD939X";
+	wcd939x->irq_info.regmap = wcd939x->regmap;
+	wcd939x->irq_info.dev = dev;
+	ret = wcd_irq_init(&wcd939x->irq_info, &wcd939x->virq);
+
+	if (ret) {
+		dev_err_ratelimited(wcd939x->dev, "%s: IRQ init failed: %d\n",
+			__func__, ret);
+		goto err;
+	}
+	wcd939x->tx_swr_dev->slave_irq = wcd939x->virq;
+
+	ret = wcd939x_set_micbias_data(wcd939x, pdata);
+	if (ret < 0) {
+		dev_err_ratelimited(dev, "%s: bad micbias pdata\n", __func__);
+		goto err_irq;
+	}
+
+	/* Request for watchdog interrupt */
+	wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT,
+			"HPHR PDM WD INT", wcd939x_wd_handle_irq, NULL);
+	wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT,
+			"HPHL PDM WD INT", wcd939x_wd_handle_irq, NULL);
+	wcd_request_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT,
+			"EAR PDM WD INT", wcd939x_wd_handle_irq, NULL);
+	/* Disable watchdog interrupt for HPH and EAR */
+	wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT);
+	wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT);
+	wcd_disable_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT);
+
+	ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
+					wcd939x_dai, ARRAY_SIZE(wcd939x_dai));
+	if (ret) {
+		dev_err_ratelimited(dev, "%s: Codec registration failed\n",
+				__func__);
+		goto err_irq;
+	}
+	wcd939x->dev_up = true;
+
+	return ret;
+err_irq:
+	wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
+err:
+	component_unbind_all(dev, wcd939x);
+	return ret;
+}
+
+static void wcd939x_unbind(struct device *dev)
+{
+	struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
+
+	wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHR_PDM_WD_INT, NULL);
+	wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_HPHL_PDM_WD_INT, NULL);
+	wcd_free_irq(&wcd939x->irq_info, WCD939X_IRQ_EAR_PDM_WD_INT, NULL);
+	wcd_irq_exit(&wcd939x->irq_info, wcd939x->virq);
+	snd_soc_unregister_component(dev);
+	component_unbind_all(dev, wcd939x);
+}
+
+static const struct of_device_id wcd939x_dt_match[] = {
+	{ .compatible = "qcom,wcd939x-codec", .data = "wcd939x"},
+	{}
+};
+
+static const struct component_master_ops wcd939x_comp_ops = {
+	.bind   = wcd939x_bind,
+	.unbind = wcd939x_unbind,
+};
+
+static int wcd939x_compare_of(struct device *dev, void *data)
+{
+	return dev->of_node == data;
+}
+
+static void wcd939x_release_of(struct device *dev, void *data)
+{
+	of_node_put(data);
+}
+
+static int wcd939x_add_slave_components(struct device *dev,
+				struct component_match **matchptr)
+{
+	struct device_node *np, *rx_node, *tx_node;
+
+	np = dev->of_node;
+
+	rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
+	if (!rx_node) {
+		dev_err_ratelimited(dev, "%s: Rx-slave node not defined\n", __func__);
+		return -ENODEV;
+	}
+	of_node_get(rx_node);
+	component_match_add_release(dev, matchptr,
+			wcd939x_release_of,
+			wcd939x_compare_of,
+			rx_node);
+
+	tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
+	if (!tx_node) {
+		dev_err_ratelimited(dev, "%s: Tx-slave node not defined\n", __func__);
+			return -ENODEV;
+	}
+	of_node_get(tx_node);
+	component_match_add_release(dev, matchptr,
+			wcd939x_release_of,
+			wcd939x_compare_of,
+			tx_node);
+	return 0;
+}
+
+static int wcd939x_probe(struct platform_device *pdev)
+{
+	struct component_match *match = NULL;
+	struct wcd939x_priv *wcd939x = NULL;
+	struct wcd939x_pdata *pdata = NULL;
+	struct wcd_ctrl_platform_data *plat_data = NULL;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
+				GFP_KERNEL);
+	if (!wcd939x)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, wcd939x);
+	wcd939x->dev = dev;
+
+	pdata = wcd939x_populate_dt_data(dev);
+	if (!pdata) {
+		dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
+		return -EINVAL;
+	}
+	dev->platform_data = pdata;
+
+	wcd939x->rst_np = pdata->rst_np;
+	ret = msm_cdc_init_supplies(dev, &wcd939x->supplies,
+				    pdata->regulator, pdata->num_supplies);
+	if (!wcd939x->supplies) {
+		dev_err(dev, "%s: Cannot init wcd supplies\n",
+			__func__);
+		return ret;
+	}
+
+	plat_data = dev_get_platdata(dev->parent);
+	if (!plat_data) {
+		dev_err(dev, "%s: platform data from parent is NULL\n",
+			__func__);
+		return -EINVAL;
+	}
+	wcd939x->handle = (void *)plat_data->handle;
+	if (!wcd939x->handle) {
+		dev_err(dev, "%s: handle is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	wcd939x->update_wcd_event = plat_data->update_wcd_event;
+	if (!wcd939x->update_wcd_event) {
+		dev_err(dev, "%s: update_wcd_event api is null!\n",
+			__func__);
+		return -EINVAL;
+	}
+	wcd939x->register_notifier = plat_data->register_notifier;
+	if (!wcd939x->register_notifier) {
+		dev_err(dev, "%s: register_notifier api is null!\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd939x->supplies,
+					     pdata->regulator,
+					     pdata->num_supplies);
+	if (ret) {
+		dev_err(dev, "%s: wcd static supply enable failed!\n",
+			__func__);
+		return ret;
+	}
+
+	ret = wcd939x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
+					CODEC_RX);
+	ret |= wcd939x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
+					CODEC_TX);
+
+	if (ret) {
+		dev_err(dev, "Failed to read port mapping\n");
+		goto err;
+	}
+	ret = wcd939x_parse_port_params(dev, "qcom,swr-tx-port-params",
+					CODEC_TX);
+	if (ret) {
+		dev_err(dev, "Failed to read port params\n");
+		goto err;
+	}
+
+	mutex_init(&wcd939x->wakeup_lock);
+	mutex_init(&wcd939x->micb_lock);
+	ret = wcd939x_add_slave_components(dev, &match);
+	if (ret)
+		goto err_lock_init;
+
+	wcd939x_reset(dev);
+
+	wcd939x->wakeup = wcd939x_wakeup;
+
+	return component_master_add_with_match(dev,
+					&wcd939x_comp_ops, match);
+
+err_lock_init:
+	mutex_destroy(&wcd939x->micb_lock);
+	mutex_destroy(&wcd939x->wakeup_lock);
+err:
+	return ret;
+}
+
+static int wcd939x_remove(struct platform_device *pdev)
+{
+	struct wcd939x_priv *wcd939x = NULL;
+
+	wcd939x = platform_get_drvdata(pdev);
+	component_master_del(&pdev->dev, &wcd939x_comp_ops);
+	mutex_destroy(&wcd939x->micb_lock);
+	mutex_destroy(&wcd939x->wakeup_lock);
+	dev_set_drvdata(&pdev->dev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int wcd939x_suspend(struct device *dev)
+{
+	struct wcd939x_priv *wcd939x = NULL;
+	int ret = 0;
+	struct wcd939x_pdata *pdata = NULL;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd939x = dev_get_drvdata(dev);
+	if (!wcd939x)
+		return -EINVAL;
+
+	pdata = dev_get_platdata(wcd939x->dev);
+
+	if (!pdata) {
+		dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (test_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask)) {
+		ret = msm_cdc_disable_ondemand_supply(wcd939x->dev,
+						wcd939x->supplies,
+						pdata->regulator,
+						pdata->num_supplies,
+						"cdc-vdd-buck");
+		if (ret == -EINVAL) {
+			dev_err_ratelimited(dev, "%s: vdd buck is not disabled\n",
+				__func__);
+			return 0;
+		}
+		clear_bit(ALLOW_BUCK_DISABLE, &wcd939x->status_mask);
+	}
+	if (wcd939x->dapm_bias_off) {
+		msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
+					      wcd939x->supplies,
+					      pdata->regulator,
+					      pdata->num_supplies,
+					      true);
+		set_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
+	}
+	return 0;
+}
+
+static int wcd939x_resume(struct device *dev)
+{
+	struct wcd939x_priv *wcd939x = NULL;
+	struct wcd939x_pdata *pdata = NULL;
+
+	if (!dev)
+		return -ENODEV;
+
+	wcd939x = dev_get_drvdata(dev);
+	if (!wcd939x)
+		return -EINVAL;
+
+	pdata = dev_get_platdata(wcd939x->dev);
+
+	if (!pdata) {
+		dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask)) {
+		msm_cdc_set_supplies_lpm_mode(wcd939x->dev,
+					      wcd939x->supplies,
+					      pdata->regulator,
+					      pdata->num_supplies,
+					      false);
+		clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd939x->status_mask);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops wcd939x_dev_pm_ops = {
+	.suspend_late = wcd939x_suspend,
+	.resume_early = wcd939x_resume,
+};
+#endif
+
+static struct platform_driver wcd939x_codec_driver = {
+	.probe = wcd939x_probe,
+	.remove = wcd939x_remove,
+	.driver = {
+		.name = "wcd939x_codec",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(wcd939x_dt_match),
+#ifdef CONFIG_PM_SLEEP
+		.pm = &wcd939x_dev_pm_ops,
+#endif
+		.suppress_bind_attrs = true,
+	},
+};
+
+module_platform_driver(wcd939x_codec_driver);
+MODULE_DESCRIPTION("WCD939X Codec driver");
+MODULE_LICENSE("GPL v2");

asoc/codecs/wcd939x/wcd939x.h

@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _WCD939X_H
+#define _WCD939X_H
+
+#include <bindings/audio-codec-port-types.h>
+
+#define WCD939X_MAX_SLAVE_CH_TYPES 13
+#define ZERO 0
+#define WCD939X_DRV_NAME "wcd939x_codec"
+
+enum {
+	WCD9390 = 0,
+	WCD9395 = 5,
+};
+
+/* from WCD to SWR DMIC events */
+enum {
+	WCD939X_EVT_SSR_DOWN,
+	WCD939X_EVT_SSR_UP,
+};
+
+struct swr_slave_ch_map {
+	u8 ch_type;
+	u8 index;
+};
+
+static const struct swr_slave_ch_map swr_slv_tx_ch_idx[] = {
+	{ADC1, 0},
+	{ADC2, 1},
+	{ADC3, 2},
+	{ADC4, 3},
+	{DMIC0, 4},
+	{DMIC1, 5},
+	{MBHC, 6},
+	{DMIC2, 6},
+	{DMIC3, 7},
+	{DMIC4, 8},
+	{DMIC5, 9},
+	{DMIC6, 10},
+	{DMIC7, 11},
+};
+
+static int swr_master_ch_map[] = {
+	ZERO,
+	SWRM_TX_PCM_OUT,
+	SWRM_TX1_CH1,
+	SWRM_TX1_CH2,
+	SWRM_TX1_CH3,
+	SWRM_TX1_CH4,
+	SWRM_TX2_CH1,
+	SWRM_TX2_CH2,
+	SWRM_TX2_CH3,
+	SWRM_TX2_CH4,
+	SWRM_TX3_CH1,
+	SWRM_TX3_CH2,
+	SWRM_TX3_CH3,
+	SWRM_TX3_CH4,
+	SWRM_TX_PCM_IN,
+};
+
+#if IS_ENABLED(CONFIG_SND_SOC_WCD939X)
+int wcd939x_info_create_codec_entry(struct snd_info_entry *codec_root,
+				    struct snd_soc_component *component);
+
+int wcd939x_get_codec_variant(struct snd_soc_component *component);
+int wcd939x_codec_force_enable_micbias_v2(struct snd_soc_component *wcd939x,
+					int event, int micb_num);
+int wcd939x_swr_dmic_register_notifier(struct snd_soc_component *wcd939x,
+                                        struct notifier_block *nblock,
+                                        bool enable);
+int wcd939x_codec_get_dev_num(struct snd_soc_component *component);
+
+static inline int wcd939x_slave_get_master_ch_val(int ch)
+{
+	int i;
+
+	for (i = 0; i < WCD939X_MAX_SLAVE_CH_TYPES; i++)
+		if (ch == swr_master_ch_map[i])
+			return i;
+	return 0;
+}
+
+static inline int wcd939x_slave_get_master_ch(int idx)
+{
+	return swr_master_ch_map[idx];
+}
+
+static inline int wcd939x_slave_get_slave_ch_val(int ch)
+{
+	int i;
+
+	for (i = 0; i < WCD939X_MAX_SLAVE_CH_TYPES; i++)
+		if (ch == swr_slv_tx_ch_idx[i].ch_type)
+			return swr_slv_tx_ch_idx[i].index;
+
+	return -EINVAL;
+}
+#else
+static inline int wcd939x_info_create_codec_entry(
+					struct snd_info_entry *codec_root,
+					struct snd_soc_component *component)
+{
+	return 0;
+}
+static inline int wcd939x_get_codec_variant(struct snd_soc_component *component)
+{
+	return 0;
+}
+static inline int wcd939x_codec_force_enable_micbias_v2(
+					struct snd_soc_component *wcd939x,
+					int event, int micb_num)
+{
+	return 0;
+}
+
+static inline int wcd939x_slave_get_master_ch_val(int ch)
+{
+	return 0;
+}
+static inline int wcd939x_slave_get_master_ch(int idx)
+{
+	return 0;
+}
+static inline int wcd939x_slave_get_slave_ch_val(int ch)
+{
+	return 0;
+}
+static int wcd939x_codec_get_dev_num(struct snd_soc_component *component)
+{
+	return 0;
+}
+#endif /* CONFIG_SND_SOC_WCD939X */
+#endif /* _WCD939X_H */

asoc/pineapple.c

@@ -30,10 +30,10 @@
 #include "device_event.h"
 #include "asoc/msm-cdc-pinctrl.h"
 #include "asoc/wcd-mbhc-v2.h"
-#include "codecs/wcd938x/wcd938x-mbhc.h"
+#include "codecs/wcd939x/wcd939x-mbhc.h"
 #include "codecs/wsa884x/wsa884x.h"
 #include "codecs/wsa883x/wsa883x.h"
-#include "codecs/wcd938x/wcd938x.h"
+#include "codecs/wcd939x/wcd939x.h"
 #include "codecs/lpass-cdc/lpass-cdc.h"
 #include <bindings/audio-codec-port-types.h>
 #include "codecs/lpass-cdc/lpass-cdc-wsa-macro.h"
@@ -161,7 +161,7 @@ static void msm_parse_upd_configuration(struct platform_device *pdev,
 		else
 			pdata->get_dev_num = wsa884x_codec_get_dev_num;
 	} else {
-		pdata->get_dev_num = wcd938x_codec_get_dev_num;
+		pdata->get_dev_num = wcd939x_codec_get_dev_num;
 	}
 
 	ret = of_property_read_u32_array(pdev->dev.of_node,
@@ -221,7 +221,7 @@ static void msm_set_upd_config(struct snd_soc_pcm_runtime *rtd)
 			memcpy(cdc_name, "wsa-codec.1", strlen("wsa-codec.1"));
 	}
 	else
-		memcpy(cdc_name, WCD938X_DRV_NAME, sizeof(WCD938X_DRV_NAME));
+		memcpy(cdc_name, WCD939X_DRV_NAME, sizeof(WCD939X_DRV_NAME));
 
 	component = snd_soc_rtdcom_lookup(rtd, cdc_name);
 	if (!component) {
@@ -1341,7 +1341,7 @@ static int msm_snd_card_late_probe(struct snd_soc_card *card)
 		return -EINVAL;
 	}
 
-	component = snd_soc_rtdcom_lookup(rtd, WCD938X_DRV_NAME);
+	component = snd_soc_rtdcom_lookup(rtd, WCD939X_DRV_NAME);
 	if (!component) {
 		pr_err("%s component is NULL\n", __func__);
 		return -EINVAL;
@@ -1351,7 +1351,7 @@ static int msm_snd_card_late_probe(struct snd_soc_card *card)
 	if (!mbhc_calibration)
 		return -ENOMEM;
 	wcd_mbhc_cfg.calibration = mbhc_calibration;
-	ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
+	ret = wcd939x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
 	if (ret) {
 		dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
 			__func__, ret);
@@ -1718,10 +1718,10 @@ static int msm_rx_tx_codec_init(struct snd_soc_pcm_runtime *rtd)
 	if (pdata->wcd_disabled)
 		goto done;
 
-	component = snd_soc_rtdcom_lookup(rtd, WCD938X_DRV_NAME);
+	component = snd_soc_rtdcom_lookup(rtd, WCD939X_DRV_NAME);
 	if (!component) {
 		pr_err("%s could not find component for %s\n",
-			__func__, WCD938X_DRV_NAME);
+			__func__, WCD939X_DRV_NAME);
 		return -EINVAL;
 	}
 	dapm = snd_soc_component_get_dapm(component);
@@ -1747,11 +1747,11 @@ static int msm_rx_tx_codec_init(struct snd_soc_pcm_runtime *rtd)
 		}
 		pdata->codec_root = entry;
 	}
-	wcd938x_info_create_codec_entry(pdata->codec_root, component);
+	wcd939x_info_create_codec_entry(pdata->codec_root, component);
 
-	codec_variant = wcd938x_get_codec_variant(component);
+	codec_variant = wcd939x_get_codec_variant(component);
 	dev_dbg(component->dev, "%s: variant %d\n", __func__, codec_variant);
-	if (codec_variant == WCD9385)
+	if (codec_variant == WCD9395)
 		ret = lpass_cdc_rx_set_fir_capability(lpass_cdc_component, true);
 	else
 		ret = lpass_cdc_rx_set_fir_capability(lpass_cdc_component, false);

audio_kernel_modules.mk

@@ -42,7 +42,9 @@ AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/swr_dmic_dlkm.ko \
 	$(KERNEL_MODULES_OUT)/wsa884x_dlkm.ko \
 	$(KERNEL_MODULES_OUT)/wsa883x_dlkm.ko \
 	$(KERNEL_MODULES_OUT)/wcd938x_dlkm.ko \
-	$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko
+	$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko \
+	$(KERNEL_MODULES_OUT)/wcd939x_dlkm.ko \
+	$(KERNEL_MODULES_OUT)/wcd939x_slave_dlkm.ko
 endif
 ifeq ($(call is-board-platform-in-list,bengal), true)
 AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/bolero_cdc_dlkm.ko \

audio_kernel_product_board.mk

@@ -29,7 +29,9 @@ PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/swr_dmic_dlkm.ko \
 	$(KERNEL_MODULES_OUT)/wsa884x_dlkm.ko \
 	$(KERNEL_MODULES_OUT)/wsa883x_dlkm.ko \
 	$(KERNEL_MODULES_OUT)/wcd938x_dlkm.ko \
-	$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko
+	$(KERNEL_MODULES_OUT)/wcd938x_slave_dlkm.ko \
+	$(KERNEL_MODULES_OUT)/wcd939x_dlkm.ko \
+	$(KERNEL_MODULES_OUT)/wcd939x_slave_dlkm.ko
 endif
 ifeq ($(call is-board-platform-in-list,bengal), true)
 PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/bolero_cdc_dlkm.ko \

config/pineappleauto.conf

@@ -28,6 +28,8 @@ export CONFIG_LPASS_CDC_RX_MACRO=m
 export CONFIG_SND_SOC_WCD9XXX_V2=m
 export CONFIG_SND_SOC_WCD938X=m
 export CONFIG_SND_SOC_WCD938X_SLAVE=m
+export CONFIG_SND_SOC_WCD939X=m
+export CONFIG_SND_SOC_WCD939X_SLAVE=m
 export CONFIG_SND_SOC_WCD_MBHC=m
 export CONFIG_SND_SOC_WCD_MBHC_ADC=m
 export CONFIG_SND_SWR_HAPTICS=m

config/pineappleautoconf.h

@@ -35,6 +35,8 @@
 #define CONFIG_SND_SOC_WCD9XXX_V2 1
 #define CONFIG_SND_SOC_WCD938X 1
 #define CONFIG_SND_SOC_WCD938X_SLAVE 1
+#define CONFIG_SND_SOC_WCD939X 1
+#define CONFIG_SND_SOC_WCD939X_SLAVE 1
 #define CONFIG_SND_SOC_WCD_MBHC 1
 #define CONFIG_SND_SOC_WCD_MBHC_ADC 1
 #define CONFIG_SND_SWR_HAPTICS 1