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- // SPDX-License-Identifier: GPL-2.0-only
- /*
- * Copyright (c) 2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
- */
- #ifndef WCD939X_REGISTERS_H
- #define WCD939X_REGISTERS_H
- #define WCD939X_BASE 0x2fff
- #define WCD939X_REG(reg) (reg - WCD939X_BASE - 1)
- enum {
- REG_NO_ACCESS,
- RD_REG,
- WR_REG,
- RD_WR_REG
- };
- #define WCD939X_ANA_BASE (WCD939X_BASE+0x01)
- #define WCD939X_ANA_PAGE (WCD939X_ANA_BASE+0x00)
- #define WCD939X_BIAS (WCD939X_ANA_BASE+0x01)
- #define WCD939X_RX_SUPPLIES (WCD939X_ANA_BASE+0x08)
- #define WCD939X_HPH (WCD939X_ANA_BASE+0x09)
- #define WCD939X_EAR (WCD939X_ANA_BASE+0x0a)
- #define WCD939X_EAR_COMPANDER_CTL (WCD939X_ANA_BASE+0x0b)
- #define WCD939X_TX_CH1 (WCD939X_ANA_BASE+0x0e)
- #define WCD939X_TX_CH2 (WCD939X_ANA_BASE+0x0f)
- #define WCD939X_TX_CH3 (WCD939X_ANA_BASE+0x10)
- #define WCD939X_TX_CH4 (WCD939X_ANA_BASE+0x11)
- #define WCD939X_MICB1_MICB2_DSP_EN_LOGIC (WCD939X_ANA_BASE+0x12)
- #define WCD939X_MICB3_DSP_EN_LOGIC (WCD939X_ANA_BASE+0x13)
- #define WCD939X_MBHC_MECH (WCD939X_ANA_BASE+0x14)
- #define WCD939X_MBHC_ELECT (WCD939X_ANA_BASE+0x15)
- #define WCD939X_MBHC_ZDET (WCD939X_ANA_BASE+0x16)
- #define WCD939X_MBHC_RESULT_1 (WCD939X_ANA_BASE+0x17)
- #define WCD939X_MBHC_RESULT_2 (WCD939X_ANA_BASE+0x18)
- #define WCD939X_MBHC_RESULT_3 (WCD939X_ANA_BASE+0x19)
- #define WCD939X_MBHC_BTN0 (WCD939X_ANA_BASE+0x1a)
- #define WCD939X_MBHC_BTN1 (WCD939X_ANA_BASE+0x1b)
- #define WCD939X_MBHC_BTN2 (WCD939X_ANA_BASE+0x1c)
- #define WCD939X_MBHC_BTN3 (WCD939X_ANA_BASE+0x1d)
- #define WCD939X_MBHC_BTN4 (WCD939X_ANA_BASE+0x1e)
- #define WCD939X_MBHC_BTN5 (WCD939X_ANA_BASE+0x1f)
- #define WCD939X_MBHC_BTN6 (WCD939X_ANA_BASE+0x20)
- #define WCD939X_MBHC_BTN7 (WCD939X_ANA_BASE+0x21)
- #define WCD939X_MICB1 (WCD939X_ANA_BASE+0x22)
- #define WCD939X_MICB2 (WCD939X_ANA_BASE+0x23)
- #define WCD939X_MICB2_RAMP (WCD939X_ANA_BASE+0x24)
- #define WCD939X_MICB3 (WCD939X_ANA_BASE+0x25)
- #define WCD939X_MICB4 (WCD939X_ANA_BASE+0x26)
- #define WCD939X_BIAS_BASE (WCD939X_BASE+0x29)
- #define WCD939X_CTL (WCD939X_BIAS_BASE+0x00)
- #define WCD939X_VBG_FINE_ADJ (WCD939X_BIAS_BASE+0x01)
- #define WCD939X_LDOL_BASE (WCD939X_BASE+0x41)
- #define WCD939X_VDDCX_ADJUST (WCD939X_LDOL_BASE+0x00)
- #define WCD939X_DISABLE_LDOL (WCD939X_LDOL_BASE+0x01)
- #define WCD939X_MBHC_BASE (WCD939X_BASE+0x57)
- #define WCD939X_CTL_CLK (WCD939X_MBHC_BASE+0x00)
- #define WCD939X_CTL_ANA (WCD939X_MBHC_BASE+0x01)
- #define WCD939X_ZDET_VNEG_CTL (WCD939X_MBHC_BASE+0x02)
- #define WCD939X_ZDET_BIAS_CTL (WCD939X_MBHC_BASE+0x03)
- #define WCD939X_CTL_BCS (WCD939X_MBHC_BASE+0x04)
- #define WCD939X_MOISTURE_DET_FSM_STATUS (WCD939X_MBHC_BASE+0x05)
- #define WCD939X_TEST_CTL (WCD939X_MBHC_BASE+0x06)
- #define WCD939X_LDOH_BASE (WCD939X_BASE+0x68)
- #define WCD939X_MODE (WCD939X_LDOH_BASE+0x00)
- #define WCD939X_LDOH_BIAS (WCD939X_LDOH_BASE+0x01)
- #define WCD939X_STB_LOADS (WCD939X_LDOH_BASE+0x02)
- #define WCD939X_SLOWRAMP (WCD939X_LDOH_BASE+0x03)
- #define WCD939X_MICB1_BASE (WCD939X_BASE+0x6c)
- #define WCD939X_TEST_CTL_1 (WCD939X_MICB1_BASE+0x00)
- #define WCD939X_TEST_CTL_2 (WCD939X_MICB1_BASE+0x01)
- #define WCD939X_TEST_CTL_3 (WCD939X_MICB1_BASE+0x02)
- #define WCD939X_MICB2_BASE (WCD939X_BASE+0x6f)
- #define WCD939X_MICB2_TEST_CTL_1 (WCD939X_MICB2_BASE+0x00)
- #define WCD939X_MICB2_TEST_CTL_2 (WCD939X_MICB2_BASE+0x01)
- #define WCD939X_MICB2_TEST_CTL_3 (WCD939X_MICB2_BASE+0x02)
- #define WCD939X_MICB3_BASE (WCD939X_BASE+0x72)
- #define WCD939X_MICB3_TEST_CTL_1 (WCD939X_MICB3_BASE+0x00)
- #define WCD939X_MICB3_TEST_CTL_2 (WCD939X_MICB3_BASE+0x01)
- #define WCD939X_MICB3_TEST_CTL_3 (WCD939X_MICB3_BASE+0x02)
- #define WCD939X_MICB4_BASE (WCD939X_BASE+0x75)
- #define WCD939X_MICB4_TEST_CTL_1 (WCD939X_MICB4_BASE+0x00)
- #define WCD939X_MICB4_TEST_CTL_2 (WCD939X_MICB4_BASE+0x01)
- #define WCD939X_MICB4_TEST_CTL_3 (WCD939X_MICB4_BASE+0x02)
- #define WCD939X_TX_COM_BASE (WCD939X_BASE+0x78)
- #define WCD939X_ADC_VCM (WCD939X_TX_COM_BASE+0x00)
- #define WCD939X_BIAS_ATEST (WCD939X_TX_COM_BASE+0x01)
- #define WCD939X_SPARE1 (WCD939X_TX_COM_BASE+0x02)
- #define WCD939X_SPARE2 (WCD939X_TX_COM_BASE+0x03)
- #define WCD939X_TXFE_DIV_CTL (WCD939X_TX_COM_BASE+0x04)
- #define WCD939X_TXFE_DIV_START (WCD939X_TX_COM_BASE+0x05)
- #define WCD939X_SPARE3 (WCD939X_TX_COM_BASE+0x06)
- #define WCD939X_SPARE4 (WCD939X_TX_COM_BASE+0x07)
- #define WCD939X_TX_1_2_BASE (WCD939X_BASE+0x80)
- #define WCD939X_TEST_EN (WCD939X_TX_1_2_BASE+0x00)
- #define WCD939X_ADC_IB (WCD939X_TX_1_2_BASE+0x01)
- #define WCD939X_ATEST_REFCTL (WCD939X_TX_1_2_BASE+0x02)
- #define WCD939X_TX_1_2_TEST_CTL (WCD939X_TX_1_2_BASE+0x03)
- #define WCD939X_TEST_BLK_EN1 (WCD939X_TX_1_2_BASE+0x04)
- #define WCD939X_TXFE1_CLKDIV (WCD939X_TX_1_2_BASE+0x05)
- #define WCD939X_SAR2_ERR (WCD939X_TX_1_2_BASE+0x06)
- #define WCD939X_SAR1_ERR (WCD939X_TX_1_2_BASE+0x07)
- #define WCD939X_TX_3_4_BASE (WCD939X_BASE+0x88)
- #define WCD939X_TX_3_4_TEST_EN (WCD939X_TX_3_4_BASE+0x00)
- #define WCD939X_TX_3_4_ADC_IB (WCD939X_TX_3_4_BASE+0x01)
- #define WCD939X_TX_3_4_ATEST_REFCTL (WCD939X_TX_3_4_BASE+0x02)
- #define WCD939X_TX_3_4_TEST_CTL (WCD939X_TX_3_4_BASE+0x03)
- #define WCD939X_TEST_BLK_EN3 (WCD939X_TX_3_4_BASE+0x04)
- #define WCD939X_TXFE3_CLKDIV (WCD939X_TX_3_4_BASE+0x05)
- #define WCD939X_SAR4_ERR (WCD939X_TX_3_4_BASE+0x06)
- #define WCD939X_SAR3_ERR (WCD939X_TX_3_4_BASE+0x07)
- #define WCD939X_TEST_BLK_EN2 (WCD939X_TX_3_4_BASE+0x08)
- #define WCD939X_TXFE2_CLKDIV (WCD939X_TX_3_4_BASE+0x09)
- #define WCD939X_TX_3_4_SPARE1 (WCD939X_TX_3_4_BASE+0x0a)
- #define WCD939X_TEST_BLK_EN4 (WCD939X_TX_3_4_BASE+0x0b)
- #define WCD939X_TXFE4_CLKDIV (WCD939X_TX_3_4_BASE+0x0c)
- #define WCD939X_TX_3_4_SPARE2 (WCD939X_TX_3_4_BASE+0x0d)
- #define WCD939X_CLASSH_BASE (WCD939X_BASE+0x98)
- #define WCD939X_MODE_1 (WCD939X_CLASSH_BASE+0x00)
- #define WCD939X_MODE_2 (WCD939X_CLASSH_BASE+0x01)
- #define WCD939X_MODE_3 (WCD939X_CLASSH_BASE+0x02)
- #define WCD939X_CTRL_VCL_1 (WCD939X_CLASSH_BASE+0x03)
- #define WCD939X_CTRL_VCL_2 (WCD939X_CLASSH_BASE+0x04)
- #define WCD939X_CTRL_CCL_1 (WCD939X_CLASSH_BASE+0x05)
- #define WCD939X_CTRL_CCL_2 (WCD939X_CLASSH_BASE+0x06)
- #define WCD939X_CTRL_CCL_3 (WCD939X_CLASSH_BASE+0x07)
- #define WCD939X_CTRL_CCL_4 (WCD939X_CLASSH_BASE+0x08)
- #define WCD939X_CTRL_CCL_5 (WCD939X_CLASSH_BASE+0x09)
- #define WCD939X_BUCK_TMUX_A_D (WCD939X_CLASSH_BASE+0x0a)
- #define WCD939X_BUCK_SW_DRV_CNTL (WCD939X_CLASSH_BASE+0x0b)
- #define WCD939X_SPARE (WCD939X_CLASSH_BASE+0x0c)
- #define WCD939X_FLYBACK_BASE (WCD939X_BASE+0xa5)
- #define WCD939X_EN (WCD939X_FLYBACK_BASE+0x00)
- #define WCD939X_VNEG_CTRL_1 (WCD939X_FLYBACK_BASE+0x01)
- #define WCD939X_VNEG_CTRL_2 (WCD939X_FLYBACK_BASE+0x02)
- #define WCD939X_VNEG_CTRL_3 (WCD939X_FLYBACK_BASE+0x03)
- #define WCD939X_VNEG_CTRL_4 (WCD939X_FLYBACK_BASE+0x04)
- #define WCD939X_VNEG_CTRL_5 (WCD939X_FLYBACK_BASE+0x05)
- #define WCD939X_VNEG_CTRL_6 (WCD939X_FLYBACK_BASE+0x06)
- #define WCD939X_VNEG_CTRL_7 (WCD939X_FLYBACK_BASE+0x07)
- #define WCD939X_VNEG_CTRL_8 (WCD939X_FLYBACK_BASE+0x08)
- #define WCD939X_VNEG_CTRL_9 (WCD939X_FLYBACK_BASE+0x09)
- #define WCD939X_VNEGDAC_CTRL_1 (WCD939X_FLYBACK_BASE+0x0a)
- #define WCD939X_VNEGDAC_CTRL_2 (WCD939X_FLYBACK_BASE+0x0b)
- #define WCD939X_VNEGDAC_CTRL_3 (WCD939X_FLYBACK_BASE+0x0c)
- #define WCD939X_CTRL_1 (WCD939X_FLYBACK_BASE+0x0d)
- #define WCD939X_FLYBACK_TEST_CTL (WCD939X_FLYBACK_BASE+0x0e)
- #define WCD939X_RX_BASE (WCD939X_BASE+0xb4)
- #define WCD939X_AUX_SW_CTL (WCD939X_RX_BASE+0x00)
- #define WCD939X_PA_AUX_IN_CONN (WCD939X_RX_BASE+0x01)
- #define WCD939X_TIMER_DIV (WCD939X_RX_BASE+0x02)
- #define WCD939X_OCP_CTL (WCD939X_RX_BASE+0x03)
- #define WCD939X_OCP_COUNT (WCD939X_RX_BASE+0x04)
- #define WCD939X_BIAS_EAR_DAC (WCD939X_RX_BASE+0x05)
- #define WCD939X_BIAS_EAR_AMP (WCD939X_RX_BASE+0x06)
- #define WCD939X_BIAS_HPH_LDO (WCD939X_RX_BASE+0x07)
- #define WCD939X_BIAS_HPH_PA (WCD939X_RX_BASE+0x08)
- #define WCD939X_BIAS_HPH_RDACBUFF_CNP2 (WCD939X_RX_BASE+0x09)
- #define WCD939X_BIAS_HPH_RDAC_LDO (WCD939X_RX_BASE+0x0a)
- #define WCD939X_BIAS_HPH_CNP1 (WCD939X_RX_BASE+0x0b)
- #define WCD939X_BIAS_HPH_LOWPOWER (WCD939X_RX_BASE+0x0c)
- #define WCD939X_BIAS_AUX_DAC (WCD939X_RX_BASE+0x0d)
- #define WCD939X_BIAS_AUX_AMP (WCD939X_RX_BASE+0x0e)
- #define WCD939X_BIAS_VNEGDAC_BLEEDER (WCD939X_RX_BASE+0x0f)
- #define WCD939X_BIAS_MISC (WCD939X_RX_BASE+0x10)
- #define WCD939X_BIAS_BUCK_RST (WCD939X_RX_BASE+0x11)
- #define WCD939X_BIAS_BUCK_VREF_ERRAMP (WCD939X_RX_BASE+0x12)
- #define WCD939X_BIAS_FLYB_ERRAMP (WCD939X_RX_BASE+0x13)
- #define WCD939X_BIAS_FLYB_BUFF (WCD939X_RX_BASE+0x14)
- #define WCD939X_BIAS_FLYB_MID_RST (WCD939X_RX_BASE+0x15)
- #define WCD939X_HPH_BASE (WCD939X_BASE+0xca)
- #define WCD939X_L_STATUS (WCD939X_HPH_BASE+0x00)
- #define WCD939X_R_STATUS (WCD939X_HPH_BASE+0x01)
- #define WCD939X_CNP_EN (WCD939X_HPH_BASE+0x02)
- #define WCD939X_CNP_WG_CTL (WCD939X_HPH_BASE+0x03)
- #define WCD939X_CNP_WG_TIME (WCD939X_HPH_BASE+0x04)
- #define WCD939X_HPH_OCP_CTL (WCD939X_HPH_BASE+0x05)
- #define WCD939X_AUTO_CHOP (WCD939X_HPH_BASE+0x06)
- #define WCD939X_CHOP_CTL (WCD939X_HPH_BASE+0x07)
- #define WCD939X_PA_CTL1 (WCD939X_HPH_BASE+0x08)
- #define WCD939X_PA_CTL2 (WCD939X_HPH_BASE+0x09)
- #define WCD939X_L_EN (WCD939X_HPH_BASE+0x0a)
- #define WCD939X_L_TEST (WCD939X_HPH_BASE+0x0b)
- #define WCD939X_L_ATEST (WCD939X_HPH_BASE+0x0c)
- #define WCD939X_R_EN (WCD939X_HPH_BASE+0x0d)
- #define WCD939X_R_TEST (WCD939X_HPH_BASE+0x0e)
- #define WCD939X_R_ATEST (WCD939X_HPH_BASE+0x0f)
- #define WCD939X_RDAC_CLK_CTL1 (WCD939X_HPH_BASE+0x10)
- #define WCD939X_RDAC_CLK_CTL2 (WCD939X_HPH_BASE+0x11)
- #define WCD939X_RDAC_LDO_CTL (WCD939X_HPH_BASE+0x12)
- #define WCD939X_RDAC_CHOP_CLK_LP_CTL (WCD939X_HPH_BASE+0x13)
- #define WCD939X_REFBUFF_UHQA_CTL (WCD939X_HPH_BASE+0x14)
- #define WCD939X_REFBUFF_LP_CTL (WCD939X_HPH_BASE+0x15)
- #define WCD939X_L_DAC_CTL (WCD939X_HPH_BASE+0x16)
- #define WCD939X_R_DAC_CTL (WCD939X_HPH_BASE+0x17)
- #define WCD939X_HPH_SURGE_BASE (WCD939X_BASE+0xe2)
- #define WCD939X_HPHLR_SURGE_COMP_SEL (WCD939X_HPH_SURGE_BASE+0x00)
- #define WCD939X_HPHLR_SURGE_EN (WCD939X_HPH_SURGE_BASE+0x01)
- #define WCD939X_HPHLR_SURGE_MISC1 (WCD939X_HPH_SURGE_BASE+0x02)
- #define WCD939X_HPHLR_SURGE_STATUS (WCD939X_HPH_SURGE_BASE+0x03)
- #define WCD939X_EAR_BASE (WCD939X_BASE+0xea)
- #define WCD939X_EAR_EN_REG (WCD939X_EAR_BASE+0x00)
- #define WCD939X_EAR_PA_CON (WCD939X_EAR_BASE+0x01)
- #define WCD939X_EAR_SP_CON (WCD939X_EAR_BASE+0x02)
- #define WCD939X_EAR_DAC_CON (WCD939X_EAR_BASE+0x03)
- #define WCD939X_EAR_CNP_FSM_CON (WCD939X_EAR_BASE+0x04)
- #define WCD939X_EAR_TEST_CTL (WCD939X_EAR_BASE+0x05)
- #define WCD939X_STATUS_REG_1 (WCD939X_EAR_BASE+0x06)
- #define WCD939X_STATUS_REG_2 (WCD939X_EAR_BASE+0x07)
- #define WCD939X_ANA_NEW_BASE (WCD939X_BASE+0x101)
- #define WCD939X_ANA_NEW_PAGE (WCD939X_ANA_NEW_BASE+0x00)
- #define WCD939X_HPH_NEW_BASE (WCD939X_BASE+0x102)
- #define WCD939X_ANA_HPH2 (WCD939X_HPH_NEW_BASE+0x00)
- #define WCD939X_ANA_HPH3 (WCD939X_HPH_NEW_BASE+0x01)
- #define WCD939X_SLEEP_BASE (WCD939X_BASE+0x104)
- #define WCD939X_SLEEP_CTL (WCD939X_SLEEP_BASE+0x00)
- #define WCD939X_WATCHDOG_CTL (WCD939X_SLEEP_BASE+0x01)
- #define WCD939X_MBHC_NEW_BASE (WCD939X_BASE+0x120)
- #define WCD939X_ELECT_REM_CLAMP_CTL (WCD939X_MBHC_NEW_BASE+0x00)
- #define WCD939X_CTL_1 (WCD939X_MBHC_NEW_BASE+0x01)
- #define WCD939X_CTL_2 (WCD939X_MBHC_NEW_BASE+0x02)
- #define WCD939X_PLUG_DETECT_CTL (WCD939X_MBHC_NEW_BASE+0x03)
- #define WCD939X_ZDET_ANA_CTL (WCD939X_MBHC_NEW_BASE+0x04)
- #define WCD939X_ZDET_RAMP_CTL (WCD939X_MBHC_NEW_BASE+0x05)
- #define WCD939X_FSM_STATUS (WCD939X_MBHC_NEW_BASE+0x06)
- #define WCD939X_ADC_RESULT (WCD939X_MBHC_NEW_BASE+0x07)
- #define WCD939X_TX_NEW_BASE (WCD939X_BASE+0x128)
- #define WCD939X_TX_CH12_MUX (WCD939X_TX_NEW_BASE+0x00)
- #define WCD939X_TX_CH34_MUX (WCD939X_TX_NEW_BASE+0x01)
- #define WCD939X_DIE_CRACK_BASE (WCD939X_BASE+0x12d)
- #define WCD939X_DIE_CRK_DET_EN (WCD939X_DIE_CRACK_BASE+0x00)
- #define WCD939X_DIE_CRK_DET_OUT (WCD939X_DIE_CRACK_BASE+0x01)
- #define WCD939X_HPH_NEW_INT_BASE (WCD939X_BASE+0x133)
- #define WCD939X_RDAC_GAIN_CTL (WCD939X_HPH_NEW_INT_BASE+0x00)
- #define WCD939X_PA_GAIN_CTL_L (WCD939X_HPH_NEW_INT_BASE+0x01)
- #define WCD939X_RDAC_VREF_CTL (WCD939X_HPH_NEW_INT_BASE+0x02)
- #define WCD939X_RDAC_OVERRIDE_CTL (WCD939X_HPH_NEW_INT_BASE+0x03)
- #define WCD939X_PA_GAIN_CTL_R (WCD939X_HPH_NEW_INT_BASE+0x04)
- #define WCD939X_PA_MISC1 (WCD939X_HPH_NEW_INT_BASE+0x05)
- #define WCD939X_PA_MISC2 (WCD939X_HPH_NEW_INT_BASE+0x06)
- #define WCD939X_PA_RDAC_MISC (WCD939X_HPH_NEW_INT_BASE+0x07)
- #define WCD939X_HPH_TIMER1 (WCD939X_HPH_NEW_INT_BASE+0x08)
- #define WCD939X_HPH_TIMER2 (WCD939X_HPH_NEW_INT_BASE+0x09)
- #define WCD939X_HPH_TIMER3 (WCD939X_HPH_NEW_INT_BASE+0x0a)
- #define WCD939X_HPH_TIMER4 (WCD939X_HPH_NEW_INT_BASE+0x0b)
- #define WCD939X_PA_RDAC_MISC2 (WCD939X_HPH_NEW_INT_BASE+0x0c)
- #define WCD939X_PA_RDAC_MISC3 (WCD939X_HPH_NEW_INT_BASE+0x0d)
- #define WCD939X_RDAC_HD2_CTL_L (WCD939X_HPH_NEW_INT_BASE+0x0e)
- #define WCD939X_RDAC_HD2_CTL_R (WCD939X_HPH_NEW_INT_BASE+0x0f)
- #define WCD939X_RX_NEW_INT_BASE (WCD939X_BASE+0x146)
- #define WCD939X_HPH_RDAC_BIAS_LOHIFI (WCD939X_RX_NEW_INT_BASE+0x00)
- #define WCD939X_HPH_RDAC_BIAS_ULP (WCD939X_RX_NEW_INT_BASE+0x01)
- #define WCD939X_HPH_RDAC_LDO_LP (WCD939X_RX_NEW_INT_BASE+0x02)
- #define WCD939X_MBHC_NEW_INT_BASE (WCD939X_BASE+0x1b0)
- #define WCD939X_MOISTURE_DET_DC_CTRL (WCD939X_MBHC_NEW_INT_BASE+0x00)
- #define WCD939X_MOISTURE_DET_POLLING_CTRL (WCD939X_MBHC_NEW_INT_BASE+0x01)
- #define WCD939X_MECH_DET_CURRENT (WCD939X_MBHC_NEW_INT_BASE+0x02)
- #define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW (WCD939X_MBHC_NEW_INT_BASE+0x03)
- #define WCD939X_EAR_INT_NEW_BASE (WCD939X_BASE+0x1b8)
- #define WCD939X_EAR_CHOPPER_CON (WCD939X_EAR_INT_NEW_BASE+0x00)
- #define WCD939X_CNP_VCM_CON1 (WCD939X_EAR_INT_NEW_BASE+0x01)
- #define WCD939X_CNP_VCM_CON2 (WCD939X_EAR_INT_NEW_BASE+0x02)
- #define WCD939X_EAR_DYNAMIC_BIAS (WCD939X_EAR_INT_NEW_BASE+0x03)
- #define WCD939X_SLEEP_INT_BASE (WCD939X_BASE+0x1d1)
- #define WCD939X_WATCHDOG_CTL_1 (WCD939X_SLEEP_INT_BASE+0x00)
- #define WCD939X_WATCHDOG_CTL_2 (WCD939X_SLEEP_INT_BASE+0x01)
- #define WCD939X_DIE_CRACK_INT_BASE (WCD939X_BASE+0x1d4)
- #define WCD939X_DIE_CRK_DET_INT1 (WCD939X_DIE_CRACK_INT_BASE+0x00)
- #define WCD939X_DIE_CRK_DET_INT2 (WCD939X_DIE_CRACK_INT_BASE+0x01)
- #define WCD939X_TX_COM_NEW_INT_BASE (WCD939X_BASE+0x1d6)
- #define WCD939X_TXFE_DIVSTOP_L2 (WCD939X_TX_COM_NEW_INT_BASE+0x00)
- #define WCD939X_TXFE_DIVSTOP_L1 (WCD939X_TX_COM_NEW_INT_BASE+0x01)
- #define WCD939X_TXFE_DIVSTOP_L0 (WCD939X_TX_COM_NEW_INT_BASE+0x02)
- #define WCD939X_TXFE_DIVSTOP_ULP1P2M (WCD939X_TX_COM_NEW_INT_BASE+0x03)
- #define WCD939X_TXFE_DIVSTOP_ULP0P6M (WCD939X_TX_COM_NEW_INT_BASE+0x04)
- #define WCD939X_TXFE_ICTRL_STG1_L2L1 (WCD939X_TX_COM_NEW_INT_BASE+0x05)
- #define WCD939X_TXFE_ICTRL_STG1_L0 (WCD939X_TX_COM_NEW_INT_BASE+0x06)
- #define WCD939X_TXFE_ICTRL_STG1_ULP (WCD939X_TX_COM_NEW_INT_BASE+0x07)
- #define WCD939X_TXFE_ICTRL_STG2MAIN_L2L1 (WCD939X_TX_COM_NEW_INT_BASE+0x08)
- #define WCD939X_TXFE_ICTRL_STG2MAIN_L0 (WCD939X_TX_COM_NEW_INT_BASE+0x09)
- #define WCD939X_TXFE_ICTRL_STG2MAIN_ULP (WCD939X_TX_COM_NEW_INT_BASE+0x0a)
- #define WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0 (WCD939X_TX_COM_NEW_INT_BASE+0x0b)
- #define WCD939X_TXFE_ICTRL_STG2CASC_ULP (WCD939X_TX_COM_NEW_INT_BASE+0x0c)
- #define WCD939X_TXADC_SCBIAS_L2L1 (WCD939X_TX_COM_NEW_INT_BASE+0x0d)
- #define WCD939X_TXADC_SCBIAS_L0ULP (WCD939X_TX_COM_NEW_INT_BASE+0x0e)
- #define WCD939X_TXADC_INT_L2 (WCD939X_TX_COM_NEW_INT_BASE+0x0f)
- #define WCD939X_TXADC_INT_L1 (WCD939X_TX_COM_NEW_INT_BASE+0x10)
- #define WCD939X_TXADC_INT_L0 (WCD939X_TX_COM_NEW_INT_BASE+0x11)
- #define WCD939X_TXADC_INT_ULP (WCD939X_TX_COM_NEW_INT_BASE+0x12)
- #define WCD939X_DIGITAL_BASE (WCD939X_BASE+0x401)
- #define WCD939X_DIGITAL_PAGE (WCD939X_DIGITAL_BASE+0x00)
- #define WCD939X_CHIP_ID0 (WCD939X_DIGITAL_BASE+0x01)
- #define WCD939X_CHIP_ID1 (WCD939X_DIGITAL_BASE+0x02)
- #define WCD939X_CHIP_ID2 (WCD939X_DIGITAL_BASE+0x03)
- #define WCD939X_CHIP_ID3 (WCD939X_DIGITAL_BASE+0x04)
- #define WCD939X_SWR_TX_CLK_RATE (WCD939X_DIGITAL_BASE+0x05)
- #define WCD939X_CDC_RST_CTL (WCD939X_DIGITAL_BASE+0x06)
- #define WCD939X_TOP_CLK_CFG (WCD939X_DIGITAL_BASE+0x07)
- #define WCD939X_CDC_ANA_CLK_CTL (WCD939X_DIGITAL_BASE+0x08)
- #define WCD939X_CDC_DIG_CLK_CTL (WCD939X_DIGITAL_BASE+0x09)
- #define WCD939X_SWR_RST_EN (WCD939X_DIGITAL_BASE+0x0a)
- #define WCD939X_CDC_PATH_MODE (WCD939X_DIGITAL_BASE+0x0b)
- #define WCD939X_CDC_RX_RST (WCD939X_DIGITAL_BASE+0x0c)
- #define WCD939X_CDC_RX0_CTL (WCD939X_DIGITAL_BASE+0x0d)
- #define WCD939X_CDC_RX1_CTL (WCD939X_DIGITAL_BASE+0x0e)
- #define WCD939X_CDC_RX2_CTL (WCD939X_DIGITAL_BASE+0x0f)
- #define WCD939X_CDC_TX_ANA_MODE_0_1 (WCD939X_DIGITAL_BASE+0x10)
- #define WCD939X_CDC_TX_ANA_MODE_2_3 (WCD939X_DIGITAL_BASE+0x11)
- #define WCD939X_CDC_COMP_CTL_0 (WCD939X_DIGITAL_BASE+0x14)
- #define WCD939X_CDC_ANA_TX_CLK_CTL (WCD939X_DIGITAL_BASE+0x17)
- #define WCD939X_CDC_HPH_DSM_A1_0 (WCD939X_DIGITAL_BASE+0x18)
- #define WCD939X_CDC_HPH_DSM_A1_1 (WCD939X_DIGITAL_BASE+0x19)
- #define WCD939X_CDC_HPH_DSM_A2_0 (WCD939X_DIGITAL_BASE+0x1a)
- #define WCD939X_CDC_HPH_DSM_A2_1 (WCD939X_DIGITAL_BASE+0x1b)
- #define WCD939X_CDC_HPH_DSM_A3_0 (WCD939X_DIGITAL_BASE+0x1c)
- #define WCD939X_CDC_HPH_DSM_A3_1 (WCD939X_DIGITAL_BASE+0x1d)
- #define WCD939X_CDC_HPH_DSM_A4_0 (WCD939X_DIGITAL_BASE+0x1e)
- #define WCD939X_CDC_HPH_DSM_A4_1 (WCD939X_DIGITAL_BASE+0x1f)
- #define WCD939X_CDC_HPH_DSM_A5_0 (WCD939X_DIGITAL_BASE+0x20)
- #define WCD939X_CDC_HPH_DSM_A5_1 (WCD939X_DIGITAL_BASE+0x21)
- #define WCD939X_CDC_HPH_DSM_A6_0 (WCD939X_DIGITAL_BASE+0x22)
- #define WCD939X_CDC_HPH_DSM_A7_0 (WCD939X_DIGITAL_BASE+0x23)
- #define WCD939X_CDC_HPH_DSM_C_0 (WCD939X_DIGITAL_BASE+0x24)
- #define WCD939X_CDC_HPH_DSM_C_1 (WCD939X_DIGITAL_BASE+0x25)
- #define WCD939X_CDC_HPH_DSM_C_2 (WCD939X_DIGITAL_BASE+0x26)
- #define WCD939X_CDC_HPH_DSM_C_3 (WCD939X_DIGITAL_BASE+0x27)
- #define WCD939X_CDC_HPH_DSM_R1 (WCD939X_DIGITAL_BASE+0x28)
- #define WCD939X_CDC_HPH_DSM_R2 (WCD939X_DIGITAL_BASE+0x29)
- #define WCD939X_CDC_HPH_DSM_R3 (WCD939X_DIGITAL_BASE+0x2a)
- #define WCD939X_CDC_HPH_DSM_R4 (WCD939X_DIGITAL_BASE+0x2b)
- #define WCD939X_CDC_HPH_DSM_R5 (WCD939X_DIGITAL_BASE+0x2c)
- #define WCD939X_CDC_HPH_DSM_R6 (WCD939X_DIGITAL_BASE+0x2d)
- #define WCD939X_CDC_HPH_DSM_R7 (WCD939X_DIGITAL_BASE+0x2e)
- #define WCD939X_CDC_EAR_DSM_A1_0 (WCD939X_DIGITAL_BASE+0x2f)
- #define WCD939X_CDC_EAR_DSM_A1_1 (WCD939X_DIGITAL_BASE+0x30)
- #define WCD939X_CDC_EAR_DSM_A2_0 (WCD939X_DIGITAL_BASE+0x31)
- #define WCD939X_CDC_EAR_DSM_A2_1 (WCD939X_DIGITAL_BASE+0x32)
- #define WCD939X_CDC_EAR_DSM_A3_0 (WCD939X_DIGITAL_BASE+0x33)
- #define WCD939X_CDC_EAR_DSM_A3_1 (WCD939X_DIGITAL_BASE+0x34)
- #define WCD939X_CDC_EAR_DSM_A4_0 (WCD939X_DIGITAL_BASE+0x35)
- #define WCD939X_CDC_EAR_DSM_A4_1 (WCD939X_DIGITAL_BASE+0x36)
- #define WCD939X_CDC_EAR_DSM_A5_0 (WCD939X_DIGITAL_BASE+0x37)
- #define WCD939X_CDC_EAR_DSM_A5_1 (WCD939X_DIGITAL_BASE+0x38)
- #define WCD939X_CDC_EAR_DSM_A6_0 (WCD939X_DIGITAL_BASE+0x39)
- #define WCD939X_CDC_EAR_DSM_A7_0 (WCD939X_DIGITAL_BASE+0x3a)
- #define WCD939X_CDC_EAR_DSM_C_0 (WCD939X_DIGITAL_BASE+0x3b)
- #define WCD939X_CDC_EAR_DSM_C_1 (WCD939X_DIGITAL_BASE+0x3c)
- #define WCD939X_CDC_EAR_DSM_C_2 (WCD939X_DIGITAL_BASE+0x3d)
- #define WCD939X_CDC_EAR_DSM_C_3 (WCD939X_DIGITAL_BASE+0x3e)
- #define WCD939X_CDC_EAR_DSM_R1 (WCD939X_DIGITAL_BASE+0x3f)
- #define WCD939X_CDC_EAR_DSM_R2 (WCD939X_DIGITAL_BASE+0x40)
- #define WCD939X_CDC_EAR_DSM_R3 (WCD939X_DIGITAL_BASE+0x41)
- #define WCD939X_CDC_EAR_DSM_R4 (WCD939X_DIGITAL_BASE+0x42)
- #define WCD939X_CDC_EAR_DSM_R5 (WCD939X_DIGITAL_BASE+0x43)
- #define WCD939X_CDC_EAR_DSM_R6 (WCD939X_DIGITAL_BASE+0x44)
- #define WCD939X_CDC_EAR_DSM_R7 (WCD939X_DIGITAL_BASE+0x45)
- #define WCD939X_CDC_HPH_GAIN_RX_0 (WCD939X_DIGITAL_BASE+0x46)
- #define WCD939X_CDC_HPH_GAIN_RX_1 (WCD939X_DIGITAL_BASE+0x47)
- #define WCD939X_CDC_HPH_GAIN_DSD_0 (WCD939X_DIGITAL_BASE+0x48)
- #define WCD939X_CDC_HPH_GAIN_DSD_1 (WCD939X_DIGITAL_BASE+0x49)
- #define WCD939X_CDC_HPH_GAIN_DSD_2 (WCD939X_DIGITAL_BASE+0x4a)
- #define WCD939X_CDC_EAR_GAIN_DSD_0 (WCD939X_DIGITAL_BASE+0x4b)
- #define WCD939X_CDC_EAR_GAIN_DSD_1 (WCD939X_DIGITAL_BASE+0x4c)
- #define WCD939X_CDC_EAR_GAIN_DSD_2 (WCD939X_DIGITAL_BASE+0x4d)
- #define WCD939X_CDC_HPH_GAIN_CTL (WCD939X_DIGITAL_BASE+0x4e)
- #define WCD939X_CDC_EAR_GAIN_CTL (WCD939X_DIGITAL_BASE+0x4f)
- #define WCD939X_CDC_EAR_PATH_CTL (WCD939X_DIGITAL_BASE+0x50)
- #define WCD939X_CDC_SWR_CLH (WCD939X_DIGITAL_BASE+0x51)
- #define WCD939X_SWR_CLH_BYP (WCD939X_DIGITAL_BASE+0x52)
- #define WCD939X_CDC_TX0_CTL (WCD939X_DIGITAL_BASE+0x53)
- #define WCD939X_CDC_TX1_CTL (WCD939X_DIGITAL_BASE+0x54)
- #define WCD939X_CDC_TX2_CTL (WCD939X_DIGITAL_BASE+0x55)
- #define WCD939X_CDC_TX_RST (WCD939X_DIGITAL_BASE+0x56)
- #define WCD939X_CDC_REQ_CTL (WCD939X_DIGITAL_BASE+0x57)
- #define WCD939X_CDC_RST (WCD939X_DIGITAL_BASE+0x58)
- #define WCD939X_CDC_AMIC_CTL (WCD939X_DIGITAL_BASE+0x5a)
- #define WCD939X_CDC_DMIC_CTL (WCD939X_DIGITAL_BASE+0x5b)
- #define WCD939X_CDC_DMIC1_CTL (WCD939X_DIGITAL_BASE+0x5c)
- #define WCD939X_CDC_DMIC2_CTL (WCD939X_DIGITAL_BASE+0x5d)
- #define WCD939X_CDC_DMIC3_CTL (WCD939X_DIGITAL_BASE+0x5e)
- #define WCD939X_CDC_DMIC4_CTL (WCD939X_DIGITAL_BASE+0x5f)
- #define WCD939X_EFUSE_PRG_CTL (WCD939X_DIGITAL_BASE+0x60)
- #define WCD939X_EFUSE_CTL (WCD939X_DIGITAL_BASE+0x61)
- #define WCD939X_CDC_DMIC_RATE_1_2 (WCD939X_DIGITAL_BASE+0x62)
- #define WCD939X_CDC_DMIC_RATE_3_4 (WCD939X_DIGITAL_BASE+0x63)
- #define WCD939X_PDM_WD_CTL0 (WCD939X_DIGITAL_BASE+0x65)
- #define WCD939X_PDM_WD_CTL1 (WCD939X_DIGITAL_BASE+0x66)
- #define WCD939X_PDM_WD_CTL2 (WCD939X_DIGITAL_BASE+0x67)
- #define WCD939X_INTR_MODE (WCD939X_DIGITAL_BASE+0x6a)
- #define WCD939X_INTR_MASK_0 (WCD939X_DIGITAL_BASE+0x6b)
- #define WCD939X_INTR_MASK_1 (WCD939X_DIGITAL_BASE+0x6c)
- #define WCD939X_INTR_MASK_2 (WCD939X_DIGITAL_BASE+0x6d)
- #define WCD939X_INTR_STATUS_0 (WCD939X_DIGITAL_BASE+0x6e)
- #define WCD939X_INTR_STATUS_1 (WCD939X_DIGITAL_BASE+0x6f)
- #define WCD939X_INTR_STATUS_2 (WCD939X_DIGITAL_BASE+0x70)
- #define WCD939X_INTR_CLEAR_0 (WCD939X_DIGITAL_BASE+0x71)
- #define WCD939X_INTR_CLEAR_1 (WCD939X_DIGITAL_BASE+0x72)
- #define WCD939X_INTR_CLEAR_2 (WCD939X_DIGITAL_BASE+0x73)
- #define WCD939X_INTR_LEVEL_0 (WCD939X_DIGITAL_BASE+0x74)
- #define WCD939X_INTR_LEVEL_1 (WCD939X_DIGITAL_BASE+0x75)
- #define WCD939X_INTR_LEVEL_2 (WCD939X_DIGITAL_BASE+0x76)
- #define WCD939X_INTR_SET_0 (WCD939X_DIGITAL_BASE+0x77)
- #define WCD939X_INTR_SET_1 (WCD939X_DIGITAL_BASE+0x78)
- #define WCD939X_INTR_SET_2 (WCD939X_DIGITAL_BASE+0x79)
- #define WCD939X_INTR_TEST_0 (WCD939X_DIGITAL_BASE+0x7a)
- #define WCD939X_INTR_TEST_1 (WCD939X_DIGITAL_BASE+0x7b)
- #define WCD939X_INTR_TEST_2 (WCD939X_DIGITAL_BASE+0x7c)
- #define WCD939X_TX_MODE_DBG_EN (WCD939X_DIGITAL_BASE+0x7f)
- #define WCD939X_TX_MODE_DBG_0_1 (WCD939X_DIGITAL_BASE+0x80)
- #define WCD939X_TX_MODE_DBG_2_3 (WCD939X_DIGITAL_BASE+0x81)
- #define WCD939X_LB_IN_SEL_CTL (WCD939X_DIGITAL_BASE+0x82)
- #define WCD939X_LOOP_BACK_MODE (WCD939X_DIGITAL_BASE+0x83)
- #define WCD939X_SWR_DAC_TEST (WCD939X_DIGITAL_BASE+0x84)
- #define WCD939X_SWR_HM_TEST_RX_0 (WCD939X_DIGITAL_BASE+0x85)
- #define WCD939X_SWR_HM_TEST_TX_0 (WCD939X_DIGITAL_BASE+0x86)
- #define WCD939X_SWR_HM_TEST_RX_1 (WCD939X_DIGITAL_BASE+0x87)
- #define WCD939X_SWR_HM_TEST_TX_1 (WCD939X_DIGITAL_BASE+0x88)
- #define WCD939X_SWR_HM_TEST_TX_2 (WCD939X_DIGITAL_BASE+0x89)
- #define WCD939X_SWR_HM_TEST_0 (WCD939X_DIGITAL_BASE+0x8a)
- #define WCD939X_SWR_HM_TEST_1 (WCD939X_DIGITAL_BASE+0x8b)
- #define WCD939X_PAD_CTL_SWR_0 (WCD939X_DIGITAL_BASE+0x8c)
- #define WCD939X_PAD_CTL_SWR_1 (WCD939X_DIGITAL_BASE+0x8d)
- #define WCD939X_I2C_CTL (WCD939X_DIGITAL_BASE+0x8e)
- #define WCD939X_CDC_TX_TANGGU_SW_MODE (WCD939X_DIGITAL_BASE+0x8f)
- #define WCD939X_EFUSE_TEST_CTL_0 (WCD939X_DIGITAL_BASE+0x90)
- #define WCD939X_EFUSE_TEST_CTL_1 (WCD939X_DIGITAL_BASE+0x91)
- #define WCD939X_EFUSE_T_DATA_0 (WCD939X_DIGITAL_BASE+0x92)
- #define WCD939X_EFUSE_T_DATA_1 (WCD939X_DIGITAL_BASE+0x93)
- #define WCD939X_PAD_CTL_PDM_RX0 (WCD939X_DIGITAL_BASE+0x94)
- #define WCD939X_PAD_CTL_PDM_RX1 (WCD939X_DIGITAL_BASE+0x95)
- #define WCD939X_PAD_CTL_PDM_TX0 (WCD939X_DIGITAL_BASE+0x96)
- #define WCD939X_PAD_CTL_PDM_TX1 (WCD939X_DIGITAL_BASE+0x97)
- #define WCD939X_PAD_CTL_PDM_TX2 (WCD939X_DIGITAL_BASE+0x98)
- #define WCD939X_PAD_INP_DIS_0 (WCD939X_DIGITAL_BASE+0x99)
- #define WCD939X_PAD_INP_DIS_1 (WCD939X_DIGITAL_BASE+0x9a)
- #define WCD939X_DRIVE_STRENGTH_0 (WCD939X_DIGITAL_BASE+0x9b)
- #define WCD939X_DRIVE_STRENGTH_1 (WCD939X_DIGITAL_BASE+0x9c)
- #define WCD939X_DRIVE_STRENGTH_2 (WCD939X_DIGITAL_BASE+0x9d)
- #define WCD939X_RX_DATA_EDGE_CTL (WCD939X_DIGITAL_BASE+0x9e)
- #define WCD939X_TX_DATA_EDGE_CTL (WCD939X_DIGITAL_BASE+0x9f)
- #define WCD939X_GPIO_MODE (WCD939X_DIGITAL_BASE+0xa0)
- #define WCD939X_PIN_CTL_OE (WCD939X_DIGITAL_BASE+0xa1)
- #define WCD939X_PIN_CTL_DATA_0 (WCD939X_DIGITAL_BASE+0xa2)
- #define WCD939X_PIN_CTL_DATA_1 (WCD939X_DIGITAL_BASE+0xa3)
- #define WCD939X_PIN_STATUS_0 (WCD939X_DIGITAL_BASE+0xa4)
- #define WCD939X_PIN_STATUS_1 (WCD939X_DIGITAL_BASE+0xa5)
- #define WCD939X_DIG_DEBUG_CTL (WCD939X_DIGITAL_BASE+0xa6)
- #define WCD939X_DIG_DEBUG_EN (WCD939X_DIGITAL_BASE+0xa7)
- #define WCD939X_ANA_CSR_DBG_ADD (WCD939X_DIGITAL_BASE+0xa8)
- #define WCD939X_ANA_CSR_DBG_CTL (WCD939X_DIGITAL_BASE+0xa9)
- #define WCD939X_SSP_DBG (WCD939X_DIGITAL_BASE+0xaa)
- #define WCD939X_MODE_STATUS_0 (WCD939X_DIGITAL_BASE+0xab)
- #define WCD939X_MODE_STATUS_1 (WCD939X_DIGITAL_BASE+0xac)
- #define WCD939X_SPARE_0 (WCD939X_DIGITAL_BASE+0xad)
- #define WCD939X_SPARE_1 (WCD939X_DIGITAL_BASE+0xae)
- #define WCD939X_SPARE_2 (WCD939X_DIGITAL_BASE+0xaf)
- #define WCD939X_EFUSE_REG_0 (WCD939X_DIGITAL_BASE+0xb0)
- #define WCD939X_EFUSE_REG_1 (WCD939X_DIGITAL_BASE+0xb1)
- #define WCD939X_EFUSE_REG_2 (WCD939X_DIGITAL_BASE+0xb2)
- #define WCD939X_EFUSE_REG_3 (WCD939X_DIGITAL_BASE+0xb3)
- #define WCD939X_EFUSE_REG_4 (WCD939X_DIGITAL_BASE+0xb4)
- #define WCD939X_EFUSE_REG_5 (WCD939X_DIGITAL_BASE+0xb5)
- #define WCD939X_EFUSE_REG_6 (WCD939X_DIGITAL_BASE+0xb6)
- #define WCD939X_EFUSE_REG_7 (WCD939X_DIGITAL_BASE+0xb7)
- #define WCD939X_EFUSE_REG_8 (WCD939X_DIGITAL_BASE+0xb8)
- #define WCD939X_EFUSE_REG_9 (WCD939X_DIGITAL_BASE+0xb9)
- #define WCD939X_EFUSE_REG_10 (WCD939X_DIGITAL_BASE+0xba)
- #define WCD939X_EFUSE_REG_11 (WCD939X_DIGITAL_BASE+0xbb)
- #define WCD939X_EFUSE_REG_12 (WCD939X_DIGITAL_BASE+0xbc)
- #define WCD939X_EFUSE_REG_13 (WCD939X_DIGITAL_BASE+0xbd)
- #define WCD939X_EFUSE_REG_14 (WCD939X_DIGITAL_BASE+0xbe)
- #define WCD939X_EFUSE_REG_15 (WCD939X_DIGITAL_BASE+0xbf)
- #define WCD939X_EFUSE_REG_16 (WCD939X_DIGITAL_BASE+0xc0)
- #define WCD939X_EFUSE_REG_17 (WCD939X_DIGITAL_BASE+0xc1)
- #define WCD939X_EFUSE_REG_18 (WCD939X_DIGITAL_BASE+0xc2)
- #define WCD939X_EFUSE_REG_19 (WCD939X_DIGITAL_BASE+0xc3)
- #define WCD939X_EFUSE_REG_20 (WCD939X_DIGITAL_BASE+0xc4)
- #define WCD939X_EFUSE_REG_21 (WCD939X_DIGITAL_BASE+0xc5)
- #define WCD939X_EFUSE_REG_22 (WCD939X_DIGITAL_BASE+0xc6)
- #define WCD939X_EFUSE_REG_23 (WCD939X_DIGITAL_BASE+0xc7)
- #define WCD939X_EFUSE_REG_24 (WCD939X_DIGITAL_BASE+0xc8)
- #define WCD939X_EFUSE_REG_25 (WCD939X_DIGITAL_BASE+0xc9)
- #define WCD939X_EFUSE_REG_26 (WCD939X_DIGITAL_BASE+0xca)
- #define WCD939X_EFUSE_REG_27 (WCD939X_DIGITAL_BASE+0xcb)
- #define WCD939X_EFUSE_REG_28 (WCD939X_DIGITAL_BASE+0xcc)
- #define WCD939X_EFUSE_REG_29 (WCD939X_DIGITAL_BASE+0xcd)
- #define WCD939X_EFUSE_REG_30 (WCD939X_DIGITAL_BASE+0xce)
- #define WCD939X_EFUSE_REG_31 (WCD939X_DIGITAL_BASE+0xcf)
- #define WCD939X_TX_REQ_FB_CTL_0 (WCD939X_DIGITAL_BASE+0xd0)
- #define WCD939X_TX_REQ_FB_CTL_1 (WCD939X_DIGITAL_BASE+0xd1)
- #define WCD939X_TX_REQ_FB_CTL_2 (WCD939X_DIGITAL_BASE+0xd2)
- #define WCD939X_TX_REQ_FB_CTL_3 (WCD939X_DIGITAL_BASE+0xd3)
- #define WCD939X_TX_REQ_FB_CTL_4 (WCD939X_DIGITAL_BASE+0xd4)
- #define WCD939X_DEM_BYPASS_DATA0 (WCD939X_DIGITAL_BASE+0xd5)
- #define WCD939X_DEM_BYPASS_DATA1 (WCD939X_DIGITAL_BASE+0xd6)
- #define WCD939X_DEM_BYPASS_DATA2 (WCD939X_DIGITAL_BASE+0xd7)
- #define WCD939X_DEM_BYPASS_DATA3 (WCD939X_DIGITAL_BASE+0xd8)
- #define WCD939X_DEM_SECOND_ORDER (WCD939X_DIGITAL_BASE+0xd9)
- #define WCD939X_DSM_CTRL (WCD939X_DIGITAL_BASE+0xda)
- #define WCD939X_DSM_0_STATIC_DATA_0 (WCD939X_DIGITAL_BASE+0xdb)
- #define WCD939X_DSM_0_STATIC_DATA_1 (WCD939X_DIGITAL_BASE+0xdc)
- #define WCD939X_DSM_0_STATIC_DATA_2 (WCD939X_DIGITAL_BASE+0xdd)
- #define WCD939X_DSM_0_STATIC_DATA_3 (WCD939X_DIGITAL_BASE+0xde)
- #define WCD939X_DSM_1_STATIC_DATA_0 (WCD939X_DIGITAL_BASE+0xdf)
- #define WCD939X_DSM_1_STATIC_DATA_1 (WCD939X_DIGITAL_BASE+0xe0)
- #define WCD939X_DSM_1_STATIC_DATA_2 (WCD939X_DIGITAL_BASE+0xe1)
- #define WCD939X_DSM_1_STATIC_DATA_3 (WCD939X_DIGITAL_BASE+0xe2)
- #define WCD939X_RX_PAGE (WCD939X_RX_BASE+0x00)
- #define WCD939X_TOP_CFG0 (WCD939X_RX_BASE+0x01)
- #define WCD939X_HPHL_COMP_WR_LSB (WCD939X_RX_BASE+0x02)
- #define WCD939X_HPHL_COMP_WR_MSB (WCD939X_RX_BASE+0x03)
- #define WCD939X_HPHL_COMP_LUT (WCD939X_RX_BASE+0x04)
- #define WCD939X_HPHL_COMP_RD_LSB (WCD939X_RX_BASE+0x05)
- #define WCD939X_HPHL_COMP_RD_MSB (WCD939X_RX_BASE+0x06)
- #define WCD939X_HPHR_COMP_WR_LSB (WCD939X_RX_BASE+0x07)
- #define WCD939X_HPHR_COMP_WR_MSB (WCD939X_RX_BASE+0x08)
- #define WCD939X_HPHR_COMP_LUT (WCD939X_RX_BASE+0x09)
- #define WCD939X_HPHR_COMP_RD_LSB (WCD939X_RX_BASE+0x0a)
- #define WCD939X_HPHR_COMP_RD_MSB (WCD939X_RX_BASE+0x0b)
- #define WCD939X_DSD0_DEBUG_CFG1 (WCD939X_RX_BASE+0x0c)
- #define WCD939X_DSD0_DEBUG_CFG2 (WCD939X_RX_BASE+0x0d)
- #define WCD939X_DSD0_DEBUG_CFG3 (WCD939X_RX_BASE+0x0e)
- #define WCD939X_DSD0_DEBUG_CFG4 (WCD939X_RX_BASE+0x0f)
- #define WCD939X_DSD0_DEBUG_CFG5 (WCD939X_RX_BASE+0x10)
- #define WCD939X_DSD0_DEBUG_CFG6 (WCD939X_RX_BASE+0x11)
- #define WCD939X_DSD1_DEBUG_CFG1 (WCD939X_RX_BASE+0x12)
- #define WCD939X_DSD1_DEBUG_CFG2 (WCD939X_RX_BASE+0x13)
- #define WCD939X_DSD1_DEBUG_CFG3 (WCD939X_RX_BASE+0x14)
- #define WCD939X_DSD1_DEBUG_CFG4 (WCD939X_RX_BASE+0x15)
- #define WCD939X_DSD1_DEBUG_CFG5 (WCD939X_RX_BASE+0x16)
- #define WCD939X_DSD1_DEBUG_CFG6 (WCD939X_RX_BASE+0x17)
- #define WCD939X_HPHL_RX_PATH_CFG0 (WCD939X_RX_BASE+0x1c)
- #define WCD939X_HPHL_RX_PATH_CFG1 (WCD939X_RX_BASE+0x1d)
- #define WCD939X_HPHR_RX_PATH_CFG0 (WCD939X_RX_BASE+0x1e)
- #define WCD939X_HPHR_RX_PATH_CFG1 (WCD939X_RX_BASE+0x1f)
- #define WCD939X_RX_PATH_CFG2 (WCD939X_RX_BASE+0x20)
- #define WCD939X_HPHL_RX_PATH_SEC0 (WCD939X_RX_BASE+0x21)
- #define WCD939X_HPHL_RX_PATH_SEC1 (WCD939X_RX_BASE+0x22)
- #define WCD939X_HPHL_RX_PATH_SEC2 (WCD939X_RX_BASE+0x23)
- #define WCD939X_HPHL_RX_PATH_SEC3 (WCD939X_RX_BASE+0x24)
- #define WCD939X_HPHR_RX_PATH_SEC0 (WCD939X_RX_BASE+0x25)
- #define WCD939X_HPHR_RX_PATH_SEC1 (WCD939X_RX_BASE+0x26)
- #define WCD939X_HPHR_RX_PATH_SEC2 (WCD939X_RX_BASE+0x27)
- #define WCD939X_HPHR_RX_PATH_SEC3 (WCD939X_RX_BASE+0x28)
- #define WCD939X_RX_PATH_SEC4 (WCD939X_RX_BASE+0x29)
- #define WCD939X_RX_PATH_SEC5 (WCD939X_RX_BASE+0x2a)
- #define WCD939X_COMPANDER_HPHL_BASE (WCD939X_BASE+0x541)
- #define WCD939X_CTL0 (WCD939X_COMPANDER_HPHL_BASE+0x00)
- #define WCD939X_CTL1 (WCD939X_COMPANDER_HPHL_BASE+0x01)
- #define WCD939X_CTL2 (WCD939X_COMPANDER_HPHL_BASE+0x02)
- #define WCD939X_CTL3 (WCD939X_COMPANDER_HPHL_BASE+0x03)
- #define WCD939X_CTL4 (WCD939X_COMPANDER_HPHL_BASE+0x04)
- #define WCD939X_CTL5 (WCD939X_COMPANDER_HPHL_BASE+0x05)
- #define WCD939X_CTL6 (WCD939X_COMPANDER_HPHL_BASE+0x06)
- #define WCD939X_CTL7 (WCD939X_COMPANDER_HPHL_BASE+0x07)
- #define WCD939X_CTL8 (WCD939X_COMPANDER_HPHL_BASE+0x08)
- #define WCD939X_CTL9 (WCD939X_COMPANDER_HPHL_BASE+0x09)
- #define WCD939X_CTL10 (WCD939X_COMPANDER_HPHL_BASE+0x0a)
- #define WCD939X_CTL11 (WCD939X_COMPANDER_HPHL_BASE+0x0b)
- #define WCD939X_CTL12 (WCD939X_COMPANDER_HPHL_BASE+0x0c)
- #define WCD939X_CTL13 (WCD939X_COMPANDER_HPHL_BASE+0x0d)
- #define WCD939X_CTL14 (WCD939X_COMPANDER_HPHL_BASE+0x0e)
- #define WCD939X_CTL15 (WCD939X_COMPANDER_HPHL_BASE+0x0f)
- #define WCD939X_CTL16 (WCD939X_COMPANDER_HPHL_BASE+0x10)
- #define WCD939X_CTL17 (WCD939X_COMPANDER_HPHL_BASE+0x11)
- #define WCD939X_CTL18 (WCD939X_COMPANDER_HPHL_BASE+0x12)
- #define WCD939X_CTL19 (WCD939X_COMPANDER_HPHL_BASE+0x13)
- #define WCD939X_R_BASE (WCD939X_BASE+0x561)
- #define WCD939X_R_CTL0 (WCD939X_R_BASE+0x00)
- #define WCD939X_R_CTL1 (WCD939X_R_BASE+0x01)
- #define WCD939X_R_CTL2 (WCD939X_R_BASE+0x02)
- #define WCD939X_R_CTL3 (WCD939X_R_BASE+0x03)
- #define WCD939X_R_CTL4 (WCD939X_R_BASE+0x04)
- #define WCD939X_R_CTL5 (WCD939X_R_BASE+0x05)
- #define WCD939X_R_CTL6 (WCD939X_R_BASE+0x06)
- #define WCD939X_R_CTL7 (WCD939X_R_BASE+0x07)
- #define WCD939X_R_CTL8 (WCD939X_R_BASE+0x08)
- #define WCD939X_R_CTL9 (WCD939X_R_BASE+0x09)
- #define WCD939X_R_CTL10 (WCD939X_R_BASE+0x0a)
- #define WCD939X_R_CTL11 (WCD939X_R_BASE+0x0b)
- #define WCD939X_R_CTL12 (WCD939X_R_BASE+0x0c)
- #define WCD939X_R_CTL13 (WCD939X_R_BASE+0x0d)
- #define WCD939X_R_CTL14 (WCD939X_R_BASE+0x0e)
- #define WCD939X_R_CTL15 (WCD939X_R_BASE+0x0f)
- #define WCD939X_R_CTL16 (WCD939X_R_BASE+0x10)
- #define WCD939X_R_CTL17 (WCD939X_R_BASE+0x11)
- #define WCD939X_R_CTL18 (WCD939X_R_BASE+0x12)
- #define WCD939X_R_CTL19 (WCD939X_R_BASE+0x13)
- #define WCD939X_E_BASE (WCD939X_BASE+0x581)
- #define WCD939X_PATH_CTL (WCD939X_E_BASE+0x00)
- #define WCD939X_CFG0 (WCD939X_E_BASE+0x01)
- #define WCD939X_CFG1 (WCD939X_E_BASE+0x02)
- #define WCD939X_CFG2 (WCD939X_E_BASE+0x03)
- #define WCD939X_CFG3 (WCD939X_E_BASE+0x04)
- #define WCD939X_DSD_HPHL_BASE (WCD939X_BASE+0x591)
- #define WCD939X_DSD_HPHL_PATH_CTL (WCD939X_DSD_HPHL_BASE+0x00)
- #define WCD939X_DSD_HPHL_CFG0 (WCD939X_DSD_HPHL_BASE+0x01)
- #define WCD939X_DSD_HPHL_CFG1 (WCD939X_DSD_HPHL_BASE+0x02)
- #define WCD939X_DSD_HPHL_CFG2 (WCD939X_DSD_HPHL_BASE+0x03)
- #define WCD939X_DSD_HPHL_CFG3 (WCD939X_DSD_HPHL_BASE+0x04)
- #define WCD939X_CFG4 (WCD939X_DSD_HPHL_BASE+0x05)
- #define WCD939X_CFG5 (WCD939X_DSD_HPHL_BASE+0x06)
- #define WCD939X_DSD_HPHR_BASE (WCD939X_BASE+0x5a1)
- #define WCD939X_DSD_HPHR_PATH_CTL (WCD939X_DSD_HPHR_BASE+0x00)
- #define WCD939X_DSD_HPHR_CFG0 (WCD939X_DSD_HPHR_BASE+0x01)
- #define WCD939X_DSD_HPHR_CFG1 (WCD939X_DSD_HPHR_BASE+0x02)
- #define WCD939X_DSD_HPHR_CFG2 (WCD939X_DSD_HPHR_BASE+0x03)
- #define WCD939X_DSD_HPHR_CFG3 (WCD939X_DSD_HPHR_BASE+0x04)
- #define WCD939X_DSD_HPHR_CFG4 (WCD939X_DSD_HPHR_BASE+0x05)
- #define WCD939X_DSD_HPHR_CFG5 (WCD939X_DSD_HPHR_BASE+0x06)
- #define WCD939X_NUM_REGISTERS (WCD939X_DSD_HPHR_CFG5+1)
- #define WCD939X_MAX_REGISTER (WCD939X_NUM_REGISTERS-1)
- #endif /* WCD939X_REGISTERS_H */
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