qcacmn: Fix hal/wifi3.0 documentation

The kernel-doc script identified a number of kernel-doc issues in the
hal/wifi3.0 folder, so fix them.

Note that there are a number of instances where public functions have
their implementation documented in addition to having their interface
documented, so remove the duplicate documentation since only the
interfaces should be documented.

Change-Id: Ic238c0f53658e8754882c83204ffae5ad713ec6b
CRs-Fixed: 3410624

hal/wifi3.0/hal_api_mon.h

@@ -195,7 +195,7 @@
 #define HAL_RX_FRAME_CTRL_TYPE_DATA 0x2
 
 /**
- * hal_dl_ul_flag - flag to indicate UL/DL
+ * enum hal_dl_ul_flag - flag to indicate UL/DL
  * @dl_ul_flag_is_dl_or_tdls: DL
  * @dl_ul_flag_is_ul: UL
  */
@@ -204,8 +204,8 @@ enum hal_dl_ul_flag {
 	dl_ul_flag_is_ul,
 };
 
-/*
- * hal_eht_ppdu_sig_cmn_type - PPDU type
+/**
+ * enum hal_eht_ppdu_sig_cmn_type - PPDU type
  * @eht_ppdu_sig_tb_or_dl_ofdma: TB/DL_OFDMA PPDU
  * @eht_ppdu_sig_su: SU PPDU
  * @eht_ppdu_sig_dl_mu_mimo: DL_MU_MIMO PPDU
@@ -216,8 +216,8 @@ enum hal_eht_ppdu_sig_cmn_type {
 	eht_ppdu_sig_dl_mu_mimo,
 };
 
-/*
- * hal_mon_packet_info - packet info
+/**
+ * struct hal_mon_packet_info - packet info
  * @sw_cookie: 64-bit SW desc virtual address
  * @dma_length: packet DMA length
  * @msdu_continuation: msdu continulation in next buffer
@@ -230,8 +230,8 @@ struct hal_mon_packet_info {
 		 truncated : 1;
 };
 
-/*
- * hal_rx_mon_msdu_info - msdu info
+/**
+ * struct hal_rx_mon_msdu_info - msdu info
  * @first_buffer: first buffer of msdu
  * @last_buffer: last buffer of msdu
  * @first_mpdu: first MPDU
@@ -270,8 +270,8 @@ struct hal_rx_mon_msdu_info {
 	int16_t user_rssi;
 };
 
-/*
- * hal_rx_mon_mpdu_info - MPDU info
+/**
+ * struct hal_rx_mon_mpdu_info - MPDU info
  * @decap_type: decap_type
  * @mpdu_length_err: MPDU length error
  * @fcs_err: FCS error
@@ -302,7 +302,7 @@ struct hal_rx_mon_mpdu_info {
  * @status_buf_count:        number of status buffer count
  * @rxdma_push_reason:       rxdma push reason
  * @rxdma_error_code:        rxdma error code
- * @msdu_cnt:                msdu count
+ * @msdu_count:              msdu count
  * @end_of_ppdu:             end of ppdu
  * @link_desc:               msdu link descriptor address
  * @status_buf:              for a PPDU, status buffers can span acrosss
@@ -324,8 +324,8 @@ struct hal_rx_mon_desc_info {
 	bool drop_ppdu;
 };
 
-/*
- * Struct hal_rx_su_evm_info - SU evm info
+/**
+ * struct hal_rx_su_evm_info - SU evm info
  * @number_of_symbols: number of symbols
  * @nss_count:         nss count
  * @pilot_count:       pilot count
@@ -378,12 +378,12 @@ hal_rx_reo_ent_get_src_link_id(hal_soc_handle_t hal_soc_hdl,
 }
 
 /**
- * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
- *			cookie from the REO entrance ring element
- * @hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
- * the current descriptor
- * @ buf_info: structure to return the buffer information
- * @ msdu_cnt: pointer to msdu count in MPDU
+ * hal_rx_reo_ent_buf_paddr_get() - Gets the physical address and cookie from
+ *                                  the REO entrance ring element
+ * @hal_soc_hdl: HAL version of the SOC pointer
+ * @rx_desc: rx descriptor
+ * @buf_info: structure to return the buffer information
+ * @msdu_cnt: pointer to msdu count in MPDU
  *
  * CAUTION: This API calls a hal_soc ops, so be careful before calling this in
  * per packet path
@@ -535,11 +535,10 @@ hal_rx_hw_desc_mpdu_user_id(hal_soc_handle_t hal_soc_hdl,
 /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
 
 /**
- * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
- *
- * @ soc		: HAL version of the SOC pointer
- * @ src_srng_desc	: void pointer to the WBM Release Ring descriptor
- * @ buf_addr_info	: void pointer to the buffer_addr_info
+ * hal_rx_mon_msdu_link_desc_set() - Retrieves MSDU Link Descriptor to WBM
+ * @hal_soc_hdl: HAL version of the SOC pointer
+ * @src_srng_desc: void pointer to the WBM Release Ring descriptor
+ * @buf_addr_info: void pointer to the buffer_addr_info
  *
  * Return: void
  */
@@ -623,7 +622,7 @@ enum {
 	HAL_RX_TYPE_UL,
 };
 
-/*
+/**
  * enum
  * @HAL_RECEPTION_TYPE_SU: Basic SU reception
  * @HAL_RECEPTION_TYPE_DL_MU_MIMO: DL MU_MIMO reception
@@ -655,15 +654,16 @@ enum {
 	HAL_RX_MON_PPDU_RESET,
 };
 
-/* struct hal_rx_ppdu_common_info  - common ppdu info
- * @ppdu_id - ppdu id number
- * @ppdu_timestamp - timestamp at ppdu received
- * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok
- * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err
- * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap
- * @last_ppdu_id - last received ppdu id
- * @mpdu_cnt - total mpdu count
- * @num_users - num users
+/**
+ * struct hal_rx_ppdu_common_info  - common ppdu info
+ * @ppdu_id: ppdu id number
+ * @ppdu_timestamp: timestamp at ppdu received
+ * @mpdu_cnt_fcs_ok: mpdu count in ppdu with fcs ok
+ * @mpdu_cnt_fcs_err: mpdu count in ppdu with fcs err
+ * @num_users: num users
+ * @mpdu_fcs_ok_bitmap: fcs ok mpdu count in ppdu bitmap
+ * @last_ppdu_id: last received ppdu id
+ * @mpdu_cnt: total mpdu count
  */
 struct hal_rx_ppdu_common_info {
 	uint32_t ppdu_id;
@@ -939,7 +939,7 @@ struct hal_mon_usig_hdr {
 		 HAL_RX_MON_USIG_RX_INTEGRITY_CHECK_PASSED_LSB)
 
 /**
- * enum hal_eht_bw: Reception bandwidth
+ * enum hal_eht_bw - Reception bandwidth
  * @HAL_EHT_BW_20: 20Mhz
  * @HAL_EHT_BW_40: 40Mhz
  * @HAL_EHT_BW_80: 80Mhz
@@ -975,7 +975,7 @@ struct hal_eht_sig_non_mu_mimo_user_info {
 };
 
 /**
- * union hal_eht_sig_user_field: User field in EHTSIG
+ * union hal_eht_sig_user_field - User field in EHTSIG
  * @mu_mimo_usr: MU-MIMO user field information in EHTSIG
  * @non_mu_mimo_usr: Non MU-MIMO user field information in EHTSIG
  */
@@ -1223,7 +1223,8 @@ struct hal_rx_tlv_aggr_info {
 	uint8_t buf[HAL_RX_MON_MAX_AGGR_SIZE];
 };
 
-/* struct hal_rx_u_sig_info - Certain fields from U-SIG header which are used
+/**
+ * struct hal_rx_u_sig_info - Certain fields from U-SIG header which are used
  *		for other header field parsing.
  * @ul_dl: UL or DL
  * @bw: EHT BW
@@ -1249,7 +1250,7 @@ struct hal_rx_user_ctrl_frm_info {};
 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */
 
 #ifdef MONITOR_TLV_RECORDING_ENABLE
-/*
+/**
  * struct hal_rx_tlv_info - TLV info to pass to dp layer
  * @tlv_tag: Tag of the TLV
  * @tlv_category: Category of TLV
@@ -1378,15 +1379,17 @@ hal_rx_status_get_next_tlv(uint8_t *rx_tlv, bool is_tlv_hdr_64_bit) {
 /**
  * hal_rx_proc_phyrx_other_receive_info_tlv()
  *				    - process other receive info TLV
+ * @hal_soc: HAL soc object
  * @rx_tlv_hdr: pointer to TLV header
  * @ppdu_info: pointer to ppdu_info
  *
  * Return: None
  */
-static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
-						     void *rx_tlv_hdr,
-						     struct hal_rx_ppdu_info
-						     *ppdu_info)
+static inline void
+hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
+					 void *rx_tlv_hdr,
+					 struct hal_rx_ppdu_info
+					 *ppdu_info)
 {
 	hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr,
 							(void *)ppdu_info);
@@ -1396,7 +1399,7 @@ static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_
  * hal_rx_status_get_tlv_info() - process receive info TLV
  * @rx_tlv_hdr: pointer to TLV header
  * @ppdu_info: pointer to ppdu_info
- * @hal_soc: HAL soc handle
+ * @hal_soc_hdl: HAL soc handle
  * @nbuf: PPDU status network buffer
  *
  * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv

hal/wifi3.0/hal_generic_api.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -26,7 +26,7 @@
 
 /**
  * hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value
- * from stats enum to radiotap enum
+ *                                from stats enum to radiotap enum
  * @he_gi: HE GI value used in stats
  * @he_ltf: HE LTF value used in stats
  *
@@ -83,8 +83,8 @@ static inline void hal_get_radiotap_he_gi_ltf(uint16_t *he_gi, uint16_t *he_ltf)
 #define FREQ_MULTIPLIER_CONST_20MHZ 20
 /**
  * hal_rx_radiotap_num_to_freq() - Get frequency from chan number
- * @chan_num - Input channel number
- * @center_freq - Input Channel Center frequency
+ * @chan_num: Input channel number
+ * @center_freq: Input Channel Center frequency
  *
  * Return - Channel frequency in Mhz
  */
@@ -120,9 +120,9 @@ hal_rx_radiotap_num_to_freq(uint16_t chan_num, qdf_freq_t center_freq)
 }
 
 /**
- * hal_get_hw_hptp_generic()  - Get HW head and tail pointer value for any ring
+ * hal_get_hw_hptp_generic() - Get HW head and tail pointer value for any ring
  * @hal_soc: Opaque HAL SOC handle
- * @hal_ring: Source ring pointer
+ * @hal_ring_hdl: Source ring pointer
  * @headp: Head Pointer
  * @tailp: Tail Pointer
  * @ring: Ring type
@@ -196,9 +196,9 @@ void hal_srng_src_hw_write_cons_prefetch_timer(struct hal_srng *srng,
 }
 
 /**
- * hal_srng_hw_disable_generic - Private function to disable SRNG
- * source ring HW
- * @hal_soc: HAL SOC handle
+ * hal_srng_hw_disable_generic() - Private function to disable SRNG
+ *                                 source ring HW
+ * @hal: HAL SOC handle
  * @srng: SRNG ring pointer
  */
 static inline
@@ -230,9 +230,9 @@ void hal_srng_src_hw_write_cons_prefetch_timer(struct hal_srng *srng,
 }
 #endif
 /**
- * hal_srng_src_hw_init - Private function to initialize SRNG
- * source ring HW
- * @hal_soc: HAL SOC handle
+ * hal_srng_src_hw_init_generic() - Private function to initialize SRNG
+ *                                  source ring HW
+ * @hal: HAL SOC handle
  * @srng: SRNG ring pointer
  * @idle_check: Check if ring is idle
  * @idx: ring index
@@ -425,9 +425,9 @@ static inline void hal_srng_dst_near_full_int_setup(struct hal_srng *srng)
 #endif
 
 /**
- * hal_srng_dst_hw_init - Private function to initialize SRNG
- * destination ring HW
- * @hal_soc: HAL SOC handle
+ * hal_srng_dst_hw_init_generic() - Private function to initialize SRNG
+ *                                  destination ring HW
+ * @hal: HAL SOC handle
  * @srng: SRNG ring pointer
  * @idle_check: Check if ring is idle
  * @idx: Ring index
@@ -591,7 +591,7 @@ static inline void hal_srng_hw_reg_offset_init_generic(struct hal_soc *hal_soc)
 #ifdef FEATURE_DIRECT_LINK
 /**
  * hal_srng_set_msi_config() - Set the MSI config and enable the SRNG
- * @hal_ring_hdl: srng handle
+ * @ring_hdl: srng handle
  * @params: ring parameters
  *
  * Return: QDF status

hal/wifi3.0/hal_hw_headers.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -168,7 +168,7 @@
 
 #define WBM_IDLE_DESC_LIST 1
 
-/**
+/*
  * Common SRNG register access macros:
  * The SRNG registers are distributed across various UMAC and LMAC HW blocks,
  * but the register group and format is exactly same for all rings, with some
@@ -219,7 +219,7 @@
 #define HP_GROUP R2
 #define TP_GROUP R2
 
-/**
+/*
  * Register definitions for all SRNG based rings are same, except few
  * differences between source (HW consumer) and destination (HW producer)
  * registers. Following macros definitions provide generic access to all
@@ -319,7 +319,7 @@
 #define SRNG_MAX_SIZE_DWORDS \
 	(SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff))
 
-/**
+/*
  * HW ring configuration table to identify hardware ring attributes like
  * register addresses, number of rings, ring entry size etc., for each type
  * of SRNG ring.
@@ -332,14 +332,13 @@
 			(&_hal_soc->hw_srng_table[_ring_type])
 
 /**
- * hal_set_link_desc_addr - Setup link descriptor in a buffer_addr_info
- * HW structure
- *
+ * hal_set_link_desc_addr() - Setup link descriptor in a buffer_addr_info
+ *                            HW structure
  * @hal_soc_hdl: HAL soc handle
  * @desc: Descriptor entry (from WBM_IDLE_LINK ring)
  * @cookie: SW cookie for the buffer/descriptor
  * @link_desc_paddr: Physical address of link descriptor entry
- *
+ * @bm_id: idle link BM id
  */
 static inline void hal_set_link_desc_addr(hal_soc_handle_t hal_soc_hdl,
 					  void *desc, uint32_t cookie,
@@ -362,7 +361,7 @@ static inline void hal_set_link_desc_addr(hal_soc_handle_t hal_soc_hdl,
 /**
  * hal_get_reo_qdesc_size - Get size of reo queue descriptor
  *
- * @hal_soc: Opaque HAL SOC handle
+ * @hal_soc_hdl: Opaque HAL SOC handle
  * @ba_window_size: BlockAck window size
  * @tid: TID number
  *
@@ -382,7 +381,7 @@ uint32_t hal_get_reo_qdesc_size(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_get_rx_max_ba_window - Get RX max BA window size per target
- * @hal_soc: Opaque HAL SOC handle
+ * @hal_soc_hdl: Opaque HAL SOC handle
  * @tid: TID number
  *
  * Return: Max RX BA window size
@@ -398,6 +397,7 @@ uint16_t hal_get_rx_max_ba_window(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_get_idle_link_bm_id() - Get idle link BM id from chid_id
+ * @hal_soc_hdl: Opaque HAL SOC handle
  * @chip_id: mlo chip_id
  *
  * Returns: RBM ID

hal/wifi3.0/hal_internal.h

@@ -117,49 +117,55 @@ struct hal_hw_cc_config {
 		 reserved:2;
 };
 
+struct hal_soc_handle;
 /*
- * dp_hal_soc - opaque handle for DP HAL soc
+ * typedef hal_soc_handle_t - opaque handle for DP HAL soc
  */
-struct hal_soc_handle;
 typedef struct hal_soc_handle *hal_soc_handle_t;
 
-/**
- * hal_ring_desc - opaque handle for DP ring descriptor
- */
 struct hal_ring_desc;
+/*
+ * typedef hal_ring_desc_t - opaque handle for DP ring descriptor
+ */
 typedef struct hal_ring_desc *hal_ring_desc_t;
 
-/**
- * hal_link_desc - opaque handle for DP link descriptor
- */
 struct hal_link_desc;
+/*
+ * typedef hal_link_desc_t - opaque handle for DP link descriptor
+ */
 typedef struct hal_link_desc *hal_link_desc_t;
 
-/**
- * hal_rxdma_desc - opaque handle for DP rxdma dst ring descriptor
- */
 struct hal_rxdma_desc;
+/*
+ * typedef hal_rxdma_desc_t - opaque handle for DP rxdma dst ring descriptor
+ */
 typedef struct hal_rxdma_desc *hal_rxdma_desc_t;
 
-/**
- * hal_buff_addrinfo - opaque handle for DP buffer address info
- */
 struct hal_buff_addrinfo;
+/*
+ * typedef hal_buff_addrinfo_t - opaque handle for DP buffer address info
+ */
 typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
 
-/**
- * hal_rx_mon_desc_info - opaque handle for sw monitor ring desc info
- */
 struct hal_rx_mon_desc_info;
+/*
+ * typedef hal_rx_mon_desc_info_t - opaque handle for sw monitor ring desc info
+ */
 typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
 
 struct hal_buf_info;
+/*
+ * typedef hal_buf_info_t - opaque handle for HAL buffer info
+ */
 typedef struct hal_buf_info *hal_buf_info_t;
 
 struct rx_msdu_desc_info;
+/*
+ * typedef rx_msdu_desc_info_t - opaque handle for rx MSDU descriptor info
+ */
 typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t;
 
-/**
+/*
  * Opaque handler for PPE VP config.
  */
 union hal_tx_ppe_vp_config;
@@ -421,11 +427,11 @@ enum hal_reo_remap_reg {
 #define SRNG_LOCK_DESTROY(_lock) qdf_spinlock_destroy(_lock)
 
 struct hal_soc;
+struct hal_ring_handle;
 
-/**
- * dp_hal_ring - opaque handle for DP HAL SRNG
+/*
+ * typedef hal_ring_handle_t - opaque handle for DP HAL SRNG
  */
-struct hal_ring_handle;
 typedef struct hal_ring_handle *hal_ring_handle_t;
 
 #define MAX_SRNG_REG_GROUPS 2
@@ -540,6 +546,7 @@ struct hal_offload_info {
  * @HAL_SRNG_HIGH_WM_BIN_70_to_80: 70-80% SRNG entries used
  * @HAL_SRNG_HIGH_WM_BIN_80_to_90: 80-90% SRNG entries used
  * @HAL_SRNG_HIGH_WM_BIN_90_to_100: 90-100% SRNG entries used
+ * @HAL_SRNG_HIGH_WM_BIN_MAX: maximum enumeration
  */
 enum hal_srng_high_wm_bin {
 	HAL_SRNG_HIGH_WM_BIN_BELOW_50_PERCENT,
@@ -570,23 +577,23 @@ struct hal_srng_high_wm_info {
 
 /**
  * enum hal_scratch_reg_enum - Enum to indicate scratch register values
- * @PMM_QTIMER_GLOBAL_OFFSET_LO_US - QTIMER GLOBAL OFFSET LOW
- * @PMM_QTIMER_GLOBAL_OFFSET_HI_US - QTIMER GLOBAL OFFSET HIGH
- * @PMM_MAC0_TSF1_OFFSET_LO_US - MAC0 TSF1 OFFSET LOW
- * @PMM_MAC0_TSF1_OFFSET_HI_US - MAC0 TSF1 OFFSET HIGH
- * @PMM_MAC0_TSF2_OFFSET_LO_US - MAC0 TSF2 OFFSET LOW
- * @PMM_MAC0_TSF2_OFFSET_HI_US - MAC0 TSF2 OFFSET HIGH
- * @PMM_MAC1_TSF1_OFFSET_LO_US - MAC1 TSF1 OFFSET LOW
- * @PMM_MAC1_TSF1_OFFSET_HI_US - MAC1 TSF1 OFFSET HIGH
- * @PMM_MAC1_TSF2_OFFSET_LO_US - MAC1 TSF2 OFFSET LOW
- * @PMM_MAC1_TSF2_OFFSET_HI_US - MAC1 TSF2 OFFSET HIGH
- * @PMM_MLO_OFFSET_LO_US - MLO OFFSET LOW
- * @PMM_MLO_OFFSET_HI_US - MLO OFFSET HIGH
- * @PMM_TQM_CLOCK_OFFSET_LO_US - TQM CLOCK OFFSET LOW
- * @PMM_TQM_CLOCK_OFFSET_HI_US - TQM CLOCK OFFSET HIGH
- * @PMM_Q6_CRASH_REASON - Q6 CRASH REASON
- * @PMM_SCRATCH_TWT_OFFSET - TWT OFFSET
- * @PMM_PMM_REG_MAX - Max PMM REG value
+ * @PMM_QTIMER_GLOBAL_OFFSET_LO_US: QTIMER GLOBAL OFFSET LOW
+ * @PMM_QTIMER_GLOBAL_OFFSET_HI_US: QTIMER GLOBAL OFFSET HIGH
+ * @PMM_MAC0_TSF1_OFFSET_LO_US: MAC0 TSF1 OFFSET LOW
+ * @PMM_MAC0_TSF1_OFFSET_HI_US: MAC0 TSF1 OFFSET HIGH
+ * @PMM_MAC0_TSF2_OFFSET_LO_US: MAC0 TSF2 OFFSET LOW
+ * @PMM_MAC0_TSF2_OFFSET_HI_US: MAC0 TSF2 OFFSET HIGH
+ * @PMM_MAC1_TSF1_OFFSET_LO_US: MAC1 TSF1 OFFSET LOW
+ * @PMM_MAC1_TSF1_OFFSET_HI_US: MAC1 TSF1 OFFSET HIGH
+ * @PMM_MAC1_TSF2_OFFSET_LO_US: MAC1 TSF2 OFFSET LOW
+ * @PMM_MAC1_TSF2_OFFSET_HI_US: MAC1 TSF2 OFFSET HIGH
+ * @PMM_MLO_OFFSET_LO_US: MLO OFFSET LOW
+ * @PMM_MLO_OFFSET_HI_US: MLO OFFSET HIGH
+ * @PMM_TQM_CLOCK_OFFSET_LO_US: TQM CLOCK OFFSET LOW
+ * @PMM_TQM_CLOCK_OFFSET_HI_US: TQM CLOCK OFFSET HIGH
+ * @PMM_Q6_CRASH_REASON: Q6 CRASH REASON
+ * @PMM_SCRATCH_TWT_OFFSET: TWT OFFSET
+ * @PMM_PMM_REG_MAX: Max PMM REG value
  */
 enum hal_scratch_reg_enum {
 	PMM_QTIMER_GLOBAL_OFFSET_LO_US,
@@ -613,8 +620,8 @@ enum hal_scratch_reg_enum {
  *
  * @tsf_id: tsf id
  * @mac_id: mac id
- * @enum_lo: Pointer to update low scratch register
- * @enum_hi: Pointer to update hi scratch register
+ * @tsf_enum_low: Pointer to update low scratch register
+ * @tsf_enum_hi: Pointer to update hi scratch register
  *
  * Return: void
  */
@@ -1412,77 +1419,90 @@ struct hal_suspend_write_history {
  * struct hal_soc - HAL context to be used to access SRNG APIs
  *		    (currently used by data path and
  *		    transport (CE) modules)
+ * @hif_handle: HIF handle to access HW registers
+ * @qdf_dev: QDF device handle
+ * @dev_base_addr: Device base address
+ * @dev_base_addr_ce: Device base address for ce - qca5018 target
+ * @dev_base_addr_cmem: Device base address for CMEM
+ * @dev_base_addr_pmm: Device base address for PMM
+ * @srng_list: HAL internal state for all SRNG rings
+ * @shadow_rdptr_mem_vaddr: Remote pointer memory for HW/FW updates (virtual)
+ * @shadow_rdptr_mem_paddr: Remote pointer memory for HW/FW updates (physical)
+ * @shadow_wrptr_mem_vaddr: Shared memory for ring pointer updates from host
+ *                          to FW (virtual)
+ * @shadow_wrptr_mem_paddr: Shared memory for ring pointer updates from host
+ *                          to FW (physical)
+ * @reo_res_bitmap: REO blocking resource index
+ * @index:
+ * @target_type:
+ * @version:
+ * @shadow_config: shadow register configuration
+ * @num_shadow_registers_configured:
+ * @use_register_windowing:
+ * @register_window:
+ * @register_access_lock:
+ * @static_window_map: Static window map configuration for multiple window write
+ * @hw_srng_table: srng table
+ * @hal_hw_reg_offset:
+ * @ops: TXRX operations
+ * @init_phase: Indicate srngs initialization
+ * @stats: Hal level stats
+ * @reg_wr_fail_hist: write failure history
+ * @reg_write_queue: queue(array) to hold register writes
+ * @reg_write_work: delayed work to be queued into workqueue
+ * @reg_write_wq: workqueue for delayed register writes
+ * @write_idx: write index used by caller to enqueue delayed work
+ * @read_idx: read index used by worker thread to dequeue/write registers
+ * @active_work_cnt:
  * @list_shadow_reg_config: array of generic regs mapped to
  *			    shadow regs
  * @num_generic_shadow_regs_configured: number of generic regs
  *					mapped to shadow regs
+ * @dmac_cmn_src_rxbuf_ring: flag to indicate cmn dmac rings in beryllium
+ * @reo_qref: Reo queue ref table items
  */
 struct hal_soc {
-	/* HIF handle to access HW registers */
 	struct hif_opaque_softc *hif_handle;
-
-	/* QDF device handle */
 	qdf_device_t qdf_dev;
-
-	/* Device base address */
 	void *dev_base_addr;
-	/* Device base address for ce - qca5018 target */
 	void *dev_base_addr_ce;
-
 	void *dev_base_addr_cmem;
-
 	void *dev_base_addr_pmm;
-	/* HAL internal state for all SRNG rings.
-	 * TODO: See if this is required
-	 */
 	struct hal_srng srng_list[HAL_SRNG_ID_MAX];
 
-	/* Remote pointer memory for HW/FW updates */
 	uint32_t *shadow_rdptr_mem_vaddr;
 	qdf_dma_addr_t shadow_rdptr_mem_paddr;
 
-	/* Shared memory for ring pointer updates from host to FW */
 	uint32_t *shadow_wrptr_mem_vaddr;
 	qdf_dma_addr_t shadow_wrptr_mem_paddr;
 
-	/* REO blocking resource index */
 	uint8_t reo_res_bitmap;
 	uint8_t index;
 	uint32_t target_type;
 	uint32_t version;
 
-	/* shadow register configuration */
 	union hal_shadow_reg_cfg shadow_config[MAX_SHADOW_REGISTERS];
 	int num_shadow_registers_configured;
 	bool use_register_windowing;
 	uint32_t register_window;
 	qdf_spinlock_t register_access_lock;
 
-	/* Static window map configuration for multiple window write*/
 	bool static_window_map;
 
-	/* srng table */
 	struct hal_hw_srng_config *hw_srng_table;
 	int32_t hal_hw_reg_offset[SRNG_REGISTER_MAX];
 	struct hal_hw_txrx_ops *ops;
 
-	/* Indicate srngs initialization */
 	bool init_phase;
-	/* Hal level stats */
 	struct hal_soc_stats stats;
 #ifdef ENABLE_HAL_REG_WR_HISTORY
 	struct hal_reg_write_fail_history *reg_wr_fail_hist;
 #endif
 #ifdef FEATURE_HAL_DELAYED_REG_WRITE
-	/* queue(array) to hold register writes */
 	struct hal_reg_write_q_elem *reg_write_queue;
-	/* delayed work to be queued into workqueue */
 	qdf_work_t reg_write_work;
-	/* workqueue for delayed register writes */
 	qdf_workqueue_t *reg_write_wq;
-	/* write index used by caller to enqueue delayed work */
 	qdf_atomic_t write_idx;
-	/* read index used by worker thread to dequeue/write registers */
 	uint32_t read_idx;
 #endif /*FEATURE_HAL_DELAYED_REG_WRITE */
 	qdf_atomic_t active_work_cnt;
@@ -1491,15 +1511,13 @@ struct hal_soc {
 		list_shadow_reg_config[MAX_GENERIC_SHADOW_REG];
 	int num_generic_shadow_regs_configured;
 #endif
-	/* flag to indicate cmn dmac rings in berryllium */
 	bool dmac_cmn_src_rxbuf_ring;
-	/* Reo queue ref table items */
 	struct reo_queue_ref_table reo_qref;
 };
 
 #if defined(FEATURE_HAL_DELAYED_REG_WRITE)
 /**
- *  hal_delayed_reg_write() - delayed register write
+ * hal_delayed_reg_write() - delayed register write
  * @hal_soc: HAL soc handle
  * @srng: hal srng
  * @addr: iomem address
@@ -1530,9 +1548,9 @@ void hal_qcn9224v1_attach(struct hal_soc *hal_soc);
 void hal_qcn9224v2_attach(struct hal_soc *hal_soc);
 
 /**
- * hal_soc_to_dp_hal_roc() - API to convert hal_soc to opaque
- * dp_hal_soc handle type
- * @hal_soc - hal_soc type
+ * hal_soc_to_hal_soc_handle() - API to convert hal_soc to opaque
+ *                               hal_soc_handle_t type
+ * @hal_soc: hal_soc type
  *
  * Return: hal_soc_handle_t type
  */
@@ -1542,10 +1560,10 @@ hal_soc_handle_t hal_soc_to_hal_soc_handle(struct hal_soc *hal_soc)
 	return (hal_soc_handle_t)hal_soc;
 }
 
-/*
- * hal_srng_to_hal_ring_handle - API to convert hal_srng to opaque
- * dp_hal_ring handle type
- * @hal_srng - hal_srng type
+/**
+ * hal_srng_to_hal_ring_handle() - API to convert hal_srng to opaque
+ *                                 hal_ring handle_t type
+ * @hal_srng: hal_srng type
  *
  * Return: hal_ring_handle_t type
  */
@@ -1555,9 +1573,9 @@ hal_ring_handle_t hal_srng_to_hal_ring_handle(struct hal_srng *hal_srng)
 	return (hal_ring_handle_t)hal_srng;
 }
 
-/*
- * hal_ring_handle_to_hal_srng - API to convert dp_hal_ring to hal_srng handle
- * @hal_ring - hal_ring_handle_t type
+/**
+ * hal_ring_handle_to_hal_srng() - API to convert hal_ring_handle_t to hal_srng
+ * @hal_ring: hal_ring_handle_t type
  *
  * Return: hal_srng pointer type
  */
@@ -1595,6 +1613,7 @@ struct hal_srng *hal_ring_handle_to_hal_srng(hal_ring_handle_t hal_ring)
  * @HAL_DOT11BE: 802.11be PPDU type
  * @HAL_DOT11AZ: 802.11az (ranging) PPDU type
  * @HAL_DOT11N_GF: 802.11n Green Field PPDU type
+ * @HAL_DOT11_MAX: Maximum enumeration
  *
  * Enum indicating the packet type reported by HW in rx_pkt_tlvs (RX data)
  * or WBM2SW ring entry's descriptor (TX data completion)

hal/wifi3.0/hal_reo.h

@@ -150,6 +150,9 @@ enum reo_thres_index_reg {
  *	was blocked
  * @HAL_REO_CMD_FAILED: Command has encountered problems when executing, like
  *	the queue descriptor not being valid
+ * @HAL_REO_CMD_RESOURCE_BLOCKED: Command could not be executed as a resource
+ *	was blocked
+ * @HAL_REO_CMD_DRAIN: Command was drained before it could be executed
  */
 enum reo_cmd_exec_status {
 	HAL_REO_CMD_SUCCESS = 0,
@@ -160,7 +163,7 @@ enum reo_cmd_exec_status {
 };
 
 /**
- * struct hal_reo_cmd_params_std: Standard REO command parameters
+ * struct hal_reo_cmd_params_std - Standard REO command parameters
  * @need_status: Status required for the command
  * @addr_lo: Lower 32 bits of REO queue descriptor address
  * @addr_hi: Upper 8 bits of REO queue descriptor address
@@ -172,8 +175,8 @@ struct hal_reo_cmd_params_std {
 };
 
 /**
- * struct hal_reo_cmd_get_queue_stats_params: Parameters to
- *	CMD_GET_QUEUE_STATScommand
+ * struct hal_reo_cmd_get_queue_stats_params - Parameters to
+ *                                             CMD_GET_QUEUE_STATScommand
  * @clear: Clear stats after retrieving
  */
 struct hal_reo_cmd_get_queue_stats_params {
@@ -181,8 +184,8 @@ struct hal_reo_cmd_get_queue_stats_params {
 };
 
 /**
- * struct hal_reo_cmd_flush_queue_params: Parameters to CMD_FLUSH_QUEUE
- * @use_after_flush: Block usage after flush till unblock command
+ * struct hal_reo_cmd_flush_queue_params - Parameters to CMD_FLUSH_QUEUE
+ * @block_use_after_flush: Block usage after flush till unblock command
  * @index: Blocking resource to be used
  */
 struct hal_reo_cmd_flush_queue_params {
@@ -191,13 +194,14 @@ struct hal_reo_cmd_flush_queue_params {
 };
 
 /**
- * struct hal_reo_cmd_flush_cache_params: Parameters to CMD_FLUSH_CACHE
+ * struct hal_reo_cmd_flush_cache_params - Parameters to CMD_FLUSH_CACHE
  * @fwd_mpdus_in_queue: Forward MPDUs before flushing descriptor
  * @rel_block_index: Release blocking resource used earlier
  * @cache_block_res_index: Blocking resource to be used
  * @flush_no_inval: Flush without invalidatig descriptor
- * @use_after_flush: Block usage after flush till unblock command
+ * @block_use_after_flush: Block usage after flush till unblock command
  * @flush_entire_cache: Flush entire REO cache
+ * @flush_q_1k_desc:
  */
 struct hal_reo_cmd_flush_cache_params {
 	bool fwd_mpdus_in_queue;
@@ -210,7 +214,7 @@ struct hal_reo_cmd_flush_cache_params {
 };
 
 /**
- * struct hal_reo_cmd_unblock_cache_params: Parameters to CMD_UNBLOCK_CACHE
+ * struct hal_reo_cmd_unblock_cache_params - Parameters to CMD_UNBLOCK_CACHE
  * @type: Unblock type (enum reo_unblock_cache_type)
  * @index: Blocking index to be released
  */
@@ -220,8 +224,8 @@ struct hal_reo_cmd_unblock_cache_params {
 };
 
 /**
- * struct hal_reo_cmd_flush_timeout_list_params: Parameters to
- *		CMD_FLUSH_TIMEOUT_LIST
+ * struct hal_reo_cmd_flush_timeout_list_params - Parameters to
+ *                                                CMD_FLUSH_TIMEOUT_LIST
  * @ac_list: AC timeout list to be flushed
  * @min_rel_desc: Min. number of link descriptors to be release
  * @min_fwd_buf: Min. number of buffers to be forwarded
@@ -233,7 +237,8 @@ struct hal_reo_cmd_flush_timeout_list_params {
 };
 
 /**
- * struct hal_reo_cmd_update_queue_params: Parameters to CMD_UPDATE_RX_REO_QUEUE
+ * struct hal_reo_cmd_update_queue_params - Parameters to
+ *                                          CMD_UPDATE_RX_REO_QUEUE
  * @update_rx_queue_num: Update receive queue number
  * @update_vld: Update valid bit
  * @update_assoc_link_desc: Update associated link descriptor
@@ -335,8 +340,8 @@ struct hal_reo_cmd_update_queue_params {
 };
 
 /**
- * struct hal_reo_cmd_params: Common structure to pass REO command parameters
- * @hal_reo_cmd_params_std: Standard parameters
+ * struct hal_reo_cmd_params - Common structure to pass REO command parameters
+ * @std: Standard parameters
  * @u: Union of various REO command parameters
  */
 struct hal_reo_cmd_params {
@@ -352,7 +357,7 @@ struct hal_reo_cmd_params {
 };
 
 /**
- * struct hal_reo_status_header: Common REO status header
+ * struct hal_reo_status_header - Common REO status header
  * @cmd_num: Command number
  * @exec_time: execution time
  * @status: command execution status
@@ -366,27 +371,36 @@ struct hal_reo_status_header {
 };
 
 /**
- * struct hal_reo_queue_status: REO queue status structure
+ * struct hal_reo_queue_status - REO queue status structure
  * @header: Common REO status header
  * @ssn: SSN of current BA window
  * @curr_idx: last forwarded pkt
- * @pn_31_0, pn_63_32, pn_95_64, pn_127_96:
- *	PN number bits extracted from IV field
+ * @pn_31_0:
+ * @pn_63_32:
+ * @pn_95_64:
+ * @pn_127_96: PN number bits extracted from IV field
  * @last_rx_enq_tstamp: Last enqueue timestamp
  * @last_rx_deq_tstamp: Last dequeue timestamp
- * @rx_bitmap_31_0, rx_bitmap_63_32, rx_bitmap_95_64
- * @rx_bitmap_127_96, rx_bitmap_159_128, rx_bitmap_191_160
- * @rx_bitmap_223_192, rx_bitmap_255_224: Each bit corresponds to a frame
- *	held in re-order queue
- * @curr_mpdu_cnt, curr_msdu_cnt: Number of MPDUs and MSDUs in the queue
+ * @rx_bitmap_31_0:
+ * @rx_bitmap_63_32:
+ * @rx_bitmap_95_64:
+ * @rx_bitmap_127_96:
+ * @rx_bitmap_159_128:
+ * @rx_bitmap_191_160:
+ * @rx_bitmap_223_192:
+ * @rx_bitmap_255_224: bits of rx bitmap where each bit corresponds to a frame
+ *	               held in re-order queue
+ * @curr_mpdu_cnt: Number of MPDUs in the queue
+ * @curr_msdu_cnt: Number of MSDUs in the queue
  * @fwd_timeout_cnt: Frames forwarded due to timeout
  * @fwd_bar_cnt: Frames forwarded BAR frame
  * @dup_cnt: duplicate frames detected
  * @frms_in_order_cnt: Frames received in order
  * @bar_rcvd_cnt: BAR frame count
- * @mpdu_frms_cnt, msdu_frms_cnt, total_cnt: MPDU, MSDU, total frames
-	processed by REO
- * @late_recv_mpdu_cnt; received after window had moved on
+ * @mpdu_frms_cnt: MPDUs processed by REO
+ * @msdu_frms_cnt: MSDUs processed by REO
+ * @total_cnt: frames processed by REO
+ * @late_recv_mpdu_cnt: received after window had moved on
  * @win_jump_2k: 2K jump count
  * @hole_cnt: sequence hole count
  */
@@ -411,7 +425,7 @@ struct hal_reo_queue_status {
 };
 
 /**
- * struct hal_reo_flush_queue_status: FLUSH_QUEUE status structure
+ * struct hal_reo_flush_queue_status - FLUSH_QUEUE status structure
  * @header: Common REO status header
  * @error: Error detected
  */
@@ -421,7 +435,7 @@ struct hal_reo_flush_queue_status {
 };
 
 /**
- * struct hal_reo_flush_cache_status: FLUSH_CACHE status structure
+ * struct hal_reo_flush_cache_status - FLUSH_CACHE status structure
  * @header: Common REO status header
  * @error: Error detected
  * @block_error: Blocking related error
@@ -439,10 +453,10 @@ struct hal_reo_flush_cache_status {
 };
 
 /**
- * struct hal_reo_unblk_cache_status: UNBLOCK_CACHE status structure
+ * struct hal_reo_unblk_cache_status - UNBLOCK_CACHE status structure
  * @header: Common REO status header
  * @error: error detected
- * unblock_type: resource or cache
+ * @unblock_type: resource or cache
  */
 struct hal_reo_unblk_cache_status {
 	struct hal_reo_status_header header;
@@ -451,7 +465,8 @@ struct hal_reo_unblk_cache_status {
 };
 
 /**
- * struct hal_reo_flush_timeout_list_status: FLUSH_TIMEOUT_LIST status structure
+ * struct hal_reo_flush_timeout_list_status - FLUSH_TIMEOUT_LIST status
+ *                                            structure
  * @header: Common REO status header
  * @error: error detected
  * @list_empty: timeout list empty
@@ -467,11 +482,13 @@ struct hal_reo_flush_timeout_list_status {
 };
 
 /**
- * struct hal_reo_desc_thres_reached_status: desc_thres_reached status structure
+ * struct hal_reo_desc_thres_reached_status - desc_thres_reached status
+ *                                            structure
  * @header: Common REO status header
  * @thres_index: Index of descriptor threshold counter
- * @link_desc_counter0, link_desc_counter1, link_desc_counter2: descriptor
- *	counter values
+ * @link_desc_counter0: descriptor counter value
+ * @link_desc_counter1: descriptor counter value
+ * @link_desc_counter2: descriptor counter value
  * @link_desc_counter_sum: overall descriptor count
  */
 struct hal_reo_desc_thres_reached_status {
@@ -482,7 +499,7 @@ struct hal_reo_desc_thres_reached_status {
 };
 
 /**
- * struct hal_reo_update_rx_queue_status: UPDATE_RX_QUEUE status structure
+ * struct hal_reo_update_rx_queue_status - UPDATE_RX_QUEUE status structure
  * @header: Common REO status header
  */
 struct hal_reo_update_rx_queue_status {
@@ -490,7 +507,7 @@ struct hal_reo_update_rx_queue_status {
 };
 
 /**
- * union hal_reo_status: Union to pass REO status to callbacks
+ * union hal_reo_status - Union to pass REO status to callbacks
  * @queue_status: Refer to struct hal_reo_queue_status
  * @fl_cache_status: Refer to struct hal_reo_flush_cache_status
  * @fl_queue_status: Refer to struct hal_reo_flush_queue_status
@@ -552,9 +569,10 @@ static inline uint8_t hal_find_zero_bit(uint8_t x)
 /* REO command ring routines */
 
 /**
- * hal_uniform_desc_hdr_setup - setup reo_queue_ext descriptor
- * @owner - owner info
- * @buffer_type - buffer type
+ * hal_uniform_desc_hdr_setup() - setup reo_queue_ext descriptor
+ * @desc: descriptor to setup
+ * @owner: owner info
+ * @buffer_type: buffer type
  */
 static inline void
 hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner, uint32_t buffer_type)
@@ -690,8 +708,7 @@ static inline void hal_reo_qdesc_setup(hal_soc_handle_t hal_soc_hdl, int tid,
 
 /**
  * hal_get_ba_aging_timeout - Retrieve BA aging timeout
- *
- * @hal_soc: Opaque HAL SOC handle
+ * @hal_soc_hdl: Opaque HAL SOC handle
  * @ac: Access category
  * @value: timeout duration in millisec
  */
@@ -705,11 +722,10 @@ static inline void hal_get_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl,
 }
 
 /**
- * hal_set_aging_timeout - Set BA aging timeout
- *
- * @hal_soc: Opaque HAL SOC handle
- * @ac: Access category in millisec
- * @value: timeout duration value
+ * hal_set_ba_aging_timeout() - Set BA aging timeout
+ * @hal_soc_hdl: Opaque HAL SOC handle
+ * @ac: Access category
+ * @value: timeout duration value in millisec
  */
 static inline void hal_set_ba_aging_timeout(hal_soc_handle_t hal_soc_hdl,
 					    uint8_t ac,
@@ -766,9 +782,10 @@ hal_get_tlv_hdr_size(hal_soc_handle_t hal_soc_hdl)
 
 /**
  * hal_reo_init_cmd_ring() - Initialize descriptors of REO command SRNG
- * with command number
- * @hal_soc: Handle to HAL SoC structure
- * @hal_ring: Handle to HAL SRNG structure
+ *                           with command number
+ * @hal_soc_hdl: Handle to HAL SoC structure
+ * @hal_ring_hdl: Handle to HAL SRNG structure
+ *
  * Return: none
  */
 void hal_reo_init_cmd_ring(hal_soc_handle_t hal_soc_hdl,
@@ -777,7 +794,8 @@ void hal_reo_init_cmd_ring(hal_soc_handle_t hal_soc_hdl,
 #ifdef REO_SHARED_QREF_TABLE_EN
 /**
  * hal_reo_shared_qaddr_setup(): Setup reo qref LUT
- * @hal_soc: Hal soc pointer
+ * @hal_soc_hdl: Hal soc pointer
+ * @reo_qref: REO QREF table to populate
  *
  * Allocate MLO and Non MLO table for storing REO queue
  * reference pointers
@@ -799,7 +817,7 @@ hal_reo_shared_qaddr_setup(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_reo_shared_qaddr_detach(): Detach reo qref LUT
- * @hal_soc: Hal soc pointer
+ * @hal_soc_hdl: Hal soc pointer
  *
  * Detach MLO and Non MLO table start addr to HW reg
  *

hal/wifi3.0/hal_rx_flow.c

@@ -136,14 +136,6 @@ void hal_rx_dump_cmem_fse(hal_soc_handle_t hal_soc_hdl, uint32_t fse_offset,
 }
 #endif
 
-/**
- * hal_rx_flow_setup_fse() - Setup a flow search entry in HW FST
- * @fst: Pointer to the Rx Flow Search Table
- * @table_offset: offset into the table where the flow is to be setup
- * @flow: Flow Parameters
- *
- * Return: Success/Failure
- */
 void *
 hal_rx_flow_setup_fse(hal_soc_handle_t hal_soc_hdl,
 		      struct hal_rx_fst *fst, uint32_t table_offset,
@@ -161,15 +153,6 @@ hal_rx_flow_setup_fse(hal_soc_handle_t hal_soc_hdl,
 }
 qdf_export_symbol(hal_rx_flow_setup_fse);
 
-/**
- * hal_rx_flow_setup_cmem_fse() - Setup a flow search entry in HW CMEM FST
- * @hal_soc_hdl: HAL SOC handle
- * @cmem_ba: CMEM base address
- * @table_offset: offset into the table where the flow is to be setup
- * @flow: Flow Parameters
- *
- * Return: Success/Failure
- */
 uint32_t
 hal_rx_flow_setup_cmem_fse(hal_soc_handle_t hal_soc_hdl, uint32_t cmem_ba,
 			   uint32_t table_offset, struct hal_rx_flow *flow)
@@ -186,13 +169,6 @@ hal_rx_flow_setup_cmem_fse(hal_soc_handle_t hal_soc_hdl, uint32_t cmem_ba,
 }
 qdf_export_symbol(hal_rx_flow_setup_cmem_fse);
 
-/**
- * hal_rx_flow_get_cmem_fse_timestamp() - Get timestamp field from CMEM FSE
- * @hal_soc_hdl: HAL SOC handle
- * @fse_offset: CMEM FSE offset
- *
- * Return: Timestamp
- */
 uint32_t hal_rx_flow_get_cmem_fse_timestamp(hal_soc_handle_t hal_soc_hdl,
 					    uint32_t fse_offset)
 {
@@ -207,14 +183,6 @@ uint32_t hal_rx_flow_get_cmem_fse_timestamp(hal_soc_handle_t hal_soc_hdl,
 }
 qdf_export_symbol(hal_rx_flow_get_cmem_fse_timestamp);
 
-/**
- * hal_rx_flow_delete_entry() - Delete a flow from the Rx Flow Search Table
- * @hal_soc_hdl: HAL SOC handle
- * @fst: Pointer to the Rx Flow Search Table
- * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
- *
- * Return: Success/Failure
- */
 QDF_STATUS
 hal_rx_flow_delete_entry(hal_soc_handle_t hal_soc_hdl,
 			 struct hal_rx_fst *fst, void *hal_rx_fse)
@@ -244,7 +212,7 @@ static void hal_rx_fst_key_configure(struct hal_rx_fst *fst)
 
 	qdf_mem_copy(key_bytes, fst->key, HAL_FST_HASH_KEY_SIZE_BYTES);
 
-	/**
+	/*
 	 * The Toeplitz algorithm as per the Microsoft spec works in a
 	 * “big-endian” manner, using the MSBs of the key to hash the
 	 * initial bytes of the input going on to use up the lower order bits
@@ -275,6 +243,7 @@ static inline void *hal_rx_fst_get_base(struct hal_rx_fst *fst)
 
 /**
  * hal_rx_fst_get_fse_size() - Retrieve the size of each entry(flow) in Rx FST
+ * @hal_soc_hdl: HAL SOC handle
  *
  * Return: size of each entry/flow in Rx FST
  */
@@ -318,12 +287,10 @@ hal_rx_flow_get_tuple_info(hal_soc_handle_t hal_soc_hdl,
 #ifndef WLAN_SUPPORT_RX_FISA
 /**
  * hal_flow_toeplitz_create_cache() - Calculate hashes for each possible
- * byte value with the key taken as is
- *
+ *                                    byte value with the key taken as is
  * @fst: FST Handle
- * @key: Hash Key
  *
- * Return: Success/Failure
+ * Return: None
  */
 static void hal_flow_toeplitz_create_cache(struct hal_rx_fst *fst)
 {
@@ -384,17 +351,6 @@ static void hal_flow_toeplitz_create_cache(struct hal_rx_fst *fst)
 }
 #endif
 
-/**
- * hal_rx_fst_attach() - Initialize Rx flow search table in HW FST
- *
- * @qdf_dev: QDF device handle
- * @hal_fst_base_paddr: Pointer to the physical base address of the Rx FST
- * @max_entries: Max number of flows allowed in the FST
- * @max_search: Number of collisions allowed in the hash-based FST
- * @hash_key: Toeplitz key used for the hash FST
- *
- * Return:
- */
 struct hal_rx_fst *
 hal_rx_fst_attach(hal_soc_handle_t hal_soc_hdl,
 		  qdf_device_t qdf_dev,
@@ -462,15 +418,6 @@ out:
 }
 qdf_export_symbol(hal_rx_fst_attach);
 
-/**
- * hal_rx_fst_detach() - De-init the Rx flow search table from HW
- *
- * @hal_soc_hdl: HAL SOC handler
- * @rx_fst: Pointer to the Rx FST
- * @qdf_dev: QDF device handle
- *
- * Return:
- */
 void hal_rx_fst_detach(hal_soc_handle_t hal_soc_hdl, struct hal_rx_fst *rx_fst,
 		       qdf_device_t qdf_dev, uint64_t fst_cmem_base)
 {
@@ -491,14 +438,6 @@ void hal_rx_fst_detach(hal_soc_handle_t hal_soc_hdl, struct hal_rx_fst *rx_fst,
 qdf_export_symbol(hal_rx_fst_detach);
 
 #ifndef WLAN_SUPPORT_RX_FISA
-/**
- * hal_flow_toeplitz_hash() - Calculate Toeplitz hash by using the cached key
- *
- * @hal_fst: FST Handle
- * @flow: Flow Parameters
- *
- * Return: Success/Failure
- */
 uint32_t
 hal_flow_toeplitz_hash(void *hal_fst, struct hal_rx_flow *flow)
 {
@@ -547,14 +486,6 @@ hal_flow_toeplitz_hash(void *hal_fst, struct hal_rx_flow *flow)
 #endif
 qdf_export_symbol(hal_flow_toeplitz_hash);
 
-/**
- * hal_rx_get_hal_hash() - Retrieve hash index of a flow in the FST table
- *
- * @hal_fst: HAL Rx FST Handle
- * @flow_hash: Flow hash computed from flow tuple
- *
- * Return: hash index truncated to the size of the hash table
- */
 uint32_t hal_rx_get_hal_hash(struct hal_rx_fst *hal_fst, uint32_t flow_hash)
 {
 	uint32_t trunc_hash = flow_hash;
@@ -566,16 +497,6 @@ uint32_t hal_rx_get_hal_hash(struct hal_rx_fst *hal_fst, uint32_t flow_hash)
 }
 qdf_export_symbol(hal_rx_get_hal_hash);
 
-/**
- * hal_rx_insert_flow_entry() - Add a flow into the FST table
- * @hal_soc: HAL SOC handle
- * @hal_fst: HAL Rx FST Handle
- * @flow_hash: Flow hash computed from flow tuple
- * @flow_tuple_info: Flow tuple used to compute the hash
- * @flow_index: Hash index of the flow in the table when inserted successfully
- *
- * Return: Success if flow is inserted into the table, error otherwise
- */
 QDF_STATUS
 hal_rx_insert_flow_entry(hal_soc_handle_t hal_soc,
 			 struct hal_rx_fst *fst, uint32_t flow_hash,
@@ -615,16 +536,6 @@ hal_rx_insert_flow_entry(hal_soc_handle_t hal_soc,
 }
 qdf_export_symbol(hal_rx_insert_flow_entry);
 
-/**
- * hal_rx_find_flow_from_tuple() - Find a flow in the FST table
- *
- * @fst: HAL Rx FST Handle
- * @flow_hash: Flow hash computed from flow tuple
- * @flow_tuple_info: Flow tuple used to compute the hash
- * @flow_index: Hash index of the flow in the table when found
- *
- * Return: Success if matching flow is found in the table, error otherwise
- */
 QDF_STATUS
 hal_rx_find_flow_from_tuple(hal_soc_handle_t hal_soc_hdl,
 			    struct hal_rx_fst *fst, uint32_t flow_hash,

hal/wifi3.0/hal_rx_flow.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -32,7 +32,7 @@
 #define HAL_FST_HASH_MASK 0x7ffff
 #define HAL_RX_FST_ENTRY_SIZE (NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY * 4)
 
-/**
+/*
  * Four possible options for IP SA/DA prefix, currently use 0x0 which
  * maps to type 2 in HW spec
  */
@@ -40,13 +40,13 @@
 
 #define HAL_IP_DA_SA_PREFIX_IPV4_COMPATIBLE_IPV6 0x0
 
-/**
+/*
  * REO destination indication is a lower 4-bits of hash value
  * This should match the REO destination used in Rx hash based routing.
  */
 #define HAL_REO_DEST_IND_HASH_MASK	0xF
 
-/**
+/*
  * REO destinations are valid from 16-31 for Hawkeye
  * and 0-15 are not setup for SW
  */
@@ -68,6 +68,7 @@ enum hal_rx_fse_reo_destination_handler {
 
 /**
  * hal_rx_flow_setup_fse() - Setup a flow search entry in HW FST
+ * @hal_soc_hdl: HAL SOC handle
  * @fst: Pointer to the Rx Flow Search Table
  * @table_offset: offset into the table where the flow is to be setup
  * @flow: Flow Parameters
@@ -121,7 +122,7 @@ hal_rx_flow_delete_entry(hal_soc_handle_t hal_soc_hdl,
  * @hal_hash: HAL 5 tuple hash
  * @tuple_info: 5-tuple info of the flow returned to the caller
  *
- * Return: Success/Failure
+ * Return: 5-tuple flow info
  */
 void *
 hal_rx_flow_get_tuple_info(hal_soc_handle_t hal_soc_hdl,
@@ -131,15 +132,15 @@ hal_rx_flow_get_tuple_info(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_rx_fst_attach() - Initialize Rx flow search table in HW FST
- *
  * @hal_soc_hdl: HAL SOC handle
  * @qdf_dev: QDF device handle
  * @hal_fst_base_paddr: Pointer to the physical base address of the Rx FST
  * @max_entries: Max number of flows allowed in the FST
  * @max_search: Number of collisions allowed in the hash-based FST
  * @hash_key: Toeplitz key used for the hash FST
+ * @fst_cmem_base: FST CMEM base address
  *
- * Return:
+ * Return: FST object on success, NULL on memory allocation failure
  */
 struct hal_rx_fst *
 hal_rx_fst_attach(hal_soc_handle_t hal_soc_hdl,
@@ -150,10 +151,10 @@ hal_rx_fst_attach(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_rx_fst_detach() - De-init the Rx flow search table from HW
- *
  * @hal_soc_hdl: HAL SOC handler
  * @rx_fst: Pointer to the Rx FST
  * @qdf_dev: QDF device handle
+ * @fst_cmem_base: FST CMEM base address
  *
  * Return:
  */
@@ -163,10 +164,10 @@ void hal_rx_fst_detach(hal_soc_handle_t hal_soc_hdl, struct hal_rx_fst *rx_fst,
 /**
  * hal_rx_insert_flow_entry() - Add a flow into the FST table
  * @hal_soc_hdl: HAL SOC handle
- * @hal_fst: HAL Rx FST Handle
+ * @fst: HAL Rx FST Handle
  * @flow_hash: Flow hash computed from flow tuple
  * @flow_tuple_info: Flow tuple used to compute the hash
- * @flow_index: Hash index of the flow in the table when inserted successfully
+ * @flow_idx: Hash index of the flow in the table when inserted successfully
  *
  * Return: Success if flow is inserted into the table, error otherwise
  */
@@ -177,11 +178,11 @@ hal_rx_insert_flow_entry(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_rx_find_flow_from_tuple() - Find a flow in the FST table
- *
+ * @hal_soc_hdl: HAL SOC handle
  * @fst: HAL Rx FST Handle
  * @flow_hash: Flow hash computed from flow tuple
  * @flow_tuple_info: Flow tuple used to compute the hash
- * @flow_index: Hash index of the flow in the table when found
+ * @flow_idx: Hash index of the flow in the table when found
  *
  * Return: Success if matching flow is found in the table, error otherwise
  */
@@ -192,7 +193,6 @@ hal_rx_find_flow_from_tuple(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_rx_get_hal_hash() - Retrieve hash index of a flow in the FST table
- *
  * @hal_fst: HAL Rx FST Handle
  * @flow_hash: Flow hash computed from flow tuple
  *
@@ -202,7 +202,6 @@ uint32_t hal_rx_get_hal_hash(struct hal_rx_fst *hal_fst, uint32_t flow_hash);
 
 /**
  * hal_flow_toeplitz_hash() - Calculate Toeplitz hash by using the cached key
- *
  * @hal_fst: FST Handle
  * @flow: Flow Parameters
  *
@@ -211,6 +210,10 @@ uint32_t hal_rx_get_hal_hash(struct hal_rx_fst *hal_fst, uint32_t flow_hash);
 uint32_t
 hal_flow_toeplitz_hash(void *hal_fst, struct hal_rx_flow *flow);
 
+/**
+ * hal_rx_dump_fse_table() - Dump the RX FSE table
+ * @fst: HAL RX FST table to dump
+ */
 void hal_rx_dump_fse_table(struct hal_rx_fst *fst);
 
 /**

hal/wifi3.0/hal_srng.c

@@ -133,7 +133,7 @@ static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type,
 		return -EINVAL;
 	}
 
-	/**
+	/*
 	 * Some DMAC rings share a common source ring, hence don't provide them
 	 * with separate ring IDs per LMAC.
 	 */
@@ -409,7 +409,7 @@ error:
 
 static void hal_target_based_configure(struct hal_soc *hal)
 {
-	/**
+	/*
 	 * Indicate Initialization of srngs to avoid force wake
 	 * as umac power collapse is not enabled yet
 	 */
@@ -684,7 +684,7 @@ hal_process_reg_write_q_elem(struct hal_soc *hal,
 /**
  * hal_reg_write_fill_sched_delay_hist() - fill reg write delay histogram in hal
  * @hal: hal_soc pointer
- * @delay: delay in us
+ * @delay_us: delay in us
  *
  * Return: None
  */
@@ -936,7 +936,7 @@ static void hal_reg_write_enqueue(struct hal_soc *hal_soc,
 
 /**
  * hal_delayed_reg_write_init() - Initialization function for delayed reg writes
- * @hal_soc: hal_soc pointer
+ * @hal: hal_soc pointer
  *
  * Initialize main data structures to process register writes in a delayed
  * workqueue.
@@ -964,7 +964,7 @@ static QDF_STATUS hal_delayed_reg_write_init(struct hal_soc *hal)
 
 /**
  * hal_delayed_reg_write_deinit() - De-Initialize delayed reg write processing
- * @hal_soc: hal_soc pointer
+ * @hal: hal_soc pointer
  *
  * De-initialize main data structures to process register writes in a delayed
  * workqueue.
@@ -1086,18 +1086,6 @@ void hal_delayed_reg_write(struct hal_soc *hal_soc,
 #endif
 #endif
 
-/**
- * hal_attach - Initialize HAL layer
- * @hif_handle: Opaque HIF handle
- * @qdf_dev: QDF device
- *
- * Return: Opaque HAL SOC handle
- *		 NULL on failure (if given ring is not available)
- *
- * This function should be called as part of HIF initialization (for accessing
- * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
- *
- */
 void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
 {
 	struct hal_soc *hal;
@@ -1195,12 +1183,6 @@ fail0:
 }
 qdf_export_symbol(hal_attach);
 
-/**
- * hal_mem_info - Retrieve hal memory base address
- *
- * @hal_soc: Opaque HAL SOC handle
- * @mem: pointer to structure to be updated with hal mem info
- */
 void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem)
 {
 	struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
@@ -1216,18 +1198,7 @@ void hal_get_meminfo(hal_soc_handle_t hal_soc_hdl, struct hal_mem_info *mem)
 }
 qdf_export_symbol(hal_get_meminfo);
 
-/**
- * hal_detach - Detach HAL layer
- * @hal_soc: HAL SOC handle
- *
- * Return: Opaque HAL SOC handle
- *		 NULL on failure (if given ring is not available)
- *
- * This function should be called as part of HIF initialization (for accessing
- * copy engines). DP layer will get hal_soc handle using hif_get_hal_handle()
- *
- */
-extern void hal_detach(void *hal_soc)
+void hal_detach(void *hal_soc)
 {
 	struct hal_soc *hal = (struct hal_soc *)hal_soc;
 
@@ -1254,10 +1225,12 @@ qdf_export_symbol(hal_detach);
 #define HAL_CE_CHANNEL_DST_DEST_CTRL_DEST_MAX_LENGTH_BMSK	0x0000ffff
 #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)	((x) + 0x00000040)
 #define HAL_CE_CHANNEL_DST_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK	0x00000007
+
 /**
- * hal_ce_dst_setup - Initialize CE destination ring registers
- * @hal_soc: HAL SOC handle
+ * hal_ce_dst_setup() - Initialize CE destination ring registers
+ * @hal: HAL SOC handle
  * @srng: SRNG ring pointer
+ * @ring_num: ring number
  */
 static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng,
 				    int ring_num)
@@ -1292,15 +1265,6 @@ static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng,
 
 }
 
-/**
- * hal_reo_read_write_ctrl_ix - Read or write REO_DESTINATION_RING_CTRL_IX
- * @hal: HAL SOC handle
- * @read: boolean value to indicate if read or write
- * @ix0: pointer to store IX0 reg value
- * @ix1: pointer to store IX1 reg value
- * @ix2: pointer to store IX2 reg value
- * @ix3: pointer to store IX3 reg value
- */
 void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
 				uint32_t *ix0, uint32_t *ix1,
 				uint32_t *ix2, uint32_t *ix3)
@@ -1376,14 +1340,6 @@ void hal_reo_read_write_ctrl_ix(hal_soc_handle_t hal_soc_hdl, bool read,
 
 qdf_export_symbol(hal_reo_read_write_ctrl_ix);
 
-/**
- * hal_srng_dst_set_hp_paddr_confirm() - Set physical address to dest ring head
- *  pointer and confirm that write went through by reading back the value
- * @srng: sring pointer
- * @paddr: physical address
- *
- * Return: None
- */
 void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *srng, uint64_t paddr)
 {
 	SRNG_DST_REG_WRITE_CONFIRM(srng, HP_ADDR_LSB, paddr & 0xffffffff);
@@ -1392,13 +1348,6 @@ void hal_srng_dst_set_hp_paddr_confirm(struct hal_srng *srng, uint64_t paddr)
 
 qdf_export_symbol(hal_srng_dst_set_hp_paddr_confirm);
 
-/**
- * hal_srng_dst_init_hp() - Initialize destination ring head
- * pointer
- * @hal_soc: hal_soc handle
- * @srng: sring pointer
- * @vaddr: virtual address
- */
 void hal_srng_dst_init_hp(struct hal_soc_handle *hal_soc,
 			  struct hal_srng *srng,
 			  uint32_t *vaddr)
@@ -1427,7 +1376,7 @@ qdf_export_symbol(hal_srng_dst_init_hp);
 
 /**
  * hal_srng_hw_init - Private function to initialize SRNG HW
- * @hal_soc: HAL SOC handle
+ * @hal: HAL SOC handle
  * @srng: SRNG ring pointer
  * @idle_check: Check if ring is idle
  * @idx: ring index
@@ -1442,16 +1391,6 @@ static inline void hal_srng_hw_init(struct hal_soc *hal,
 }
 
 #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
-/**
- * hal_srng_is_near_full_irq_supported() - Check if near full irq is
- *				supported on this SRNG
- * @hal_soc: HAL SoC handle
- * @ring_type: SRNG type
- * @ring_num: ring number
- *
- * Return: true, if near full irq is supported for this SRNG
- *	   false, if near full irq is not supported for this SRNG
- */
 bool hal_srng_is_near_full_irq_supported(hal_soc_handle_t hal_soc,
 					 int ring_type, int ring_num)
 {
@@ -1530,7 +1469,6 @@ hal_srng_set_nf_thresholds(struct hal_srng *srng,
 #if defined(CLEAR_SW2TCL_CONSUMED_DESC)
 /**
  * hal_srng_last_desc_cleared_init - Initialize SRNG last_desc_cleared ptr
- *
  * @srng: Source ring pointer
  *
  * Return: None
@@ -1579,27 +1517,6 @@ static inline void hal_srng_update_high_wm_thresholds(struct hal_srng *srng)
 }
 #endif
 
-/**
- * hal_srng_setup_idx - Initialize HW SRNG ring.
- * @hal_soc: Opaque HAL SOC handle
- * @ring_type: one of the types from hal_ring_type
- * @ring_num: Ring number if there are multiple rings of same type (staring
- * from 0)
- * @mac_id: valid MAC Id should be passed if ring type is one of lmac rings
- * @ring_params: SRNG ring params in hal_srng_params structure.
- * @idle_check: Check if ring is idle
- * @idx: Ring index to be programmed as init value in HP/TP based on srng type
- *
- * Callers are expected to allocate contiguous ring memory of size
- * 'num_entries * entry_size' bytes and pass the physical and virtual base
- * addresses through 'ring_base_paddr' and 'ring_base_vaddr' in
- * hal_srng_params structure. Ring base address should be 8 byte aligned
- * and size of each ring entry should be queried using the API
- * hal_srng_get_entrysize
- *
- * Return: Opaque pointer to ring on success
- *		 NULL on failure (if given ring is not available)
- */
 void *hal_srng_setup_idx(void *hal_soc, int ring_type, int ring_num, int mac_id,
 			 struct hal_srng_params *ring_params, bool idle_check,
 			 uint32_t idx)
@@ -1830,11 +1747,6 @@ void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
 }
 qdf_export_symbol(hal_srng_setup);
 
-/**
- * hal_srng_cleanup - Deinitialize HW SRNG ring.
- * @hal_soc: Opaque HAL SOC handle
- * @hal_srng: Opaque HAL SRNG pointer
- */
 void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
 {
 	struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
@@ -1844,12 +1756,6 @@ void hal_srng_cleanup(void *hal_soc, hal_ring_handle_t hal_ring_hdl)
 }
 qdf_export_symbol(hal_srng_cleanup);
 
-/**
- * hal_srng_get_entrysize - Returns size of ring entry in bytes
- * @hal_soc: Opaque HAL SOC handle
- * @ring_type: one of the types from hal_ring_type
- *
- */
 uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type)
 {
 	struct hal_soc *hal = (struct hal_soc *)hal_soc;
@@ -1859,13 +1765,6 @@ uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type)
 }
 qdf_export_symbol(hal_srng_get_entrysize);
 
-/**
- * hal_srng_max_entries - Returns maximum possible number of ring entries
- * @hal_soc: Opaque HAL SOC handle
- * @ring_type: one of the types from hal_ring_type
- *
- * Return: Maximum number of entries for the given ring_type
- */
 uint32_t hal_srng_max_entries(void *hal_soc, int ring_type)
 {
 	struct hal_soc *hal = (struct hal_soc *)hal_soc;
@@ -1885,10 +1784,6 @@ enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type)
 	return ring_config->ring_dir;
 }
 
-/**
- * hal_srng_dump - Dump ring status
- * @srng: hal srng pointer
- */
 void hal_srng_dump(struct hal_srng *srng)
 {
 	if (srng->ring_dir == HAL_SRNG_SRC_RING) {
@@ -1908,16 +1803,9 @@ void hal_srng_dump(struct hal_srng *srng)
 	}
 }
 
-/**
- * hal_get_srng_params - Retrieve SRNG parameters for a given ring from HAL
- *
- * @hal_soc: Opaque HAL SOC handle
- * @hal_ring: Ring pointer (Source or Destination ring)
- * @ring_params: SRNG parameters will be returned through this structure
- */
-extern void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
-				hal_ring_handle_t hal_ring_hdl,
-				struct hal_srng_params *ring_params)
+void hal_get_srng_params(hal_soc_handle_t hal_soc_hdl,
+			 hal_ring_handle_t hal_ring_hdl,
+			 struct hal_srng_params *ring_params)
 {
 	struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
 	int i =0;

hal/wifi3.0/hal_tx.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -206,6 +206,7 @@ do {                                            \
  * @mcs: Transmit MCS Rate
  * @ofdma: Set when the transmission was an OFDMA transmission
  * @tones_in_ru: The number of tones in the RU used.
+ * @valid:
  * @tsf: Lower 32 bits of the TSF
  * @ppdu_id: TSF, snapshot of this value when transmission of the
  *           PPDU containing the frame finished.
@@ -374,7 +375,7 @@ static inline void hal_tx_ext_desc_set_tso_enable(void *desc,
 /**
  * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags
  * @desc: Handle to Tx MSDU Extension Descriptor
- * @flags: 32-bit word with all TSO flags consolidated
+ * @tso_flags: 32-bit word with all TSO flags consolidated
  *
  * Return: none
  */
@@ -631,6 +632,7 @@ static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc)
 #ifdef QCA_WIFI_KIWI
 /**
  * hal_tx_comp_get_buffer_source() - Get buffer release source value
+ * @hal_soc_hdl: HAL SoC context
  * @hal_desc: completion ring descriptor pointer
  *
  * This function will get buffer release source from Tx completion descriptor
@@ -657,6 +659,7 @@ hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl,
 /**
  * hal_tx_comp_get_release_reason() - TQM Release reason
  * @hal_desc: completion ring descriptor pointer
+ * @hal_soc_hdl: HAL SoC context
  *
  * This function will return the type of pointer - buffer or descriptor
  *
@@ -672,7 +675,7 @@ uint8_t hal_tx_comp_get_release_reason(void *hal_desc,
 }
 
 /**
- * hal_tx_comp_get_peer_id() - Get peer_id value()
+ * hal_tx_comp_get_peer_id() - Get peer_id value
  * @hal_desc: completion ring descriptor pointer
  *
  * This function will get peer_id value from Tx completion descriptor
@@ -709,7 +712,7 @@ static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc)
 
 /**
  * hal_tx_comp_desc_sync() - collect hardware descriptor contents
- * @hal_desc: hardware descriptor pointer
+ * @hw_desc: hardware descriptor pointer
  * @comp: software descriptor pointer
  * @read_status: 0 - Do not read status words from descriptors
  *		 1 - Enable reading of status words from descriptor
@@ -732,7 +735,7 @@ static inline void hal_tx_comp_desc_sync(void *hw_desc,
 
 /**
  * hal_dump_comp_desc() - dump tx completion descriptor
- * @hal_desc: hardware descriptor pointer
+ * @hw_desc: hardware descriptor pointer
  *
  * This function will print tx completion descriptor
  *
@@ -755,7 +758,7 @@ static inline void hal_dump_comp_desc(void *hw_desc)
 
 /**
  * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor
- * @hal_desc: Hardware (WBM) descriptor pointer
+ * @hw_desc: Hardware (WBM) descriptor pointer
  * @htt_desc: Software HTT descriptor pointer
  *
  * This function will read the HTT structure overlaid on WBM descriptor
@@ -772,7 +775,7 @@ static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc)
 /**
  * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG
  * @hal_soc_hdl: Handle to HAL SoC structure
- * @hal_srng: Handle to HAL SRNG structure
+ * @hal_ring_hdl: Handle to HAL SRNG structure
  *
  * Return: none
  */
@@ -785,9 +788,8 @@ static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl,
 }
 
 /**
- * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
- *
- * @soc: HAL SoC context
+ * hal_tx_set_dscp_tid_map() - Configure default DSCP to TID map table
+ * @hal_soc_hdl: HAL SoC context
  * @map: DSCP-TID mapping table
  * @id: mapping table ID - 0,1
  *
@@ -803,11 +805,10 @@ static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user
- *
- * @soc: HAL SoC context
- * @map: DSCP-TID mapping table
- * @id : MAP ID
- * @dscp: DSCP_TID map index
+ * @hal_soc_hdl: HAL SoC context
+ * @tid: TID
+ * @id: MAP ID
+ * @dscp: DSCP
  *
  * Return: void
  */
@@ -822,7 +823,9 @@ void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid,
 
 /**
  * hal_tx_comp_get_status() - TQM Release reason
- * @hal_desc: completion ring Tx status
+ * @desc: completion ring Tx status
+ * @ts: returned tx completion status
+ * @hal_soc_hdl: HAL SoC context
  *
  * This function will parse the WBM completion descriptor and populate in
  * HAL structure
@@ -839,8 +842,7 @@ static inline void hal_tx_comp_get_status(void *desc, void *ts,
 
 /**
  * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table
- *
- * @soc: HAL SoC context
+ * @hal_soc_hdl: HAL SoC context
  * @map: PCP-TID mapping table
  *
  * Return: void
@@ -855,8 +857,7 @@ static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_tx_update_pcp_tid_map() - Update PCP to TID map table
- *
- * @soc: HAL SoC context
+ * @hal_soc_hdl: HAL SoC context
  * @pcp: pcp value
  * @tid: tid no
  *
@@ -872,8 +873,7 @@ static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl,
 
 /**
  * hal_tx_set_tidmap_prty() - Configure TIDmap priority
- *
- * @soc: HAL SoC context
+ * @hal_soc_hdl: HAL SoC context
  * @val: priority value
  *
  * Return: void
@@ -888,6 +888,7 @@ void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val)
 
 /**
  * hal_get_wbm_internal_error() - wbm internal error
+ * @hal_soc_hdl: HAL SoC context
  * @hal_desc: completion ring descriptor pointer
  *
  * This function will return the type of pointer - buffer or descriptor
@@ -904,7 +905,6 @@ uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc)
 
 /**
  * hal_get_tsf2_offset() - get tsf2 offset
- *
  * @hal_soc_hdl: HAL SoC context
  * @mac_id: mac id
  * @value: pointer to update tsf2 offset value